FEDL610Q111-01
Issue Date: Sep. 26, 2013
ML610Q111/ML610Q112
8-bit Microcontroller
1/26
GENERAL DESCRIPTION
This LS I is a high-perf ormance 8-bit C MOS microcontroller i nto which rich peripheral circui ts, such as timers , PWM, UART, I2C
bus interface (master/slave), synchronous serial port, voltage level supervisor analog comparators and 10-bit successive
approximation type A/D converter, are incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipe line architecture parallel
processin g. The Flash ROM that i s inst alled as prog ram memory , and the on- chip debug function th at is inst alled, en able program
debugging and programming on customer’s board.
FEATURES
z CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic
operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
− On-Chip d ebug function
− Minimum instruction execution time:
30.5us (@32.768kHz system clock)
0.122us (@8.192MHz system clock)
z Internal memory
− ML610Q111:
Flash memor y :
Internal 24Kbyte Flash memory (12K x 16bit) for program including unusable 32byte test data area.
Internal 4Kbyte Flash memory (2K x 16bit) for data.
SRAM :
Internal 2Kbyte data RAM (2K x 8bit)
− ML610Q112:
Flash memor y :
Internal 32Kbyte Flash memory (16K x 16bit) for program including unusable 32byte test data area.
Internal 4Kbyte Flash memory (2K x 16bit) for data.
SRAM :
Internal 4Kbyte data RAM (4K x 8bit)
− Flash Memory operating conditio n and specification
Refer to the chapter Electrical characteristics “FLASH MEMORY SPECIFI ACTION”.
z Interrupt controller
− 1 non-maskable interrupt source (Internal source: 1(WDT) )
− 30 maskable interrupt sources (Internal sources: 23, External source: 7)
z Time base counter (TBC)
− Low-speed time base counter: 1 channel
− High-speed time base counter: 1 channel
(This time base counter is divided by 1-16, then it can be used as a clock of the Timer and PWM.)
FEDL610Q111-01
ML610Q111/ML610Q112
2/26
z Watchdog timer (WDT)
− Non-maskable interrupt and reset
(Non-maskable interrupt is generated by the first overflo w, and reset is generated by the second overflow)
− Free running
− Overflow period: 7 types selectable by software (23.4ms, 31.25ms, 62.5ms, 125ms, 500ms, 2s, and 8s)
z Timer
− 8-bit x 6 channels (16-bit configuration available, 16-bit x 3ch)
− Supports auto reload timer mode/One shot timer mode
− Timer count start/stop by software or external input trigger
(Timer function with external trigger input supports for only 2ch. Selectable external pins/analog comparator output as
an exeternal trigger.)
− The effective minimum pulse width of the external trigger input: Timer clock 3φ (about 183 ns @ 16.384 MHz)
− Allows measurement of pulse width etc. using an external trigger input.
− 8-selectable clock frequency as counter clock per channel
z PWM
− Resolution 16-bit
− Single output x 3ch, Multiple three outputs x 1ch
− Allows an output of the PWM signal in a cycle of about 122ns (@PLLCLK = 16.384MHz) to 2s (@LSCLK =
32.768kHz)
− Supports one shot PWM mode
− PWM start/stop b y software and external trigger input
(Selectable external pins, analog comparator output or timer interrupt as external trigger)
− 3-selectable clock frequency as PWM clock per channel
z UART
− TXD/RXD x 2ch
− Half -D up le x Co mmu nic a t io n
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/ne gative logic selectable
− Built-in baud rate generator
z I2C bus interface
− Master function: standard mode (100kbit/s@8MHz), Fast mode (400kbit/s@8MHz)
− Slave function : standard mode (100kbit/s)
z Synchr onous serial port (SSIO)
− 1ch
− Master/slave selectable
− LSB first/MSB first se lectable
− 8-bit length/16-bit length selectable
z Successive approximatio n type A/D converter (SA-ADC)
− 10-bit A/D converter
− Analog Input
6ch (ML610Q111)
8ch (ML610Q112)
FEDL610Q111-01
ML610Q111/ML610Q112
3/26
z Analog comparator
− 2ch
ch0: Allows comparison of the voltage level of the two external pins or comparison of one external pin and internal
refe rence voltage level.
ch1: Allows comparison of one external pin and internal reference voltage level
− Input common mode volt age r ange : VDD = 0.1V to VDD - 1.5V
− Internal reference voltage : 0.1-0.8V (Selectable in 50mV increments)
− Hysteresis (Comparator0 only): 20mV(Typ.)
− Allows selection of with/without interrupt sampli ng and interrupt edge.
z General-purpose ports (GPIO)
− Input/output port
15ch (ML610Q111)
25ch (ML610Q112)
z Reset
− Reset by the RESET_N pin
− Reset by power-on detection
− Reset by the watchdog timer (WDT) 2nd overflow
− Reset by the voltage level supervisor (VLS) function: Selectable by software
z Voltage level supervisor (VLS)
− 2ch
ch0: It can be used for voltage level detection reset
ch1: It can be used for voltage level detection i nterrupt
− Judgment accuracy: ±3.0% (Typ.)
z Clock
− Low-speed clock:
Built-in RC oscillatio n (32.768kHz)
− High-speed clock:
Built-in PLL oscillation (16.384MHz)
High-speed external clock (max. 8.192MHz)
Maximum CPU clock is 8.192MHz.
− Selec t ion of high- speed clock mod e by so ftware:
Built-in PLL oscillation
External clock
z Po wer manage men t
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states)
− STOP mode: Stop of oscillation (Operations of CPU and peripheral circuits are stopped.)
− Clock gear: The frequency of system clock can be chan ged b y software (1/1, 1 /2 , 1 /4, or 1/8 of the oscillation clock).
− Blo ck Control Functi on: Power down (reset registers a nd sto p cloc k suppl y) the circuits of unused periphera l s.
FEDL610Q111-01
ML610Q111/ML610Q112
4/26
z Shipment
− ML610Q111:
20-pin TSSOP:
ML610Q111-xxxTD (blank product: ML610Q111-NNNTD)
− ML610Q112:
32-pin LQFP:
ML610Q112-xxxTC (blank product: ML610Q112-NNNTC)
z Guaranteed operating range
− Operating temperature (ambience): -40°C to 105°C (Flash write/erase: -20°C to +85°C)
− Operating voltage: VDD=2.7V to 5.5V
FEDL610Q111-01
ML610Q111/ML610Q112
5/26
BLOCK DIAGRAM
The block diagram is shown in figure 1.
“*” mea ns seco ndary function, tertiary function or q uaternary function of each port.
“()*2” means the function of ML610Q112.
Figure 1. ML610Q111/ML610Q112 Block Diagram
Program
Memory
(Flash)
24Kbyte
(32Kbyte)*2
UART
RXD0
TXD0*
INT
2
RAM
2Kbyte
(4Kbyte)*2
Interrupt
Controller
CPU (nX-U8/100)
Timing
Controller
EA
SP
On-Chip
ICE
Instruction
Decoder
BUS
Controller
Instruction
Register
TBC
INT
4
INT
1WDT
INT
68bit Timer
x 6
INT
4
PWM
GPIO
PA0 to PA2
(PC4 to PC7)
*2
INT
7
PB0 to PB7
Data-bus
PWMC*
PWMD*,
PWME*
PWMF0*
PWMF1*
PWMF2*
TEST
RESET_N
Power
RESET &
TEST
ALU
EPSW1 - 3
PSW
ELR1 - 3
LR
ECSR1 - 3
DSR/CSR
PC
GREG
0 - 15
VDD
VSS
10bit-ADC
AIN0
to
AIN5(AIN7)*2
INT
1
VLS
INT
2I
2
C
Master/Slave SCL*
SDA*
SSIO
SCK*
SOUT*
SIN*
INT
1
(
PD0 to PD5
)
*2
Analog
Comparator
x 2
CMP0P
CMP0M
INT
2
CMP0OUT*
CMP1OUT*
CMP1P
TEST
RESET_N
Clock
Generator
INT
1
Data
Memory
(Flash)
4Kbyte RXD1
TXD1*
PC0 to PC3
FEDL610Q111-01
ML610Q111/ML610Q112
6/26
PIN CONFIGURATION (TOP VIEW)
z ML610Q111-xxxTD
The pin layout is shown in figure 2.
* PIN No.4-8, 12-15, 18, 19 can be used as external trigger of the Timer E-F and PWMC-F.
Figure 2. ML610Q111 TSSOP20 Pin Configuration
CMP0OUT / CLKIN / PWME / EXI2 / PA2
1
2
3
4
5
6
7
8
9
10
RESET_N
TEST
TXD1 / TXD0 / PWMD / AIN3 / EXI5 / PB1
PWME / RXD1 / EXI6 / PB2
TXD1 / SIN / EXI7 / PB3
TESTF
TMFOUT / PC3
CMP1OUT / OUTCLK / PWMC / RXD0 / AIN2 / EXI4 / PB0
TM9OUT / PWMF0 / PC0 20
19
18
17
16
15
14
13
12
11
PC1 / PWMF1
PA0 / EXI0 / AIN0 / PWMC / OUTCLK / TM9OUT
PB7 /
A
IN5 / RXD1 / LSCLK / PWMF0 / PWMC
VDD
VSS
PB6 / AIN4 / CLKIN / SDA / PWMF1
PB5 / CMP0M / RXD0 / SCK / SCL / PWMF2
PB4 / CMP0P / SOUT / TXD0 / TXD1
PA1 / EXI1 / AIN1 / CMP1P / PWMD / LSCLK / TMFOUT
PC2 / PWMF2
FEDL610Q111-01
ML610Q111/ML610Q112
7/26
z ML610Q112-xxxTC
The pin layout is shown in figure 3.
* PIN No.3, 5-8, 16-19, 24, 25 can be used as external trigger of the Timer E- F and PWMC-F.
Figure 3. ML610Q112 LQFP32 Pin Configuration
26
PA0 / EXI0 / AIN0 / PWMC
/
OUTCLK / TM9OUT
27 28 29 30 31 3225
RESET_N
PC6 / AIN6
PC1 / PWMF1
PC5 / SDA
PC4 / SCL
PD0
PC0 / PWMF0 / TM9OUT
PD5
PWMF2 / PC2
PD4
PD3
TMFOUT / PC3
PD2
15 14 13 12 11 10 9
16
TESTF
PB3 / EXI7 / SIN / TXD1
PB2
/
EXI6 / RXD1 / PWME
PB1 / EXI5 / AIN3 / PWMD / TXD0 / TXD1
N.C.
PB0 / EXI4 / AIN2 / RXD0 / PWMC / OUTCLK / CMP1OUT
PD1
TEST
1
2
3
4
5
6
7
8PA2 / EXI2 / PWME / CLKIN / CMP0OUT
PWMF1 / SDA / CLKIN / AIN4 / PB6
N.C.
VSS
VDD
AIN7 / PC7
24
23
22
21
20
19
18
17
TXD1 / TXD0 / SOUT / CMP0P / PB4
PWMF2 / SCL / SCK / RXD0 / CMP0M / PB5
PWMC / PWMF0 / LSCLK / RXD1 / AIN5 / PB7
CMP1P / AIN1 / EXI1 / PA1
/ TMFOUT / LSCLK / PWMD
FEDL610Q111-01
ML610Q111/ML610Q112
8/26
PIN LIST Table 1. ML610Q111/ML610Q112 Pin List
PIN No. Primary function Secondary function Tertiary function Quaternary function
32
LQFP 20
TSSOP Name I/O Function Name I/O Function Name I/O Function Name I/O function
21 16 VSS — power supply — — — — — — — — —
22 17 VDD — power supply — — — — — — — — —
9 9 TESTF — TEST — — — — — — — — —
32 2 RESE T_N I SYSTEM — — — — — — — — —
1 3 TEST I/O TEST — — — — — — — — —
25 19
PA0/
EXI0/
AIN0/
TnTG*/
PmTG**
I/O
GPIO/
EXINT/
SA-ADC/
TIMER/
PWM
PWMC O PWM OUTCLK O SYSTEM TM9OUT O TIMER
16 12
PA1/
EXI1/
AIN1/
CMP1P/
TnTG*/
PmTG**
I/O
GPIO/
EXINT/
SA-ADC/
COMP/
TIMER/
PWM
PWMD O PWM LSCLK O SYSTEM TMFOUT O TIMER
8 8
PA2/
EXI2/
TnTG*/
PmTG**
I/O
GPIO/
EXINT/
TIMER/
PWM
PWME O PWM CLKIN I SYSTEM CMP0OUT O COMP
3 4
PB0/
EXI4/
AIN2/
RXD0/
TnTG*/
PmTG**
I/O
GPIO/
EXINT/
SA-ADC/
UART/
TIMER/
PWM
PWMC O PWM OUTCLK O SYSTEM CMP1OUT O COMP
5 5
PB1/
EXI5/
AIN3/
TnTG*/
PmTG**
I/O
GPIO/
EXINT/
SA-ADC/
TIMER/
PWM
PWMD O PWM TXD0 O UART TXD1 O UART
6 6
PB2/
EXI6/
RXD1/
TnTG*/
PmTG**
I/O
GPIO/
EXINT/
UART/
TIMER/
PWM
PWME O PWM — — — — — —
7 7
PB3/
EXI7/
TnTG*/
PmTG**
I/O
GPIO/
EXINT/
TIMER/
PWM
SIN I SSIO TXD1 O UART — — —
17 13 PB4/
CMP0P I/O GPIO/
COMP SOUT O SSIO TXD0 O UART TXD1 O UART
18 14 PB5/
RXD0/
CMP0M I/O GPIO/
UART/
COMP SCK I/O SSIO SCL I/O I2C PWMF2 O PWM
19 15 PB6/
AIN4 I/O GPIO/
SA-ADC CLKIN I SYSTEM SDA I/O I2C PWMF1 O PWM
24 18 PB7/
AIN5/
RXD1 I/O GPIO/
SA-ADC/
UART LSCLK O SYSTEM PWMF0 O PWM PWMC O PWM
30 1 PC0 I/O GPIO — — — PWMF0 O PWM TM9OUT O TIMER
27 20 PC1 I/O GPIO — — — PWMF1 O PWM — — —
14 11 PC2 I/O GPIO — — — PWMF2 O PWM — — —
11 10 PC3 I/O GPIO — — — — — — TMFOUT O TIMER
FEDL610Q111-01
ML610Q111/ML610Q112
9/26
PIN No. Primary function Secondary function Tertiary function Quaternary function
32
LQFP 20
TSSOP Name I/O Function Name I/O Function Name I/O Function Name I/O function
29 — PC4 I/O GPIO SCL I/O I2C — — — — — —
28 — PC5 I/O GPIO SDA I/O I2C — — — — — —
26 — PC6/
AIN6 I/O GPIO/
SA-ADC — — — — — — — — —
23 — PC7/
AIN7 I/O GPIO/
SA-ADC — — — — — — — — —
31 — PD0 I/O GPIO/ — — — — — — — — —
2 — PD1 I/O GPIO/ — — — — — — — — —
10 — PD2 I/O GPIO — — — — — — — — —
12 — PD3 I/O GPIO — — — — — — — — —
13 — PD4 I/O GPIO — — — — — — — — —
15 — PD5 I/O GPIO — — — — — — — — —
* : TnTG = TETG, TFTG.
** : PmTG = PCTG, PDTG, PETG, PFTG.
FEDL610Q111-01
ML610Q111/ML610Q112
10/26
PIN DESCRIPTION Table 2. ML610Q111/ML610Q112 Pin Description
Pin name I/O Desc r iption
Primary
Secondary
Tertiary,
Quaternary
Logic
Syste m
RESET_N I
Reset input pin. When this pin is set to “L” level, system reset mode is set and the
internal section is initialized. When this pin is set to “H” level subsequently, program
execution starts. A pull-up resistor is internally connected. Primary Negative
CLKIN I
High-speed clock input pin. This pin is used as the secondary function of PB6 pin and
also as the tertiary function of PA2 pin. Secondary,
Tertiary —
LSCLK O
Low-speed clock output pin. This pin is used as the secondary function of PB7 pin and
also as the tertiary function of the PA1. Secondary,
Tertiary —
OUTCLK O
High-s peed cloc k output p in. This pin is use d as the ter tiary function of the PA0 a nd PB0
pin. Tertiary —
General Purpose Input/Output Port
PA0 to PA2
PB0 to PB7
PC0 to PC7
PD0 to PD5
I/O General-purpose input/output port.
Since t hese pins have secon dary , tertiary or quat ernary func tions, th e pins c annot be used
as a port when the secondary, tertiary or quaternary functions are used. Primary Positive
Synchronous Serial I/O
SIN I Synchronous seria l data inp ut pin. T his pin is use d as t he s econda ry function of PB3 pin . Secondary Positive
SCK I/O
Synchronous serial clock input/output pin. This pin is used as the secondary function of
PB5 pin. Secondary —
SOUT O
Synchronous serial data output pin. This pin is used as the secondary function of PB4
pin. Secondary Positive
UART
TXD0 O UA RT0 da ta output p in. This pin is use d as the te rtiary function of the PB1 and PB4 pin. Tertiary Positive
RXD0 I UART0 data input pin. This pin is used as the primary function of the PB0 and PB5 pin Primary Positive
TXD1 O
UART1 data output pin. This pin is used as the tertiary function of the PB3 pin and also
the quaternary function of the PB1 and PB4 pin. Tertiary
Quaternary Positive
RXD1 I UART1 data input pin. This pi n is used as the primary f unc tion of the PB2 an d PB 7 pi n . Primary Positive
I2C Bus Interface
SCL I/O
Serial clock input/output. This pin is used as the tertiary function of the PB5 and the
secondary function of the PC4 pin. Tertiary
Secondary Positive
SDA I/O
Serial data input/output. This pin is used as the tertiary function of the PB6 and the
secondary function of the PC5 pin. Tertiary
Secondary Positive
PWM
PWMC O
PWMC output pin. This pin is used as the secondary function of the PA0 and PB0 and
also the quaternary function of the PB7 pin. Secondary
Quaternary Positive/
Negative
PWMD O PWMD output pin. This pin is used as the secondary function of the PA1 and PB1 pin. Secondary Positive/
Negative
PWME O PWME output pin. This pin is used as the secondary function of the PA2 and PB2 pin. Secondary Positive/
Negative
PWMF0 O PWMF0 output pin. This pin is used as the tertiary function of the PB7 and PC0 pin. Tertiary Positive/
Negative
PWMF1 O
PWMF1 output pin. This pin is used as the tertiary function of the PC1 and also the
quaternary function of PB6 pin. Tertiary/
Quaternary Positive/
Negative
FEDL610Q111-01
ML610Q111/ML610Q112
11/26
PWMF2 O
PWMF2 output pin. This pin is used as the tertiary function of the PC2 and also the
quaternary function of the PB5 pin. Tertiary/
Quaternary Positive/
Negative
Pin name I/O Descr iption
Primary
Secondary
Tertiary,
Quaternary
Logic
External Interrupt
EXI0 to 2 I External maskable interrupt input pins. Interrupt enable and edge selection can be
p
erformed for each b it by software. These p ins are used as the primar y function s of the
PA0 – PA2 pins. Primary Positive/
negative
EXI4 to 7 I External maskable interrupt input pins. Interrupt enable and edge selection can be
p
erformed for each b it by software. These p ins are used as the primar y function s of the
PB0 – PB3 pins . Primary Positive/
negative
Timer
TETE, TF T G I External clock input pin used for both Timer E and Timer F.These pins are used as the
prim ary function of the PA0- PA 2 , PB0- PB 7 pins. Primary —
TM9OUT O Timer 9 output pin. This pin is used as the quaternary function of the PA0 and PC0 pin. Quaternary Positive
TMFOUT O Timer F output pin. This pin is used as the quaternary function of the PA1 and PC3 pin. Quaternary Positive
Successive approximation type A/D converter
AIN0 I Channel 0 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PA0 pin. Primary —
AIN1 I Channel 1 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PA1 pin. Primary —
AIN2 I Channel 2 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PB0 pin. Primary —
AIN3 I Channel 3 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PB1 pin. Primary —
AIN4 I Channel 4 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PB6 pin. Primary —
AIN5 I Channel 5 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PB7 pin. Primary —
AIN6 I Channel 6 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PC6 pin. Primary —
AIN7 I Channel 7 analog input for successive approximation type A/D converter. This pin is
used as the primary function of the PC7 pin. Primary —
Comparator
CMP0P I Non-i nverting inpu t for c omparat or0. This pi n is used a s the prim ary function of the PB4
pin. Primary —
CMP0M I Inverting in put for comparat or0. This pin is used as the primary f unction of t he PB5 pin. Prim a ry —
CMP0OUT O Output for comparator0. This pin is used as the quaternary function of the PA2 pin. Quaternary —
CMP1P I Non-i nverting inp ut for c ompara tor1. This pin is used a s the prim ary function of the PA 1
pin. Primary —
CMP1OUT O Output for comparator1. This pin is used as the quaternary function of the PB0 pin. Quaternary —
TEST
TEST I/O Input/output pin for testing. A pull-down resistor is internally connected. — Positive
TESTF — Test pin for flash memory. A pull-down resistor is internally connected. — —
Power Supply
VSS — Negative power supply pin. — —
VDD — Positive power supply pin. — —
FEDL610Q111-01
ML610Q111/ML610Q112
12/26
TERMINATION OF UNUSED PINS
Table 3 shows methods of terminating the unused pins for ML610Q111/ML610Q112
Table 3. Termination of Unused Pins
Pin Recommended pin termination
RESET_N Open
TEST Open
TESTF Open
PA0 to PA2 Open
PB0 to PB7 Open
PC0 to PC7 Open
PD0 to PD5 Open
N.C. Open
Note:
It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or
the output mode since the supply current may become excessively large if the pins are left open in the high impedance input
setting.
FEDL610Q111-01
ML610Q111/ML610Q112
13/26
ELECTRICAL CHARACTERISTICS
z ABSOLUTE MAXIMUM RATINGS
(VSS=0V)
Parameter Symbol Condition Rating Unit
Power supply voltage VDD Ta = 25°C -0.3 to +7.0 V
Input voltage VIN Ta = 25°C -0.3 to VDD+0.3 V
Output voltage VOUT Ta = 25°C -0.3 to VDD+0.3 V
Output current IOUT Ta = 25°C -12 to +11 mA
Power dissipation PD Ta = 25°C 0.84 W
Storage temperature TSTG ― -55 to 150 °C
z RECOMMENDED OPERATING CONDITIONS
(VSS=0V)
Parameter Symbol Condition Range Unit
Operating temperature
(ambience) TOP ― -40 to +105 °C
Operating voltage VDD ― 2.7 to 5.5 V
z FLASH MEMORY SPECIFICATION
(VSS= 0V)
Parameter Symbol Condition Rating Unit
At read -40 to +105 °C
Operating temperature
(ambience) TOPF At write/erase -20 to +85 °C
CEPD Data flash memory (4KB) 6000
Rewrite counts*1 CEPP Program flash memory 80 cycles
― Chip-erase
Program flash and Data
flash memory ―
― Block-erase
(Program flash memory) 8 KB
― Block-erase
(Data flash memory) 4 KB
Erase unit
― Sector-erase
(Data flash memory) 1 KB
Erase time (max.) ― Chip-erase/Block-erase/Sector-erase 100 ms
Write unit ― ― 1word(2bytes) ―
Write time (max.) ― 1word(2bytes) 40 μs
Data retention*2 Y
DR ― 15 years
*1: Rewrite counts is counted as one even if you erase suspend.
*2: However, keep active time of the LSI from exceeding ten years.
In addition, following capability of Flash memory is available;
- security function: providing security ID for the protection of program code implemented in Flash memory
- accidental-write protection: providing special sequence to protect accidental write data to Flash memory. By writing “0FAx” and“0F5x”
sequentially, before write/erase, writing one word is available just only one time.
- erase interrupt function: in the case of external interrupt during erasing flash memory, erase execution is suspended. And then the interrupt
is activated. Please re-erase after interrupt execution.
FEDL610Q111-01
ML610Q111/ML610Q112
14/26
z DC CHARACTERISTICS (Supply Current)
(VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105°C, unless otherwise specified)
Rating
Parameter Symbol Condition Min. Typ. Max.
Unit Measuring
circuit
Supply current 1 IDD1
CPU : In STOP state
(All clock stop)
VDD=5.0V
― 1 50 μA
Supply current 2 IDD2
CPU : In HALT state*1
(Only CR oscillation operates)
VDD=5.0V
― 240 ― μA
Supply current 3 IDD3
CPU : CR32.768kHz
operating state*2
(Only CR oscillation operates)
VDD=5.0V
― 250 ― μA
Supply current 4 IDD4
CPU : CR8.192MHz
operating state*3
(CR and PLL oscillation operate)
VDD=5.0V
― 4 6 mA
1
*1 : LTBC and WDT are operating ,and significant bits of BLKCON0 to BLKCON7 registers are all “1”.
*2 : When the CPU operating rate is 100%. Minimum instruction execution time: Approx 30.52 μs (at 32.768kHz system clock)
*3 : When the CPU operating rate is 100%. Minimum instruction execution time: Approx 122 ns (at 8.192MHz system clock)
FEDL610Q111-01
ML610Q111/ML610Q112
15/26
z DC CHARACTERISTICS (VLS, Comparator)
(VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105°C, unless otherwise specified)
Rating
Parameter Symbol Condition Min. Typ. Max.
Unit Measuring
circuit
Ta=25°C Typ
-3.0%
Typ
+3.0%
VLS0 threshold
voltage
(VDD=fall)
VVLS0F
― Typ
-5.0%
2.85 Typ
+5.0%
Ta=25°C Typ
-3.0%
Typ
+3.0%
VLS0 threshold
voltage
(VDD=rise)
VVLS0R
― Typ
-5.0%
2.92 Typ
+5.0%
VLS1=0 3.3
VLS1=1 3.6
VLS1=2 3.9
Ta=25°C
VLS1=3
Typ
-3.0%
4.2
Typ
+3.0%
VLS1=0 3.3
VLS1=1 3.6
VLS1=2 3.9
VLS1 threshold
voltage
(VDD=fall)
VVLS1
―
VLS1=3
Typ
-5.0%
4.2
Typ
+5.0%
V
Comparator0
In-phase input
voltage range
VCMR ― 0.1 ― V
DD -1.5 V
Ta=25°C , VDD = 5.0V 10 20 30
Comparator0
hysteresis VHYSP VDD = 5.0V 5 20 35
Comparator0
Input offset voltage VCMOF Ta=25°C , VDD = 5.0V ― ― 7
Ta=25°C -25 ― 25
Comparator
Reference-
voltage error*1
VCMREF ― -50 ― 50
mV
1
*1 :Comparator input offset voltage is included.
FEDL610Q111-01
ML610Q111/ML610Q112
16/26
z DC CHARACTERISTICS (IO pins)
(VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105°C, unless otherwise specified)
Rating
Parameter Symbol Condition Min. Typ. Max.
Unit Measuring
circuit
IOH=-3.0mA, VDD=4.5V*1
Ta= -40 to 85°C
VDD
-0.7 ― ―
VOH1
IOH=-3.0mA, VDD=4.5V*1 VDD
-0.8 ― ―
IOL=+8.5mA, VDD=4.5V*1
Ta= -40 to 85°C ― ― 0.6
Output voltage1
( TEST,
PA0-2, PB0-7,
PC0-7, PD0-5 )
VOL1
IOL=+8.5mA, VDD=4.5V*1 ― ― 0.7
Output voltage2
(PB5, PB6 PC4, PC5) VOL2 IOL=+3.0mA ― ― 0.4
V 2
IOOH VOH = VDD (in high-impedance state) ― ― 1
Output leakage
( PA0-2, PB0-7,
PC0-7, PD0-5 ) IOOL VOL = VSS (in high-impedance state) -1 ― ―
μA 3
IIH1 VIH1 = VDD ― ― 1
Input current 1
( RESET_N ) IIL1 VIL1 = VSS, VDD = 5.0V −650 −500 −350
IIH2 VIH2= VDD = 5.0V 20 115 200
Input current 2
( TEST ) IIL2 VIL2 = VSS −1 ― ―
IIH3 VIH3 = VDD = 5.0V (when pulled-down) 20 115 200
IIL3 VIL3 = VSS, VDD = 5.0V (when pulled-up) −200 −100 −20
IIH3Z VIH3 = VDD (in high-impedance stat) ― ― 1
Input current 3
( PA0-2, PB0-7,
PC0-7, PD0-5 )
IIL3Z VIH3 = VSS (in high-impedance stat) -1 ― ―
μA 4
*1 : When the one terminal output state.
(VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105°C, unless otherwise specified)
Rating
Parameter Symbol Condition Min. Typ. Max.
Unit Measuring
circuit
VIH1 ― 0.7
×VDD ― VDD V
Input voltage 1
( RESET_N, TEST,
PA0-2, PB0-7,
PC0-7, PD0-5 ) VIL1 ― 0 ― 0.3
×VDD
2
Input pin capacitance
( PA0-2, PB0-7,
PC0-7, PD0-5 )
CIN f = 10kHz
Ta = 25°C ― ― 20 pF ―
FEDL610Q111-01
ML610Q111/ML610Q112
17/26
z MEASURING CIRCUITS
Measuring circuit 1
V
VDD VSS
VIH
VIL
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
*3: Measured at the specified input pins.
(*2)
(*1)
(*3)
Measuring circuit 4
Measuring circuit 2
VDD VSS
VIH
VIL
(*2)
A
VDD VSS
A
Input pins
VDD V
SS
A
CV : 1μF
Output pins
Output pins
Input pins
Input pins
Input pins
Output pins
Output pins
Measuring circuit 3
CV
FEDL610Q111-01
ML610Q111/ML610Q112
18/26
z AC CHARACTERISTICS (Clo ck)
(VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105°C, unless otherwise specified)
Rating
Parameter Symbol Condition Min. Typ. Max. Unit
Ta = -20 to 85°C Typ.
-3%
Typ.
+3%
32kHz RC oscillation frequency fRCL
― Typ.
-4%
32.768
Typ.
+4%
kHz
Ta = -20 to 85°C Typ.
-3%
Typ.
+3%
PLL oscillation frequency *1 fPLL
― Typ.
-4%
16.384 Typ.
+4%
MHz
*1 : 1024 clock average. Maximum CPU clock frequency is fPLL/2.
z AC CHARACTERISTICS (Power on / Reset sequence)
(VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105°C, unless otherwise specified)
Rating
Parameter Symbol Condition Min. Typ. Max. Unit
Reset pulse width PRST ― 100 ― ― μs
Reset noise elimination
pulse width PNRST ― ― ― 0.4
Power-on reset activation
power rise time TPOR ― ― ― 10
ms
PRST
RESET_N
VDD
0.9*VDD
0.3*VDD
VDD
0.9*VDD
0.1*VDD
TPOR
PRST
0.3*VDD
0.3*VDD
Powe
r
-on Reset sequence
External Reset sequence
FEDL610Q111-01
ML610Q111/ML610Q112
19/26
z AC CHARACTERISTICS (External Interrupt)
(VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105°C, unless otherwise specified)
Rating
Parameter Symbol Condition Min. Typ. Max. Unit
External interrupt disable
period TNUL Interrupt: Enabled (MIE = 1),
CPU: NOP operation
2.5 x
sysclk ― 3.5 x
sysclk φ
tNUL
PA0 - PA2, PB0 - PB3
PA0 - PA2, PB0 - PB3
PA0 - PA2, PB0 - PB3
tNUL
(Rising-edge interrupt)
(Falling-edge interrupt)
(Both-edge interrupt)
tNUL
FEDL610Q111-01
ML610Q111/ML610Q112
20/26
z AC CHARACTERISTICS (Synchronous Serial Port)
(VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105°C, unless otherwise specified)
Rating
Parameter Symbol Condition Min. Typ. Max.
Unit
When high-speed oscillation is not
active 10 ― ― μs
SCK input cycle
(slave mode) tSCYC When high-speed oscillation is
active 500 ― ― ns
SCKoutput cycle
(master mode) tSCYC ― ― SCK*1 ― s
When high-speed oscillation is not
active 4 ― ― μs
SCK input pulse width
(slave mode) tSW When high-speed oscillation is
active 200 ― ― ns
SCK output pulse width
(master mode) tSW ― tSCYC
×0.4
tSCYC
×0.5
tSCYC
×0.6 s
SOUT output delay
(slave mode) tSD ― ― ― 180 ns
SOUT output delay
(master mode) tSD ― ― ― 80 ns
SIN input
setup time
(slave mode)
tSS ― 50 ― ― ns
SIN input
hold time tSH ― 50 ― ― ns
*
1 : Clock period selected with S0CK3-0 of the serial port 0 mode register(SIO0MOD1)
tSD
SCK0
SIN0
SOUT0
tSD
tSS tSH
tSW
tSCYC
tSW
FEDL610Q111-01
ML610Q111/ML610Q112
21/26
z AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz)
(VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105°C, unless otherwise specified)
Rating
Parameter Symbol Condition Min. Typ. Max. Unit
SCL clock frequency fSCL ― 0 ― 100 kHz
SCL hold time
(start/restart condition) tHD:STA ― 4.0 ― ― μs
SCL”L” level time tLOW ― 4.7 ― ― μs
SCL”H” level time tHIGH ― 4.0 ― ― μs
SCL setup time
(restart condition) tSU:STA ― 4.7 ― ― μs
SDA hold time tHD:DAT ― 0 ― ― μs
SDA setup time tSU:DAT ― 0.25 ― ― μs
SDA setup time
(stop condition) tSU:STO ― 4.0 ― ― μs
Bus-free time tBUF ― 4.7 ― ― μs
z AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz)
(VDD=2.7 to 5.5V, VSS=0V, Tj=-40 to +105°C, unless otherwise specified)
Rating
Parameter Symbol Condition Min. Typ. Max. Unit
SCL clock frequency fSCL ― 0 ― 400 kHz
SCL hold time
(start/restart condition) tHD:STA ― 0.6 ― ― μs
SCL”L” level time tLOW ― 1.3 ― ― μs
SCL”H” level time tHIGH ― 0.6 ― ― μs
SCL setup time
(restart condition) tSU:STA ― 0.6 ― ― μs
SDA hold time tHD:DAT ― 0 ― ― μs
SDA setup time tSU:DAT ― 0.1 ― ― μs
SDA setup time
(stop condition) tSU:STO ― 0.6 ― ― μs
Bus-free time tBUF ― 1.3 ― ― μs
SCL
SDA
start condition restart condition stop condition
tBUF
tHD:STA t
LOW t
HIGH t
SU:STA tHD:STA t
SU:DAT t
HD:DAT tSU:STO
FEDL610Q111-01
ML610Q111/ML610Q112
22/26
z Electrical Characteristics of Successive Approximation Type A/D Converter
(VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105°C, unless otherwise specified)
Rating
Parameter Symbol Condition Min. Typ. Max. Unit
Resolution n ― ― ― 10 bit
Integral non-linearity error INL ― -4 ― +4
Differential non-linearity
error DNL ― -3 ― +3
Zero-scale error VOFF ― -4 ― +4
Full-scale error FSE ― -4 ― +4
LSB
Conversion time tCONV ― ― 102 ― φ/CH
Φ : period of OSCLK (more than 3MHz)
A
VDD
VSS
Analog input
- RI
≤
5k
Ω
A
IN
0.1μF
+
10μF
FEDL610Q111-01
ML610Q111/ML610Q112
23/26
PACKAGE DIMENSIONS
z ML610Q111-xxxTD
Figure 4 TSSOP20
FEDL610Q111-01
ML610Q111/ML610Q112
24/26
z ML610Q112-xxxTC
Figure 5 LQFP32
z Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package
name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
FEDL610Q111-01
ML610Q111/ML610Q112
25/26
REVISION HISTORY
Page
Document No. Date Previous
Edition
Current
Edition Description
FEDL610Q111-01 2013.9.26 ― ― Final edition 1
FEDL610Q111-01
ML610Q111/ML610Q112
26/26
NOTES
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co.,
Ltd.
The content specified herein is subject to change for improvement without notice.
Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and
operations of the Products. The perip heral conditions must b e taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any
damage arising from any inaccuracy or misprint o f suc h info rmation, LAPIS Semiconductor shall bear no responsibility for such
damage.
The technical infor mation spe cified herein is intended o nly to show the t ypical functions o f and examples o f application circuits
for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual
property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no responsibility
whatsoever for any dispute arising from the use of such technical information.
The Products specified in this docu ment are intended to be used with general-use electronic equipment or devices (such as audio
visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical
injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and
fail-safe designs. LAPIS Semiconductor shall bear no responsibility whatsoever for your use of any Product outside of the
prescribed scope or not in accordance with the instruction manual.
The Products are not desi gned or m anufactured to be us ed with any equipment, device or sy stem which requ ires an extremely high
level of reliability the fail ure or malfunction of whic h may result in a direct threat to hu man life or create a risk of hu man injury
(such as a medical instrument, transportation equ ipm ent, aeros pace machinery, nuclear-reactor controller, fu el-c on troller or ot her
safety device). LAPIS Semiconductor shall bear no respo nsi bility in any way for use of an y of the Products for the above special
purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before
purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign
Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Copyright 2013 LAPIS Semiconductor Co., Ltd.
