1
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
19-5644; Rev 1; 3/11
General Description
The MAX9263/MAX9264 chipset extends Maxim’s gigabit
multimedia serial link (GMSL) technology to include high-
bandwidth digital content protection (HDCP) encryption
for content protection of DVD and Blu-ray™ video and
audio data. The MAX9263 serializer, or any HDCP-GMSL
serializer, pairs with the MAX9264 deserializer, or any
HDCP-GMSL deserializer, to form a digital serial link for
the transmission of control data and HDCP encrypted
video and audio data. GMSL is an HDCP technology
approved protocol by Digital Content Protection (DCP),
LLC.
The parallel interface is programmable for 24-bit or
32-bit width and operates with a pixel clock of 8.33MHz
to 104MHz (24 bit) or 6.25MHz to 78MHz (32 bit). When
programmed for 24-bit or 32-bit width, three inputs are
for I2S audio, supporting a sampling frequency from
8kHz to 192kHz and a sample depth of 4 bits to 32
bits. The embedded control channel forms a full-duplex
differential 9.6kbps to 1Mbps UART link between the
serializer and deserializer. An electronic control unit
(ECU), or microcontroller (FC), can be located on the
serializer side of the link (typical for video display), on the
deserializer side of the link (typical for image sensing), or
on both sides (typical for HDCP video display repeaters).
The control channel enables ECU/FC control of peripher-
als on the remote side, such as backlight control, touch
screen, and perform HDCP-related operations.
The serial link signaling is AC-coupled CML with 8b/10b
coding. For driving longer cables, the serializer has pro-
grammable pre/deemphasis, and the deserializer has a
programmable channel equalizer. The GMSL devices
have programmable spread spectrum on the serial
(serializer) and parallel (deserializer) output. The serial
link input and output meet ISO 10605 and IEC 61000-
4-2 ESD standards. The serializer core supply is 1.8V
and the deserializer core supply is 3.3V. The I/O supply
is 1.8V to 3.3V. Both devices are available in a 64-pin
TQFP package with an exposed pad and are specified
over the -40NC to +105NC automotive temperature range.
Applications
High-Resolution Automotive Navigation
Rear-Seat Infotainment
Megapixel Camera Systems
Features
S HDCP Encryption Enable/Disable Programmable
Through Control Channel
S Control Channel Handles All HDCP Protocol
Transactions—Separate Control Bus Not Required
S HDCP Keys Preprogrammed in Secure Nonvolatile
Memory
S 2.5Gbps Payload Data Rate (3.125Gbps with
Overhead)
S AC-Coupled Serial Link with 8b/10b Line Coding
S 8.33MHz to 104MHz (24-Bit Mode) or 6.25MHz to
78MHz (32-Bit Mode) Pixel Clock
S 4-Bit to 32-Bit Word Length, 8kHz to 192kHz I2S
Audio Channel Supports High-Definition Audio
S Embedded Half-/Full-Duplex Bidirectional Control
Channel
Base Mode: 9.6kbps to 1Mbps
Bypass Mode: 9.6kbps to 1Mbps
S Interrupt Supports Touch-Screen Displays
S Remote-End I2C Master for Peripherals
S Programmable Pre/Deemphasis and Channel
Equalizer for 15m Cable Drive at 3.125Gbps
S Programmable Spread Spectrum on Serial or
Parallel Output Reduces EMI
S Deserializer Serial-Data Clock Recovery
Eliminates External Reference Clock
S Auto Data-Rate Detection Allows On-The-Fly
Data-Rate Change
S Bypassable PLL on Serializer Pixel Clock Input for
Jitter Attenuation
S Built-In PRBS Generator/Checker for BER Testing
of the Serial Link
S Fault Detection of Serial Link Shorted Together, to
Ground, to Battery, or Open
S ISO 10605 and IEC 61000-4-2 ESD Tolerance
Ordering Information
/V denotes an automotive qualified product.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
Blu-ray is a trademark of Blu-ray Disc Association.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX9263GCB/V+ -40NC to +105NC64 TQFP-EP*
MAX9263GCB/V+T -40NC to +105NC64 TQFP-EP*
MAX9264GCB/V+ -40NC to +105NC64 TQFP-EP*
MAX9264GCB/V+T -40NC to +105NC64 TQFP-EP*
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
2
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND
MAX9263 ............................................................ -0.5V to +1.9V
MAX9264 ............................................................ -0.5V to +3.9V
DVDD to GND (MAX9263) ...................................-0.5V to +1.9V
DVDD to DGND (MAX9264) .................................-0.5V to +3.9V
IOVDD to GND (MAX9263) ..................................-0.5V to +3.9V
IOVDD to IOGND (MAX9264) ..............................-0.5V to +3.9V
Any Ground to Any Ground .................................-0.5V to +0.5V
OUT+, OUT- to AGND (MAX9263) ......................-0.5V to +1.9V
IN+, IN- to AGND (MAX9264) ..............................-0.5V to +1.9V
LMN_ to AGND (MAX9263)
(15mA current limit) ..........................................-0.5V to +3.9V
All Other Pins to GND (MAX9263) ...... -0.5V to (VIOVDD + 0.5V)
All Other Pins to IOGND (MAX9264) ... -0.5V to (VIOVDD + 0.5V)
Continuous Power Dissipation (TA = +70NC )
64-Pin TQFP (derate 31.3mW/NC above +70NC) .....2507.8mW
Operating Temperature Range ........................ -40NC to +105NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
PACKAGE THERMAL CHARACTERISTICS (Note 1)
64 TQFP-EP
Junction-to-Ambient Thermal Resistance (BJA) ...........39.1NC/W
Junction-to-Case Thermal Resistance (BJC) .....................1NC/W
ABSOLUTE MAXIMUM RATINGS
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
MAX9263 DC ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS (DIN_, PCLKIN, SD, SCK, WS, AUTOS, MS, CDS, PWDN, SSEN, DRS, ES, BWS)
High-Level Input Voltage VIH1
DIN_, PCLKIN, AUTOS, MS, CDS, SSEN,
DRS, ES, BWS
0.65 x
VIOVDD V
SD, SCK, WS 0.7 x
VIOVDD
Low-Level Input Voltage VIL1 0.35 x
VIOVDD V
Input Current IIN1 VIN = 0 to VIOVDD -10 +10 FA
Input Clamp Voltage VCL ICL = -18mA -1.5 V
SINGLE-ENDED OUTPUT (INT)
High-Level Output Voltage VOH1 IOUT = -2mA VIOVDD
- 0.2 V
Low-Level Output Voltage VOL1 IOUT = 2mA 0.2 V
OUTPUT Short-Circuit Current IOS VO = VGND
VIOVDD = 3.0V to 3.6V 16 35 64 mA
VIOVDD = 1.7V to 1.9V 3 12 21
I2C/UART, I/O, AND OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, LFLT)
High-Level Input Voltage VIH2 0.7 x
VIOVDD V
Low-Level Input Voltage VIL2 0.3 x
VIOVDD V
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
3
MAX9263 DC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Current IIN2 VIN = 0 to VIOVDD (Note 2) -110 +5 FA
Low-Level Output Voltage VOL2 IOUT = 3mA VIOVDD = 1.7V to 1.9V 0.4 V
VIOVDD = 3.0V to 3.6V 0.3
DIFFERENTIAL OUTPUT (OUT+, OUT-)
Differential Output Voltage VOD
Preemphasis off (Figure 1) 300 400 500
mV3.3dB preemphasis setting (Figure 2) 350 610
3.3dB deemphasis setting (Figure 2) 240 425
Change in VOD Between
Complementary Output States DVOD 15 mV
Output Offset Voltage (VOUT+ +
VOUT-)/2 = VOS VOS Preemphasis off 1.1 1.4 1.56 V
Change in VOS Between
Complementary Output States DVOS 15 mV
Output Short-Circuit Current IOS
VOUT+ or VOUT- = 0V -60 mA
VOUT+ or VOUT- = 1.9V 25
Magnitude of Differential Output
Short-Circuit Current IOSD VOD = 0V 25 mA
Output Termination Resistance
(Internal) ROFrom OUT+, OUT- to VAVDD 45 54 63 I
REVERSE CONTROL-CHANNEL RECEIVER (OUT+, OUT-)
High Switching Threshold VCHR 27 mV
Low Switching Threshold VCLR -27 mV
LINE-FAULT-DETECTION INPUTS (LMN_)
Short-to-GND Threshold VTG Figure 3 0.3 V
Normal Thresholds VTN Figure 3 0.57 1.07 V
Open Thresholds VTO Figure 3 1.45 VIO +
60mV V
Open Input Voltage VIO Figure 3 1.47 1.75 V
Short-to-Battery Threshold VTE Figure 3 2.47 V
POWER SUPPLY
Worst-Case Supply Current
(Figure 4, Note 3) IWCS BWS = GND
fPCLKIN = 16.6MHz 105 132
mA
fPCLKIN = 33.3MHz 110 152
fPCLKIN = 66.6MHz 120 160
fPCLKIN = 104MHz 145 188
Sleep Mode Supply Current ICCS 45 225 FA
Power-Down Supply Current ICCZ PWDN = GND 7 180 FA
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
4
MAX9263 AC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.)
MAX9263 DC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLOCK INPUT TIMING (PCLKIN)
Clock Frequency fPCLKIN
BWS = GND, VDRS = VIOVDD 8.33 16.66
MHz
BWS = GND, DRS = GND 16.66 104
VBWS = VIOVDD, VDRS = VIOVDD 6.25 12.5
VBWS = VIOVDD, DRS = GND 12.5 78
Clock Duty Cycle DC tHIGH/tT or tLOW/tT (Figure 5, Note 6) 35 50 65 %
Clock Transition Time tR, tF(Figure 5, Note 6) 4 ns
Clock Jitter tJ3.125Gbps, 300kHz sinusoidal jitter (Note 6) 800 ps(P-P)
I2C/UART PORT TIMING
I2C/UART Bit Rate 9.6 1000 kbps
Output Rise Time tR30% to 70%, CL = 10pF to 100pF,
1kI pullup to VIOVDD 20 150 ns
Output Fall Time tF70% to 30%, CL = 10pF to 100pF,
1kI pullup to VIOVDD 20 150 ns
Input Setup Time tSET I2C only (Figure 6, Note 6) 100 ns
Input Hold Time tHOLD I2C only (Figure 6, Note 6) 0 ns
SWITCHING CHARACTERISTICS
Differential Output Rise/Fall Time tR, tF20% to 80%, VOD ≥ 400mV, RL = 100I,
serial-bit rate = 3.125Gbps (Note 6) 90 150 ps
Total Serial Output Jitter tTSOJ1
3.125Gbps PRBS signal, measured at
VOD = 0V differential, preemphasis
disabled (Figure 7)
0.25 UI
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ESD PROTECTION
OUT+, OUT- VESD
Human Body Model, RD = 1.5kI,
CS = 100pF (Note 4) Q8
kV
IEC 61000-4-2,
RD = 330I,
CS = 150pF (Note 5)
Contact discharge Q10
Air discharge Q12
ISO 10605,
RD = 2kI,
CS = 330pF (Note 5)
Contact discharge Q10
Air discharge Q25
All Other Pins VESD Human Body Model, RD = 1.5kI,
CS = 100pF (Note 4) Q4kV
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
5
MAX9263 AC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.)
MAX9264 DC ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Deterministic Serial Output Jitter tDSOJ2 3.125Gbps PRBS signal 0.15 UI
Parallel Data Input Setup Time tSET (Figure 8, Note 6) 1 ns
Parallel Data Input Hold Time tHOLD (Figure 8, Note 6) 1.5 ns
Serializer Delay (Notes 6, 7)
(Figure 1) tSD (Figure 9) Spread spectrum enabled 2830 Bits
Spread spectrum disabled 270
Link Start Time tLOCK (Figure 10) 3.5 ms
Power-Up Time tPU (Figure 11) 6 ms
I2S INPUT TIMING
WS Frequency fWS See Table 4 8 192 kHz
Sample Word Length nWS See Table 4 4 32 bits
SCK Frequency fSCK fSCK = fWS x nWS x 2 (8 x
4) x 2
(192 x
32) x 2 kHz
SCK Clock High Time tHC VSCK R VIH, tSCK = 1/fSCK 0.35 x
tSCK ns
SCK Clock Low Time tLC VSCK P VIL, tSCK = 1/fSCK 0.35 x
tSCK ns
SD, WS Setup Time tSET (Figure 12) 2 ns
SD, WS Hold Time tHOLD (Figure 12) 2 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS (ENABLE, BWS, INT, CDS, ES, EQS, DCS, MS, PWDN, SSEN, DRS)
High-Level Input Voltage VIH1 0.65 x
VIOVDD V
Low-Level Input Voltage VIL1 0.35 x
VIOVDD V
Input Current IIN1 VIN = 0 to VIOVDD -10 +10 FA
Input Clamp Voltage VCL ICL = -18mA -1.5 V
SINGLE-ENDED OUTPUTS (WS, SCK, SD, DOUT_, PCLKOUT)
High-Level Output Voltage VOH1 IOUT = -2mA
DCS = IOGND VIOVDD
- 0.3 V
VDCS = VIOVDD VIOVDD
- 0.2
Low-Level Output Voltage VOL1 IOUT = 2mA DCS = IOGND 0.3 V
VDCS = VIOVDD 0.2
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
6
MAX9264 DC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OUTPUT Short-Circuit Current IOS
WS, SCK,
SD, DOUT_
VO = 0V,
DCS =
IOGND
VIOVDD =
3.0V to 3.6V 14 25 39
mA
VIOVDD =
1.7V to 1.9V 3 7 13
VO = 0V,
VDCS =
VIOVDD
VIOVDD =
3.0V to 3.6V 20 35 63
VIOVDD =
1.7V to 1.9V 5 10 21
PCLKOUT
VO = 0V,
DCS =
IOGND
VIOVDD =
3.0V to 3.6V 15 33 50
VIOVDD =
1.7V to 1.9V 4 10 17
VO = 0V,
VDCS =
VIOVDD
VIOVDD =
3.0V to 3.6V 30 54 97
VIOVDD =
1.7V to 1.9V 9 16 32
I2C/UART, I/O, AND OPEN-DRAIN OUTPUTS (GPIO_, RX/SDA, TX/SCL, ERR, LOCK)
High-Level Input Voltage VIH2 0.7 x
VIOVDD V
Low-Level Input Voltage VIL2 0.3 x
VIOVDD V
Input Current IIN2 VIN = 0 to
VIOVDD (Note 2)
RX/SDA, TX/SCL -100 +1 FA
LOCK, ERR, GPIO_ -80 +1
Low-Level Output Voltage VOL2 IOUT = 3mA VIOVDD = 1.7V to 1.9V 0.4 V
VIOVDD = 3.0V to 3.6V 0.3
DIFFERENTIAL OUTPUT FOR REVERSE CONTROL CHANNEL (IN+, IN-)
Differential High Output Peak
Voltage, (VIN+) - (VIN-) VROH No high-speed data transmission
(Figure 13) 30 60 mV
Differential Low Output Peak
Voltage, (VIN+) - (VIN-) VROL No high-speed data transmission
(Figure 13) -60 -30 mV
DIFFERENTIAL INPUTS (IN+, IN-)
Differential High Input Threshold
(Peak) Voltage, (VIN+) - (VIN-) VIDH(P) Figure 14 40 90 mV
Differential Low Input Threshold
(Peak) Voltage, (VIN+) - (VIN-) VIDL(P) Figure 14 -90 -40 mV
Input Common-Mode Voltage
((VIN+) + (VIN-))/2 VCMR 1 1.3 1.6 V
Differential Input Resistance
(Internal) RI80 100 130 I
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
7
MAX9264 DC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
Worst-Case Supply Current
(Figure 15, Note 3)IWCS
BWS = IOGND,
fPCLKOUT = 16.6MHz
2% spread
spectrum active 132 186
mA
Spread spectrum
disabled 125 175
BWS = IOGND,
fPCLKOUT = 33.3MHz
2% spread
spectrum active 145 204
Spread spectrum
disabled 133 188
BWS = IOGND,
fPCLKOUT = 66.6MHz
2% spread
spectrum active 174 241
Spread spectrum
disabled 157 220
BWS = IOGND,
fPCLKOUT = 104MHz
2% spread
spectrum active 210 275
Spread spectrum
disabled 186 242
Sleep Mode Supply Current ICCS 80 230 FA
Power-Down Current ICCZ PWDN = IOGND 25 156 FA
ESD PROTECTION
IN+, IN- VESD
Human Body Model, RD = 1.5kI,
CS = 100pF (Note 4) Q8
kV
IEC 61000-4-2,
RD = 330I,
CS = 150pF (Note 5)
Contact discharge Q10
Air discharge Q12
ISO 10605,
RD = 2kI,
CS = 330pF (Note 5)
Contact discharge Q8
Air discharge Q20
All Other Pins VESD Human Body Model, RD = 1.5kI,
CS = 100pF (Note 4) Q4kV
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
8
MAX9264 AC ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PARALLEL CLOCK OUTPUT (PCLKOUT)
Clock Frequency fPCLKOUT
BWS = IOGND, VDRS = VIOVDD 8.33 16.66
MHz
BWS = IOGND, DRS = IOGND 16.66 104
VBWS = VIOVDD, VDRS = VIOVDD 6.25 12.5
VBWS = VIOVDD, DRS = IOGND 12.5 78
Clock Duty Cycle DC tHIGH/tT or tLOW/tT (Figure 16, Note 6) 40 50 60 %
Clock Jitter tJPeriod jitter, RMS, spread off, 3.125Gbps,
PRBS pattern, UI = 1/fPCLKOUT (Note 6) 0.05 UI
I2C/UART PORT TIMING
I2C/UART Bit Rate 9.6 1000 kbps
Output Rise Time tR30% to 70%, CL = 10pF to 100pF,
1kI pullup to VIOVDD 20 150 ns
Output Fall Time tF70% to 30%, CL = 10pF to 100pF,
1kI pullup to VIOVDD 20 150 ns
Input Setup Time tSET I2C only (Figure 6, Note 6) 100 ns
Input Hold Time tHOLD I2C only (Figure 6, Note 6) 0 ns
SWITCHING CHARACTERISTICS (NOTE 6)
PCLKOUT Rise-and-Fall Time tR, tF
20% to 80%,
VIOVDD = 1.7V to 1.9V
VDCS = VIOVDD,
CL = 10pf 0.4 2.2
ns
DCS = IOGND,
CL = 5pF 0.5 2.8
20% to 80%,
VIOVDD = 3.0V to 3.6V
VDCS = VIOVDD,
CL = 10pF 0.25 1.7
DCS = IOGND,
CL = 5pF 0.3 2.0
Parallel Data Rise-and-Fall Time
(Figure 17) tR, tF
20% to 80%,
VIOVDD = 1.7V to 1.9V
VDCS = VIOVDD,
CL = 10pf 0.5 3.1
ns
DCS = IOGND,
CL = 5pF 0.6 3.8
20% to 80%,
VIOVDD = 3.0V to 3.6V
VDCS = VIOVDD,
CL = 10pF 0.3 2.2
DCS = IOGND,
CL = 5pF 0.4 2.4
Deserializer Delay tSD (Figure 18, Note 7)
Spread spectrum
enabled 2880
Bits
Spread spectrum
disabled 750
Reverse Control-Channel Output
Rise Time tRNo forward channel data transmission
(Figure 13) 180 400 ns
Reverse Control-Channel Output
Fall Time tFNo forward channel data transmission
(Figure 13) 180 400 ns
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
9
MAX9264 AC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.)
Note 2: Minimum IIN due to voltage drop across the internal pullup resistor.
Note 3: HDCP enabled.
Note 4: Tested terminal to all grounds.
Note 5: Tested terminal to AGND.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured in CML bit times. Bit time = 1/(30 x fPCLKOUT) for BWS = GND. Bit time = 1/(40 x fPCLKOUT) for VBWS = VIOVDD.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Lock Time tLOCK Figure 19
Spread spectrum
enabled 1.5
ms
Spread spectrum
disabled 1
Power-Up Time tPU Figure 20 2.5 ms
I2S OUTPUT TIMING (NOTE 6)
WS Jitter tAJ-WS
tWS = 1/fWS, rising
(falling) edge to
falling (rising) edge
fWS = 48kHz or
44.1kHz
0.4e - 3
x tWS
0.5e - 3
x tWS
ns
fWS = 96kHz 0.8e - 3
x tWS
1e - 3
x tWS
fWS = 192kHz 1.6e - 3
x tWS
2e - 3
x tWS
SCK Jitter tAJ-SCK tSCK = 1/fSCK, rising
edge to rising edge
nWS = 16 bits,
fWS = 48kHz or
44.1kHz
13e - 3
x tSCK
16e - 3
x tSCK
ns
nWS = 24 bits,
fWS = 96kHz
39e - 3
x tSCK
48e - 3
x tSCK
nWS = 32 bits,
fWS = 192kHz
0.1
x tSCK
0.13
x tSCK
Audio Skew Relative to Video tASK Video and audio synchronized 3 x tWS 4 x tWS Fs
SCK, SD, WS Rise-and-Fall Time tR, tF20% to 80%,
CL = 10pF
VDCS = VIOVDD,
CL = 10pF 0.3 3.1
ns
DCS = IOGND,
CL = 5pF 0.4 3.8
SD, WS Valid Time Before SCK tDVB tSCK = 1/fSCK (Figure 21) 0.35
x tSCK
0.5
x tSCK ns
SD, WS Valid Time After SCK tDVA tSCK = 1/fSCK (Figure 21) 0.35
x tSCK
0.5
x tSCK ns
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
10
Typical Operating Characteristics
(VAVDD = VDVDD = VIOVDD = 1.8V (MAX9263), VAVDD = VDVDD = VIOVDD = 3.3V (MAX9264), TA = +25NC, unless otherwise noted.)
MAX9263 SUPPLY CURRENT
vs. PCLK FREQUENCY (24-BIT MODE)
MAX9263 toc01
PCLK FREQUENCY (MHz)
SUPPLY CURRENT (mA)
85654525
110
120
130
140
150
160
100
5 105
PRBS ON, HDCP ON
PREEMPHASIS = 0x00
PREEMPHASIS = 0x0B TO 0x0F
PREEMPHASIS = 0x01 TO 0x04
MAX9264 SUPPLY CURRENT
vs. PCLK FREQUENCY (24-BIT MODE)
MAX9263 toc03
PCLK FREQUENCY (MHz)
SUPPLY CURRENT (mA)
85654525
120
130
140
150
160
170
110
5 105
PRBS ON, HDCP ON, SS OFF
ALL EQ SETTINGS
MAX9264 SUPPLY CURRENT
vs. PCLK FREQUENCY (24-BIT MODE)
MAX9263 toc05
SUPPLY CURRENT (mA)
120
130
140
150
160
170
180
190
200
110
PCLK FREQUENCY (MHz)
856545255 105
PRBS ON, HDCP ON
0% SPREAD
2%, 4% SPREAD
MAX9263 SUPPLY CURRENT
vs. PCLK FREQUENCY (32-BIT MODE)
MAX9263 toc02
PCLK FREQUENCY (MHz)
SUPPLY CURRENT (mA)
65503520
110
120
130
140
150
100
58
0
PRBS ON, HDCP ON
PREEMPHASIS = 0x0B TO 0x0F
PREEMPHASIS = 0x01 TO 0x04
PREEMPHASIS = 0x00
MAX9264 SUPPLY CURRENT
vs. PCLK FREQUENCY (32-BIT MODE)
MAX9263 toc04
PCLK FREQUENCY (MHz)
SUPPLY CURRENT (mA)
65503520
120
130
140
150
160
110
58
0
PRBS ON, HDCP ON, SS OFF
ALL EQ SETTINGS
MAX9264 SUPPLY CURRENT
vs. PCLK FREQUENCY (32-BIT MODE)
PCLK FREQUENCY (MHz)
SUPPLY CURRENT (mA)
655020 35
120
130
140
150
170
160
180
190
110
58
0
MAX9263 toc06
PRBS ON, HDCP ON
0% SPREAD
2%, 4% SPREAD
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
11
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = VIOVDD = 1.8V (MAX9263), VAVDD = VDVDD = VIOVDD = 3.3V (MAX9264), TA = +25NC, unless otherwise noted.)
OUTPUT POWER SPECTRUM vs. PCLK
FREQUENCY (VARIOUS MAX9263 SPREAD)
MAX9263 toc07
PCLK FREQUENCY (MHz)
OUTPUT POWER SPECTRUM (dBm)
3534333231
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
30 36
2% SPREAD
0% SPREAD 0.5% SPREAD
4% SPREAD
fPCLK = 33MHz
OUTPUT POWER SPECTRUM vs. PCLK
FREQUENCY (VARIOUS MAX9263 SPREAD)
MAX9263 toc09
PCLK FREQUENCY (MHz)
OUTPUT POWER SPECTRUM (dBm)
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
61 71
69676563
0% SPREAD
fPCLK = 66MHz
4% SPREAD
0.5% SPREAD
2% SPREAD
MAXIMUM PCLK FREQUENCY
vs. STP CABLE LENGTH (BER < 10-9)
MAX9263 toc11
STP CABLE LENGTH (m)
MAXIMUM PCLK FREQUENCY (MHz)
15105
20
40
60
80
100
120
0
02
0
OPTIMUM
PE/EQ SETTINGS
NO PE, 10.7dB
EQUALIZATION
NO PE, 5.2dB
EQUALIZATION
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 10m
OUTPUT POWER SPECTRUM vs. PCLK
FREQUENCY (VARIOUS MAX9264 SPREAD)
MAX9263 toc08
PCLK FREQUENCY (MHz)
OUTPUT POWER SPECTRUM (dBm)
3534333231
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
30 36
2% SPREAD
0% SPREAD
4% SPREAD
fPCLK = 33MHz
OUTPUT POWER SPECTRUM vs. PCLK
FREQUENCY (VARIOUS MAX9264 SPREAD)
MAX9263 toc10
PCLK FREQUENCY (MHz)
OUTPUT POWER SPECTRUM (dBm)
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
61 71
69676563
0% SPREAD
fPCLK = 66MHz
4%
SPREAD
2% SPREAD
MAXIMUM PCLK FREQUENCY vs.
ADDITIONAL DIFFERENTIAL CL (BER < 10-9)
MAX9263 toc12
ADDITIONAL DIFFERENTIAL LOAD CAPACITANCE (pF)
8642
01
0
MAXIMUM PCLK FREQUENCY (MHz)
20
40
60
80
100
120
0
10m STP CABLE
OPTIMUM
PE/EQ SETTINGS
NO PE, 10.7dB
EQUALIZATION
NO PE, 5.2dB EQUALIZATION
BER CAN BE AS LOW AS 10-12 FOR CL < 4pF
FOR OPTIMUM PE/EQ SETTINGS
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
12
Pin Configurations
4243444546 3839404147
22
23
24
25
26
27
28
29
30
31
DIN8
DIN14
ES
TQFP
TOP VIEW
DRS
INT
LMN0
AVDD
OUT+
OUT-
AGND
LMN1
3637 333435
SSEN
TX/SCL
RX/SDA
CDS
DIN13
DIN16
DIN15
IOVDD
PCLKIN
AGND
GND
DIN17
AVDD
DIN19/VS
DIN18/HS
DIN21
DIN20
DIN22
GND
IOVDD
WS
SCK
SD
DIN28
DIN27
DIN26
DIN25
17
18
19
20
21 DIN24
GND
DVDD
AGND
DIN23
DIN7
DIN6
DIN5
DIN4
DIN3
DIN11
*CONNECT EXPOSED PAD TO AGND
DIN10
DVDD
GND
DIN9
DIN2
DIN1
IOVDD
GND
32 MSDIN0
48
BWS
DIN12
7654311109821312 1615141
59
58
57
56
55
54
53
52
51
50
64
63
62
61
60
49
MAX9263
LFLT
AUTOS
PWDN
EP*
+
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
13
Pin Configurations (continued)
4243444546 3839404147
22
23
24
25
26
27
28
29
30
31
DOUT0
INT
TQFP
TOP VIEW
3637 333435
BWS
GPIO0
CDS
AVDD
ES
IN-
IN+
EQS
AGND
DCS
GPIO1
DVDD
MS
DGND
IOGND
IOVDD
DOUT26
DOUT27
DOUT28/MCLK
SD
SCK
WS
LOCK
17
18
19
20
21 IOGND
TX/SCL
RX/SDA
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
AGND
*CONNECT EXPOSED PAD TO AGND
AVDD
DRS
SSEN
IOGND
DOUT6
DOUT7
IOVDD
IOGND
32 DOUT24DOUT8
48
DOUT9
DOUT10
DOUT11
DOUT12
DOUT13
DOUT14
DOUT15
PCLKOUT
DOUT16
DOUT17
DOUT18/HS
DOUT19/VS
DOUT20
DOUT21
DOUT22
DOUT23
7654311109821312 1615141
59
58
57
56
55
54
53
52
51
50
64
63
62
61
60
49
MAX9264
DOUT25
ERR
PWDN
ENABLE
+
EP*
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
14
MAX9263 Pin Description
PIN NAME FUNCTION
1–5 DIN[12:16] Data Input [12:16]. Parallel data inputs with internal pulldown to GND. Encrypted when HDCP
is enabled (see Table 3).
6 PCLKIN Parallel Clock Input. Latches parallel data inputs and provides the PLL reference clock.
7, 30, 51 IOVDD
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with 0.1FF
and 0.001FF capacitors as close as possible to the device with the smaller capacitor closest
to IOVDD.
8, 20, 31, 50,
61 GND Digital and I/O Ground
9, 18, 39 AGND Analog Ground
10, 42 AVDD 1.8V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller capacitor closest to AVDD.
11 DIN17 Data Input 17. Parallel data input with internal pulldown to GND. Encrypted when HDCP is
enabled (see Table 3).
12 DIN18/HS Data Input 18/HSYNC. Parallel data input with internal pulldown to GND. Use DIN18/HS for
HSYNC when HDCP is enabled (Table 3).
13 DIN19/VS Data Input 19/VSYNC. Parallel data input with internal pulldown to GND. Use DIN19/VS for
VSYNC when HDCP is enabled (Table 3).
14 DIN20 Data Input 20. Parallel data input with internal pulldown to GND. DIN20 is not encrypted when
HDCP is enabled (see Table 3).
15, 16, 17 DIN[21:23]
Data Input [21:23]. Parallel data inputs with internal pulldown to GND. DIN[21:23] are not
used in 24-bit mode. Set BWS = high (32-bit mode) to use [DIN21:23]. Encrypted when
HDCP is enabled (Table 3).
19, 62 DVDD 1.8V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as close
as possible to the device with the smaller capacitor closest to DVDD.
21, 22, 23 DIN[24:26]
Data Input [24:26]. Parallel data inputs with internal pulldown to GND. DIN[24:26] are not
used in 24-bit mode. Set BWS = high (32-bit mode) to use [DIN24:26]. Encrypted when
HDCP is enabled (see Table 3).
24, 25 DIN[27:28]
Data Input [27:28]. Parallel data inputs with internal pulldown to GND. DIN[27:28] are not
used in 24-bit mode. Set BWS = high (32-bit mode) to use [DIN27:28]. DIN[27:28] are not
encrypted when HDCP is enabled (see Table 3).
26 SD I2S Serial-Data Input with Internal Pulldown to GND. Disable I2S to use SD as an additional
control/data input latched on the selected edge of PCLKIN. Encrypted when HDCP is enabled.
27 SCK I2S Serial-Clock Input with Internal Pulldown to GND
28 WS I2S Word-Select Input with Internal Pulldown to GND
29 AUTOS
Active-Low Autostart Setting. AUTOS requires an external pulldown or pullup resistor. Set
AUTOS = high to power up the device with no link active. Set AUTOS = low to have the
serializer power up the serial link with autorange detection (see Tables 13 and 14).
32 MS Mode Select. Control link mode-selection input requires an external pulldown or pullup
resistor. Set MS = low to select base mode. Set MS = high to select the bypass mode.
33 CDS
Control Direction Selection. Control link direct selection input requires external pulldown or
pullup resistor. Set CDS = low for UART connection of a FC as a control master. Set CDS =
high for peripheral connection as a control-channel I2C or UART slave.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
15
MAX9263 Pin Description (continued)
PIN NAME FUNCTION
34 PWDN Active-Low, Power-Down Input. PWDN requires external pulldown or pullup resistor.
35 RX/SDA
Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI pullup to
IOVDD. In UART mode, RX/SDA is the Rx input of the serializer’s UART. In I2C mode,
RX/SDA is the SDA input/output of the serializer’s I2C master. RX/SDA has an open-drain
driver and requires a pullup resistor.
36 TX/SCL
Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI pullup to
IOVDD. In UART mode, TX/SCL is the Tx output of the serializer’s UART. In I2C mode,
TX/SCL is the SCL output of the serializer’s I2C master. TX/SCL is an open-drain driver and
requires a pullup resistor.
37 SSEN
Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external
pulldown or pullup resistor. The state of SSEN latches upon power-up or when resuming from
power-down mode (PWDN = low). Set SSEN = high for Q0.5% spread spectrum on the serial
link. Set SSEN = low to use the serial link without spread spectrum.
38 LMN1 Line-Fault Monitor Input 1. See Figure 3 for details.
40, 41 OUT-, OUT+ Differential CML Output Q. Differential outputs of the serial link.
43 LMN0 Line-Fault Monitor Input 0. See Figure 3 for details.
44 LFLT Line Fault, Active-Low Open-Drain Line-Fault Output. LFLT has a 60kI internal pullup
resistor. LFLT = low indicates a line fault. LFLT is high impedance when PWDN = low.
45 INT Interrupt Output. Indicates remote-side interrupt requests. INT = low upon power-up and when
PWDN = low. A transition on the INT input of the deserializer toggles the serializer’s INT output.
46 DRS
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup
resistor. The state of DRS latches upon power-up or when resuming from power-down mode
(PWDN = low). Set DRS = high for PCLKIN frequencies of 8.33MHz to 16.66MHz
(24-bit mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for PCLKIN frequencies
of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).
47 ES
Edge Select. PCLKIN trigger edge selection requires external pulldown or pullup resistor. Set
ES = low to trigger on the rising edge of PCLKIN. Set ES = high to trigger on the falling edge
of PCLKIN.
48 BWS Bus-Width Select. BWS requires external pulldown or pullup resistor. Set BWS = low for 24-bit
mode. Set BWS = high for 32-bit mode.
49 DIN0 Data Input 0. Parallel data input with internal pulldown to GND. Encrypted when HDCP is
enabled (Table 3).
52–60 DIN[1:9] Data Input [1:9]. Parallel data inputs with internal pulldown to GND. Encrypted when HDCP is
enabled (Table 3).
63, 64 DIN[10:11] Data Input [10:11]. Parallel data inputs with internal pulldown to GND. Encrypted when HDCP
is enabled (Table 3).
— EP Exposed Pad. EP is internally connected to AGND. MUST externally connect EP to the AGND
plane for proper thermal and electrical performance.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
16
MAX9264 Pin Description
PIN NAME FUNCTION
1ENABLE
Active-Low Parallel Output-Enable Input. Requires an external pulldown or pullup resistor. Set
ENABLE = low to enable PCLKOUT, SD, SCK, WS, and DOUT_. Set ENABLE = high to put
PCLKOUT, SD, SCK, WS, and DOUT_ into high impedance.
2 BWS Bus-Width Select. BWS requires an external pulldown or pullup resistor. Set BWS = low for
24-bit mode. Set BWS = high for 32-bit mode.
3 INT Interrupt Input. INT requires an external pullup or pulldown resistor. A transition on the
deserializer’s INT input toggles the serializer’s INT output.
4 CDS
Control Direction Selection. Control link direction selection input requires external pulldown or
pullup resistor. Set CDS = high for UART connection of a FC as control-channel master. Set
CDS = low for peripheral connection as a control-channel I2C or UART slave.
5 GPIO0 GPIO0. Open-drain general-purpose input/output with an internal 60kI pullup resistor to
IOVDD. GPIO0 is high impedance during power-up and when PWDN = low.
6 ES Edge Select. PCLKOUT edge-selection input requires an external pulldown or pullup resistor.
Set ES = low for a rising-edge trigger. Set ES = high for a falling-edge trigger.
7, 63 AVDD 3.3V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller capacitor closest to AVDD.
8, 9 IN+, IN- Differential CML Input Q. Differential inputs of the serial link.
10, 64 AGND Analog Ground
11 EQS
Equalizer Select Input Requires an External Pulldown or Pullup Resistor. The state of EQS
latches upon power-up or when resuming from power-down mode (PWDN = low). Set EQS =
low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB equalizer boost
(EQTUNE = 0100).
12 GPIO1 GPIO1. Open-drain general-purpose input/output with an internal 60kI pullup resistor to
IOVDD. GPIO1 is high impedance during power-up and when PWDN = low.
13 DCS
Drive Current Select. Driver current-selection input requires an external pulldown or
pullup resistor to IOVDD. Set DCS = high for stronger parallel data and clock output drivers.
Set DCS = low for normal parallel data and clock drivers. See the MAX9264 DC Electrical
Characteristics table.
14 MS
Mode Select. Control-channel mode selection input requires an external pulldown or
pullup resistor. MS sets the control-link mode when CDS = high. See the Control-Channel and
Register Programming section. MS sets autostart mode when CDS = low. See Table 13.
15 DVDD 3.3V Digital Power Supply. Bypass DVDD to DGND with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller capacitor closest to DVDD.
16 DGND Digital Ground
17 RX/SDA
Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI pullup to
IOVDD. In UART mode, RX/SDA is the Rx input of the deserializer’s UART. In I2C mode,
RX/SDA is the SDA input/output of the deserializer’s I2C master. RX/SDA has an open-drain
driver and requires a pullup resistor.
18 TX/SCL
Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI pullup to
IOVDD. In UART mode, TX/SCL is the Tx output of the deserializer’s UART. In I2C mode,
TX/SCL is the SCL output of the deserializer’s I2C master. TX/SCL is an open-drain driver and
requires a pullup resistor.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
17
MAX9264 Pin Description (continued)
PIN NAME FUNCTION
19 PWDN Active-Low, Power-Down Input. PWDN requires an external pulldown or pullup resistor.
20 ERR
Active-Low Open-Drain Video Data Error Output with Internal 60kI Pullup to IOVDD. ERR goes
low when the number of decoding errors during normal operation exceed a programmed error
threshold or when at least one PRBS error is detected during PRBS test. ERR is high
impedance when PWDN = low. ERR is an open-drain driver and requires a pullup resistor.
21, 31, 50, 60 IOGND Input/Output Ground
22 LOCK
Open-Drain Lock Output with Internal 60kI Pullup to IOVDD. LOCK = high indicates PLLs
are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs are not
locked or incorrect serial-word-boundary alignment. LOCK remains low when the
configuration link is active. LOCK is high impedance when PWDN = low. LOCK is an
open-drain driver and requires a pullup resistor.
23 WS I2S Word-Select Output
24 SCK I2S Serial-Clock Output
25 SD I2S Serial-Data Output. Disable I2S to use SD as an additional control output latched on the
selected edge of PCLKOUT. Encrypted when HDCP is enabled.
26 DOUT28/
MCLK
Data Output 28/MCLK. Parallel data or master clock output. Output data can be strobed on
the selected edge of PCLKOUT. DOUT28 is not used in 24-bit mode and remains low. Set
BWS = high (32-bit mode) to use DOUT28. DOUT28/MCLK is not encrypted when HDCP is
enabled (Table 3). DOUT28/MCLK can be used to output MCLK. See the Additional MCLK
Output for Audio Applications section.
27 DOUT27
Data Output 27. Parallel data output. Output data can be strobed on the selected edge of
PCLKOUT. DOUT27 is not used in 24-bit mode and remains low. Set BWS = high (32-bit
mode) to use DOUT27. DOUT27 is not encrypted when HDCP is enabled. See Table 3.
28, 29 DOUT[26:25]
Data Output [26:25]. Parallel data outputs. Output data can be strobed on the selected edge
of PCLKOUT. DOUT[26:25] are not used in 24-bit mode and remain output low. Set BWS =
high (32-bit mode) to use DOUT[26:25]. Encrypted when HDCP is enabled. See Table 3.
30, 51 IOVDD
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to IOGND with 0.1FF
and 0.001FF capacitors as close as possible to the device with the smaller capacitor closest
to IOVDD.
32–35 DOUT[24:21]
Data Output [24:21]. Parallel data outputs. Output data can be strobed on the selected edge
of PCLKOUT. DOUT[24:21] are not used in 24-bit mode and remain low. Set BWS = high
(32-bit mode) to use DOUT[24:21]. Encrypted when HDCP is enabled. See Table 3.
36 DOUT20 Data Output 20. Parallel data output. Output data can be strobed on the selected edge of
PCLKOUT. DOUT20 is not encrypted when HDCP is enabled. See Table 3.
37 DOUT19/VS Data Output 19/VSYNC. Parallel data output. Output data can be strobed on the selected
edge of PCLKOUT. Use DOUT19/VS for VSYNC when HDCP is enabled. See Table 3.
38 DOUT18/HS Data Output 18/HSYNC. Parallel data output. Output data can be strobed on the selected
edge of PCLKOUT. Use DOUT18/HS for HSYNC when HDCP is enabled. See Table 3.
39, 40 DOUT[17:16] Data Output [17:16]. Parallel data outputs. Output data can be strobed on the selected edge
of PCLKOUT. Encrypted when HDCP is enabled. See Table 3.
41 PCLKOUT Parallel Clock Output. Used for DOUT[28:0].
42–49 DOUT[15:8] Data Output [15:8]. Parallel data outputs. Output data can be strobed on the selected edge
of PCLKOUT. Encrypted when HDCP is enabled. See Table 3.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
18
MAX9264 Pin Description (continued)
Functional Diagrams
RGB[17:0] RGB
HS
PCLKIN
DIN[17:0]
DIN[26:21]
(4-CH)
DIN[28:27]
(4-CH)
DIN18/HS
DIN19/VS
DIN20
VS VIDEO
AUDIO
HDCP
ENCRYPT
LINE
FAULT
DETECT
CLKDIV
HDCP
KEYS
HDCP
CONTROL
SCRAMBLE/
PARITY/
8b/10b
ENCODE
CML Tx
REVERSE
CONTROL
CHANNEL
Rx
PARALLEL
TO
SERIAL
HDCP
ENCRYPT
UART/I2C
SCKSD WS RX/SDATX/SCL
FIFO
DE
HS
VS
DIN[28:27]
(4-CH)
DE
ACB
FCC
RGB[23:18]
(4-CH)
SSPLL
FILTER
PLL
LEFT
LMN0
LMN1
OUT+
OUT-
MAX9263
PIN NAME FUNCTION
52–59 DOUT[7:0] Data Output [7:0]. Parallel data outputs. Output data can be strobed on the selected edge of
PCLKOUT. Encrypted when HDCP is enabled. See Table 3.
61 SSEN
Spread-Spectrum Enable Input. Serial link spread-spectrum enable input requires an external
pulldown or pullup resistor. The state of SSEN latches upon power-up or when resuming from
power-down mode (PWDN = low). Set SSEN = high for Q2% spread spectrum on parallel
outputs. Set SSEN = low to use the parallel outputs without spread spectrum.
62 DRS
Data-Rate Select. Data-rate range-selection input requires an external pulldown or pullup
resistor. The state of DRS latches upon power-up or when resuming from power-down mode
(PWDN = low). Set DRS = high for PCLKOUT frequencies of 8.33MHz to 16.66MHz (24-bit
mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for PCLKOUT frequencies of
16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).
— EP Exposed Pad. EP is internally connected to AGND. MUST externally connect EP to the AGND
plane for proper thermal and electrical performance.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
19
Functional Diagrams (continued)
RGB[17:0] RGB
HS
PCLKOUT
DOUT[17:0]
DOUT[26:21]
(4-CH)
DOUT27
(4-CH)
DOUT28/MCLK
(4-CH)
DOUT18/HS
DOUT19/VS
DOUT20
VS VIDEO
AUDIO
HDCP
DECRYPT
HDCP
KEYS
HDCP
CONTROL
8b/10b
DECODE/
UNSCRAMBLE
CML Rx
AND EQ
REVERSE
CONTROL
CHANNEL
Tx
SERIAL
TO
PARALLEL
HDCP
DECRYPT
UART/I2C
SCKSD WS RX/SDATX/SCL
FIFO
DE
HS
VS
DIN[28:27]
(4-CH)
DE
ACB
FCC
RGB[23:18]
(4-CH)
CLKDIVSSPLL CDRPLL
IN+
IN-
MAX9264
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
20
Figure 1. Serializer Serial-Output Parameters
Figure 2. Serializer Output Waveforms at OUT+, OUT-
OUT-
VOD
VOS
GND
RL/2
RL/2
OUT+
OUT-
OUT+
(OUT+) - (OUT-)
VOS(-) VOS(+)
((OUT+) + (OUT-))/2
VOS(-)
VOD(-)
VOD(-)
VOD = 0V
DVOS = |VOS(+) - VOS(-)|
DVOD = |VOD(+) - VOD(-)|
VOD(+)
OUT+
OUT-
VOS VOD(P) VOD(D)
SERIAL-BIT
TIME
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
21
Figure 3. Line-Fault Detector Circuit
Figure 4. Serializer Worst-Case Pattern Input
OUTPUT
LOGIC
(OUT+)
LFLT REFERENCE
VOLTAGE
GENERATOR
CONNECTORS
*Q1% TOLERANCE
OUTPUT
LOGIC
(OUT-)
MAX9263 45kI*
LMN1
LMN0
45kI*
1.7V TO 1.9V
5kI*
50kI* 50kI*
5kI*
TWISTED PAIR
OUT+
OUT-
PCLKIN
NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE.
DIN_
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
22
Figure 5. Serializer Parallel Input Clock Requirements
Figure 6. I2C Timing Parameters
Figure 7. Serializer Differential Output Template
VIL MAX
tHIGH
tLOW
tT
tR
tF
VIH MIN
PCLKIN
P
tR
P
S
S
tHOLD
tF
tSET
TX/
SCL
RX/
SDA
800mVP-P
tTSOJ1
2
tTSOJ1
2
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
23
Figure 8. Serializer Input Setup and Hold Times
Figure 9. Serializer Delay
VIH MIN
VIH MIN
VIH MIN
VIL MAX VIL MAX
VIL MAX
PCLKIN
DIN_
tHOLD
tSET
NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE.
tSD FIRST BIT LAST BIT
N
N+3
EXPANDED TIME SCALE
N+4
NN+1 N+2
N-1
DIN_
PCLKIN
OUT+/-
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
24
Figure 10. Serializer Link Startup Time
Figure 11. Serializer Power-Up Delay
SERIAL LINK INACTIVE SERIAL LINK ACTIVE
CHANNEL
DISABLED
REVERSE CONTROL CHANNEL
DISABLED
tLOCK
350Fs
PCLKIN
REVERSE CONTROL CHANNEL
AVAILABLE
PWDN MUST BE HIGH
PWDN
POWERED DOWN
VIH1
tPU
REVERSE CONTROL
CHANNEL DISABLED
350µs
PCLKIN
POWERED UP,
SERIAL LINK INACTIVE POWERED UP, SERIAL LINK ACTIVE
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL
CHANNEL DISABLED
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
25
Figure 12. Input I2S Timing Parameters
Figure 13. Reverse Control-Channel Output Parameters
WS
tHOLD tSET
tHOLD tSET tHC
tSCK
tLC
SCK
SD
MAX9264
REVERSE
CONTROL-CHANNEL
TRANSMITTER
IN+
IN-
IN-
IN+
IN+
IN-
VOD
RL/2
RL/2
VCMR
VCMR
VROH
(IN+) - (IN-)
tR
0.1 x VROL
0.9 x VROL
tF
VROL
0.9 x VROH
0.1 x VROH
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
26
Figure 16. Deserializer Clock Output High and Low Times
Figure 17. Deserializer Output Rise and Fall Times
Figure 14. Test Circuit for Differential Input Measurement Figure 15. Deserializer Worst-Case Pattern Output
VIN+
RL/2
RL/2
CIN
CIN
VID(P)
IN+
IN-
VID(P) = | VIN+ - VIN- |
VCMR = (VIN+ + VIN-)/2
VIN-
_
+
_
_
+
PCLKOUT
DOUT_
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE.
VOL MAX
tHIGH
tLOW
tT
VOH MIN
PCLKOUT
0.8 x VI0VDD
0.2 x VI0VDD
tF
tR
CL
SINGLE-ENDED OUTPUT LOAD
MAX9264
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
27
Figure 18. Deserializer Delay
Figure 21. Deserializer Output I2S Timing Parameters
Figure 19. Deserializer Lock Time Figure 20. Deserializer Power-Up Delay
FIRST BIT
IN+/-
DOUT_
PCLKOUT
LAST BIT
SERIAL WORD N
SERIAL-WORD LENGTH
SERIAL WORD N+1 SERIAL WORD N+2
tSD
PARALLEL WORD N-2 PARALLEL WORD N-1 PARALLEL WORD N
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE.
IN+ - IN-
LOCK
tLOCK
PWDN MUST BE HIGH
VOH
IN+/-
LOCK
tPU
PWDN
VOH
VIH1
WS
tDVA
tDVB tDVA tF
tDVB tR
SCK
SD
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
28
Detailed Description
The MAX9263/MAX9264 serializer/deserializer chipset
utilizes Maxim’s GMSL technology and HDCP. When
HDCP is enabled, the serializer/deserializer encrypt
video and audio data on the serial link. The serializer/
deserializer are backward compatible with the MAX9259/
MAX9260 serializer/deserializer.
The serializer/deserializer have a maximum serial pay-
load data rate of 2.5Gbps for 15m or more of STP cable.
The serializer/deserializer pair operates up to a maxi-
mum pixel clock of 104MHz for 24-bit mode, or 78MHz
for 32-bit mode, respectively. This serial link supports a
wide range of display panels, from QVGA (320 x 240) to
WXGA (1280 x 800) and higher with 24-bit color.
The 24-bit mode handles 21 bits of high-speed data,
UART control signals, and three audio signals. The 32-bit
mode handles 29 bits of high-speed data, UART control
signals, and three audio signals. The three audio signals
are a standard I2S interface, supporting sample rates
from 8kHz to 192kHz and audio word lengths of 4 bits
to 32 bits. The embedded control channel forms a full-
duplex, differential 9.6kbps to 1Mbps UART link between
the serializer and deserializer for HDCP-related control
operations. In addition, the control channel enables
electronic control unit (ECU), or microcontroller (FC) con-
trol of peripherals in the remote side, such as backlight
control, grayscale gamma correction, camera module,
and touch screen. An ECU/FC, can be located on the
serializer side of the link (typical for video display), on
the deserializer side of the link (typical for image sens-
ing), or on both sides. Base-mode communication with
peripherals uses either I2C or the GMSL UART format. A
bypass mode enables full-duplex communication using
a user-defined UART format.
The serializer pre/deemphasis, along with the deseri-
alizer channel equalizer, extends the link length and
enhances the link reliability. Spread spectrum is avail-
able to reduce EMI on the serial and parallel outputs. The
serial link connections comply with ISO 10605 and IEC
61000-4-2 ESD protection standards.
Register Mapping
The FC configures various operating conditions of the
serializer and the deserializer through internal registers.
The default device address of the serializer is 0x80
and default device address of the deserializer is 0x90
(Tables 1 and 2). Write to registers 0x00 or 0x01 in both
devices to change the device address of the serializer
or the deserializer.
Table 1. Power-Up Default Register Map (see Tables 22 and 24)
REGISTER
ADDRESS
(hex)
POWER-UP DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
0x00 0x80 SERID = 1000000, serializer device address is 1000 000
CFGBLOCK = 0, registers 0x00 to 0x1F are read/write
0x01 0x90 DESID = 1001000, deserializer device address is 1001 000
RESERVED = 0
0x02 0x1F, 0x3F
SS = 000 (SSEN = low), SS = 001 (SSEN = high), spread-spectrum settings depend
on SSEN pin state at power-up
AUDIOEN = 1, I2S channel enabled
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
0x03 0x00 AUTOFM = 00, calibrate spread-modulation rate only once after locking
SDIV = 000000, autocalibrate sawtooth divider
0x04 0x03, 0x13, 0x83, or
0x93
SEREN = 0 (AUTOS = high), SEREN = 1 (AUTOS = low), serial link enable default
depends on AUTOS pin state at power-up
CLINKEN = 0, configuration link disabled
PRBSEN = 0, PRBS test disabled
SLEEP = 0 or 1, sleep mode state depends on CDS and AUTOS pin state at
power-up (see the Link Startup Procedure section)
INTTYPE = 00, base mode uses I2C
REVCCEN = 1, reverse control channel active (receiving)
FWDCCEN = 1, forward control channel active (sending)
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
29
Table 1. Power-Up Default Register Map (see Tables 22 and 24) (continued)
REGISTER
ADDRESS
(hex)
POWER-UP DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
0x05 0x70
I2CMETHOD = 0, I2C packets include register address
DISFPLL = 1, filter PLL disabled
CMLLVL = 11, 400mV CML signal level
PREEMP = 0000, preemphasis disabled
0x06 0x40 RESERVED = 01000000
0x07 0x22 RESERVED = 00100010
0x08 0x0A
(read only)
RESERVED = 0000
LFNEG = 10, no faults detected
LFPOS = 10, no faults detected
0x0C 0x70 RESERVED = 01110000
0x0D 0x0F
SETINT = 0, interrupt output set to low
INVVSYNC = 0, serializer does not invert DIN19/VS
INVHSYNC = 0, serializer does not invert DIN18/HS
RESERVED = 0000
0x1E 0x05
(read only) ID = 00000101, device ID is 0x05
0x1F 0x1X
(read only)
RESERVED = 000
CAPS = 1, serializer is HDCP capable
REVISION = XXXX, Revision number
0x80 to 0x84 0x0000000000 BKSV = 0x0000000000, HDCP receiver KSV is 0x0000000000
0x85, 0x86 0x0000 RI = 0x0000, RI of the transmitter is 0x0000
0x87 0x00 PJ = 0x00, PJ of the transmitter is 0x00
0x88 to 0x8F 0x0000000000000000
(read only) AN = 0x0000000000000000, session random number (read only)
0x90 to 0x94 0xXXXXXXXXXX
(read only)
AKSV = 0xXXXXXXXXXXXXXXXX, HDCP transmitter KSV is 0xXXXXXXXXXX (read
only)
0x95 0x00
PD_HDCP = 0, HDCP circuits powered up
EN_INT_COMP = 0, internal link verification disabled
FORCE_AUDIO = 0, normal I2S audio operation
FORCE_VIDEO = 0, normal video link operation
RESET_HDCP = 0, normal HDCP operation
START_AUTHENTICATION = 0, HDCP authentication not started
VSYNC_DET = 0, VSYNC rising edge not detected
ENCRYPTION_ENABLE = 0, HDCP encryption disabled
0x96 0x01
(read only)
RESERVED = 0000
V_MATCHED = 0, SHA-1 hash value not matched
PJ_MATCHED = 0, enhanced link verification response not matched
R0_RI_MATCHED = 0, link verification response not matched
BKSV_INVALID = 1, invalid receiver KSV
0x97 0x00 RESERVED = 0000000
REPEATER = 0, HDCP receiver is not a repeater
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
30
Table 1. Power-Up Default Register Map (see Tables 22 and 24) (continued)
Table 2. Power-Up Default Register Map (see Tables 23 and 25)
X = Indeterminate.
REGISTER
ADDRESS
(hex)
POWER-UP DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
0x98 to 0x9C 0x0000000000 ASEED = 0x0000000000, optional RNG seed value is 0x0000000000
0x9D to 0x9F 0x000000 DFORCE = 0x000000, video data forced to 0x000000 when FORCE_VIDEO = 1
0xA0 to 0xA3 0x00000000 H0 part of SHA-1 hash value is 0x00000000
0xA4 to 0xA7 0x00000000 H1 part of SHA-1 hash value is 0x00000000
0xA8 to 0xAB 0x00000000 H2 part of SHA-1 hash value is 0x00000000
0xAC to 0xAF 0x00000000 H3 part of SHA-1 hash value is 0x00000000
0xB0 to 0xB3 0x00000000 H4 part of SHA-1 hash value is 0x00000000
0xB4 0x00
Reserved = 0000
MAX_CASCADE_EXCEEDED = 0, 7 or fewer cascaded HDCP devices attached
DEPTH = 000, device cascade depth is zero
0xB5 0x00 MAX_DEVS_EXCEEDED = 0, 14 or fewer HDCP devices attached
DEVICE_COUNT = 0000000, zero attached devices
0xB6 0x00 GPMEM = 00000000, 0x00 stored in general-purpose memory
0xB7 to 0xB9 0x000000 Reserved = 0x000000
0xBA to 0xFF All zero KSV_LIST = all zero, no KSVs stored
REGISTER
ADDRESS
(hex)
POWER-UP DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
0x00 0x80 SERID = 1000000, serializer device address is 1000 000
RESERVED = 0
0x01 0x90 DESID = 1001000, deserializer device address is 1001 000
CFGBLOCK = 0, registers 0x00 to 0x1F are read/write
0x02 0x1F or 0x5F
SS = 00 (SSEN = low), SS = 01 (SSEN = high), spread-spectrum settings depend
on SSEN pin state at power-up
RESERVED = 0
AUDIOEN = 1, I2S channel enabled
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
0x03 0x00
AUTOFM = 00, calibrate spread-modulation rate only once after locking
RESERVED = 0
SDIV = 00000, autocalibrate sawtooth divider
0x04 0x03, 0x13, 0x43, 0x53
LOCKED = 0, LOCK output is low (read only)
OUTENB = 0 (ENABLE = low), OUTENB = 1 (ENABLE = high), OUTENB default
depends on ENABLE pin state at power-up
PRBSEN = 0, PRBS test disabled
SLEEP = 0 or 1, SLEEP setting default depends on CDS and MS pin state at
power-up (see the Link Startup Procedure section)
INTTYPE = 00, base mode uses I2C
REVCCEN = 1, reverse control channel active (sending)
FWDCCEN = 1, forward control channel active (receiving)
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
31
Table 2. Power-Up Default Register Map (see Tables 23 and 25) (continued)
REGISTER
ADDRESS
(hex)
POWER-UP DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
0x05 0x24 or 0x29
I2CMETHOD = 0, I2C master sends the register address
HPFTUNE = 01, 3.75MHz equalizer highpass cutoff frequency
PDHF = 0, high-frequency boosting disabled
EQTUNE = 0100 (EQS = high, 5.2dB), EQTUNE = 1001 (EQS = low, 10.7dB),
EQTUNE default setting depends on EQS pin state at power-up
0x06 0x0F
DISSTAG = 0, outputs are staggered
AUTORST = 0, error registers/output autoreset disabled
DISINT = 0, INT transmission enabled
INT = 0, INT output is low (read only)
GPIO1OUT = 1, GPIO1 output set to high
GPIO1 = 1, GPIO1 input = high (read only)
GPIO0OUT = 1, GPIO0 output set to high
GPIO0 = 1, GPIO0 input = high (read only)
0x07 0x54 RESERVED = 01010100
0x08 0x30
RESERVED = 001100
DISVSFILT = 0, DOUT19/VS glitch filter active
DISHSFILT = 0, DOUT18/HS glitch filter active
0x09 0xC8 RESERVED = 11001000
0x0A 0x12 RESERVED = 00010010
0x0B 0x20 RESERVED = 00100000
0x0C 0x00 ERRTHR = 00000000, error threshold set to zero for decoding errors
0x0D 0x00
(read only) DECERR = 00000000, zero decoding errors detected
0x0E 0x00
(read only) PRBSERR = 00000000, zero PRBS errors detected
0x12 0x00 MCLKSRC = 0, MCLK is derived from PCLK (see Table 5)
MCLKDIV = 0000000, MCLK output is disabled
0x13 0x10 RESERVED = 00010000
0x14 0x09
INVVSYNC = 0, deserializer does not invert DOUT19/VS
INVHSYNC = 0, deserializer does not invert DOUT18/HS
RESERVED = 001001
0x1E 0x06
(read only) ID = 00000100, device ID is 0x06
0x1F 0x1X
(read only)
RESERVED = 000
CAPS = 1 HDCP capable
REVISION = XXXX
0x80 to 0x84 0xXXXXXXXXXX
(read only) BKSV = 0xXXXXXXXXXX, HDCP receiver KSV is 0xXXXXXXXXXX
0x85, 0x86 0xXXXX
(read only) RI’ = 0xXXXX, RI’ of the transmitter is 0xXXXX
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
32
Table 2. Power-Up Default Register Map (see Tables 23 and 25) (continued)
X = Indeterminate.
REGISTER
ADDRESS
(hex)
POWER-UP DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
0x87 0xXX
(read only) PJ’ = 0xXXXX, PJ’ of the transmitter is 0xXX
0x88 to 0x8F 0x00000000
00000000 AN = 0000000000000000, session random number is 0000000000000000
0x90 to 0x94 0x00000000
00000000 AKSV = 0x0000000000, HDCP transmitter KSV is 0x0000000000000000
0x95 0x00
PD_HDCP = 0, HDCP circuits powered up
RESERVED = 000
GPIO1_FUNCTION = 0, normal GPIO1 function
GPIO0_FUNCTION = 0, normal GPIO0 function
AUTH_STARTED = 0, HDCP authentication not started
ENCRYPTION_ENABLE = 0, HDCP encryption disabled
0x96 0x00
RESERVED = 000000
NEW_DEV_CONN = 0, no new devices connected
KSV_LIST_READY = 0, KSV list is not ready
0x97 0x00 RESERVED = 0000000
REPEATER = 0, HDCP receiver is not a repeater
0x98 to 0x9F
0x00000000
00000000
(read only)
RESERVED = 0x0000000000000000
0xA0 to 0xA3 0xXXXXXXXX
(read only) H0 part of SHA-1 hash value is 0xXXXXXXXX
0xA4 to 0xA7 0xXXXXXXXX
(read only) H1 part of SHA-1 hash value is 0xXXXXXXXX
0xA8 to 0xAB 0xXXXXXXXX
(read only) H2 part of SHA-1 hash value is 0xXXXXXXXX
0xAC to 0xAF 0xXXXXXXXX
(read only) H3 part of SHA-1 hash value is 0xXXXXXXXX
0xB0 to 0xB3 0xXXXXXXXX
(read only) H4 part of SHA-1 hash value is 0xXXXXXXXX
0xB4 0x00
Reserved = 0000
MAX_CASCADE_EXCEEDED = 0, 7 or fewer cascaded HDCP devices attached
DEPTH = 000, device cascade depth is zero
0xB5 0x00 MAX_DEVS_EXCEEDED = 0, 14 or fewer HDCP devices attached
DEVICE_COUNT = 0000000, zero attached devices
0xB6 0x00 GPMEM = 00000000, 0x00 stored in general-purpose memory
0xB7 to 0xB9 0x000000
(read only) Reserved = 0x000000
0xBA to 0xFF All zero KSV_LIST = all zero, no KSVs stored
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
33
HDCP Bitmapping and Bus-Width Selection
The parallel input/outputs have two selectable modes,
24-bit mode and 32-bit mode. In 24-bit mode, DIN[28:21]
are not available. For both modes, the SD, SCK, and WS
pins are for I2S audio. The serializer/deserializer use
pixel clock rates from 8.33MHz to 104MHz for 24-bit
mode and 6.25MHz to 78MHz for 32-bit mode.
Table 3 lists the HDCP bit mapping for the parallel inputs.
DIN18/HS and DIN19/VS are reserved for HSYNC and
VSYNC, respectively. The serializer/deserializer have
HDCP encryption on DIN[17:0] and the I2S input. 32-bit
mode has additional HDCP encryption on DIN[26:21].
DIN[28:27] and DIN20 do not have HDCP encryption. SD,
when used as an additional data input (AUDIOEN = 0),
also does not have HDCP encryption.
Serial Link Signaling and Data Format
The serializer uses CML signaling with programmable
pre/deemphasis and AC-coupling. The deserializer uses
AC-coupling and programmable channel equalization.
Together, the GMSL link can operate at full speed over
STP cable lengths to 15m or more.
The serializer scrambles and encodes the input data and
sends the 8b/10b coded signal through the serial link.
The deserializer recovers the embedded serial clock and
then samples, decodes, and descrambles before out-
putting the data. Figures 22 and 23 show the serial-data
packet format after unscrambling and 8b/10b decoding.
In 24-bit or 32-bit mode, 21 or 29 bits map to the paral-
lel outputs. The audio channel bit (ACB) contains an
encoded audio signal derived from the three I2S signals
(SD, SCK, and WS). The forward control channel (FCC)
Table 3. HDCP Mapping and Bus Width Selection
Figure 22. 24-Bit Mode Serial Link Data Format
*Bit assignments of DIN[28:0] are interchangeable if HDCP is not used.
**HDCP encryption on SD when used as an I2S signal.
DIN0
R0
RGB DATA CONTROL BITS AUDIO
CHANNEL
BIT
FORWARD
CONTROL-
CHANNEL BIT
PACKET
PARITY
CHECK BIT
R1
DIN1 DIN17
B5 HS VS DE
24 BITS
DIN18 DIN19 DIN20 ACB FCC PCB
NOTE: LOCATIONS OF THE RGB DATA ARE INTERCHANGABLE
ACCORDINGLY ON BOTH SIDES OF THE LINK.
ONLY DIN[17:0], AND ACB HAVE HDCP ENCRYPTION.
INPUT BITS
24-BIT MODE (BWS = LOW) 32-BIT MODE (BWS = HIGH)
HDCP MAPPING* HDCP ENCRYPTION
CAPABILITY HDCP MAPPING* HDCP ENCRYPTION
CAPABILITY
DIN[17:0] RGB Yes RGB Yes
DIN18/HS HS No HS No
DIN19/VS VS No VS No
DIN20 DE No DE No
DIN[26:21] Not Available — RGB Yes
DIN[28:27] Not Available — CNTL No
SD SD I2S** SD I2S**
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
34
bit carries the forward control data. The last bit (PCB) is
the parity bit of the previous 23 or 31 bits.
Reverse Control Channel
The serializer uses the reverse control channel to receive
I2C/UART and interrupt signals from the deserializer in
the opposite direction of the video stream. The reverse
control channel and forward video data coexist on
the same twisted pair forming a bidirectional link. The
reverse control channel operates independently from the
forward control channel. The reverse control channel is
available 500Fs after power-up. The serializer temporar-
ily disables the reverse control channel for 350Fs after
starting/stopping the forward serial link.
Data-Rate Selection
The serializer/deserializer use the DRS input to set the
PCLKIN frequency range. Set DRS high for a PCLKIN
frequency range of 6.25MHz to 12.5MHz (32-bit mode)
or 8.33MHz to 16.66MHz (24-bit mode). Set DRS low
for normal operation with a PCLKIN frequency range
of 12.5MHz to 78MHz (32-bit mode) or 16.66MHz to
104MHz (24-bit mode).
Audio Channel
The I2S audio channel supports audio sampling rates
from 8kHz to 192kHz and audio word lengths from 4 bits
to 32 bits. The audio bit clock (SCK) does not have to be
synchronized with PCLKIN. The serializer automatically
encodes audio data into a single bit stream synchronous
with PCLKIN. The deserializer decodes the audio stream
and stores audio words in a FIFO. Audio rate detection
uses an internal oscillator to continuously determine the
audio data rate and output the audio in I2S format. The
audio channel is enabled by default. When the audio
channel is disabled, the audio data on the serializer and
deserializer are treated as an additional parallel signal
(DIN_/DOUT_).
Since the audio data sent through the serial link is
synchronized with PCLKIN, low PCLKIN frequencies
limit the maximum audio sampling rate. Table 4 lists
Table 4. Maximum Audio WS Frequency (kHz) for Various PCLKIN Frequencies
Figure 23. 32-Bit Mode Serial Link Data Format
DIN0
R0
RGB DATA CONTROL BITS RGB DATA ADDITIONAL
VIDEO DATA/
CONTROL BITS
AUDIO
CHANNEL
BIT
FORWARD
CONTROL-
CHANNEL BIT
PACKET
PARITY
CHECK BIT
R1
DIN1 DIN17
B5 HS VS DE R6 R7
32 BITS
G6 G7 B6 B7
DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 DIN24 DIN25 DIN26 DIN27 DIN28 ACB FCC PCB
NOTE: LOCATIONS OF THE RGB DATA ARE INTERCHANGABLE
ACCORDINGLY ON BOTH SIDES OF THE LINK.
ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION.
WORD
LENGTH
(bits)
PCLKIN FREQUENCY
(DRS = LOW) (MHz)
PCLKIN FREQUENCY
(DRS = HIGH) (MHz)
12.5 15 16.6 > 20 6.25 7.5 8.33 > 10
8> 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192
16 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192
18 185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192
20 174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192
24 152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192
32 123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
35
the maximum audio sampling rate for various PCLKIN
frequencies. Spread-spectrum settings do not affect
the I2S data rate or WS clock frequency.
Additional MCLK Output for
Audio Applications
Some audio DACs, such as the MAX9850, do not require
a synchronous main clock (MCLK), while other DACs
require MCLK to be a specific multiple of WS. If an audio
DAC chip needs the MCLK to be a multiple of WS, use
an external PLL to regenerate the required MCLK from
PCLKOUT or SCK.
For audio applications that cannot directly use PCLKOUT,
the MAX9264 provides a divided MCLK output on
DOUT28/MCLK at the expense of one less control line
in 32-bit mode (24-bit mode is not affected). By default,
DOUT28/MCLK operates as a parallel data output, and
MCLK is turned off. Set MCLKDIV (MAX9264 register
0x12, D[6:0]) to a non-zero value to enable the MCLK
output. Set MCLKDIV to 0x00 to disable MCLK and set
DOUT28/MCLK as a parallel data output.
The output MCLK frequency is:
SRC
MCLK
f
fMCLKDIV
=
where fSRC is the MCLK source frequency (Table 5)
MCLKDIV is the divider ratio from 1 to 127
Choose MCLKDIV values so that fMCLK is not greater
than 60MHz. MCLK frequencies derived from PCLKIN
(MCLKSRC = 0) are not affected by spread-spectrum
settings in the deserializer. Enabling spread spectrum
in the serializer, however, introduces spread spectrum
into MCLK. Spread-spectrum settings of either device
do not affect MCLK frequencies derived from the internal
oscillator. The internal oscillator frequency ranges from
100MHz to 150MHz over all process corners and operat-
ing conditions.
Control Channel and Register Programming
The control channel is available for the FC to send and
receive control data over the serial link simultaneously
with the high-speed data. Configuring the CDS pin allows
the FC to control the link from either the serializer or the
deserializer side to support video-display or image-
sensing applications. The control channel between the
FC and serializer or deserializer runs in base mode or
bypass mode according to the mode selection (MS)
input of the device connected to the FC. Base mode is
a half-duplex control channel and the bypass mode is a
full-duplex control channel.
Base Mode
In base mode, the FC is the host and can access the
core and HDCP registers of both the serializer and
deserializer from either side of the link by using the
GMSL UART protocol. The FC can also program the
peripherals on the remote side by sending the UART
packets to the serializer or deserializer, with the UART
packets converted to I2C by the device on the remote
side of the link (deserializer for LCD or serializer for
image-sensing applications). The FC communicates
with a UART peripheral in base mode (through INTTYPE
register settings), using the half-duplex default GMSL
UART protocol of the serializer/deserializer. The device
addresses of the serializer and deserializer in base
mode are programmable. The default value is 0x80 for
the serializer and 0x90 for the deserializer.
When the peripheral interface uses I2C (default), the
serializer/deserializer convert packets to I2C that have
device addresses different from those of the serializer or
deserializer. The converted I2C bit rate is the same as
the original UART bit rate.
The deserializer uses a proprietary differential line cod-
ing to send signals back towards the serializer. The
speed of the control channel ranges from 9.6kbps to
Table 5. Deserializer fSRC Settings
MCLKSRC SETTING
(REGISTER 0x12, D7) DATA RATE SETTING BIT WIDTH SETTING MCLK SOURCE
FREQUENCY (fSRC)
0
High speed 24-bit mode 3 x fPCLKIN
32-bit mode 4 x fPCLKIN
Low speed 24-bit mode 6 x fPCLKIN
32-bit mode 8 x fPCLKIN
1— — Internal oscillator
(120MHz typ)
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
36
1Mbps in both directions. The serializer and deserial-
izer automatically detect the control-channel bit rate in
base mode. Packet bit rates can vary up to 3.5x from the
previous bit rate. See the Changing the Clock Frequency
section.
Figure 24 shows the UART protocol for writing and read-
ing in base mode between the µC and the serializer/
deserializer.
Figure 25 shows the UART data format. Figures 26 and
27 detail the formats of the SYNC byte (0x79) and the
ACK byte (0xC3). The FC and the connected slave chip
generate the SYNC byte and ACK byte, respectively.
Events such as device wake-up and interrupt generate
transitions on the control channel that should be ignored
by the FC. Data written to the serializer/deserializer
registers do not take effect until after the acknowledge
byte is sent. This allows the FC to verify write commands
received without error, even if the result of the write
command directly affects the serial link. The slave uses
the SYNC byte to synchronize with the host UART data
rate automatically. If the INT or MS inputs of the deserial-
izer toggle while there is control-channel communication,
the control-channel communication can be corrupted.
Figure 24. GMSL UART Protocol for Base Mode
Figure 25. GMSL UART Data Format for Base Mode
Figure 26. SYNC Byte (0x79) Figure 27. ACK Byte (0xC3)
WRITE DATA FORMAT
SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES
SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1 BYTE N
ACK
BYTE NBYTE 1ACK
MASTER READS FROM SLAVE
READ DATA FORMAT
MASTER WRITES TO SLAVE
MASTER WRITES TO SLAVE
MASTER READS FROM SLAVE
START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP
1 UART FRAME
FRAME 1 FRAME 2 FRAME 3
STOP START STOP START
START
D0
10011110
D1 D2 D3 D4 D5 D6 D7
PARITY STOP START
D0
11000011
D1 D2 D3 D4 D5 D6 D7
PARITY STOP
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
37
In the event of a missed acknowledge, the FC should
assume there was an error in the packet when the slave
device receives it, or that an error occurred during the
response from the slave device. In base mode, the FC
must keep the UART Tx/Rx lines high for 16 bit-times
before starting to send a new packet.
As shown in Figure 28, the remote-side device converts
the packets going to or coming from the peripherals from
the UART format to the I2C format and vice versa. The
remote device removes the byte number count and adds
or receives the ACK between the data bytes of I2C. The
I2C’s data rate is the same as the UART data rate.
Interfacing Command-Byte-Only I2C Devices
The serializer and deserializer UART-to-I2C conver-
sion interfaces with devices that do not require register
addresses, such as the MAX7324 GPIO expander. In
this mode, the I2C master ignores the register address
byte and directly reads/writes the subsequent data bytes
(Figure 29). Change the communication method of the
I2C master using the I2CMETHOD bit. I2CMETHOD = 1
sets command-byte-only mode, while I2CMETHOD = 0
sets normal mode where the first byte in the data stream
is the register address.
Bypass Mode
In bypass mode, the serializer/deserializer ignore UART
commands from the FC and the FC communicates with
the peripherals directly using its own defined UART pro-
tocol. The FC cannot access the serializer/deserializer’s
registers in this mode. Peripherals accessed through the
forward control channel using the UART interface need
to handle at least one PCLKIN period ±10ns of jitter due
to the asynchronous sampling of the UART signal by
PCLKIN. Set MS = high to put the control channel into
bypass mode. For applications with the FC connected to
the deserializer, (CDS is high) there is a 1ms wait time
between setting MS high and the bypass control channel
being active. There is no delay time when switching to
bypass mode when the FC is connected to the serial-
izer (CDS = low). Do not send a logic-low value longer
than 100Fs to ensure proper interrupt functionality.
Bypass mode accepts bit rates down to 10kbps in either
direction. See the Interrupt Control section for interrupt
functionality limitations. The control-channel data pattern
should not be held low longer than 100Fs if interrupt
control is used.
Figure 28. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)
11
SYNC FRAME REGISTER ADDRESS NUMBER OF BYTESDEVICE ID + WR DATA 0
DEV ID A
11 11 11 11
DATA N
11 11
S
1 11
ACK FRAME
7
: MASTER TO SLAVE
8
SERIALIZER/DESERIALIZER PERIPHERAL
W
1
REG ADDR
8
A
1181
11
SYNC FRAME REGISTER ADDRESS NUMBER OF BYTESDEVICE ID + RD
11 11 11 11
ACK FRAME DATA 0
11
DATA N
11
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0)
S: START P: STOP A: ACKNOWLEDGE
: SLAVE TO MASTER
DATA 0A DATA NAP
DEV ID AS
117
W
1
DEV ID AS
117
R
1
DATA NP
18
A
1
DATA 0
8
A
1
REG ADDR
8
A
1
FCSERIALIZER/DESERIALIZER
FCSERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER PERIPHERAL
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
38
Interrupt Control
The INT pin of the serializer is the interrupt output and
the INT pin of the deserializer is the interrupt input. The
interrupt output on the serializer follows the transitions
at the interrupt input. This interrupt function supports
remote-side functions such as touch-screen peripherals,
remote power-up, or remote monitoring. Interrupts that
occur during periods where the reverse control channel
is disabled, such as link startup/shutdown, are automati-
cally resent once the reverse control channel becomes
available again. Bit D4 of register 0x06 in the deserializer
also stores the interrupt input state. The INT output of
the serializer is low after power-up. In addition, the FC
can set the INT output of the serializer by writing to the
SETINT register bit. In normal operation, the state of the
interrupt output changes when the interrupt input on the
deserializer toggles. Do not send a logic-low value lon-
ger than 100Fs in either base or bypass mode to ensure
proper interrupt functionality.
Pre/Deemphasis Driver
The serial line driver in the serializer employs current-
mode logic (CML) signaling. The driver can generate
an adjustable waveform according to the cable length
and characteristics. There are 13 preemphasis settings
as shown in Table 6. Negative preemphasis levels are
deemphasis levels in which the preemphasized swing
level is the same as normal swing, but the no-transition
data is deemphasized. Program the preemphasis lev-
els through register 0x05 D[3:0] of the serializer. This
preemphasis function compensates the high frequency
loss of the cable and enables reliable transmission over
longer link distances. Additionally, a lower power drive
mode can be entered by programming CMLLVL bits
(0x05, D[5:4]) to reduce the driver strength down to
75% (CMLLVL = 10) or 50% (CMLLVL = 01) from 100%
(CMLLVL = 11, default).
Figure 29. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1)
: MASTER TO SLAVE
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1)
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
FC
SERIALIZER/DESERIALIZERFC
SYNC FRAME
11 11 11 11 11 11 11
1111 11 11 11 11 11
DEVICE ID + RD REGISTER ADDRESS NUMBER OF BYTES
SYNC FRAME DEVICE ID + WR REGISTER ADDRESS NUMBER OF BYTES DATA 0 DATA N ACK FRAME
ACK FRAME DATA 0 DATA N
DATA NADATA 0WADEV IDS AP
PERIPHERAL
PERIPHERAL
S
1118
8811117 11
8
1117
DEV ID RA AAPDATA 0 DATA N
: SLAVE TO MASTER S: START P: STOP A: ACKNOWLEDGE
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
39
Line Equalizer
The deserializer includes an adjustable line equalizer to
further compensate cable attenuation at high frequen-
cies. The cable equalizer has 11 selectable levels of
compensation from 2.1dB to 13dB (Table 7). The EQS
input selects the default equalization level at power-up.
The state of EQS is latched upon power-up or when
resuming from power-down mode. To select other
equalization levels, set the corresponding register bits
in the deserializer (0x05 D[3:0]). Use equalization in the
deserializer, together with preemphasis in the serializer,
to create the most reliable link for a given cable.
Table 6. Serializer CML Driver Strength (Default Level, CMLLVL = 11)
Table 7. Deserializer Cable Equalizer Boost Levels
*Negative preemphasis levels denote deemphasis.
PREEMPHASIS LEVEL (dB)* PREEMPHASIS SETTING
(0x05, D[3:0])
ICML
(mA)
IPRE
(mA)
SINGLE-ENDED VOLTAGE SWING
MAX (mV) MIN (mV)
-6.0 0100 12 4 400 200
-4.1 0011 13 3 400 250
-2.5 0010 14 2 400 300
-1.2 0001 15 1 400 350
0 0000 16 0 400 400
1.1 1000 16 1 425 375
2.2 1001 16 2 450 350
3.3 1010 16 3 475 325
4.4 1011 16 4 500 300
6.0 1100 15 5 500 250
8.0 1101 14 6 500 200
10.5 1110 13 7 500 150
14.0 1111 12 8 500 100
BOOST SETTING (0x05 D[3:0]) TYPICAL BOOST GAIN (dB)
0000 2.1
0001 2.8
0010 3.4
0011 4.2
0100
5.2
Power-Up Default
(EQS = high)
0101 6.2
0110 7
0111 8.2
1000 9.4
1001
10.7
Power-Up Default
(EQS = low)
1010 11.7
1011 13
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
40
Spread Spectrum
To reduce the EMI generated by the transitions on
the serial link and parallel outputs, both the serial-
izer and deserializer support spread spectrum. Turning
on spread spectrum on the deserializer spreads the
parallel video outputs. Turning on spread spectrum
on the serializer spreads the serial link, along with the
deserializer parallel outputs. Do not enable spread for
both the serializer and deserializer. The six selectable
spread-spectrum rates at the serializer serial output are
Q0.5%, Q1%, Q1.5%, Q2%, Q3%, and Q4% (Table 8).
Some spread-spectrum rates can only be used at lower
PCLK_ frequencies (Table 9). There is no PCLK_ fre-
quency limit for the 0.5% spread rate. The two selectable
spread-spectrum rates at the deserializer parallel output
are Q2% and Q4% (Table 10).
Set the serializer SSEN input high to select 0.5% spread
at power-up and SSEN input low to select no spread at
power-up. Set the deserializer SSEN input high to select
2% spread at power-up and SSEN input low to select no
spread at power-up. The state of SSEN is latched upon
power-up or when resuming from power-down mode.
Whenever the serializer spread spectrum is turned on
or off, the serial link automatically restarts and remains
unavailable while the deserializer relocks to the serial
data. Turning on spread spectrum on the serializer
or deserializer does not affect the audio data stream.
Changes in the serializer spread settings only affect
the deserializer MCLK output if it is derived from PCLK_
(MCLKSRC = 0).
The serializer/deserializer include a sawtooth divider to
control the spread-modulation rate. Auto detection or
manual programming of the PCLKIN operation range
guarantees a spread-spectrum modulation frequency
within 20kHz to 40kHz. Additionally, manual configura-
tion of the sawtooth divider (SDIV: 0x03, D[5:0]) allows
the user to set a modulation frequency according to
the PCLKIN frequency. Always keep the modulation
frequency between 20kHz to 40kHz to ensure proper
operation.
Table 8. Serializer Serial Output Spread
Table 10. Deserializer Parallel Output Spread
Table 9. Serializer Spread Rate Limitations
SS SPREAD (%)
000 No spread spectrum. Power-up default when SSEN = low.
001 Q0.5% spread spectrum. Power-up default when SSEN = high.
010 Q1.5% spread spectrum.
011 Q2% spread spectrum.
100 No spread spectrum.
101 Q1% spread spectrum.
110 Q3% spread spectrum.
111 Q4% spread spectrum.
24-BIT MODE PCLK_
FREQUENCY (MHz)
32-BIT MODE PCLK_
FREQUENCY (MHz)
SERIAL LINK BIT-RATE
(Mbps)
AVAILABLE SPREAD
RATES
< 33.3 < 25 < 1000 All rates available
33.3 to < 66.7 20 to < 50 1000 to < 2000 1.5%, 1.0%, 0.5%
66.7+ 50+ 2000+ 0.5%
SS SPREAD (%)
00 No spread spectrum. Power-up default when SSEN = low.
01 Q2% spread spectrum. Power-up default when SSEN = high.
10 No spread spectrum.
11 Q4% spread spectrum.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
41
Manual Programming of the
Spread-Spectrum Divider
The modulation rate for the serializer/deserializer relates
to the PCLK_ frequency as follows:
PCLK_
M
f
f (1 DRS) MOD SDIV
= +
×
where:
fM = Modulation frequency
DRS = DRS pin input value (0 or 1)
fPCLK_ = PCLK_ frequency
MOD = Modulation coefficient given in Table 11 or 12
SDIV = 6- or 5-bit SDIV setting, manually programmed
by the FC
To program the SDIV setting, first look up the modulation
coefficient according to the part number and desired
bus-width and spread-spectrum settings. Solve the
above equation for SDIV using the desired pixel clock
and modulation frequencies. If the calculated SDIV
value is larger than the maximum allowed SDIV value in
Table 11 or 12, set SDIV to the maximum value.
Sleep Mode
The serializer/deserializer include a low-power sleep
mode to reduce power consumption on the device not
attached to the FC (the deserializer in LCD applications
and the serializer in camera applications). Set the cor-
responding remote IC’s SLEEP bit to 1 to initiate sleep
mode. The serializer sleeps immediately after setting
its SLEEP = 1. The deserializer sleeps after serial link
inactivity or 8ms (whichever arrives first) after setting
its SLEEP = 1. See the Link Startup Procedure section
for details on waking up the device for different FC and
starting conditions.
The FC side device cannot enter into sleep mode. If
an attempt is made to program the FC side device for
sleep, the SLEEP bit remains 0. Use the PWDN input
pin to bring the FC side device into a low-power state.
Entering sleep mode resets the HDCP registers, but not
the configuration registers.
Power-Down Mode
The serializer/deserializer include a power-down mode
to further reduce power consumption. Set PWDN low to
enter power-down mode. While in power-down mode, the
Table 11. Serializer Modulation Coefficients and Maximum SDIV Settings
Table 12. Deserializer Modulation Coefficients and Maximum SDIV Settings
BIT-WIDTH MODE SPREAD-SPECTRUM
SETTING (%)
MODULATION
COEFFICIENT MOD (dec) SDIV UPPER LIMIT (dec)
32 bit
1 104 40
0.5 104 63
3 152 27
1.5 152 54
4 204 15
2 204 30
24 bit
1 80 52
0.5 80 63
3 112 37
1.5 112 63
4 152 21
2 152 42
SPREAD-SPECTRUM SETTING (%) MODULATION COEFFICIENT (dec) SDIV UPPER LIMIT (dec)
4 208 15
2 208 30
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
42
outputs of the device remain high impedance. Entering
power-down mode resets the internal registers of the
device. In addition, upon exiting power-down mode, the
serializer/deserializer relatch the state of external pins
SSEN, DRS, AUTOS, and EQS.
Configuration Link Mode
The GMSL includes a low-speed configuration link to
allow control-data connection between the two devices
in the absence of a valid clock input. In either display or
camera applications, the configuration link can be used
to program equalizer/preemphasis or other registers
before establishing the video link. An internal oscillator
provides PCLKIN for establishing the serial configuration
link between the serializer and deserializer. Set CLINKEN
= 1 on the serializer to turn on the configuration link. The
configuration link remains active as long as the video
link has not been enabled. The video link overrides the
configuration link and attempts to lock when SEREN = 1.
Link Startup Procedure
Table 13 lists four startup cases for video-display
applications. Table 14 lists two startup cases for image-
sensing applications. In either video-display or image-
sensing applications, the control link is always available
after the high-speed data link or the configuration link is
established and the serializer/deserializer registers or
the peripherals are ready for programming.
Video-Display Applications
For the video-display application, with a remote display
unit, connect the FC to the serializer and set CDS = low
for both the serializer and deserializer. Table 13 sum-
marizes the four startup cases based on the settings of
AUTOS and MS.
Case 1: Autostart Mode
After power-up or when PWDN transitions from low to
high for both the serializer and deserializer, the serial
link establishes if a stable clock is present. The serial-
izer locks to the clock and sends the serial data to the
deserializer. The deserializer then detects activity on the
serial link and locks to the input serial data.
Case 2: Standby Start Mode
After power-up or when PWDN transitions from low to
high for both the serializer and deserializer, the deserial-
izer starts up in sleep mode, and the serializer stays in
standby mode (does not send serial data). Use the FC
and program the serializer to set SEREN = 1 to establish
a video link or CLINKEN = 1 to establish the configura-
tion link. After locking to a stable clock (for SEREN = 1)
or the internal oscillator (for CLINKEN = 1), the serializer
sends a wake-up signal to the deserializer. The deserial-
izer exits sleep mode after locking to the serial data and
sets SLEEP = 0. If after 8ms the deserializer does not
lock to the input serial data, the deserializer goes back to
sleep, and the internal sleep bit remains set (SLEEP = 1).
Table 13. Start Mode Selection for Display Applications (CDS = Low)
CASE AUTOS
(SERIALIZER)
SERIALIZER
POWER-UP STATE
MS
(DESERIALIZER)
DESERIALIZER
POWER-UP STATE LINK STARTUP MODE
1 Low Serialization
enabled Low Normal
(SLEEP = 0)
Both devices power up with serial
link active (autostart).
2 High Serialization
disabled High Sleep mode
(SLEEP = 1)
Serial link is disabled and the
deserializer powers up in
sleep mode. Set SEREN = 1 or
CLINKEN = 1 in the serializer to
start the serial link and wake up
the deserializer.
3 High Serialization
disabled Low Normal
(SLEEP = 0)
Both devices power up in normal
mode with the serial link disabled.
Set SEREN = 1 or CLINKEN = 1 in
the serializer to start the serial link.
4 Low Serialization
enabled High In sleep mode
(SLEEP = 1)
The deserializer starts in sleep
mode. Link autostarts upon seri-
alizer power-up. Use this case
when the deserializer powers up
before the serializer.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
43
Case 3: Remote Side Autostart Mode
After power-up or when PWDN transitions from low to
high, the remote device (deserializer) starts up and tries
to lock to an incoming serial signal with sufficient power.
The host side (serializer) is in standby mode and does
not try to establish a link. Use the FC and program the
serializer to set SEREN = 1 (and apply a stable clock
signal) to establish a video link or CLINKEN = 1 to estab-
lish the configuration link. In this case, the deserializer
ignores the short wake-up signal sent from the serializer.
Case 4: Remote Side in Sleep Mode
After power-up or when PWDN transitions from low to
high, the remote device (deserializer) starts up in sleep
mode. The high-speed link establishes automatically
after the serializer powers up with a stable clock signal
and sends a wake-up signal to the deserializer. Use this
mode in applications where the deserializer powers up
before the serializer.
Image-Sensing Applications
For image-sensing applications, connect the FC to the
deserializer and set CDS = high for both the serializer
and deserializer. The deserializer powers up normally
(SLEEP = 0) and continuously tries to lock to a valid
serial input. Table 14 summarizes both startup cases,
based on the state of the serializer’s AUTOS pin.
Case 1: Autostart Mode
After power-up, or when PWDN transitions from low to
high, the serializer locks to a stable input clock and
sends the high-speed data to the deserializer. The dese-
rializer locks to the serial data and outputs the video data
and clock.
Figure 30. Serializer State Diagram, CDS = Low (LCD Application)
POWER-DOWN
OR POWER-OFF
POWER-ON
IDLE
CONFIG LINK
OPERATING
ALL STATES VIDEO
LINK LOCKING
VIDEO LINK
UNLOCKED
AUTOS PIN
SETTING
LOW
HIGH
1
0
SEREN BIT
POWER-UP VALUE
PWDN = LOW OR
POWER-OFF
SEREN = 1,
PCLKIN RUNNING
SEREN = 0, OR
NO PCLKIN
SEREN = 0,
NO PCLKIN
PWDN = HIGH
POWER-ON,
AUTOS = LOW
CONFIG
LINK STARTING PROGRAM
REGISTERS
VIDEO LINK
OPERATING
PRBSEN = 0
PRBSEN = 1
VIDEO LINK
PRBS TEST
CLINKEN = 0 OR
SEREN = 1
CLINKEN = 1
CLINKEN = 0 OR
SEREN = 1
CONFIG LINK
UNLOCKED
VIDEO LINK
LOCKED
LOCKED
CONFIG LINK
PWDN = HIGH,
POWER-ON
AUTOS = LOW
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
44
Case 2: Sleep Mode
After power-up or when PWDN transitions from low to
high, the serializer starts up in sleep mode. To wake up
the serializer, use the FC to send a GMSL protocol UART
frame containing at least three rising edges (e.g., 0x66),
at a bit rate no greater than 1Mbps. The low-power wake-
up receiver of the serializer detects the wake-up frame
over the reverse control channel and powers up. Reset
the sleep bit (SLEEP = 0) of the serializer using a regular
control-channel write packet to power up the device fully.
Send the sleep bit write packet at least 500Fs after the
wake-up frame. The serializer goes back to sleep mode
if its sleep bit is not cleared within 5ms (min) after detect-
ing a wake-up frame.
Figure 31. Deserializer State Diagram, CDS = Low (LCD Application)
Table 14. Start Mode Selection for Image-Sensing Application (CDS = High)
SLEEP
MS PIN
SETTING
LOW
HIGH
0
1
SLEEP BIT
POWER-UP VALUE
CONFIG LINK
OPERATING
PROGRAM
REGISTERS
POWER-OFF
HIGH TO LOW
SLEEP = 1, VIDEO LINK OR CONFIG
LINK NOT LOCKED AFTER 8ms
POWER-ON
IDLE
WAKE-UP
SIGNAL
SERIAL PORT
LOCKING
SIGNAL
DETECTED
CONFIG LINK
UNLOCKED
CONFIG LINK
LOCKED
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
0 SLEEP
0 SLEEP
ALL STATES
INT CHANGES FROM
LOW TO HIGH OR
PWDN = LOW OR
SEND INT TO
MAX9263
PWDN = HIGH,
POWER-ON
POWER-DOWN
OR
POWER-OFF
SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER
FC SETS SLEEP = 1
VIDEO LINK
OPERATING
PRBSEN = 0
PRBSEN = 1
VIDEO LINK
PRBS TEST
CASE AUTOS
(SERIALIZER)
SERIALIZER
POWER-UP STATE
DESERIALIZER
POWER-UP STATE LINK STARTUP MODE
1 Low Serialization
enabled
Normal
(SLEEP = 0) Autostart
2 High Sleep mode
(SLEEP = 1)
Normal
(SLEEP = 0)
The serializer is in sleep mode. Wake up
the serializer through the control channel
(FC attached to deserializer).
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
45
High-Bandwidth Digital
Content Protection (HDCP)
Note: The explanation of HDCP operation in this data
sheet is given as a guide for general understanding.
Implementation of HDCP in a product must meet the
requirements given in the HDCP System v1.3 Amendment
for GMSL available from DCP, LLC.
HDCP uses two main phases of operation: authentication
and the link integrity check. The FC starts authentica-
tion by writing to the START_AUTHENTICATION bit in
the serializer. The serializer generates a 64-bit random
number. The host FC first reads the 64-bit random num-
ber from the serializer and writes it to the deserializer.
The FC then reads the serializer public key selection
vector (AKSV) and writes it to the deserializer. The FC
Figure 32. Serializer State Diagram, CDS = High (Camera Application)
Figure 33. Deserializer State Diagram, CDS = High (Camera Application)
LOW
HIGH
1
0
0
SEREN SLEEP
1
POWER-UP VALUE
SEREN = 0
FOR > 8ms
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
WAKE-UP
SLEEP = 1
WAKE-UP SIGNAL
REVERSE LINK
CONFIG
LINK STARTED
CLINKEN = 0 OR
SEREN = 1
CLINKEN = 1
UNLOCKED
LOCKED
CONFIG LINK
CONFIG LINK
SLEEP = 0,
SLEEP POWER-ON
IDLE
POWER-OFF
ALL STATES PWDN = LOW OR
SLEEP = 1
POWER-DOWN
OR
POWER-OFF AUTOS = LOW
PWDN = HIGH,
POWER-ON VIDEO
LINK LOCKING
AUTOS PIN
SETTING
CONFIG LINK
OPERATING
PROGRAM
REGISTERS
CLINKEN = 0 OR
SEREN = 1
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
PRBSEN = 0
PRBSEN = 1
SEREN = 1,
PCLKIN RUNNING
SEREN = 0 OR
NO PCLKIN
SEREN = 0 OR
NO PCLKIN
PWDN = HIGH,
POWER-ON,
AUTOS = HIGH SLEEP = 0,
SLEEP = 1
POWER-ON
IDLE SERIAL PORT
LOCKING
ALL STATES
POWER-DOWN
OR
POWER-OFF
NO SIGNAL
DETECTED
PWDN = HIGH,
POWER-ON
CONFIG
LINK OPERATING
VIDEO LINK
OPERATING
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
PRBSEN = 0
PRBSEN = 1
VIDEO LINK
PRBS TEST
CONFIG LINK
UNLOCKED
CONFIG LINK
LOCKED
SIGNAL
DETECTED PROGRAM
REGISTERS
PWDN = LOW OR
POWER-OFF
(REVERSE
CHANNEL
ACTIVE)
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
46
then reads the deserializer KSV (BKSV) and writes it to
the serializer. The FC begins checking BKSV against the
revocation list. Using the cipher, the serializer and dese-
rializer calculate a 16-bit response value, R0 and R0’,
respectively. The GMSL amendment for HDCP reduces
the 100ms minimum wait time allowed for the receiver
to generate R0’ (specified in HDCP rev 1.3) to 128 pixel
clock cycles in the GMSL amendment.
There are two response value comparison modes: inter-
nal comparison and FC comparison. Set EN_INT_COMP = 1
to select internal comparison mode. Set EN_INT_COMP
= 0 to select FC comparison mode. In internal compari-
son mode, the FC reads the deserializer response R0’
and writes it to the serializer. The serializer compares
R0’ to its internally generated response value R0, and
sets R0_RI_MATCHED. In FC comparison mode, the FC
reads and compares the R0/R0’ values from the serial-
izer/deserializer.
During response value generation and comparison, the
host FC checks for a valid BKSV (having 20 1’s and 20
0’s, which is also reported in BKSV_INVALID) and checks
BKSV against the revocation list. If BKSV is not on the list,
and the response values match, the host authenticates
the link. If the response values do not match, the FC
resamples the response values (as described in HDCP
rev 1.3 Appendix C). If resampling fails, the FC restarts
authentication by setting the RESET_HDCP bit in the
serializer. If BKSV appears on the revocation list, the
host cannot transmit data that requires protection. The
host knows when the link is authenticated and decides
when to output data requiring protection. The FC per-
forms a link integrity check every 128 frames or every 2
seconds Q0.5 seconds. The serializer/deserializer gener-
ate response values every 128 frames. These values are
compared internally (internal comparison mode) or can
be compared in the host FC.
In addition, the serializer/deserializer provide response
values for the enhanced link verification. Enchanced
link verification is an optional method of link verification
for faster detection of loss of synchronization. For this
option, the serializer and deserializer generate 8-bit
enhanced link verification response values, PJ and PJ’,
every 16 frames. The host must detect three consecutive
PJ/PJ’ mismatches before resampling.
Encryption Enable
The GMSL link transfers either encrypted or nonen-
crypted data. To encrypt data, the host FC sets the
encryption enable (ENCRYPTION_ENABLE) bit in
both the serializer and deserializer. The FC must set
ENCRYPTION_ENABLE in the same VSYNC cycle in
both the serializer and deserializer (no internal VSYNC
falling edges between the two writes). The same timing
applies when clearing ENCRYPTION_ENABLE to disable
encryption.
Note: ENCRYPTION_ENABLE enables/disables encryp-
tion on the GMSL irrespective of the content. To comply
with HDCP, the FC must not allow content requiring
encryption to cross the GMSL unencrypted. See the
Force Video/Force Audio Data section.
The FC must complete the authentication process before
enabling encryption. In addition, encryption must be
disabled before starting a new authentication session.
VSYNC Detection
If the FC cannot detect the VSYNC falling edge, it can
use the serializer’s VSYNC_DET register bit. The host
FC first writes 0 to the VSYNC_DET bit. The serializer
then sets VSYNC_DET = 1 once it detects an internal
VSYNC falling edge (which may correspond to an exter-
nal VSYNC rising edge if INVVSYNC of the serializer is
set). The FC continuously reads VSYNC_DET and waits
for the next internal VSYNC falling edge before setting
ENCRYPTION_ENABLE. Poll VSYNC_DET fast enough
to allow time to set ENCRYPTION_ENABLE in both the
serializer/deserializer within the same VSYNC cycle.
Synchronization of Encryption
The video vertical sync (VSYNC) synchronizes the start
of encryption. Once encryption has started, the GMSL
generates a new encryption key for each frame and each
line, with the internal falling edge of VSYNC and HSYNC.
Rekeying is transparent to data and does not disrupt the
encryption of video or audio data.
Repeater Support
The serializer/deserializer have features to build an
HDCP repeater. An HDCP repeater receives and
decrypts HDCP content and then encrypts and transmits
on one or more downstream links. A repeater can also
use decrypted HDCP content (for example to display
on a screen). To support HDCP repeater authentication
protocol, the deserializer has a REPEATER register bit.
This register bit must be set to 1 by a FC (most likely on
repeater module). Both the serializer and deserializer use
SHA-1 hash value calculation over the assembled KSV
lists. HDCP GMSL links support a maximum 15 receivers
(total number including the ones in repeater modules). If
the total number of downstream receivers exceeds 14,
the FC must set the MAX_DEVS_EXCEEDED register bit
when it assembles the KSV list.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
47
Force Video/Force Audio Data
The serializer masks audio and video data through two
control bits: FORCE_AUDIO and FORCE_VIDEO. Set
FORCE_VIDEO = 1 to transmit the 24-bit data word in
the DFORCE register instead of the video data received
at the serializer video inputs. Set FORCE_AUDIO = 1 to
transmit 0 instead of the SD input (SCK and WS continue
to be output from the deserializer). Use these features to
blank out the screen and mute the audio.
HDCP Authentication Procedures
The serializer generates a 64-bit random number
exceeding the HDCP requirement. The serializer/dese-
rializer internal one-time programmable (OTP) memo-
ries contain unique HDCP keyset programmed at the
factory. The host FC initiates and controls the HDCP
authentication procedure. The serializer and deserializer
generate HDCP authentication response values for the
verification of authentication. Use the following proce-
dures to authenticate the HDCP-GMSL encryption. Refer
to the HDCP 1.3 Amendment for GMSL for details. The
FC must perform link integrity checks while encryption is
enabled. See the Link Integrity Check section. Any event
that indicates that the deserializer has lost link synchro-
nization should retrigger authentication. The FC must
first write 1 to RESET_HDCP bit in the serializer before
starting a new authentication attempt.
HDCP Protocol Summary
Tables 15, 16, and 17 list the summaries of the HDCP
protocol. These tables serve as an implementation guide
only. Meet the requirements in the GMSL amendment for
HDCP to be in full compliance.
Table 15. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a
Repeater)—First Part of the HDCP Authentication Protocol
NO. µC SERIALIZER DESERIALIZER
1Initial state after power-up. Powers up waiting for
HDCP authentication.
Powers up waiting for
HDCP authentication.
2
Makes sure that A/V data not requiring protection (low-value
content) is available at the serializer inputs (such as blue or
informative screen). Alternatively, uses the FORCE_VIDEO
and FORCE_AUDIO bits of the serializer to mask A/V data
at the input of the serializer. Starts the link by writing SEREN
= H or the link starts automatically if AUTOS is low.
— —
3 —
Starts serialization and
transmits low-value content
A/V data.
Locks to incoming data
stream and outputs low-
value content A/V data.
4Reads the locked bit of the deserializer and ensures that
the link is established. — —
5Optionally writes a random-number seed to the serializer.
Combines the seed with
an internally generated
random number. If no seed
is provided, only internal
random number is used.
—
6
If HDCP encryption is required, starts authentication by
writing 1 to the START_AUTHENTICATION bit of the
serializer.
Generates (stores) AN
and resets the
START_AUTHENTICATION
bit to 0.
—
7Reads AN and AKSV from the serializer and writes to the
deserializer. —Generates R0’ triggered by
the FC’s write of AKSV.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
48
Table 15. Startup, HDCP Authentication, and Normal Operation (Deserializer is not a
Repeater)—First Part of the HDCP Authentication Protocol (continued)
Table 16. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption
is Enabled
NO. µC SERIALIZER DESERIALIZER
8Reads the BKSV and REPEATER bit from the deserializer
and writes to the serializer.
Generates R0, triggered by
the FC’s write of BKSV. —
9
Reads the INVALID_BKSV bit of the serializer and continues
with authentication if it is 0. Authentication can be restarted
if it fails (set RESET_HDCP = 1 before restarting authentica-
tion).
— —
10
Reads R0’ from the deserializer and reads R0 from the seri-
alizer. If they match, continues with authentication;
otherwise, retries up to two more times (optionally, the seri-
alizer comparison can be used to detect if R0/R0’ match).
Authentication can be restarted if it fails (set the
RESET_HDCP = 1 before restarting authentication).
— —
11
Waits for the VSYNC falling edge (internal to the serializer)
and then sets the ENCRYPTION_ENABLE bit to 1 in the
deserializer and the serializer (if the FC is not able to
monitor VSYNC, it can utilize the VSYNC_DET bit in the
deserializer).
Encryption is enabled after
the next VSYNC falling
edge.
Decryption is enabled after
the next VSYNC falling
edge.
12
Checks that BKSV is not in the Key Revocation list and
continues if it is not. Authentication can be restarted if it fails.
Note: Revocation list check can start after BKSV is read in
step 8.
— —
13 Starts transmission of A/V content that needs protection.
Performs HDCP encryption
on high-value content A/V
data.
Performs HDCP decryption
on high-value content A/V
data.
NO. µC SERIALIZER DESERIALIZER
1 —
Generates Ri and updates
the RI register every 128
VSYNC cycles.
Generates Ri’ and updates
the RI’ register every 128
VSYNC cycles.
2 — Continues to encrypt and
transmit A/V data.
Continues to receive, decrypt,
and output A/V data.
3Every 128 video frames (VSYNC cycles) or every 2s. — —
4Reads RI from the serializer. — —
5Reads RI’ from the deserializer. — —
6
Reads RI again from the serializer and ensures it is
stable (matches the previous RI that it has read from the
serializer). If RI is not stable, go back to step 5.
— —
7If RI matches RI’, link integrity check is successful, go
back to step 3. — —
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
49
Table 16. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption
is Enabled (continued)
Table 17. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After
Encryption is Enabled
NO. µC SERIALIZER DESERIALIZER
8
If RI does not match RI’, link integrity check fails. After
the detection of failure of link integrity check, the FC
ensures that A/V data not requiring protection (low-value
content) is available at the serializer inputs (such as blue
or informative screen). Alternatively, the FORCE_VIDEO
and FORCE_AUDIO bits of the serializer can be used to
mask the A/V data input of the serializer.
— —
9Writes 0 to the ENCRYPTION_ENABLE bit of the
serializer and deserializer.
Disables encryption and
transmits low-value content
A/V data.
Disables decryption and
outputs low-value content
A/V data.
10
Restarts authentication by writing 1 to the
RESET_HDCP bit followed by writing 1 to the
START_AUTHENTICATION bit in the serializer.
— —
NO. µC SERIALIZER DESERIALIZER
1 —
Generates Pj and updates
PJ register every 16
VSYNC cycles.
Generates Pj’ and updates
PJ’ register every 16
VSYNC cycles.
2 — Continues to encrypt and
transmit A/V data.
Continues to receive,
decrypt, and output A/V
data.
3Every 16 video frames: Reads PJ from the serializer and PJ’
from the deserializer. — —
4If PJ matches PJ’, the enhanced link integrity check is suc-
cessful, go back to step 3. — —
5
If there is a mismatch, retry up to two more times from step
3. Enhanced link integrity check fails after three mismatch-
es. After the detection of failure of enhanced link integrity
check, the FC ensures that the A/V data not requiring
protection (low-value content) is available at the serializer
inputs (such as blue or informative screen). Alternatively,
the FORCE_VIDEO and FORCE_AUDIO bits of the serializer
can be used to mask the A/V data input of the serializer.
— —
6Writes 0 to the ENCRYPTION_ENABLE bit of the serializer
and the deserializer.
Disables encryption and
transmits low-value content
A/V data.
Disables decryption and
outputs low-value content
A/V data.
7
Restarts authentication by writing 1 to the RESET_HDCP bit
followed by writing 1 to the START_AUTHENTICATION bit in
the serializer.
— —
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
50
Example Repeater Network—Two µCs
The following example has one repeater and two FCs
(Figure 34). Table 18 summarizes the authentication
operation.
Table 18. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol
Figure 34. Example Network with One Repeater and Two µCs—TXs are for the Serializer, RXs are for the Deserializer
VIDEO CONNECTION
BD-DRIVE
TX_B1 RX_R1
RX_R2
TX_R1 RX_D1
TX_R2
µC_B
µC_R
REPEATER DISPLAY 1
RX_D2
DISPLAY 2
MEMORY
WITH SRM
VIDEO
ROUTING
CONTROL CONNECTION 1 (µC_B IN BD-DRIVE IS MASTER)
CONTROL CONNECTION 2 (µC_R IN REPEATER IS MASTER)
NO. µC_B µC_R
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
1Initial state after power-up. Initial state after power-up.
All: Power-up
waiting for HDCP
authentication.
All: Power-up
waiting for HDCP
authentication.
2 —
Writes REPEATER = 1 in RX_R1.
Retries until proper acknowledge
frame is received.
Note: This step must be completed
before the first part of authentica-
tion is started between TX_B1 and
RX_R1 by FC_B (step 7). To satisfy
this requirement, for example:
RX_R1 can be held at power-down
until FC_R is ready to write the
REPEATER bit.
Or, the FC_B can poll FC_R before
starting authentication.
— —
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
51
Table 18. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
NO. µC_B µC_R
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
3
Makes sure that the A/V data not
requiring protection (low-value
content) is available at the TX_B1
inputs (such as blue or informative
screen). Alternatively, the FORCE_
VIDEO and FORCE_AUDIO bits of
TX_B1 can be used to mask the
A/V data input of TX_B1. Starts the
link between TX_B1 and RX_R1 by
writing SEREN = H to TX_B1, or link
starts automatically if AUTOS is low.
—
TX_B1: Starts serial-
ization and transmits
low-value content
A/V data.
RX_R1: Locks to
incoming data
stream and outputs
low-value content
A/V data.
4 —
Starts all downstream links by writ-
ing SEREN = H to TX_R1, TX_R2,
or links start automatically if AUTOS
of transmitters are low.
TX_R1, TX_R2:
Starts serialization
and transmits low-
value content A/V
data.
RX_D1, RX_D2:
Locks to incoming
data stream and
outputs low-value
content A/V data.
5
Reads the locked bit of RX_R1 and
ensures that link between TX_B1
and RX_R1 is established.
Reads the locked bit of RX_D1
and makes sure that link between
TX_R1 and RX_D1 is established.
Reads the locked bit of RX_D2 and
ensures that link between TX_R2
and RX_D2 is established.
— —
6Optionally, writes a random-number
seed to TX_B1.
Writes 1 to the GPIO_0_FUNCTION
and GPIO_1_FUNCTION bits in
RX_R1 to change the GPIO
functionality to be used for HDCP
purpose. Optionally, writes a
random-number seed to TX_R1
and TX_R2.
— —
7
Starts and completes the first
part of the authentication protocol
between TX_B1, RX_R1. See steps
6–10 in Table 15.
—
TX_B1: According to
the commands from
FC_B, generates
AN, computes R0.
RX_R1: According
to the commands
from FC_B, com-
putes R0’.
8 —
When GPIO_1 = 1 is detected, starts
and completes the first part of the
authentication protocol between
(TX_R1, RX_D1) and (TX_R2, RX_D2)
links. See steps 6–10 in Table 15.
TX_R1, TX_R2:
According to the
commands from
FC_R, generates
AN, computes R0.
RX_D1, RX_D2:
According to the
commands from
FC_R, computes
R0’.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
52
Table 18. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
NO. µC_B µC_R
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
9
Waits for the VSYNC falling edge
and then enables encryption on the
(TX_B1, RX_R1) link. Full
authentication is not yet complete,
so it ensures that A/V content that
needs protection is not transmitted.
Since REPEATER = 1 was read
from RX_R1, the second part of
authentication is required.
—
TX_B1: Encryption
is enabled after the
next VSYNC falling
edge.
RX_R1: Decryption
is enabled after the
next VSYNC falling
edge.
10 —
When GPIO_0 = 1 is detected,
enables encryption on the (TX_R1,
RX_D1) and (TX_R2, RX_D2) links.
TX_R1, TX_R2:
Encryption is
enabled after the
next VSYNC falling
edge.
RX_D1, RX_D2:
Decryption is
enabled after the
next VSYNC falling
edge.
11
Waits for some time to allow FC_R
to make the KSV list ready in
RX_R1. Then polls (reads) the
KSV_LIST_READY bit of RX_R1
regularly until the proper acknowl-
edge frame is received and the bit
is read as 1.
Blocks the control channel from the
FC_B side by setting REVCCEN =
FWDCCEN = 0 in RX_R1. Retries
until the proper acknowledge frame
is received.
—
RX_R1: Control
channel from the
serializer side
(TX_B1) is blocked
after FWDCCEN =
REVCCEN = 0 is
written.
12
Writes BKSVs of RX_D1 and RX_D2
to the KSV list in RX_R1. Then cal-
culates and writes the BINFO regis-
ter of RX_R1.
—
RX_R1: Triggered
by FC_R’s write of
BINFO, calculates
the hash-value,
V’, on the KSV list,
BINFO, and the
secret-value M0’.
13
Writes 1 to the KSV_LIST_READY
bit of RX_R1 and then unblocks the
control channel from the FC_B side
by setting REVCCEN = FWDCCEN
= 1 in RX_R1.
—
RX_R1: Control
channel from the
serializer side (TX_
B1) is unblocked
after FWDCCEN =
REVCCEN = 1 is
written.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
53
Detection and Action Upon
New Device Connection
When a new device is connected to the system, the
device must be authenticated and the device’s KSV
checked against the revocation list. The downstream
FCs can set the NEW_DEV_CONN bit of the upstream
receiver and invoke an interrupt to notify upstream FCs.
Notification of Start of Authentication and
Enable of Encryption to Downstream Links
HDCP repeaters do not immediately begin authentication
upon startup or detection of a new device, but instead
wait for an authentication request from the upstream
transmitter/repeaters.
Use the following procedure to notify downstream links of
the start of a new authentication request:
1) Host FC begins authentication with the HDCP repeat-
er’s input receiver.
2) When AKSV is written to HDCP repeater’s input
receiver, its AUTH_STARTED bit is automatically set
and its GPIO1 goes high (if GPIO1_FUNCTION is set
to high).
3) HDCP repeater’s FC waits for a low to high transition
on HDCP repeater input receiver’s AUTH_STARTED
bit and/or GPIO1 (if configured) and starts authentica-
tion downstream.
4) HDCP repeater’s FC resets AUTH_STARTED bit.
Set GPIO0_FUNCTION to high to have GPIO0 follow the
ENCRYPTION_ENABLE bit of the receiver. The repeater
FC can use this function to be notified when encryption
is enabled/disabled by an upstream FC.
Table 18. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
NO. µC_B µC_R
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
14
Reads the KSV list and BINFO from
RX_R1 and writes them to TX_B1. If
any of the MAX_DEVS_EXCEEDED
or MAX_CASCADE_EXCEEDED
bits is 1, then authentication fails.
Note: BINFO must be written after
the KSV list.
—
TX_B1: Triggered
by FC_B’s write of
BINFO, calculates
hash-value V on the
KSV list, BINFO,
and the secret-value
M0.
—
15
Reads V from TX_B1 and V’ from
RX_R1. If they match, continues
with authentication; otherwise,
retries up to two more times.
— — —
16
Searches for each KSV in the KSV
list and BKSV of RX_R1 in the Key
Revocation list.
— — —
17
If keys are not revoked, the second
part of the authentication protocol
is completed.
— — —
18 Starts transmission of A/V content
that needs protection. —
All: Perform HDCP
encryption on high-
value A/V data.
All: Perform HDCP
decryption on high-
value A/V data.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
54
Applications Information
Error Checking
The deserializer checks the serial link for errors and
stores the number of detected decoding errors in the
8-bit register DECERR (0x0D). If a large number of
8b/10b decoding or parity errors are detected within a
short duration (error rate R 1/4), the deserializer loses
lock and stops the error counter. The deserializer then
attempts to relock to the serial data. DECERR resets
upon successful video link lock, successful readout of
DECERR (through UART), or whenever auto error reset
is enabled. The deserializer does not check for decod-
ing or parity errors during the internal PRBS test, and
DECERR is reset to 0x00.
ERR Output
The deserializer has an open-drain ERR output. This
output asserts low whenever the number of decoding
errors exceeds the error threshold ERRTHR (0x0C)
during normal operation, or when at least 1 PRBS error
is detected during PRBS test. ERR reasserts high when-
ever DECERR (0x0D) resets, due to DECERR readout,
video link lock, or auto error reset.
Auto Error Reset
The default method to reset errors is to read the respec-
tive error registers in the deserializer (0x0D, 0x0E). Auto
error reset clears the decoding error counter DECERR
and the ERR output ~1Fs after ERR goes low. Auto error
reset is disabled on power-up. Enable auto error reset
through AUTORST (0x06, D6). Auto error reset does not
run when the device is in PRBS test mode.
PRBS Self-Test
The serializer/deserializer link includes a PRBS pattern
generator and bit-error verification function. First, dis-
able the glitch filters (set DISVSFILT, DISHSFILT to 1) in
the deserializer. Next, disable VSYNC/HSYNC inversion
in both the serializer and deserializer (set INVVSYNC,
INVHSYNC to 0). Then, set PRBSEN = 1 (0x04, D5) in the
serializer and then the deserializer to start the PRBS test.
Set PRBSEN = 0 (0x04, D5) first in the deserializer and
then the serializer to exit the PRBS self-test. The deseri-
alizer uses an 8-bit register (0x0E) to count the number
of detected errors. The control link also controls the start
and stop of the error counting. During PRBS mode, the
device does not count decoding errors and the deserial-
izer’s ERR output reflects PRBS errors only.
Microcontrollers on Both Sides
of the GMSL Link (Dual µC Control)
Usually the microcontroller is either on the serializer side
for video-display applications or on the deserializer side
for image-sensing applications. For the former case,
both the CDS pins of the serializer/deserializer are set to
low, and for the later case, the CDS pins are set to high.
However, if the CDS pin of the serializer is low and the
same pin of the deserializer is high, then the serializer/
deserializer connect to both FCs simultaneously. In such
a case, the FCs on either side can communicate with the
serializer and deserializer.
Contentions of the control link can happen if the FCs
on both sides are using the link at the same time. The
serializer/deserializer do not provide the solution for
contention avoidance. The serializer/deserializer do not
send an acknowledge frame when communication fails
due to contention. Users can always implement a
higher layer protocol to avoid the contention. In addi-
tion, if UART communication across the serial link is not
required, the FCs can disable the forward and reverse
control channel through the FWDCCEN and REVCCEN
bits (0x04, D[1:0]) in the serializer/deserializer. UART
communication across the serial link is stopped and
contention between FCs no longer occurs. During dual
FCs operation, if one of the CDS pins on either side
changes state, the link resumes the corresponding state
described in the Link Startup Procedure section.
As an example of dual FC use in an image-sensing
application, the serializer can be in sleep mode and
waiting for wake-up by the deserializer. After wake-up,
the serializer-side FC sets the serializer’s CDS pin low
and assumes master control of the serializer’s registers.
HSYNC/VSYNC Glitch Filter
The deserializer contains one-cycle glitch filters on
HSYNC and VSYNC. This eliminates single-cycle glitch-
es in HSYNC and VSYNC that can cause a loss of HDCP
synchronization between the serializer and deserializer
while encryption is enabled. The glitch filters are on by
default. Write to D[1:0] of register 0x08 in the deserializer
to disable the glitch filters for HSYNC or VSYNC.
The glitch filter, when active, suppresses all single-cycle
wide pulses sent. Disable the glitch filter before running
PRBS BER tests. The internal BER checker assumes that
the incoming bit stream is unaltered PRBS data.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
55
Jitter-Filtering PLL
In some applications, the parallel bus input clock to the
serializer (PCLKIN) includes noise, which reduces link
reliability. The serializer has a narrowband jitter-filtering
PLL to attenuate frequency components outside the
PLL’s bandwidth (< 100kHz typ). Enable the jitter-filtering
PLL by setting DISFPLL = 0 (0x05, D6).
Changing the Clock Frequency
Both the video clock rate (fPCLK_) and the control-
channel clock rate (fUART) can be changed on-the-fly
to support applications with multiple clock speeds. It is
recommended to enable the serial link after the video
clock stabilizes. Stop the video clock for 5Fs and restart
the serial link or toggle SEREN after each change in
the video clock frequency to recalibrate any automatic
settings if a clean frequency change cannot be guaran-
teed. The reverse control channel remains unavailable
for 350Fs after serial link start or stop. Limit on-the-fly
changes in fUART to factors of less than 3.5 at a time to
ensure that the device recognizes the UART sync pat-
tern. For example, when lowering the UART frequency
from 1Mbps to 100kbps, first send data at 333kbps and
then at 100kbps to have reduction ratios of 3 and 3.333,
respectively.
Do not interrupt PCLKIN or change its frequency while
encryption is enabled. Otherwise HDCP synchronization
is lost and authentication must be repeated. To change
the PCLK frequency, stop the high value content A/V
data. Then disable encryption in the serializer/deserial-
izer within the same VSYNC cycle—encryption stops
at the next VSYNC falling edge. PCLKIN can now be
changed/stopped. Reenable encryption before sending
any high value content A/V data.
Fast Detection of Loss-of-Synchronization
A measure of link quality is the recovery time from loss
of HDCP synchronization. With the GMSL, it is likely that
HDCP synchronization will not be lost unless the GMSL
synchronization is lost. The host can be quickly notified
of loss-of-lock by connecting the deserializer’s LOCK
output to the INT input. If other sources use the interrupt
input, such as a touch-screen controller, the FC can
implement a routine to distinguish between interrupts
from loss-of-sync and normal interrupts. Reverse con-
trol-channel communication does not require an active
forward link to operate and accurately tracks the LOCK
status of the GMSL link. LOCK asserts for video link only
and not for the configuration link.
Programming the Device Addresses
Both the serializer and the deserializer have programma-
ble device addresses. This allows multiple GMSL devic-
es, along with I2C peripherals, to coexist on the same
control channel. The serializer device address is stored
in register 0x00 of each device, while the deserializer
device address is stored in register 0x01 of each device.
To change the device address, first write to the device
whose address changes (register 0x00 of the serializer
for serializer device address change, or register 0x01 of
the deserializer for deserializer device address change).
Then write the same address into the corresponding reg-
ister on the other device (register 0x00 of the deserializer
for serializer device address change, or register 0x01 of
the serializer for deserializer device address change).
Configuration Blocking
The serializer/deserializer can block changes to their
non-HDCP registers. Set CFGBLOCK to make all non-
HDCP registers as read only. Once set, the registers
remain blocked until the supplies are removed or until
PWDN is low.
Backward Compatibility
The serializer and deserializer are backward compatible
with the non-HDCP MAX9259 and MAX9260. The pin-
outs and packages are the same for both devices. See
Table 3 and the Pin Description section for backward-
compatible pin mapping.
Key Memory
Each device has a unique HDCP key set that is stored
in secure on-chip nonvolatile memory (NVM). The HDCP
key set consists of forty 56-bit private keys and one
40-bit public key. The NVM is qualified for automotive
applications.
GPIOs
The deserializer has two open-drain GPIOs available.
When not used for HDCP purposes, GPIO1OUT and
GPIO0OUT (0x06, D3 and D1) set the output state of the
GPIOs. See the Notification of Start of Authentication and
Enable of Encryption to Downstream Links section. The
GPIO input buffers are always enabled. The input states
are stored in GPIO1 and GPIO0 (0x06, D2 and D0). Set
GPIO1OUT/GPIO0OUT to 1 when using GPIO1/GPIO0
as an input.
Line-Fault Detection
The line-fault detector in the serializer monitors for line
failures such as short to ground, short to battery, and
open link for system fault diagnosis. Figure 3 shows the
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
56
required external resistor connections. LFLT = low when
a line fault is detected and LFLT goes high when the line
returns to normal. The line-fault type is stored in 0x08,
D[3:0] of the serializer. Filter LFLT with the FC to reduce
the detector’s susceptibility to brief ground shifts. The
fault detector threshold voltages are referenced to the
serializer ground. Additional passive components set
the DC level of the cable (Figure 3). If the serializer and
deserializer grounds are different, the link DC voltage
during normal operation can vary and cross one of the
fault detection thresholds. For the fault detection circuit,
select the resistor’s power rating to handle a short to the
battery.
To detect the short-together case, refer to Application
Note 4709: GMSL line-fault detection. Table 19 lists the
mapping for line-fault types.
Staggered Parallel Data Outputs
The deserializer staggers the parallel data outputs to
reduce EMI and noise. Staggering outputs also reduces
the power-supply transient requirements. By default, the
deserializer staggers outputs according to Table 20.
Disable output staggering through the DISSTAG bit
(0x06, D7).
Internal Input Pulldowns
The control and configuration inputs on the serial-
izer/deserializer include a pulldown resistor to GND.
Pulldowns are disabled when the device is shut down
(PWDN = low) or put into sleep mode. Keep all inputs
driven or use external pullup/pulldown resistors to pre-
vent additional current consumption and undesired con-
figuration due to undefined inputs.
Choosing I2C/UART Pullup Resistors
Both I2C/UART open-drain lines require pullup resistors
to provide a logic-high level. There are tradeoffs between
power dissipation and speed, and a compromise made
in choosing pullup resistor values. Every device connect-
ed to the bus introduces some capacitance even when
the device is not in operation. I2C specifies 300ns rise
times to go from low to high (30% to 70%) for fast mode,
which is defined for data rates up to 400kbps (see the
I2C specifications in the Electrical Characteristics table
for details). To meet the fast-mode rise-time requirement,
choose the pullup resistors so that rise time tR = 0.85 x
RPULLUP x CBUS < 300ns. The waveforms are not recog-
nized if the transition time becomes too slow. The serial-
izer/deserializer support I2C/UART rates up to 1Mbps.
Table 19. Serializer Line-Fault Mapping*
Table 20. Staggered Output Delay
*For the short-together case, refer to Application Note 4709: MAX9259 GMSL line-fault detection.
REGISTER
ADDRESS BITS NAME VALUE LINE-FAULT TYPE
0x08
D[3:2] LFNEG
00 Negative cable wire shorted to supply voltage.
01 Negative cable wire shorted to ground.
10 Normal operation.
11 Negative cable wire disconnected.
D[1:0] LFPOS
00 Positive cable wire shorted to supply voltage.
01 Positive cable wire shorted to ground.
10 Normal operation.
11 Positive cable wire disconnected.
OUTPUT OUTPUT DELAY RELATIVE TO DOUT0 (ns)
DISSTAG = 0 DISSTAG = 1
DOUT0–DOUT5, DOUT21, DOUT22 0 0
DOUT6–DOUT10, DOUT23, DOUT24 0.5 0
DOUT11–DOUT15, DOUT25, DOUT26 1 0
DOUT16–DOUT20, DOUT27, DOUT28 1.5 0
PCLKOUT 0.75 0
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
57
AC-Coupling
AC-coupling isolates the receiver from DC voltages up to
the voltage rating of the capacitor. Four capacitors—two
at the serializer output and two at the deserializer input—
are needed for proper link operation and to provide
protection if either end of the cable is shorted to a high
voltage. AC-coupling blocks low-frequency ground shifts
and low-frequency common-mode noise.
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of
transmitted symbols cause signal transitions to start
from different voltage levels. Because the transition time
is finite, starting the signal transition from different volt-
age levels causes timing jitter. The time constant for an
AC-coupled link needs to be chosen to reduce droop
and jitter to an acceptable level. The RC network for an
AC-coupled link consists of the CML receiver termination
resistor (RTR), the CML driver termination resistor (RTD),
and the series AC-coupling capacitors (C). The RC time
constant for four equal-value series capacitors is (C x
(RTD + RTR))/4. RTD and RTR are required to match the
transmission line impedance (usually 100I). This leaves
the capacitor selection to change the system time con-
stant. Use at least 0.2FF high-frequency surface-mount
ceramic capacitors, with sufficient voltage rating to with-
stand a short to battery, to pass the lower speed reverse
control-channel signal. Use capacitors with a case size
less than 3.2mm x 1.6mm to have lower parasitic effects
to the high-speed signal.
Power-Supply Circuits and Bypassing
The serializer uses an AVDD and DVDD of 1.7V to 1.9V,
while the deserializer uses an AVDD and DVDD of 3.0V
to 3.6V. All single-ended inputs and outputs on the
serializer/deserializer derive power from an IOVDD of
1.7V to 3.6V, which scale with IOVDD. Proper voltage-
supply bypassing is essential for high-frequency circuit
stability.
Cables and Connectors
Interconnect for CML typically has a differential imped-
ance of 100I. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Twisted-pair and shielded twisted-pair
cables tend to generate less EMI due to magnetic-field
canceling effects. Balanced cables pick up noise as
common-mode rejected by the CML receiver. Table 21
lists the suggested cables and connectors used in the
GMSL link.
Board Layout
Separate the digital signals and CML high-speed sig-
nals to prevent crosstalk. Use a four-layer PCB with
separate layers for power, ground, CML, and digital sig-
nals. Layout PCB traces close to each other for a 100I
differential characteristic impedance. The trace dimen-
sions depend on the type of trace used (microstrip
or stripline). Note that two 50I PCB traces do not
have 100I differential impedance when brought close
together—the impedance goes down when the traces
are brought closer.
Route the PCB traces for a CML channel (there are two
conductors per CML channel) in parallel to maintain the
differential characteristic impedance. Avoid vias. Keep
PCB traces that make up a differential pair equal length
to avoid skew within the differential pair.
ESD Protection
The serializer/deserializer ESD tolerance is rated for
Human Body Model, IEC 61000-4-2, and ISO 10605. The
ISO 10605 and IEC 61000-4-2 standards specify ESD
tolerance for electronic systems. The serial link I/O are
tested for ISO 10605 ESD protection and IEC 61000-4-2
ESD protection. All pins are tested for the Human Body
Model. The Human Body Model discharge components
are CS = 100pF and RD = 1.5kI (Figure 35). The IEC
61000-4-2 discharge components are CS = 150pF and
RD = 330I (Figure 36). The ISO 10605 discharge com-
ponents are CS = 330pF and RD = 2kI (Figure 37).
Table 21. Suggested Connectors and
Cables for GMSL
Figure 35. Human Body Model ESD Test Circuit
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
1MI
RD
1.5kI
CS
100pF
VENDOR CONNECTOR CABLE
JAE MX38-FF A-BW-Lxxxxx
Nissei GT11L-2S F-2WME AWG28
Rosenberger D4S10A-40ML5-Z Dacar 538
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
58
Figure 36. IEC 61000-4-2 Contact Discharge ESD Test Circuit Figure 37. ISO 10605 Contact Discharge ESD Test Circuit
Table 22. Serializer GMSL Core Register Table (See Table 1)
CS
150pF STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
RD
330I
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
RD
2kI
CS
330pF
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x00
D[7:1] SERID XXXXXXX Serializer device address. 1000000
D0 CFGBLOCK 0Normal operation. 0
1Registers 0x00 to 0x1F are read only.
0x01 D[7:1] DESID XXXXXXX Deserializer device address. 1001000
D0 — 0 Reserved. 0
0x02
D[7:5] SS
000 No spread spectrum. Power-up default when SSEN
= low.
000, 001
001 Q0.5% spread spectrum. Power-up default when
SSEN = high.
010 Q1.5% spread spectrum.
011 Q2% spread spectrum.
100 No spread spectrum.
101 Q1% spread spectrum.
110 Q3% spread spectrum.
111 Q4% spread spectrum.
D4 AUDIOEN 0Disable I2S channel. 1
1Enable I2S channel.
D[3:2] PRNG
00 12.5MHz to 25MHz pixel clock.
11
01 25MHz to 50MHz pixel clock.
10 50MHz to 104MHz pixel clock.
11 Automatically detect the pixel clock range.
D[1:0] SRNG
00 0.5Gbps to 1Gbps serial-bit rate.
11
01 1Gbps to 2Gbps serial-bit rate.
10 2Gbps to 3.125Gbps serial-bit rate.
11 Automatically detect serial-bit rate.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
59
Table 22. Serializer GMSL Core Register Table (See Table 1) (continued)
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x03
D[7:6] AUTOFM
00 Calibrate spread-modulation rate only once after
locking.
00
01 Calibrate spread-modulation rate every 2ms after
locking.
10 Calibrate spread-modulation rate every 16ms after
locking.
11 Calibrate spread-modulation rate every 256ms after
locking.
D[5:0] SDIV
000000 Autocalibrate sawtooth divider.
000000
XXXXXX Manual SDIV setting. See the Manual Programming of
Spread-Spectrum Divider section.
0x04
D7 SEREN
0
Disable serial link. Power-up default when AUTOS =
high. Reverse control-channel communication remains
unavailable for 350Fs after the serializer starts/stops
the serial link.
0, 1
1
Enable serial link. Power-up default when AUTOS =
low. Reverse control-channel communication remains
unavailable for 350Fs after the serializer starts/stops
the serial link.
D6 CLINKEN 0Disable configuration link. 0
1Enable configuration link.
D5 PRBSEN 0Disable PRBS test. 0
1Enable PRBS test.
D4 SLEEP
0Normal mode (default value depends on CDS and
AUTOS pin values at power-up). 0, 1
1Activate sleep mode (default value depends on CDS
and AUTOS pin values at power-up).
D[3:2] INTTYPE
00 Base mode uses I2C peripheral interface.
0001 Base mode uses UART peripheral interface.
10, 11 Base mode peripheral interface disabled.
D1 REVCCEN
0Disable reverse control channel from deserializer
(receiving). 1
1Enable reverse control channel from deserializer
(receiving).
D0 FWDCCEN
0Disable forward control channel to deserializer
(sending). 1
1Enable forward control channel to deserializer
(sending).
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
60
Table 22. Serializer GMSL Core Register Table (See Table 1) (continued)
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x05
D7 I2CMETHOD
0 I2C conversion sends the register address.
0
1Disable sending of I2C register address
(command-byte-only mode).
D6 DISFPLL 0Filter PLL active. 1
1Filter PLL disabled.
D[5:4] CMLLVL
00 Do not use.
11
01 200mV CML signal level.
10 300mV CML signal level.
11 400mV CML signal level.
D[3:0] PREEMP
0000 Preemphasis off.
0000
0001 -1.2dB preemphasis.
0010 -2.5dB preemphasis.
0011 -4.1dB preemphasis.
0100 -6.0dB preemphasis.
0101 Do not use.
0110 Do not use.
0111 Do not use.
1000 1.1dB preemphasis.
1001 2.2dB preemphasis.
1010 3.3dB preemphasis.
1011 4.4dB preemphasis.
1100 6.0dB preemphasis.
1101 8.0dB preemphasis.
1110 10.5dB preemphasis.
1111 14.0dB preemphasis.
0x06 D[7:0] — 01000000 Reserved. 01000000
0x07 D[7:0] — 00100010 Reserved. 00100010
0x08
D[7:4] — 0000 Reserved. 0000
(read only)
D[3:2] LFNEG
00 Negative cable wire shorted to supply voltage.
10
(read only)
01 Negative cable wire shorted to ground.
10 Normal operation.
11 Negative cable wire disconnected.
D[1:0] LFPOS
00 Positive cable wire shorted to supply voltage.
10
(read only)
01 Positive cable wire shorted to ground.
10 Normal operation.
11 Positive cable wire disconnected.
0x0C D[7:0] — 01110000 Reserved. 01110000
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
61
Table 22. Serializer GMSL Core Register Table (See Table 1) (continued)
Table 23. Deserializer GMSL Core Register Table (See Table 2)
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x0D
D7 SETINT 0Set INT low when SETINT transitions from 1 to 0. 0
1Set INT high when SETINT transitions from 0 to 1.
D6 INVVSYNC 0Serializer does not invert DIN19/VS. 0
1Serializer inverts DIN19/VS.
D5 INVHSYNC 0Serializer does not invert DIN18/HS. 0
1Serializer inverts DIN18/HS.
D[4:0] — 00000 Reserved. 00000
0x1E D[7:0] ID 00000101 Device identifier (MAX9263 = 0x05). 00000101
(read only)
0x1F
D[7:5] — 000 Reserved. 000
(read only)
D4 CAPS 0Not HDCP capable. 1
(read only)
1HDCP capable.
D[3:0] REVISION XXXX Device revision. (read only)
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x00 D[7:1] SERID XXXXXXX Serializer device address. 1000000
D0 — 0 Reserved. 0
0x01
D[7:1] DESID XXXXXXX Deserializer device address. 1001000
D0 CFGBLOCK 0Normal operation. 0
1Registers 0x00 to 0x1F are read only.
0x02
D[7:6] SS
00 No spread spectrum. Power-up default when
SSEN = low.
00, 01
01 Q2% spread spectrum. Power-up default when
SSEN = high.
10 No spread spectrum.
11 Q4% spread spectrum.
D5 — 0 Reserved. 0
D4 AUDIOEN 0Disable I2S channel. 1
1Enable I2S channel.
D[3:2] PRNG
00 12.5MHz to 25MHz pixel clock.
11
01 25MHz to 50MHz pixel clock.
10 50MHz to 104MHz pixel clock.
11 Automatically detect the pixel clock range.
D[1:0] SRNG
00 0.5Gbps to 1Gbps serial-data rate.
11
01 1Gbps to 2Gbps serial-data rate.
10 2Gbps to 3.125Gbps serial-data rate.
11 Automatically detect serial-data rate.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
62
Table 23. Deserializer GMSL Core Register Table (See Table 2) (continued)
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x03
D[7:6] AUTOFM
00 Calibrate spread-modulation rate only once after
locking.
00
01 Calibrate spread-modulation rate every 2ms after
locking.
10 Calibrate spread-modulation rate every 16ms after
locking.
11 Calibrate spread-modulation rate every 256ms
after locking.
D5 — 0 Reserved. 0
D[4:0] SDIV
00000 Autocalibrate sawtooth divider.
00000
XXXXX Manual SDIV setting. See the Manual Programming
of Spread-Spectrum Divider section.
0x04
D7 LOCKED 0LOCK output is low. 0
(read only)
1LOCK output is high.
D6 OUTENB 0Enable outputs. 0
1Disable outputs.
D5 PRBSEN 0Disable PRBS test. 0
1Enable PRBS test.
D4 SLEEP
0Normal mode. Default value depends on CDS and
MS pin values at power-up. 0, 1
1Activate sleep mode. Default value depends on
CDS and MS pin values at power-up.
D[3:2] INTTYPE
00 Base mode uses I2C peripheral interface.
0001 Base mode uses UART peripheral interface.
10, 11 Base mode peripheral interface disabled.
D1 REVCCEN
0Disable reverse control channel to serializer
(sending). 1
1Enable reverse control channel to serializer
(sending).
D0 FWDCCEN
0Disable forward control channel from serializer
(receiving). 1
1Enable forward control channel from serializer
(receiving).
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
63
Table 23. Deserializer GMSL Core Register Table (See Table 2) (continued)
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x05
D7 I2CMETHOD
0 I2C conversion sends the register address.
0
1Disable sending of I2C register address
(command-byte-only mode).
D[6:5] HPFTUNE
00 7.5MHz equalizer highpass cutoff frequency.
01
01 3.75MHz cutoff frequency.
10 2.5MHz cutoff frequency.
11 1.87MHz cutoff frequency.
D4 PDHF 0High-frequency boosting enabled. 0
1High-frequency boosting disabled.
D[3:0] EQTUNE
0000 2.1dB equalizer boost gain.
0100, 1001
0001 2.8dB equalizer boost gain.
0010 3.4dB equalizer boost gain.
0011 4.2dB equalizer boost gain.
0100 5.2dB equalizer boost gain. Power-up default
when EQS = high.
0101 6.2dB equalizer boost gain.
0110 7dB equalizer boost gain.
0111 8.2dB equalizer boost gain.
1000 9.4dB equalizer boost gain.
1001 10.7dB equalizer boost gain. Power-up default
when EQS = low.
1010 11.7dB equalizer boost gain.
1011 13dB equalizer boost gain.
11XX Do not use.
0x06
D7 DISSTAG 0Enable staggered outputs. 0
1Disable staggered outputs.
D7 — 0 Reserved. 0
D6 AUTORST 0Do not automatically reset error registers and
outputs. 0
1Automatically reset error registers and outputs.
D5 DISINT 0Enable interrupt transmission to serializer. 0
1Disable interrupt transmission to serializer.
D4 INT 0INT input = low (read only). 0
(read only)
1INT input = high (read only).
D3 GPIO1OUT 0Output low to GPIO1. 1
1Output high to GPIO1.
D2 GPIO1 0GPIO1 is low. 1
(read only)
1GPIO1 is high.
D1 GPIO0OUT 0Output low to GPIO0. 1
1Output high to GPIO0.
D0 GPIO0 0GPIO0 is low. 1
(read only)
1GPIO0 is high.
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
64
Table 23. Deserializer GMSL Core Register Table (See Table 2) (continued)
X = Don’t care.
REGISTER
ADDRESS BITS NAME VALUE FUNCTION DEFAULT
VALUE
0x07 D[7:0] — 01010100 Reserved. 01010100
0x08
D[7:2] — 001100 Reserved. 001100
D1 DISVSFILT 0VSYNC glitch filter active. 0
1VSYNC glitch filter disabled.
D0 DISHSFILT 0HSYNC glitch filter active. 0
1HSYNC glitch filter disabled.
0x09 D[7:0] — 11001000 Reserved. 11001000
0x0A D[7:0] — 00010010 Reserved. 00010010
0x0B D[7:0] — 00100000 Reserved. 00100000
0x0C D[7:0] ERRTHR XXXXXXXX Error threshold for decoding errors. ERR = low
when DECERR > ERRTHR. 00000000
0x0D D[7:0] DECERR XXXXXXXX Decoding error counter. This counter remains
zero while the device is in PRBS test mode.
00000000
(read only)
0x0E D[7:0] PRBSERR XXXXXXXX PRBS error counter. 00000000
(read only)
0x12
D7 MCLKSRC 0MCLK derived from PCLK. See Table 5. 0
1MCLK derived from internal oscillator.
D[6:0] MCLKDIV 0000000 MCLK disabled. 0000000
XXXXXXX MCLK divider.
0x13 D[7:0] — 00010000 Reserved. 00010000
0x14
D7 INVVSYNC 0Deserializer does not invert DOUT19/VS. 0
1Deserializer inverts DOUT19/VS.
D6 INVHSYNC 0Deserializer does not invert DOUT18/HS. 0
1Deserializer inverts DOUT18/HS.
D[5:0] — 001001 Reserved. 001001
0x1E D[7:0] ID 00000110 Device identifier (MAX9264 = 0x06). 00000110
(read only)
0x1F
D[7:5] — 000 Reserved. 000
(read only)
D4 CAPS 0Not HDCP capable. 1
(read only)
1HDCP capable.
D[3:0] REVISION XXXX Device revision. (read only)
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
65
Table 24. Serializer HDCP Register Table (See Table 1)
REGISTER
ADDRESS
SIZE
(Bytes) NAME READ/
WRITE FUNCTION DEFAULT
VALUE (hex)
0x80 to 0x84 5 BKSV Read/write HDCP receiver KSV 0x0000000000
0x85 to 0x86 2 RI/RI’ Read/write
RI (read only) of the transmitter when
EN_INT_COMP = 0
RI’ (read/write) of the receiver when
EN_INT_COMP = 1
0x0000
0x87 1 PJ/PJ’ Read/write
PJ (read only) of the transmitter when
EN_INT_COMP = 0
PJ’ (read/write) of the receiver when
EN_INT_COMP = 1
0x00
0x88 to 0x8F 8 AN Read only Session random number (Read only)
0x90 to 0x94 5 AKSV Read only HDCP transmitter KSV (Read only)
0x95 1 ACTRL Read/write
D7 = PD_HDCP
1 = Power down HDCP circuits
0 = HDCP circuits normal
0x00
D6 = EN_INT_COMP
1 = Internal comparison mode
0 = FC comparison mode
D5 = FORCE_AUDIO
1 = Force audio data to 0
0 = Normal operation
D4 = FORCE_VIDEO
1 = Force video data DFORCE value
0 = Normal operation
D3 = RESET_HDCP
1 = Reset HDCP circuits, automatically set to 0
upon completion
0 = Normal operation
D2 = START_AUTHENTICATION
1 = Start authentication, automatically set to 0
once authentication starts
0 = Normal operation
D1 = VSYNC_DET
1 = Internal falling edge on DIN19/VS detected
0 = No falling edge detected
D0 = ENCRYPTION_ENABLE
1 = Enable encryption
0 = Disable encryption
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
66
Table 24. Serializer HDCP Register Table (See Table 1) (continued)
REGISTER
ADDRESS
SIZE
(Bytes) NAME READ/
WRITE FUNCTION DEFAULT
VALUE (hex)
0x96 1 ASTATUS Read only
D[7:4] = Reserved
0x00
(read only)
D3 = V_MATCHED
1 = V matches V’ (when EN_INT_COMP = 1)
0 = V does not match V’ or EN_INT_COMP = 0
D2 = PJ_MATCHED
1 = PJ matches PJ’ (when EN_INT_COMP = 1)
0 = PJ does not match PJ’ or EN_INT_COMP = 0
D1 = R0_RI_MATCHED
1 = RI matches RI’ (when EN_INT_COMP = 1)
0 = RI does not match RI’ or EN_INT_COMP = 0
D0 = BKSV_INVALID
1 = BKSV is not valid
0 = BKSV is valid
0x97 1 BCAPS Read/write
D[7:1] = Reserved
0x00
D0 = REPEATER
1 = Set to 1 if device is a repeater
0 = Set to 0 if device is not a repeater
0x98 to 0x9C 5 ASEED Read/write Internal random-number generator optional seed
value 0x0000000000
0x9D to 0x9F 3 DFORCE Read/write
Forced video data transmitted when
FORCE_VIDEO = 1
R[7:0] = DFORCE[7:0]
G[7:0] = DFORCE[15:8]
B[7:0] = DFORCE[23:16]
0x000000
0xA0 to 0xA3 4V.H0,
V’.H0 Read/write
H0 part of SHA-1 hash value
V (read only) of the transmitter when
EN_INT_COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
0x00000000
0xA4 to 0xA7 4V.H1,
V’.H1 Read/write
H1 part of SHA-1 hash value
V (read only) of the transmitter when
EN_INT_COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
0x00000000
0xA8 to 0xAB 4V.H2,
V’.H2 Read/write
H2 part of SHA-1 hash value
V (read only) of the transmitter when
EN_INT_COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
0x00000000
0xAC to 0xAF 4V.H3,
V’.H3 Read/write
H3 part of SHA-1 hash value
V (read only) of the transmitter when EN_INT_
COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
0x00000000
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
67
Table 24. Serializer HDCP Register Table (See Table 1) (continued)
REGISTER
ADDRESS
SIZE
(Bytes) NAME READ/
WRITE FUNCTION DEFAULT
VALUE (hex)
0xB0 to 0xB3 4V.H4,
V’.H4 Read/write
H4 part of SHA-1 hash value
V (read only) of the transmitter when
EN_INT_COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
0x00000000
0xB4 to 0xB5 2 BINFO Read/write
D[15:12] = Reserved
0x0000
D11 = MAX_CASCADE_EXCEEDED
1 = Set to 1 if more than 7 cascaded devices
attached
0 = Set to 0 if 7 or fewer cascaded devices
attached
D[10:8] = DEPTH
Depth of cascaded devices
D7 = MAX_DEVS_EXCEEDED
1 = Set to 1 if more than 14 devices attached
0 = Set to 0 if 14 or fewer devices attached
D[6:0] = DEVICE_COUNT
Number of devices attached
0xB6 1 GPMEM Read/write General-purpose memory byte 0x00
0xB7 to 0xB9 3 — Read only Reserved 0x000000
0xBA to 0xFF 70 KSV_LIST Read/write List of KSV’s downstream repeaters and receivers
(maximum of 14 devices) All zero
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
68
Table 25. Deserializer HDCP Register Table (See Table 2)
REGISTER
ADDRESS
SIZE
(Bytes) NAME READ/
WRITE FUNCTION DEFAULT VALUE
(hex)
0x80 to 0x84 5 BKSV Read only HDCP receiver KSV (Read only)
0x85 to 0x86 2 RI’ Read only Link verification response (Read only)
0x87 1 PJ’ Read only Enhanced link verification response (Read only)
0x88 to 0x8F 8 AN Read/write Session random number 0x0000000000000000
0x90 to 0x94 5 AKSV Read/write HDCP transmitter KSV 0x0000000000
0x95 1 BCTRL Read/write
D7 = PD_HDCP
1 = Power down HDCP circuits
0 = HDCP circuits normal
0x00
D[6:4] = Reserved
D3 = GPIO1_FUNCTION
1 = GPIO1 mirrors AUTH_STARTED
0 = Normal GPIO1 operation
D2 = GPIO0_FUNCTION
1 = GPIO0 mirrors ENCRYPTION_ENABLE
0 = Normal GPIO0 operation
D1 = AUTH_STARTED
1 = Authentication started (triggered by
write to AKSV)
0 = Authentication not started
D0 = ENCRYPTION_ENABLE
1 = Enable encryption
0 = Disable encryption
0x96 1 BSTATUS Read/write
D[7:2] = Reserved
0x00
D1 = NEW_DEV_CONN
1 = Set to 1 if a new connected device is
detected
0 = Set to 0 if no new device is connected
D0 = KSV_LIST_READY
1 = Set to 1 if KSV list and BINFO is ready
0 = Set to 0 if KSV list or BINFO is not ready
0x97 1 BCAPS Read/write
D[7:1] = Reserved
0x00
D0 = REPEATER
1 = Set to 1 if device is a repeater
0 = Set to 0 if device is not a repeater
0x98 to 0x9F 8 — Read only Reserved 0x0000000000000000
(read only)
0xA0 to 0xA3 4 V’.H0 Read/write H0 part of SHA-1 hash value 0x00000000
0xA4 to 0xA7 4 V’.H1 Read/write H1 part of SHA-1 hash value 0x00000000
0xA8 to 0xAB 4 V’.H2 Read/write H2 part of SHA-1 hash value 0x00000000
0xAC to 0xAF 4 V’.H3 Read/write H3 part of SHA-1 hash value 0x00000000
0xB0 to 0xB3 4 V’.H4 Read/write H4 part of SHA-1 hash value 0x00000000
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
69
Table 25. Deserializer HDCP Register Table (See Table 2) (continued)
REGISTER
ADDRESS
SIZE
(Bytes) NAME READ/
WRITE FUNCTION DEFAULT VALUE
(hex)
0xB4 to 0xB5 2 BINFO Read/write
D[15:12] = Reserved
0x0000
D11 = MAX_CASCADE_EXCEEDED
1 = Set to 1 if more than 7 cascaded
devices attached
0 = Set to 0 if 7 or fewer cascaded devices
attached
D[10:8] = DEPTH
Depth of cascaded devices
D7 = MAX_DEVS_EXCEEDED
1 = Set to 1 if more than 14 devices
attached
0 = Set to 0 if 14 or fewer devices attached
D[6:0] = DEVICE_COUNT
Number of devices attached
0xB6 1 GPMEM Read/write General-purpose memory byte 0x00
0xB7 to 0xB9 3 — Read only Reserved 0x000000
0xBA to 0xFF 70 KSV_LIST Read/write List of KSV’s downstream repeaters and
receivers (maximum of 14 devices) All zero
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
70
Chip Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Typical Application Circuit
WS
LFLT
INT
MS
SCK
SD
TX
RX
CDS
INT
RX/SDA
TX/SCL
LOCK
WS
SCK
SD
SD
SCK
WS
SDA
SCL
CDS
AUTOS
RX/SDA
IN+
IN-
IN
TO PERIPHERALS
DISPLAY
VIDEO DISPLAY APPLICATION
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
OUT
PLL
OUT+
45kI45kI
5kI5kI
50kI50kI
LMN1
LMN0
OUT-
TX/SCL
LFLT
INT
MS
WS
SCK
SD
PCLK PCLKIN
RGB DIN[17:0]
HS DIN18/HS
VS DIN19/VS
DE DIN20
GPU
ECU
MCLK
UART
AUDIO
MAX9263
MAX9264
MAX9850
PCLKOUT PCLK
DOUT[17:0] RGB
DOUT18/HS HSYNC
DOUT19/VS VSYNC
DOUT20 DE
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
64 TQFP-EP C64E+10 21-0084 90-0329
MAX9263/MAX9264
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 71
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 12/10 Initial release —
1 3/11 Updated the MAX9263 SCK and WS pin descriptions 14
