2.54
±0.2
8-0.6
2.5 MIN
0.50.5
0.5
14×2.54(=35.56)
HEAT SINK SIDE
18
3 MIN
12
2-R1.6
0.28
25
4-C1.2
Type name
Lot No.
QR
Code
24
±0.5
9.5
±0.5
5.5
±0.5
(1)
TERMINAL CODE
1. NC
2. V
UFB
3. V
VFB
4. V
WFB
5. U
P
6. V
P
7. W
P
8. V
P1
9. V
NC
*
10. U
N
11. V
N
12. W
N
13. V
N1
14. F
O
15. CIN
16. V
NC
*
17. NC
18. NC
19. NC
20. N
21. W
22. V
23. U
24. P
25. NC
29.2
±0.5
14.4
±0.5
14.4
±0.5
(3.5)
(3.3)
HEAT SINK SIDE
0.4
0.4
1.5
±0.05
3.5
B
0.8
(2.656)
(2.756)
(0~5°)
(1.2)
(1.2)
DETAIL A DETAIL B
0.28
1.778
±0.2
35
±0.3
20×1.778(=35.56)
38
±0.5
17 1
A
16-0.5
0.5
1.5 MIN
PS21962-4 INTEGRATED POWER FUNCTIONS
600V/5A low-loss 5th generation IGBT inverter bridge for
three phase DC-to-AC power conversion
APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES (PS21962-4)
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21962-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE
INSULATED TYPE
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
•For upper-leg IGBTS :Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection.
•For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC).
• Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a UV fault (Lower-side supply).
• Input interface : 3V, 5V line (High Active).
•UL Approved : Yellow Card No. E80276
Dimensions in mm
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
Aug. 2007
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21962-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE
INSULATED TYPE
Aug. 2007
2
Fig. 2 LONG TERMINAL TYPE PACKAGE OUTLINES (PS21962-4A)
Fig. 3 ZIGZAG TERMINAL TYPE PACKAGE OUTLINES (PS21962-4C)
2.54
±0.2
8-0.6
2.5 MIN
14×2.54(=35.56)
HEAT SINK SIDE
18
3 MIN
12
2-R1.6
0.28
25
4-C1.2
Type name
Lot No.
QR
Code
24
±0.5
14
±0.5
5.5
±0.5
(1)
TERMINAL CODE
1. NC
2. V
UFB
3. V
VFB
4. V
WFB
5. U
P
6. V
P
7. W
P
8. V
P1
9. V
NC
*
10. U
N
11. V
N
12. W
N
13. V
N1
14. F
O
15. CIN
16. V
NC
*
17. NC
18. NC
19. NC
20. N
21. W
22. V
23. U
24. P
25. NC
29.4
±0.5
14.4
±0.5
14.4
±0.5
(3.5)
(3.3)
HEAT SINK SIDE
0.4
0.4
1.5
±0.05
3.5
B
0.8
(2.656)
(2.756)
(0~5°)
(1.2)
(1.2)
DETAIL A DETAIL B
0.28
1.778
±0.2
35
±0.3
20×1.778(=35.56)
38
±0.5
17 1
A
16-0.5
1.5 MIN
0.50.5
0.5
0.5
2.54
±0.2
8-0.6
14×2.54(=35.56)
HEAT SINK SIDE
18
3 MIN
12
2-R1.6
0.28
25
4-C1.2
Type name
Lot No.
QR
Code
24
±0.5
9.5
±0.5
5.5
±0.5
(1)
TERMINAL CODE
1. NC
2. V
UFB
3. V
VFB
4. V
WFB
5. U
P
6. V
P
7. W
P
8. V
P1
9. V
NC
*
10. U
N
11. V
N
12. W
N
13. V
N1
14. F
O
15. CIN
16. V
NC
*
17. NC
18. NC
19. NC
20. N
21. W
22. V
23. U
24. P
25. NC
29.2
±0.5
33.7
±0.5
14.4
±0.5
18.9
±0.5
14.4
±0.5
(3.5)
HEAT SINK SIDE
0.4
0.4
1.5
±0.05
3.5
B
0.8
DETAIL B
0.28
1.778
±0.2
35
±0.3
20×1.778(=35.56)
38
±0.5
17 1
A
0.4
0.5
1.5 MIN
(0~5°)
(0~5°)
16-0.5
0.5
0.5 (2.656)
(2.756)
(1.2)
(1.2)
DETAIL A
Dimensions in mm
Dimensions in mm
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21962-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE
INSULATED TYPE
Aug. 2007
3
2.54
±0.25
7-0.6
2.5 MIN
14×2.54(=35.56)
HEAT SINK SIDE
18
3 MIN
12
(1.8)
2-R1.6
0.28
25
4-C1.2
Type name
Lot No.
QR
Code
24
±0.5
11
±0.5
5.5
±0.5
(1)
TERMINAL CODE
1. NC
2. V
UFB
3. V
VFB
4. V
WFB
5. U
P
6. V
P
7. W
P
8. V
P1
9. V
NC
*
10. U
N
11. V
N
12. W
N
13. V
N1
14. F
O
15. CIN
16. V
NC
*
17. NC
18. NC
19. NC
20. N
21. W
22. V
23. U
24. P
25. NC
35.2
±0.6
29.2
±0.5
14.4
±0.5
14.4
±0.5
17.4
±0.5
17.4
±0.5
(3.5)
HEAT SINK SIDE
0.4
1.5
±0.05
3.5
B
0.8
0.4
0.4
(2.656)
(2.756)
(0~5°)
(1.2)
(1.2)
DETAIL A DETAIL B
0.28
1.778
±0.25
35
±0.3
20×1.778(=35.56)
38
±0.5
17 1
A
16-0.5
0.4
1.5 MIN
(0~5°)
0.5
0.5
0.5
M
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment).
C1 : Electrolytic type with good temperature and frequency
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering.
characteristics
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
Note1: Input logic is high-active. There is a 3.3kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the
input threshold voltage.
2: By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 11)
3: This output is open drain type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistor.
(see also Fig. 11)
4: The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these P & N1 DC power input pins.
5: High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
6: It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
7: Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.
Protection
circuit (UV)
Drive circuit
CBU–
CBU+
CBV–
CBV+
CBW–
CBW+
AC line input
Input signal
conditioning
Input signal
conditioning
Input signal
conditioning
Level shifter
Drive circuit
Level shifter
Drive circuit
Level shifter
Drive circuit
Input signal conditioning
Protection
circuit Control supply
Under-Voltage
protection
F
O
DIP-IPM
(Note 4)
Inrush current
limiter circuit
V
D
V
NC
H-side IGBT
S
L-side IGBT
S
W
V
U
C2
C1
P
V
NC
N1 N
CIN
ZC
High-side input (PWM)
(3V, 5V line)(Note 1, 2)
(Note 5)
(15V line)
AC line output
(3V, 5V line)(Note 1, 2) Fault output (5V line)
(Note 3)
Low-side input (PWM)
(Note 7)
Fo logic
(Note 6)
(Note 6)
Fig. 5 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
Fig. 4 BOTH SIDES ZIGZAG TERMINAL TYPE PACKAGE OUTLINES (PS21962-4W) Dimensions in mm
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21962-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE
INSULATED TYPE
Aug. 2007
4
V
V
V
V
mA
V
20
20
–0.5~VD+0.5
–0.5~VD+0.5
1
–0.5~VD+0.5
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-U, VVFB-V, VWFB-W
Applied between UP, VP, WP, UN, VN,
WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
VD
VDB
VIN
VFO
IFO
VSC
450
500
600
5
10
21.3
–20~+125
Applied between P-N
Applied between P-N
TC = 25°C
TC = 25°C, less than 1ms
TC = 25°C, per 1 chip
(Note 1)
VCC
VCC(surge)
VCES
±IC
±ICP
PC
Tj
ConditionSymbol Parameter Ratings Unit
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
V
V
V
A
A
W
°C
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
ConditionSymbol Parameter Ratings Unit
CONTROL (PROTECTION) PART
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ TC ≤ 100°C). However, to
ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C).
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Drive circuit
Drive circuit
Protection circuit
W
V
U
B
C
V
NC
CIN
A
P
N1
N
CR
Shunt Resistor
External protection circuit
DIP-IPM
L-side IGBT
S
H-side IGBT
S
SC Protection
Trip Level
I
C
(A)
t
w
(µs)
2
0
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
Collector current
waveform
(Note 1)
(Note 2)
Fig. 6 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21962-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE
INSULATED TYPE
Aug. 2007
5
2.20
2.30
2.20
1.60
—
0.50
2.00
0.80
1
10
4.7
5.4
mA
V
Tj = 25°C
Tj = 125°C
IC = 5A, Tj = 25°C
IC = 5A, Tj = 125°C
VCE(sat)
VEC
ton
trr
tc(on)
toff
tc(off)
ICES
ConditionSymbol Parameter Limits
Inverter IGBT part (per 1/6 module)
Inverter FWD part (per 1/6 module)
Rth(j-c)Q
Rth(j-c)F
Min.
THERMAL RESISTANCE
Typ. Max.
—
—
—
—
Unit
Tj = 25°C, –IC = 5A, VIN = 0V
Condition
Symbol Parameter Limits
Min. Typ. Max.
—
—
—
0.50
—
—
—
—
—
—
Unit
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Collector-emitter saturation
voltage
FWD forward voltage
Junction to case thermal
resistance (Note 3)
VD = VDB = 15V
VIN = 5V
Switching times
VCC = 300V, VD = VDB = 15V
IC = 5A, Tj = 125°C, VIN = 0 ↔ 5V
Inductive load (upper-lower arm)
Collector-emitter cut-off
current VCE = VCES
1.70
1.80
1.70
1.00
0.30
0.30
1.40
0.50
—
—
V
µs
µs
µs
µs
µs
°C/W
°C/W
Note 3 : Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM
and heat-sink.
The contacting thermal resistance between DIP-IPM case and heat sink (Rth(c-f)) is determined by the thickness and the thermal
conductivity of the applied grease. For reference, Rth(c-f) (per 1/6 module) is about 0.3°C/W when the grease thickness is 20µm and
the thermal conductivity is 1.0W/m·k.
Note 2: TC measurement point
DIP-IPM
IGBT chip position
Power terminals
FWD chip position
Control terminals
T
C
point
Heat sink side
11.6mm 3mm
400
–20~+100
–40~+125
1500
VD = 13.5~16.5V, Inverter part
Tj = 125°C, non-repetitive, less than 2µs
(Note 2)
60Hz, Sinusoidal, 1 minute,
Between pins and heat-sink plate
VCC(PROT)
TC
Tstg
Viso
Symbol Ratings Unit
Self protection supply voltage limit
(short circuit protection capability)
Module case operation temperature
Storage temperature
Isolation voltage
V
°C
°C
Vrms
TOTAL SYSTEM
Parameter Condition
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21962-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE
INSULATED TYPE
Aug. 2007
6
Note 7: Flatness measurement position
+–
+
–
Heat sink side
Heat sink side
4.6mm
DIP-IPM
Measurement position
Mounting screw : M3
(Note 6)
Condition
Parameter Limits
Mounting torque
Weight
Heat-sink flatness
Min.
MECHANICAL CHARACTERISTICS AND RATINGS
Typ. Max.
0.59
—
–50
Unit
—
10
—
0.78
—
100
N·m
g
µm
Recommended : 0.69 N·m
(Note 7)
Note 6 : Plain washers (ISO 7089~7094) are recommended.
CONTROL (PROTECTION) PART
Note 4 : Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is
less than 1.7 times of the current rating.
5:Fault signal is asserted corresponding to a short circuit or lower side control supply under-voltage failure.
Symbol
ID
VFOH
VFOL
VSC(ref)
IIN
UVDBt
UVDBr
UVDt
UVDr
tFO
Vth(on)
Vth(off)
Vth(hys)
Parameter Condition Limits Unit
Circuit current
Fault output voltage
Short circuit trip level
Control supply under-voltage
protection
Fault output pulse width
ON threshold voltage
OFF threshold voltage
ON/OFF threshold hysteresis
voltage
VD = VDB = 15V
VIN = 5V
Total of VP1-VNC, VN1-VNC
VUFB-U, VVFB-V, VWFB-W
VSC = 0V, FO terminal pull-up to 5V by 10kΩ
VSC = 1V, IFO = 1mA
Tj = 25°C, VD = 15V (Note 4)
VIN = 5V
Trip level
Reset level
Trip level
Reset level
(Note 5)
Applied between UP, VP, WP, UN, VN, WN-VNC
—
—
—
—
4.9
—
0.43
0.70
10.0
10.5
10.3
10.8
20
—
0.8
0.35
—
—
—
—
—
—
0.48
1.00
—
—
—
—
—
2.1
1.3
0.65
2.80
0.55
2.80
0.55
—
0.95
0.53
1.50
12.0
12.5
12.5
13.0
—
2.6
—
—
Min. Typ. Max.
mA
mA
mA
mA
V
V
V
mA
V
V
V
V
µs
V
V
V
VD = VDB = 15V
VIN = 0V
Total of VP1-VNC, VN1-VNC
VUFB-U, VVFB-V, VWFB-W
Tj ≤ 125°C
Input current
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21962-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE
INSULATED TYPE
Aug. 2007
7
Fig. 7 THE DIP-IPM INTERNAL CIRCUIT
DIP-IPM
U
OUT
V
OUT
U
OUT
V
VS
W
OUT
V
WS
V
OUT
W
OUT
V
NO
GND
Fo
W
N
V
N
U
N
V
CC
HVIC
LVIC
CIN
CIN
N
W
V
U
P
COM
VUB
VUS
VCC
VVB
VP
VWB
WP
Fo
W
N
V
N
U
N
W
P
V
P
U
P
U
P
V
NC
V
N1
V
P1
V
VFB
V
WFB
V
NC
V
UFB
IGBT1
IGBT2
IGBT3
IGBT4
IGBT5
IGBT6
Di1
Di2
Di3
Di4
Di5
Di6
V
V
V
V/µs
µs
kHz
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
Applied between P-N
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-U, VVFB-V, VWFB-W
For each input signal, TC ≤ 100°C
TC ≤ 100°C, Tj ≤ 125°C
400
16.5
18.5
1
—
20
VCC
VD
VDB
∆VD, ∆VDB
tdead
fPWM
ConditionSymbol Parameter Limits
Min. Typ. Max.
0
13.5
13.0
–1
1.5
—
Unit
RECOMMENDED OPERATION CONDITIONS
300
15.0
15.0
—
—
—
Note 8 : The allowable r.m.s. current value depends on the actual application conditions.
9:IPM might not make response if the input signal pulse width is less than the recommended minimum value.
IO
PWIN(on)
PWIN(off)
VNC
Allowable r.m.s. current
Allowable minimum input
pulse width
VNC variation
VCC = 300V, VD = VDB = 15V,
P.F = 0.8, sinusoidal PWM,
Tj ≤ 125°C, TC ≤ 100°C (Note 8)
(Note 9)
Between VNC-N (including surge)
Arms
µs
V
0.5
0.5
–5.0
—
—
—
—
—
5.0
fPWM = 5kHz
fPWM = 15kHz
—
—
—
—
2.5
1.5
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21962-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE
INSULATED TYPE
Aug. 2007
8
Error output Fo
Output current Ic
Control supply voltage V
D
Protection circuit state
Control input
b1
b2
b3
b4
b5
RESET
RESET
UV
Dt
UV
Dr
SET
b6
b7
Protection circuit state
Lower-side control
input
Error output Fo
Sense voltage of the
shunt resistor
Output current Ic
Internal IGBT gate
SC reference voltage
CR circuit time
constant DELAY
a5
a8
a4
a3
a1
a2
SC
RESET
SET
a7a6
Fig. 8 TIMING CHART OF THE DIP-IPM PROTECTIVE FUNCTIONS
[A] Short-Circuit Protection (Lower-side only with the external shunt resistor and CR filter)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit detection (SC trigger).
a3. IGBT gate hard interruption.
a4. IGBT turns OFF.
a5. FO outputs (tFO(min) = 20µs).
a6. Input “L” : IGBT OFF.
a7. Input “H” : IGBT ON.
a8. IGBT OFF in spite of input “H”.
[B] Under-Voltage Protection (Lower-side, UVD)
b1. Control supply voltage rising : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.
b2. Normal operation : IGBT ON and carrying current.
b3. Under voltage trip (UVDt).
b4. IGBT OFF in spite of control input condition.
b5. FO outputs (tFO ≥ 20µs and FO outputs continuously during UV period).
b6. Under voltage reset (UVDr).
b7. Normal operation : IGBT ON and carrying current.
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21962-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE
INSULATED TYPE
Aug. 2007
9
MCU
10kΩ
UP,VP,WP,UN,VN,WN
VNC(Logic)
Fo
DIP-IPM
5V line
3.3kΩ (min)
Error output Fo
Output current Ic
Control supply voltage VDB
Protection circuit state
Control input
c6
c1
c2 c4
c5
c3
RESET
UVDBt
UVDBr
SETRESET
High-level (no fault output)
[C] Under-Voltage Protection (Upper-side, UVDB)
c1. Control supply voltage rising : After the voltage level reaches UVDBr, the circuits start to operate when next input is applied.
c2. Normal operation : IGBT ON and carrying current.
c3. Under voltage trip (UVDBt).
c4. IGBT OFF in spite of control input signal level, but there is no FO signal outputs.
c5. Under voltage reset (UVDBr).
c6. Normal operation : IGBT ON and carrying current.
Fig. 9 RECOMMENDED MCU I/O INTERFACE CIRCUIT
Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and the
wiring impedance of the printed circuit board.
The DIP-IPM input section integrates a 3.3kΩ (min) pull-down resistor. Therefore, when using an external
filtering resistor, pay attention to the turn-on threshold voltage.
Fig. 10 WIRING CONNECTION OF SHUNT RESISTOR
N
DIP-IPM
Wiring inductance should be less than 10nH.
Shunt resistor
Equivalent to the inductance of a copper
pattern in dimension of width=3mm,
thickness=100µm, length=17mm
Please make the GND wiring connection
of shunt resistor to the V
NC
terminal
as close as possible.
V
NC
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21962-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE
INSULATED TYPE
Aug. 2007
10
Fig. 11 AN EXAMPLE OF TYPICAL DIP-IPM APPLICATION CIRCUIT
Note 1 : Input drive is High-Active type. There is a 3.3kΩ(min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the
wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on
and turn-off threshold voltage.
2:Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible.
3:FO output is open drain type. It should be pulled up to the positive side of a 5V power supply by a resistor of about 10kΩ.
4:To prevent erroneous protection, the wiring of A, B, C should be as short as possible.
5:The time constant R1C4 of the protection circuit should be selected in the range of 1.5-2µs. SC interrupting time might vary with the
wiring pattern. Tight tolerance, temp-compensated type is recommended for R1, C4.
6:All capacitors should be mounted as close to the terminals of the DIP-IPM as possible. (C1: good temperature, frequency character-
istic electrolytic type, and C2, C3: good temperature, frequency and DC bias characteristic ceramic type are recommended.)
7:To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.
Generally a 0.1-0.22µF snubber between the P-N1 terminals is recommended.
8:Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
9:It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
10 : If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended
to connect control GND and power GND at only a point.
15V line
WOUT
VOUT
DIP-IPM
C3
C2C2 C2
C1 C1 C1
UOUT
WP
VWB
VP
VVB
5V line
UP
COM
UOUT
VOUT
WOUT
GND
F
o
WN
VN
VCC
C
B
A
R1
N1
C4
CIN
N
W
V
U
P
VWS
VVS
VUS
VUB
VCC
Fo
WN
VN
UN
UN
WP
VP
UP
VNC
VNC
VN1
VP1
VUFB VVFB VWFB
C3
MCU
HVIC
LVIC
Shunt
resistor
Long wiring here might cause SC
level fluctuation and malfunction.
C1: Electrolytic capacitor with good temperature characteristics
0.22~2µF R-category ceramic capacitor for noise filteringC2,C3:
Long GND wiring here might
generate noise to input and
cause IGBT malfunction.
Long wiring here might
cause short-circuit.
Long wiring here might
cause short-circuit.
MM
Bootstrap negative
electrodes should be
connected to U, V, W
terminals directly and
separated from the
main output wires.
