Data Sheet June 1999 microelectronics group Lucent Technologies Bell Labs Innovations ORCA Series 3C and 3T Field-Programmable Gate Arrays Features High-performance, cost-effective, 0.35 pm (OR3C) and 0.3 um (OR3T) 4-level metal technology, (4- or 5-input oon table delay of 1.1 ns with -7 speed grade in 3 Em). Same basic architecture as lower-voltage, advanced process technology Series 3 architectures. (See ORCA Series 3L FPGA documentation.) Up to 186,000 usable gates. Up to 452 user I/Os. (ORSTxxx I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis.) Pin selectable /O clamping diodes provide 5 V or 3.3 V PCI compliance and 5 V tolerance on OR3T2x0 devices. Twin-quad programmable function unit (PFU) architec- ture with eight 16-bit look-up tables (LUTs) per PFU, organized in two nibbles for use in nibbie- or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU. Nine user registers per PFU, one following each LUT, plus one extra. All have programmable clock enable and local set/reset, plus a global set/reset that can be dis- abled per PFU. Flexible input structure (FINS) of the PFUs provides a routability enhancement for LUTs with shared inputs and the logic flexibility of LUTs with independent inputs. Fast-carry logic and routing to adjacent PFUs for nibble-, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. Softwired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU for up to 40% speed improvement. Supplemental logic and interconnect cell (SLIC) provides 3-statable buffers, up to 10-bit decoder, and PAL*-like AND-OR with optional INVERT in each programmable Table 1. ORCA Series 3 (3C and 3T) FPGAs logic cell (PLC), with over 50% speed improvement typi- cal. a Abundant hierarchical routing resources based on rout- ing two data nibbles and two control lines per set provide for faster place and route implementations and less rout- ing delay. TTL or CMOS input levels programmable per pin for the OR3Cxx (5.0 V) devices. a Individually programmable drive capability: 12 mA sink/6 mA source or 6 mA sink/3 mA source. = Built-in boundary scan (IEEE 1149.1 JTAG) and TS_ALL testability function to 3-state all I/O pins. m Enhanced system clock routing for low skew, high-speed clocks originating on-chip or at any I/O. a Up to four ExpressCLK inputs allow extremely fast clock- ing of signals on- and off-chip plus access to internal general clock routing. = StopCLK feature to glitchlessly stop/start ExpressCLKs independently by user command. a Programmable !/O (PIO) has: Fast-capture input latch and input flip-flop (FF) latch for reduced input setup time and zero hold time. Capability to (de)multiplex I/O signals. Fast access to SLIC for decodes and PAL-like functions. ~ Output FF and two-signal function generator to reduce CLK to output propagation delay. - Fast open-drain dive capability Capability to register 3-state enable signal. wu Baseline FPGA family used in Series 3+ FPSCs (field programmable system chips) which combine FPGA logic and standard cell logic on one device. * PAL is a trademark of Advanced Micro Devices, Inc. + /EEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Device ee LUTs | Registers | Max User RAM; User V/Os | Array Size ress ay OR3T20 36K 1152 1872 18K 196 12x 12 0.3 pm/4 LM OR3T30 48K 1568 2436 25K 228 14x14 0.3 pm/4 LM OR3C/3T55 80K 2592 3780 42k 292 18x 18 0.3 um/4 LM OR3C/3T80 116K 3872 5412 62K 356 22 x 22 0.3 um/4 LM OR3T125 186K 6272 8400 100K 452 28 x 28 0.3 pm/4 LM The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PlOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. eTData Sheet ORCA Series 3C and 3T FPGAs June 1999 Table of Contents Contents Page Contents Page FOAture ..........-.-cesccessecetscceesecceeceesseeatesessoresenssasssenseeens 1 POM Cautions ............. ssceessecccsecenesnesnereneeseeaserees 84 System-Level Features.............cssssestesseenseseeeeseeseees 6 FPGA States of Operation............cccsescsteeseeesntees 85 DEOSCIiIPtiON............-:--ceecessceececccessessnsasnsensesensesersseutenecs 7 IMitiAlI ZATION 0.0... ee eeeeeeeeeccetseeceeccesvenesesceeoeneecseneee 85 FPGA OVErVICW ou... cscceesssssensseenestereesnestsnseseeeatesees 7 COnfiQuration ........:sscscssssseesscsesssssesceustreseeeseneneeeas 86 PLC LOGIC .........scessscescsreceseserscscsceeesscerssseseessnenasenssenes 7 Start-Up oo. ce se cesesssceescsssccensesscosssessesssseassecsenssens 87 PIC LOGIC ........ssccssevessoreesensersstseatenesceessscenstetenceessen nes 8 RECONFIQUIATION .........cscessessssteesceroseessrersseserseneseens 88 System Features 00... ec ecscsssceeseeteseesenseseseseeseerenss 8 Partial Reconfiguration 0.0.0.0... csscsessstseseeeesesees 88 PROULING 00... eesessesssoesessecesenscerserssncersseensceseersesesceneaen 8 Other Configuration Options ...........ccssesssecsssosees 88 Configuration ........cssssesscsssscsssseeceersceenssseeneneeseesesees 8 Configuration Data Format 0.0... ccssessceseneessoeees 89 ORCA Foundry Development System ..............ceccs 9 Using ORCA Foundry to Generate AIChiteCture ..............-escsceescesssecessssecesssecatssonnersoosateees 9 Configuration RAM Data .........csscsssrssscerseersrees 89 Programmable Logic Cells ...........sscsescssesstseereeers 11 Configuration Data Frame ..........scsesccsrssssssereessees 89 Programmable Function Unit ...........ssssesssssseeners 11 Bit Stream Error Checking 2.0.0.0... eessscenteeseneee 91 Look-Up Table Operating Modes .............sccsessseeen 13 FPGA Configuration Modes..............-..essseseesesseeeees 92 Supplemental Logic and Interconnect Cell (SLIC) ..21 Master Parallel Mode ...............ccsccccssecestsestsnecseensee 92 PLC Latches/FIip-Flops ...........::.-seccessseoeesecsconseneoeees 25 Master Serial Mode .........cccsscscsccrsssecsssssseseeessenenee 93 PLC Routing RESOUrCES .........ccsccccesrecenreesssressseesees 27 Asynchronous Peripheral Mode ...........:::scesssesssens 94 PLC Architectural Description .............ccesessesereseees 34 Microprocessor Interface (MPI) Mode ..................... 94 Programmable Input/Output Cells .............ecscsseceees 36 Slave Serial Mode ...........::ccccccscssssnsnsscersceseeseeeeeteers 97 5 V Tolerant VO oo... cseesscesscsssesesscnsesceesenseeseevsnnenees 37 Slave Parallel Mode ...............:--sseeeececceeesesseseenneaee 97 PCI Compliant VO occ cc cscsceeseseeesesecneeersseesarenees 37 _ Datisy-Chaiiniing .........-...---sscsssesecsseeereseceeseseseessseanses 98 INPUTS 0... ec etteccensesserstecsecssosescsnsessstensnsensessneneeenssens 38 Daisy-Chaining with Boundary Scan ............s0sse0 99 OQUIDUTS ........cseseesssssesescececeesenseeseneuenseceesserseeesonesees 41 Absolute Maximum RatingS............---csssssssssseesssees 100 PIC Routing RESOUICES ..........-..-scccsssessssressecsssersees 44 Recommended Operating Conditions .................. 100 PIC Architectural Description ................ccsesscseeeeees 45 Electrical Characteristics ................s.ceccssseseeesoeceeeees 101 High-Level Routing Resources.............:sccseeresesees 47 = Timing Characteristics ....0...... ss eecceesecesseseeneensseeers 103 Interquad ROUting ..........ccsssccessseesereeseessessseeseeres 47 D@SCIIPTION ...........scseccssssesecnssesntesecsseestonsesnacerscees 103 Programmable Corner Cell ROUutING .........scceccesseees 48 PFU Timing ......--eescceeceesecececeresesseessseeeneneeneasoenes 104 PIC Interquad (MID) Routing ..............:.s:csssssssssenens 49 PL Timing ...........scssscessosscccenseetesceneseessnseneneeasees 111 Clock Distribution Network ...........cccccecsssscneseerseeees 50 SLIC Timing ........:cscsseescssscccsesscerssneessenetsressauenscees 111 PFU Clock Sources 0... cccccsscsssecescereseersesesceneereeenes 50 PIO Timing 00... sscssescssccoenencessseeeserssescnseransatenseses 112 Clock Distribution in the PLC Array ..........sccascsecsones 51 Special Function Blocks Timing ............scssseserssees 115 Clock Sources to the PLC Array ..........s:ssscsesseeers 52 COCK Timing ........---scccceceserssssseceseereccenseroaseccevses 123 Clocks in the PICS .....0.......cssessessccceessessennecceatesseesess 52 Configuration Timing ..............:.:sssssssssesssensessseones 133 ExpressCLk IMputs ............2.ccesscseecssssesonssceeseseneeranes 53 Readback Timing .............-.scsccssssscssceensnecceeseees 142 Selecting Clock Input Pins ............sscsecsscrseensereees 53 Input/Output Buffer Measurement Conditions ........ 143 Special Function BIOCKS ..............scsscesecesnenssesneneeres 54 Output Buffer Characteristics ...............ccccsseseeeees 144 Single Function BIOCKS .........cccscssssssseseesseeseensesseaes 54 ORSOXX ...ccesecsssscececceeertectsccessersscrscesessevsecaseonssooss 144 Boundary SCAN... eeseeeceessseessnessseessaessnesancsnenasees 57 ORST XXX oo. ecssscsscssenecesoeetsceesenceessecenscoesseceeseeeaneeens 145 Microprocessor Interface (MPI) ............cccssssseeecsennees 64 _ Estimating Power Dissipation ...............cssssesenseeees 146 POWErPC SYSIOM ........cccccecseeeecsnceeeeeseeessserssssesecenenes 65 ORSCOXX oo. ccccssersestsscsssecensnscecessracceeesseesaeeseentsseoes 146 I9GO SYStOM oo... cesscsssserececscessseoncersscacenersesesssenseesanes 66 OR3Toox (Preliminary Information) ..........:.ssese 147 MPI Interface to FPGA 0.0... see secsseseesestensrteesenennes G7 Pi INFOrMALION ............sessestensnecsserstneeseesneeeenssnenasees 149 MPI Setup and Control ......0.......ccscssessseessensreeseeeeaes 68 Pin De@SCTIPtionS ........::..scscssccesssesetssssscreessneerasees 149 Programmable Clock Manager (PCM) ..........ssscsee 72 Package Compatibility ..............scssssssssccsersessreenes 153 PCM ReGisters ..0......:ccccscescesssssesseeescenssseensesnessnenseee 73 Compatibility with OR2C/TXxA Series ............000 154 Delay-Locked Loop (DLL) Mode ...........s:ccsseserreees 75 Package Thermal Characteristics..............:ssccscessee 194 Phase-Locked Loop (PLL) Mode. ............ ce ecsceeesees 76 QUA wocccccssccccssscceresseesesssnccessscescessssccessenscceesoemeessones 194 PCM/FPGA Internal Interface ............scsecsersssseenees 79 WIS eccsccsscesssesecenccesecceceneeceerneceneeacscessatuesssnseeseees 194 PCM Operation 200... eee ssssencreceesreseesenersereranseoes 79 OSC ooeeessccsececsnsceccencecceseesscesecsaasasauensceeetenanseesnsseees 194 PCM Detailed Programming ..........ssscesessecceserssessees 80 OSB ooo cecccccccssseecessscessneenseseceeentencceseseoeeensesasenaaace 194 PCM Applications ............-..ecceeesseeesseserseneeseeeassesenes 83 FPGA Maximum Junction Temperature .............. 195 2 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Table of Contents Contents Page Contents Page Package Coplanarity ...........2....::ccseesseesceetseecenneoenene 196 Table 32. Configuration Frame Format and Package ParaSitics ............cccssscscessssseretconteecceneeessees 196 CONTENTS 0... eeeeescceeeetesecenecceeesnsssesesesneessenecssneessas 90 Package Outline Diagrams...............ssccssssssseeneeees 197 Table 33. Configuration Frame Size ............. eee 91 Terms and Definitions ................sscesesseensecestseeees 197 Table 34. Configuration Modes. ............:.:.cssscccceseeers 92 208-PiIN SQFP ou... cccsseceeeeetesseceetssecsesuscsenseeceane 198 Table 35. Absolute Maximum Ratings ................... 100 208-Pin SQFP2 .........cscssccssserceesnsssscceceasstesesnsessors 199 Table 36. Recommended Operating Conditions ....100 240-Pin SQFP .0.W....seeeeceeeeceesccsceesnersctcnseneonsueeteces 200 = Table 37. Electrical Characteristics ...................0 101 240-Pin SQEP2 ........ccccsssesssnrsecceeessaceeneresceceanseeces 201 Table 38. Derating for Commercial Devices 256-PIN PBGA ..........sceeseeeeceeseseeoceestneccecerteneeeenscees 202 (ORSCOXX) oo. eeecesceeeceeessceeenseetseteneseussssenurenseeeseees 103 352-Pin PBGA ........cssccccssssccccrsesscccenssnecensnecssenteees 203 Table 39. Derating for Industrial Devices (OR3Cxx) 103 432-Pin EBGA ........sccsccscssccsserececeeesnsseneceesecseaneeesee 204 ~=Table 40. Derating for Commercial/Industrial GOO-Pin EBGA 0.0.1... ccescesscscecensscceserscccssonseensenenees 205 Devices (ORSTXXX) .........ccccssssesssscceeesssncesssssceees 103 Ordering Information............c.sssccscssersssssserserserenees 206 Table 41. Combinatorial PFU Timing IN OX... ee ceseeeecccencceseesseeecscesnscescacssoesseceaonseeseesenten 207 Characteristics 20.0... eccssssscsesscsseeccesceerscessenseserees 104 Tables Table 42. Sequential PFU Timing Characteristics ..106 Table 43. Ripple Mode PFU Timing Table 1. ORCA Series 3 (3C and 3T) FPGAs ............ 2 Characteristics .0........cccccsssssscssssssscescsscscsssesesesenees 107 Table 2. ORCA Series 3 System Performance ........... 6 Table 44. Synchronous Memory Write Table 3. Look-Up Table Operating Modes ............... 13 Characteristics ............-esssecessssceeseeseecessececsareeaseesees 109 Table 4. Control Input Functionality ............:cccsessees 14 Table 45. Synchronous Memory Read Table 5. Ripple Mode Equality Comparator Characteristics .............cccccssscsssesssessesssceeeessseecsensees 110 Functions and Output ..........ccsssscsssesssseesesesseneres 18 Table 46. PFU Output MUX and Direct Routing Table 6. SLIC MOde .........:csscsssseseeeseseeneeetenencereres 21 Timing Characteristics ............cscsssesssseenseeseesees 111 Table 7. Configuration RAM Controlled Table 47. Supplemental Logic and Interconnect Latch/Flip-Flop Operation ............:sssrssessrssssesreessssees 25 ~- Cell (SLIC) Timing Characteristics ............csee0 111 Table 8. Inter-PLC Routing Resources ............:sc00 31 Table 48. Programmable I/O (PIO) Timing Table 9. PIO Options .............cccsccssserscnstecestsseneseeens 37 Characteristics ............:scccsssssccessseccesssnsrecsesennscesneees 112 Table 10. PIO Logic Options ............esscesssssseesseeoees 43 Table 49. Microprocessor Interface (MPI) Timing Table 11. PlO Register Control Signals .............:000 43 Characteristics .............:ccccsccsscsssscsssscesesesseenseersceees 115 Table 12. Readback Options ............ssssssscersestseeres 54 = Table 50. Programmable Clock Manager (PCM) Table 13. Boundary-Scan Instructions .............sse0 58 Timing Characteristics (Preliminary Information) ..121 Table 14. Boundary-Scan ID Code ..........:csssssenseens 59 Table 51. Boundary-Scan Timing Characteristics ..122 Table 15. TAP Controller Input/Outputs ................+ 61 Table 52. ExpressCLK (ECLK) and Fast Clock Table 16. PowerPC/MPI Configuration .............ss08 65 (FCLK) Timing Characteristics ................ eens 123 Table 17. i960/MPI Configuration ..........scccssecsereees 66 Table 53. General-Purpose Clock Timing Table 18. MPI Internal Interface Signals .............. 67 Characteristics (Internally Generated Clock) ......... 124 Table 19. MPI Setup and Control Registers ............. 68 Table 54. OR3Cxx ExpressCLK to Output Delay Table 20. MPI Setup and Control Registers (PiN-tO-PiM) ......csesseteecsesscenesensssesnatetsesecesetsensorssee 125 De@SCIIPtION ...........eseseesseseessssescsssssssscensesessseasceeseuseses 68 Table 55. OR3Cxx Fast Clock (FCLK) to Output Table 21. MPI Control Register 2 ...........sssseseseceees 69 Delay (Pin-to-Pin) ...........cssscsessscesecseerseseceseeseeceeeeee 126 Table 22. Status Register ..........ssssscsssssesseseseesers 70 Table 56. OR3Cxx General System Clock (SCLK) Table 23. Device ID Code... cesessssscsesesressarereesens 71 to Output Delay (Pin-to-Pin) ...........ccccssessseerrseees 127 Table 24. Series 3 Family and Device ID Values .....71 Table 57. OR3C/Txxx Input to ExpressCLK (ECLK) Table 25. ORCA Series 3 Device ID Descriptions ....71 Fast-Capture Setup/Hold Time (Pin-to-Pin) .......... 128 Table 26. PCM Registers ...........ccssesssresssesssessees 73 = Table 58. OR3C/Txxx Input to Fast Clock Table 27. DLL Mode Delay/1x Duty Cycle Setup/Hold Time (Pin-to-Pin) ...............csssccccesssees 130 Programming Values ............e:cccscccesssessesessenssenesene 75 ~~ Table 59. OR3C/Txxx Input to General System Table 28. DLL Mode Delay/2x Duty Cycle Clock (SCLK) Setup/Hold Time (Pin-to-Pin) .......... 132 Programming VAlUES ...........csscccessneecssssaetsscereeeneees 76 ~=Table 60. General Configuration Mode Timing Table 29. PCM Oscillator Frequency Range 3Txxx .78 Characteristics .....00...cccccccscsccesessessssesescessssseereeeees 133 Table 30. PCM Oscillator Frequency Range 3Cxx ...78 Table 31. PCM Control Registers ............cccsssecesse 80 Lucent Technologies Inc. Table 61. Master Serial Configuration Mode TimingData Sheet ORCA Series 3C and 3T FPGAs June 1999 Table of Contents Contents Page Contents Page Characteristics ..............ccccsesseccssessensesssseeecessseseess 136 Figure 14. Buffer-Decoder-Buffer Mode ................00 23 Table 62. Master Parallel! Configuration Mode Timing Figure 15. Buffer-Decoder-Decoder Mode ............... 24 Characteristics ............cccceecssssenseceenseceeeceeenseenaees 137 Figure 16. Decoder Mode ....w.......e ee essseccseceetesteeees 24 Table 63. Asynchronous Peripheral Configuration Mode Figure 17. Latch/FF Set/Reset Configurations. ......... 26 Timing Characteristics ........0....csccescsseneseeeeeeneeeees 138 Figure 18. Configurable Interconnect Point .............. 27 Table 64. Slave Serial Configuration Mode Timing Figure 19. Single PLC View of Inter-PLC Route Characteristics 2.0... eee escecessceeesseceeeestereeerensaee 139 SOQMOMS 1.002... ceeseeeecsecseeesceceesceccescetterseeeeonesensseetees 28 Table 65. Slave Paralle! Configuration Mode Figure 20. Multiple PLC View of Inter-PLC Routing .32 Timing Characteristics ..............:ssceseeesssesersceesneeees 140 = Figure 21. PLC Architecture ...0........e eee eeeecetseeneeees 35 Table 66. Readback Timing Characteristics ........... 142 ~=Figure 22. OR3C/Txxx Programmable Input/Output Table 67. Pin Descriptions ..............::sssccsccscssseenteeses 149 (PIO) Image from ORCA Found ry ...........cssssccseereeee 36 Table 68. ORCA VOs Summary ..........---eesecceseceoeee 153 Figure 23. Fast-Capture Latch and Timing ............... 39 Table 69. Series 3 ExpressCLK Pins. ...........csssce 154 Figure 24. PIO Input Demultiplexing ...................0006 40 Table 70. OR3T20, OR3T30, ORSC/T55, ORSC/T80, and OR3T125 208-Pin SQEP/SQFP2 Pinout ............ccsssssossversesceseecerecceeees 155 Table 71. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout .........csssscsesesessssesrenssesesoees 161 Table 72. OR3T20, OR3T30, and OR3C/TS5 256-Pin PBGA Pinout ...........cecsssereserereneesesenenees 168 Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout . 172 Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout 200... eeeccceceeseneeneneeesceseensnsnecensenneees 182 Table 75. OR3T125 600-Pin EBGA Pinout ............ 187 Table 76. Plastic Package Thermal Characteristics for the ORCA Series ...........-..-.008 195 Table 77. Package Coplanarity ..............:csssscoessees 196 Table 78. Package Parasitics .............:scccssssesesese 196 Table 79. Voltage Options 2.0.0... ecccsseereeseenceee 206 Table 80. Temperature Options .......c.ccccssserrsssseee 206 Table 81. Package Options ...........cssesccsessceereesnenes 206 Table 82. ORCA Series 3 Package Matrix ............. 206 Table 83. Speed Grade Options ...........ccsssssseeneeee 206 Figures Figure 1. ORSC/T55 Array ........... secsecceeesssseescensoree 10 Figure 2. PFU Ports ............2sssssssccsssostecessreceessoesescees i1 Figure 3. Simplified PFU Diagram ...........:csssccceeees 12 Figure 4. Simplified F4 and F5 Logic Modes ............ 14 Figure 5. Softwired LUT Topology Examples ........... 15 Figure 6. Ripple Mode. .................sccseceesesessserrreeeeesoes 16 Figure 7. Counter SuDMOde ...........ssseseeeseenesecsseesenes 17 Figure 8. Multiplier Submode ..............ssssesseerssssecesnees 18 Figure 9. Memory Mode ..........cceeseeseceessesceseenssenes 19 Figure 10. Memory Mode Expansion Example 128 X BRAM ou. ccccssseeceeeceessneetetteesstesscseeeeeones 20 Figure 11. SLIC All Modes Diagram .............csseeneese 22 Figure 12. Buffer Mode ...............:-ssseeceseserenseceeesseenes 22 Figure 13. Buffer-Buffer-Decoder Mode ............sseee 23 4 Figure 25. Output Multiplexing (OUT1OUT2 Mode) .42 Figure 26. Output Multiplexing (OUTZOUTREG Mode) .............ccsceecssseteseessssesenee 42 Figure 27. PIC Architecture 2.02... ssseeecceeseteeees 46 Figure 28. tnterquad Routing ...............::::scccesssseseees 47 Figure 29. hlQ Block Detail ..............-.s:sccccseresseceseoee 48 Figure 30. Top (TMID) Routing ...............:ssccessseccerees 49 Figure 31. PFU Clock Sources 0... cc ssssessesssesereeees 50 Figure 32. ORCA Series 3 System Clock Distribution Overview .........-..--scscecceesenteceseesessnnensoes 51 Figure 33. PIC System Clock Spine Generation ...... 52 Figure 34, ExpressCLK and Fast Clock Distribution 53 Figure 35. Top CLKCNTRL Function Block .............. 56 Figure 36. Printed-Circuit Board with Boundary- Scan Circuitry ....... ec eesssececcrnsssseceecsecesseesstsneesseneees 57 Figure 37. Boundary-Scan Interface .........ccceeeenee 58 Figure 38. ORCA Series Boundary-Scan Circuitry Functional Diagram ..........essecssceeseceseetsceesesesenseeee 60 Figure 39. TAP Controller State Transition Diagram 61 Figure 40. Boundary-Scan Cell ............scsssccsersseeeee 62 Figure 41. Instruction Register Scan Timing DiQQTam ........cscc estes ssessceecneneeneccecssneenasceeessesetereeneaeee 63 Figure 42. MPI Block Diagram ...........::.-ccsscesssceseenes 64 Figure 43. POWerPC/MPI ..........scccccsseessscceesserseecereseee 65 Figure 44. f9GO/MPI ...........ceeececeeseetssenenesceeestaneecees 66 Figure 45. PCM Block Diagram ...............esseeereeeeeee 72 Figure 46. PCM Functional Block Diagram .............. 74 Figure 47. ExpressCLK Delay Minimization Using The POM ou... cessscccescsccscsseessscecccestsneccesscnecenseesecetenss 76 Figure 48. Clock Phase Adjustment Using the PCM 83 Figure 49. FPGA States of Operation ...........csseneeee 85 Figure 50. Initialization/Configuration/Start-Up WaVePOIMS 0.0... eee ecceeeencecesceeeesteceeseeenseeusersecenenees 86 Figure 51. Start-Up Waveforms ...........sesseeeeeeeeneeee 88 Figure 52. Serial Configuration Data Format Autoincrement Mode .............:ccscsecscsssnseeteessssseeters 90 Figure 53. Serial Configuration Data Format Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Table of Contents Contents Page Contents Page Explicit Mode ...........:.:cccesceeseescseeceseseesecesceeesetesenseses 90 Figure 82. General Configuration Mode Timing Figure 54. Master Paraliel Configuration Schematic 92 DiQQram ........ ss eeeecseeceessceereeeeensaeeesoceeseeeseveesereees 135 Figure 55. Master Serial Configuration Schematic ...93 | Figure 83. Master Serial Configuration Mode Figure 56. Asynchronous Peripheral Configuration ..94 Timing Diagram ....... cece ctssssescceeeereececceeeeeesceneeee 136 Figure 57. PowerPC/MPI Configuration Schematic ..95 | Figure 84. Master Parallel Configuration Mode Figure 58. i960/MPI| Configuration Schematic .......... 95 Timing Diagram ..........cccsccsssccseststersssecesersessseeeees 137 Figure 59. Configuration Through MPI .................:0 95 Figure 85. Asynchronous Peripheral Configuration Figure 60. Readback Through MPI ..........-....:cecsesses 96 Mode Timing Diagram ................-.:ssssssssssrtecssensens 138 Figure 61. Slave Serial Configuration Schematic ..... 97 Figure 86. Slave Serial Configuration Mode Figure 62. Slave Parallel Configuration Schematic ..97 Timing Diagram ............sssscccsssessssesseeceateseeesees 139 Figure 63. Daisy-Chain Configuration Schematic .....98 | Figure 87. Slave Parallel Configuration Mode Figure 64. Combinatorial PFU Timing ................... 105 Timing Diagram ................:ccseccescsnsesesesonecenrereesees 140 Figure 65. Synchronous Memory Write Figure 88. Readback Timing Diagram ................0 142 Characteristics 022... seseececsserseresesnesssneeeeccsos 109 Figure 89. ac Test Loads .....0... ce eeessssseesnetesteceees 143 Figure 66. Synchronous Memory Read Cycle ........ 110 Figure 90. Output Buffer Delays .................... eee 143 Figure 67. MPI PowerPC User Space Read Timing 117 Figure 91. Input Buffer Delays ...................:csessseee 143 Figure 68. MPI PowerPC User Space Write Timing 117 = Figure 92. Sinklim (Ty = 25 C, Vpb = 5.0 V) .......... 144 Figure 69. MP! PowerPC internal Read Timing ..... 118 Figure 93. Slewlim (Tu = 25 C, Vpb = 5.0 V) ......... 144 Figure 70. MP! PowerPC Internal Write Timing ...... 118 Figure 94. Fast (Ts C, VDD = 5.0 V) .......ecceeeeeeee 144 Figure 71. MPI i960 User Space Read Timing ....... 119 Figure 95. Sinklim (Ts = 125 C, Vpp = 4.5 V) ........ 144 Figure 72. MPI i960 User Space Write Timing ....... 119 Figure 96. Slewlim (Ty = 125 C, Vpb = 4.5 V) ....... 144 Figure 73. MPI i960 Internal Read Timing .............. 120 Figure 97. Fast (Ty = 125C, Vod = 4.5 V) ............ 144 Figure 74. MPI i960 Internal Write Timing ............... 120 Figure 98. Sinklim (Ts = 25 C, VoD = 3.3 V) .......... 145 Figure 75. Boundary-Scan Timing Diagram ........... 122 Figure 99. Slewlim (Ty = 25 C, VoD = 3.3 V) ......... 145 Figure 76. ExpressCLK to Output Delay ................ 125 Figure 100. Fast (Ty = 25 C, VoD = 3.3 V) ............ 145 Figure 77. Fast Clock to Output Delay ................... 126 Figure 101. Sinklim (Tu = 125 C, Vob = 3.0 V) ...... 145 Figure 78. System Clock to Output Delay .............. 127 Figure 102. Slewlim (Ty = 125 C, Vob = 3.0 V) ..... 145 Figure 79. Input to ExpressCLK Setup/Hold Time ..129 Figure 103. Fast (Ts = 125 C, Vob = 3.0 V) ........... 145 Figure 80. Input to Fast Clock Setup/Hold Time .....131 Figure 104. Package Parasitics ................--:ccsessees 196 Figure 81. Input to System Clock Setup/Hold Time 132 Lucent Technologies Inc. 5ORCA Series 3C and 3T FPGAs Data Sheet June 1999 System-Level Features System-level features reduce glue logic requirements and make a system on a chip possible. These features in the ORCA Series 3 include: u Full PCI local bus compliance. u Dual-use microprocessor interface (MPI) can be used for configuration, readback, device control, and device status, as well as for a general-purpose inter- face to the FPGA. Glueless interface to i960* and PowerPCt processors with user-configurable address space provided. w Paraliel readback of configuration data capability with the built-in microprocessor interface. a Programmable clock manager (PCM) adjusts clock Table 2. ORCA Series 3 System Performance phase and duty cycle for input clock rates from 5 MHz to 120 MHz. The PCM may be combined with FPGA logic to create complex functions, such as dig- ital phase-locked loops (DPLL), frequency counters, and frequency synthesizers or clock doublers. Two PCMs are provided per device. True, internal, 3-state, bidirectional buses with simple control provided by the SLIC. 32 x 4 RAM per PFU, configurable as single- or dual- port at >176 MHz. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers. * {960 is a registered trademark of Intel Corporation. + PowerPC is a registered trademark of International Business Machines Corporation. Speed , Parameter # PFUs 4 5 % 7 Unit 16-bit Loadable Up/Down Counter 78 102 131 168 MHz 16-bit Accumulator 78 102 131 168 MHz 8 x 8 Parallel Multiplier: Multiplier Mode, Unpipelined 11.5 19 25 30 38 MHz ROM Mode, Unpipelined* 51 66 80 102 MHz Multiplier Mode, Pipelined? 15 76 104 127 166 MHz 32 x 16 RAM (synchronous): Single-port, 3-state Bus* 97 127 | 151 | 192 MHz Dual-port 127 | 166 | 203 | 253 MHz 128 x 8 RAM (synchronous): Single-port, 3-state Bus* 88 116 | 139 | 176 MHz Dual-port 88 116 | 139 | 176 MHz 8-bit Address Decode (internal): Using Softwired LUTs 0.25 4.87 3.66 | 2.58 | 2.03 ns Using SLICs 2.35 | 1.82 | 1.23 | 0.99 ns 32-bit Address Decode (internal): Using Softwired LUTs 16.06 |} 12.07; 9.01 | 7.03 ns Using SLICs 6.91 | 5.41 | 4.21 | 3.37 ns 36-bit Parity Check (internal) 16.06 | 12.07] 9.01 | 7.03 ns . Implemented using 32 x 4 dual-port RAM mode. NO ORhON = . lmplemented in five partially occupied SLICs. . Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. . Implemented using two 32 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. . Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers). . Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus. . Impiemented in one partially occupied SLIC with decoded output set up to CE in same PLC. Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Description PLC Logic FPGA Overview Each PFU within a PLC contains eight 4-input (16-bit) The ORCA Series 3 FPGAs are a new generation of SRAM-based FPGAs built on the successful OR2C/ TxxA FPGA Series from Lucent Technologies Micro- electronics Group, with enhancements and innovations geared toward todays high-speed designs and tomor- rows systems on a single chip. Designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the ORCA 2C/2T devices, Series 3 more than doubles the logic available in each logic block and incorporates sys- tem-level features that can further reduce logic require- ments and increase system speed. ORCA Series 3 devices contain many new patented enhancements and are offered in a variety of packages, speed grades, and temperature ranges. The ORCA Series 3 FPGAs consist of three basic ele- ments: programmable logic cells (PLCs), programma- ble input/output cells (PICs), and system-level features. An array of PLCs is surrounded by PICs. Each PLC contains a programmable function unit (PFU), a sup- plemental logic and interconnect cell (SLIC), local rout- ing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be per- formed in the SLIC. The PICs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals. Some of the sys- tem-level functions include the new microprocessor interface (MPI) and the programmable clock manager (PCM). Lucent Technologies Inc. look-up tables (LUTs), eight latches/flip-flops (FFs), and one additional flip-flop that may be used indepen- dently or with arithmetic functions. The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled indepen- dently. LUTs may also be combined for use in arith- metic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 sin- gle- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset. The SLIC is connected to PLC routing resources and to the outputs of the PFU. It contains 3-state, bidirectional buffers and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT (AOI) to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections to the PFU out- puts make fast, true 3-state buses possible within the FPGA, reducing required routing and allowing for real- world system performance.ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Description (continued) PIC Logic Series 3 PIC addresses the demand for ever-increas- ing system clock speeds. Each PIC contains four pro- grammable inputs/outputs (PIOs) and routing resources. On the input side, each PIO contains a fast- capture latch that is clocked by an ExpressCLK. This latch is followed by a latch/FF that is clocked by a sys- tem clock from the internal general clock routing. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer. Two input signals are available to the PLC array from each PIO, and the ORCA 2C/2T capability to use any input pin as a clock or other global input is maintained. On the output side of each PIO, two outputs from the PLC array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output sig- nals. The output FF in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The I/O buffer associated with each pad is very similar to the ORCA 2C/2T Series buffer with a new, fast, open-drain option for ease of use on system buses. System Features Series 3 also provides system-level functionality by means of its dual-use microprocessor interface and its innovative programmable clock manager. These func- tional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in todays high-speed systems. Routing The abundant routing resources of the ORCA Series 3 FPGAs are organized to route signals individually or as buses with related control signals. Clocks are routed on a low-skew, high-speed distribution network and may be sourced from PLC logic, externally from any I/O pad, or from the very fast ExpressCLK pins. Express- CLKs may be glitchlessly and independently enabled and disabled with a programmable control signal using the new StopCLK feature. The improved PIC routing resources are now similar to the patented intra-PLC routing resources and provide great flexibility in moving signals to and from the PiOs. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins. Configuration The FPGAs functionality is determined by internal configuration RAM. The FPGAs internal initialization/ configuration circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of several configuration modes. The con- figuration data resides externally in an EEPROM or any other storage media. Serial EEPROMs provide a sim- ple, low pin count method for configuring FPGAs. A new, easy method for configuring the devices is through the microprocessor interface. Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Description (continued) ORCA Foundry Development System The ORCA Foundry Development System is used to process a design from a netlist to a configured FPGA. This system is used to map a design onto the ORCA architecture and then place and route it using ORCA Foundrys timing-driven tools. The development system also includes interfaces to, and libraries for, other popu- lar CAE tools for design entry, synthesis, simulation, and timing analysis. The ORCA Foundry Development System interfaces to front-end design entry tools and provides the tools to produce a configured FPGA. In the design flow, the user defines the functionality of the FPGA at two points in the design flow: at design entry and at the bit stream generation stage. Following design entry, the development system's map, place, and route tools translate the netlist into a routed FPGA. A static timing analysis tool is provided to deter- mine device speed and a back-annotated netlist can be created to allow simulation. Timing and simulation out- put files from ORCA Foundry are also compatible with many third-party analysis tools. Its bit stream generator is then used to generate the configuration data which is loaded into the FPGA's internal configuration RAM. When using the bit stream generator, the user selects options that affect the functionality of the FPGA. Com- bined with the front-end tools, ORCA Foundry pro- duces configuration data that implements the various logic and routing options discussed in this data sheet. Architecture The ORCA Series 3 FPGA comprises three basic ele- ments: PLCs, PICs, and system-level functions. Figure 1 shows an array of programmable logic cells (PLCs) surrounded by programmable input/output cells (PICs). Also shown are the interquad routing blocks (hlQ, viQ) present in Series 3. System-level functions (located in the corners of the array) and the routing resources and configuration RAM are not shown in Figure 1. Lucent Technologies Inc. The ORS3C/T55 array in Figure 1 has PLCs arranged in an array of 18 rows and 18 columns. The location of a PLC is indicated by its row and column so that a PLC in the second row and the third column is R2C3. PICs are located on all four sides of the FPGA between the PLCs and the device edge. PICs are indicated using PT and PB to designate PICs on the top and bottom sides of the array, respectively, and PL and PR to des- ignate PICs along the left and right sides of the array, respectively. The position of a PIC on an edge of the array is indicated by a number, counting from left to right for PT and PB and top to bottom for PL and PR PiCs. Each PIC contains routing resources and four program- mable I/Os (PIOs). Each PIO contains the necessary \/O buffers to interface to bond pads. PIOs in Series 3 FPGAs also contain input and output FFs, fast open- drain capability on output buffers, special output logic functions, and signal multiplexing/demultiplexing capa- bilities. PLCs comprise a programmable function unit (PFU), a supplemental logic and interconnect cell (SLIC), and routing resources. The PFU is the main logic element of the PLC, containing elements for both combinatorial and sequential logic. Combinatorial logic is done in look-up tables (LUTs) located in the PFU. The PFU can be used in different modes to meet different logic requirements. The LUTs twin-quad architecture pro- vides a configurable medium-/large-grain architecture that can be used to implement from one to eight inde- pendent combinatorial logic functions or a large num- ber of complex logic functions using multiple LUTs. The flexibility of the LUT to handle wide input functions, as well as multiple smaller input functions, maximizes the gate count per PFU while increasing system speed. The LUTs can be programmed to operate in one of three modes: combinatorial, ripple, or memory. In com- binatorial mode, the LUTs can realize any 4- or 5-input logic function and many multilevel logic functions using ORCA's softwired LUT (SWL) connections. In ripple mode, the high-speed carry logic is used for arithmetic functions, comparator functions, or enhanced data path functions. In memory mode, the LUTs can be used as a 32 x 4 synchronous read/write or read-only memory, in either single- or dual-port mode.ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Architecture (continued) 10 Figure 1. OR3C/T55 Array ev: | pt2 | pts | ers [ pts | pre | erz | ere | pro | to | prio | eri | eri | eis | pris | pris | erie | ptiz | pris = #] pcr | rice} mics] rica} mics | rice | Ric7 | rics | Rice ric10| Rict1] RIc12| RIC1s| Acta] Arcis| Arcte] AIc17] Rice |B] i) = a] Rect | mec2| Recs | aca | Recs | Race | Rec7 | Recs | Race | ,, [Recto] Ract1| Recta] Rac13| Ract4| Rects| RecI6| RaCt7| Racis | 3 = = = z R3ci | R3IC2 | R3C3a | R3C4 | RBCS | Roce | R3C7 | RSCB | RICO R3C10 | RIC11t] F3C12) R3C13 | R3C14 | A3C15 [R13C16] R3C17] AIC18 z = = Ld Z| rect | pace | Raca | Race | Racs | Race | Rac7 | acs | Race racio| RActs| Racial RACs | Racta| acts] Recte| Ract7| Racte |B] = 2} rsct | rsc2| psc | rsce| rscs | Rsce | Asc7 | Asce | Rsco Rscio) RSC11] R5C12} R5C13| RSC14] ASC15| RSC16| ASC17] RAS5C1s 3 = | Rect | Rece| recs | Reca | Recs | Rece | Rec7 | Rece | Rece Recto} Rect] Recta] Recis| REc14| Rec15] Rect6| REc17] Recre | Z| HH = = A7c1 | Arce | R7c3 | A7C4 | A7Cs | R7cs | R7C7 | R7CA | R7C9 R7c10| A7ci1| R7C12| R7C13] A7C14| R7CIs| A7C16| A7C17| A7CIe | S| ow = = Z| Rect | Race} recs | Recs | Recs | Recs | Rec7 | Recs | Race Racto| Reci1| Raci2| REc13| Rect4| Racts| Recie|Ract7| Recie |Z] mm = = =| mec1| rece | recs | Rocs| Recs | Recs | Rac7 | Roce | Roce Recto] RSC11 Recta] ects Rec14} Rects| Recs] Rec17| Rec1s | 3] am a Q 3 hia 2 3 3 5 F F a8 2 |Rt0ct |Rioc2 |R10cs | R10c4| Riocs |Rt0Ce | R10c7| RI0C8 | R10C9 Fiocrofocgrrociz|Rrocisimtocra|atocisjArocre}r0c17| Rrocts | =| im a = 5 | Aric JRrac2 [Arics | R11C4] Mics Rr1C8 [A11C7 [RI1C8 | RI1C9 Prrcidancrfarcrgricts pricnfarcasarioifaicr ancis|2| mm =j @ s al 3| = 3 | Rt2c1 |R12c2 FR12c3 | R12c4] Rt2cs |R12C8 [R12C7 |RI2ce |RIZC9 Puzcioji2ct wRI2ciaiAt2ciaiAracralar2cis|At2creiR12c17) Rizcie |B) a e frvscre | 3| 5 2 | niac1 {r1ac2 |Ri3c | Rica] Riscs |Risce |RI3C7 |R13Ca [A13C9 isciojri3ci tarsciaiAiscisinrscraniscts|A1sc76|R13017| Aiscie | 2] a a o = < 3 = = | R1act |Riace [Race | Riaca! Rr4cs [R14ce [R14C7 |RI4ce | RI14C9 Pracio|aracr crafts Pracrafmnacispmnactefniacr7 rracis | 2] a a a 8 d be 3| 5 2 | n1sc1 | a1sc2 | Rises | R1sca] RiScs |Riscs [RI15C7 [RIsca | R15C9 RISC riscrdmrscrafscts Piscralmiscisiriscre|nisct7| niscie | 2} me a . am s i e 3| 5 5 | Rect |Riece jrtecs | R16C4) R16Cs |RI6Cs | Fu6C7 | RI6C8 | RECO Rrecrofarecrtarecs iecia Precra|arecro}Arecs Rieci7|miecie | 2] a a 6 a| @ 5 | arzcs | r7c2 | A1703 | 1704] A708 | R1706 | RI7C7 | R178 | AI7C9 PA7CIOfRI7CA AANTCIZARIZC1S|AN7CI4|AN7CIS|AI7CIe|AI7C17) A17C18 | 2) | @ a 2 ol 2] 3 | Rrect |riace |R1ecs | R1acs] R1acs | Race |R18C7 |RIEC8 | RTECS iacioinieci qRIECIaATECIsfA1aciaiRiecis|RIEcie|AIaCI7| RIecis | 2] am "8 pat | pez | pes | pes] pes | pes | pe7 | pes | pas | Pe10 | ean | P11 | PB12 | Pers | Pere | pois | Pete | PBI7 | pote BERRA ER REE RRR BE RERREEERA ERE 5-4489(F) Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells j FsD The programmable logic cell (PLC) consists of a pro- J x70 grammable function unit (PFU), a supplemental logic | Kr and interconnect cell (SLIC), and routing resources. All 8 PLCs in the array are functionally identical with only minor differences in routing connectivity for improved | Key routability. The PFU, which contains eight 4-input LUTs, 7 Ke-2 eight latches/FFs, and one FF for logic implementation, ~ is discussed in the next section, followed by discus- ee sions of the SLIC and PLC routing resources. | Ks_2 Ks_3 K+_9 Programmable Function Unit ke The PFUs are used for logic. Each PFU has 50 external m8 Cc inputs and 18 outputs and can operate in several 7 Fse Q5 - modes. The functionality of the inputs and outputs DIN7 as a depends on the operating mode. BINS Q2 [ The PFU uses 36 data input lines for the LUTs, eight 1 BIN PROGRAMMABLE Qo - data input lines for the latches/FFs, five control inputs DIN2 tar UNIT (ASWE, CLK, CE, LSR, SEL), and a carry input (CIN) bino REGSoUT for fast arithmetic functions and general-purpose data J on input for the ninth FF. There are eight combinatorial data F7 +} outputs (one from each LUT), eight latched/registered ] FsB F6 -> outputs (one from each latch/FF), a carry-out (COUT), ks.0 ei and a registered carry-out (REGCOUT) that comes from I Ket F3 -& the ninth FF. The carry-out signals are used principally j K3.3 Fe Le for fast arithmetic functions. l eo FO - Figure 2 and Figure 3 show high-level and detailed 4 views of the ports in the PFU, respectively. The eight k2_3 sets of LUT inputs are labeled as Ko through K7 with | k1.0 each of the four inputs to each LUT having a suffix of Fku1 _X, where x is a number from 0 to 3. There are four F5 _ King inputs labeled A through D. These inputs are used for a ] ko 0 fifth LUT input for 5-input LUTs or as a selector for multi- | Ko_1 plexing two 4-input LUTs. The eight direct data inputs to I Ko_2 the latches/FFs are labeled as DIN[7:0]. Registered LUT 7 outputs are shown as Q{7:0], and combinatorial LUT ] F5A outputs are labeled as F[7:0]. LSR__ CLK CE __SEL__ASWE The PFU implements combinatorial logic in the LUTs | | | | | and sequential logic in the latches/FFs. The LUTs are 5-5752(F) static random access memory (SRAM) and can be used . for read/write or read-only memory. Figure 2. PFU Ports Each latch/FF can accept data from its associated LUT. Alternatively, the latches/FFs can accept direct data The PFU can be configured to operate in four modes: from DIN[7:0], eliminating the LUT delay if no combina- logic mode, half-logic mode, ripple mode, and memory torial function is needed. Additionally, the CIN input can (RAM/ROM) mode. In addition, ripple mode has four be used as a direct data source for the ninth FF. The submodes and RAM mode can be used in either a LUT outputs can bypass the latches/FFs, which reduces single- or dual-port memory fashion. These submodes the delay out of the PFU. It is possible to use the LUTs of operation are discussed in the following sections. and latches/FFs more or less independently, allowing, for instance, a comparator function in the LUTs simulta- neously with a shift register in the FFs. Lucent Technologies Inc. 11Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Programmable Logic Cells (continued) 5-5743(F) Note: All multiplexers without select inputs are configuration selector multiplexers. Figure 3. Simplified PFU Diagram 12 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) Look-Up Table Operating Modes The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For exam- ple, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latches/FFs. In memory mode, the same DIN[?:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into LUT memory. Table 3 lists the basic operating modes of the LUT. Figure 4Figure 10 show block diagrams of the LUT operating modes. The accompanying descriptions demonstrate each modes use for generating logic. Table 3. Look-Up Table Operating Modes Mode Function Logic | 4- and 5-input LUTs; softwired LUTs; latches/FFs with direct input or LUT input; CIN as direct input to ninth FF or as pass through to COUT. Haif Logic/| Upper four LUTs and latches/FFs in logic mode; lower four LUTs and latches/FFs in ripple mode; CIN HalfRipple| and ninth FF for logic or ripple functions. Ripple } All LUTs combined to perform ripple-through data functions. Eight LUT registers available for direct-in use or to register ripple output. Ninth FF dedicated to ripple out, if used. The submodes of ripple mode are adder/subtractor, counter, multiplier, and comparator. Memory | Ail LUTs and latches/FFs used to create a 32 x 4 synchronous dual-port RAM. Can be used as single- port or as ROM. PFU Control inputs Each PFU has five routable control inputs and an active-low, asynchronous global set/reset (GSRN) signal that affects all latches and FFs in the device. The five contro! inputs are CLK, LSR, CE, ASWE, and SEL, and their functionality for each logic mode of the PFU (discussed subsequently) is shown in Table 4. The clock signal to the PFU is CLK, CE stands for clock enable, which is its primary function. LSR is the local set/reset signal that can be configured as synchronous or asynchronous. The selection of set or reset is made for each latch/FF and is not a function of the signal itself. ASWE stands for add/subtract/write enable, which are its functions, along with being an optional clock enable, and SEL is used to dynamically select between direct PFU input and LUT output data as the input to the latches/FFs. All of the control signals can be disabled and/or inverted via the configuration logic. A disabled clock enable indi- cates that the clock is always enabled. A disabled LSR indicates that the latch/FF never sets/resets (except from GSRN). A disabled SEL input indicates that DIN[7:0] PFU inputs are routed to the latches/FFs. For logic and ripple modes of the PFU, the LSR, CE, and ASWE (as a clock enable) inputs can be disabled individually for each nibble (latch/FF[3:0}, latch/FF[7:4]) and for the ninth FF. Lucent Technologies Inc. 13Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Programmable Logic Cells (continued) Table 4. Control Input Functionality Mode CLK LSR CE ASWE SEL Logic | CLK to all latches/ | LSR to all latches/ CE to all latches/FFs, | CE to all latches/FFs, | Select between LUT FFs FFs, enabled per nib- | selectable per nibble | selectable per nibble | input and direct input ble and for ninth FF =| and for ninth FF and for ninth FF for eight latches/FFs Half Logic/ | CLK to all latches/ | LSR to all latches/FF, | CE to all latches/FFs, | Ripple logic control Select between LUT Half Ripple | FFs enabled per nibble selectable per nibble | input input and direct input and for ninth FF and for ninth FF for eight latches/FFs Ripple | CLK to all latches/ | LSR to all latches/ CE to all latches/FFs, | Ripple logic control {| Select between LUT FFs FFs, enabled per nib- | selectable per nibble | input input and direct input ble and for ninth FF | and for ninth FF for eight latches/FFs Memory | CLK to RAM Port enable 2 Port enable 1 Write enable Not used (RAM) Memory | Optional for sync. | Not used Not used Not used Not used (ROM) _ | outputs Logic Mode FSD The PFU diagram of Figure 3 represents the logic mode of operation. In logic mode, the eight LUTs are used individually or in flexible groups to implement user logic functions. The latches/FFs may be used in con- junction with the LUTs or separately with the direct PFU data inputs. There are three basic submodes of LUT operation in PFU logic mode: F4 mode, F5 mode, and softwired LUT (SWL) mode. Combinations of these submodes are possible in each PFU. F4 mode, shown simplified in Figure 4, illustrates the uses of the basic 4-input LUTs in the PFU. The output of an F4 LUT can be passed out of the PFU, captured at the LUTs associated latch/FF, or multiplexed with the adjacent F4 LUT output using one of the F5[A:D] inputs to the PFU. Only adjacent LUT pairs (Ko and K1, K2 and K3, K4 and Ks, Ke and K7) can be multiplexed, and the output always goes to the even-numbered output of the pair. The F5 submode of the LUT operation, shown simpli- fied in Figure 4, indicates the use of 5-input LUTs to implement logic. 5-input LUTs are created from two 4-input LUTs and a multiplexer. The F5 LUT is the same as the multiplexing of two F4 LUTs described previously with the constraint that the inputs to the F4 LUTs be the same. The F5[A:D] input is then used as the fifth LUT input. The equations for the two F4 LUTs will differ by the assumed value for the F5[A:D] input, one F4 LUT assuming that the F5[A:D] input is zero, and the other assuming it is a one. The selection of the appropriate F4 LUT output in the F5 MUX by the F5[A:D] signal creates a 5-input LUT. Any combination of F4 and F5 LUTs is allowed per PFU using the eight 16-bit LUTs. Examples are eight F4 LUTs, four F5 LUTs, and a combination of four F4 plus two F5 LUTs. 14 a a | { 3 q T a tl el tl ta Fa x | n nN 1) FA 2 a FO ay aah Ah el ah F4 MODE ra z a F4 za F2 \_/ 3 FSA K7/K6r F6 FA i F2 Ki/Kof FO UN Ye "4 Hn F5 MODE MULTIPLEXED F4 MODE 5-5970(F) Figure 4. Simplified F4 and F5 Logic Modes Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) Softwired LUT submode uses F4 and F5 LUTs and internal PFU feedback routing to generate complex logic func- tions up to three LUT-levels deep. Figure 3 shows multiplexers between the Kz[3:0] inputs to the PFU and the LUTs. These multiplexers can be independently configured to route certain LUT outputs to the input of other LUTs. In this manner, very complex logic functions, some of up to 21 inputs, can be implemented in a single PFU at greatly enhanced speeds. Figure 5 shows several softwired LUT topologies. In this figure, each circle represents either an F4 or F5 LUT. It is important to note that an LUT output that is fed back for softwired use is still available to be registered or output from the PFU. This means, for instance, that a logic equation that is needed by itself and as a term in a larger equation need only be generated once and PLC routing resources will not be required to use it in the larger equa- FOUR 7-INPUT FUNCTIONS IN ONE PFU TWO 9-INPUT FUNCTIONS IN ONE PFU ee (TY ONE 17-INPUT FUNCTION IN ONE PFU ONE 21-INPUT FUNCTION IN ONE PFU 5-S753(F) TWO OF FOUR 10-INPUT FUNCTIONS IN ONE PFU ONE OF TWO 12-INPUT FUNCTIONS IN ONE PFU 5-5754(F) KEY: 4-INPUT LUT (*) 5-INPUT LUT Figure 5. Softwired LUT Topology Examples Lucent Technologies Inc. 15ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Logic Cells (continued) Half-Logic Mode Series 3 FPGAs are based upon a twin-quad architec- ture in the PFUs. The byte-wide nature (eight LUTs, eight latches/FFs) may just as easily be viewed as two nibbles (two sets of four LUTs, four latches/FFs). The two nibbles of the PFU are organized so that any nib- ble-wide feature (excluding some softwired LUT topolo- gies) can be swapped with any other nibble-wide feature in another PFU. This provides for very flexible use of logic and for extremely flexible routing. The half- logic mode of the PFU takes advantage of the twin- quad architecture and allows half of a PFU, K[7:4] and associated latches/FFs, to be used in logic mode while the other half of the PFU, K[3:0] and associated latches/ FFs, is used in ripple mode. In half-logic mode, the ninth FF may be used as a general-purpose FF or as a register in the ripple mode carry chain. Ripple Mode The PFU LUTs can be combined to do byte-wide ripple functions with high-speed carry logic. Each LUT has a dedicated carry-out net to route the carry to/from any adjacent LUT. Using the internal carry circuits, fast arithmetic, counter, and comparison functions can be implemented in one PFU. Similarly, each PFU has carry-in (CIN, FCIN) and carry-out (COUT, FCOUT) ports for fast-carry routing between adjacent PFUs. The ripple mode is generally used in operations on two data buses. A single PFU can support an 8-bit ripple function. Data buses of 4 bits and less can use the nibbie-wide ripple chain that is available in half-logic mode. This nibble-wide ripple chain is also useful for longer ripple chains where the length modulo 8 is four or less. For example, a 12-bit adder (12 modulo 8 = 4) can be implemented in one PFU in ripple mode (8 bits) and one PFU in half-logic mode (4 bits), freeing half of a PFU for general logic mode functions. Each LUT has two operands and a ripple (generally carry) input, and provides a result and ripple (generally carry) output. A single bit is rippled from the previous LUT and is used as input into the current LUT. For LUT Ko, the ripple input is from the PFU CIN or FCIN port. The CIN/FCIN data can come from either the fast-carry routing (FCIN) or the PFU input (CIN), or it can be tied to logic 1 or logic 0. In the following discussions, the notations LUT K7/K3 and F[7:0]/F[3:0] are used to denote the LUT that pro- vides the carry-out and the data outputs for full PFU ripple operation (K7, F[7:0]) and half-logic ripple operation (K3, F[3:0]), respectively. The ripple mode diagram in Figure 6 shows full PFU ripple operation, 16 with half-logic ripple connections shown as dashed lines. The result output and ripple output are calculated by using generate/propagate circuitry. In ripple mode, the two operands are input into Kz[1] and Kz[0] of each LUT. The result bits, one per LUT, are F[7:0)/F[3:0] (see Figure 6). The ripple output from LUT K7/K3 can be routed on dedicated carry circuitry into any of four adja- cent PLCs, and it can be placed on the PFU COUT/ FCOUT outputs. This allows the PLCs to be cascaded in the ripple mode so that nibble-wide ripple functions can be expanded easily to any length. Result outputs and the carry-out may optionally be reg- istered within the PFU. The capability to register the ripple results, including the carry output, provides for improved counter performance and simplified pipelin- ing in arithmetic functions. REGCOUT FCOUT COUT F7 K7[1] K7[0] Q7 F6 Ke[1} K6[0] Q6 F5 K5{1] K5I0} Q5 F4 Ka{t] K4[o] Q4 F3 K3[1] K3[0] F2 K2{1] K2(0] FA Ka[1} K1[0] Qi Fo Kot] Ko{0] Qo CIN/FCIN 5-5755(F) Figure 6. Ripple Mode Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) The ripple mode can be used in one of four submodes. The first of these is adder-subtractor submode. In this submode, each LUT generates three separate out- puts. One of the three outputs selects whether the carry-in is to be propagated to the carry-out of the cur- rent LUT or if the carry-out needs to be generated. If the carry-out needs to be generated, this is provided by the second LUT output. The result of this selection is placed on the carry-out signal, which is connected to the next LUT carry-in or the COUT/FCOUT signal, if it is the last LUT (K7/K3). Both of these outputs can be any equation created from Kz[1] and Kz[0], but in this case, they have been set to the propagate and gener- ate functions. The third LUT output creates the result bit for each LUT output connected to F[7:0)/F[3:0}. If an adder/subtrac- tor is needed, the control signal to select addition or subtraction is input on ASWE, with a logic 0 indicating subtraction and a logic 1 indicating addition. The result bit is created in one-half of the LUT from a single bit from each input bus Kz[1:0], along with the ripple input bit. The second submode is the counter submode (see Figure 7). The present count, which may be initialized via the PFU DIN inputs to the latches/FFs, is supplied to input KZ[O], and then output F[7:0}/F[3:0] will either be incremented by one for an up counter or decre- mented by one for a down counter. if an up/down counter is needed, the control signal to select the direc- tion (up or down) is input on ASWE with a logic 1 indi- cating an up counter and a logic 0 indicating a down counter. Generally, the latches/FFs in the same PFU are used to hold the present count value. Lucent Technologies Inc. K1 CIN/FCIN Figure 7. Counter Submode REGCOUT FCOUT Q7 F6 FS Q5 F4 F3 a3 F2 Q2 FI Qi Fo Qo 5-5756(F) 17ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Logic Cells (continued) In the third submode, multiplier submode, a single PFU can affect an 8 x 1 bit (4 x 1 for half-ripple mode) multiply and sum with a partial product (see Figure 8). The multiplier bit is input at ASWE, and the multiplicand bits are input at Kz[1], where K7[1} is the most signifi- cant bit (MSB). Kz[0] contains the partial product (or other input to be summed) from a previous stage. If ASWE is logical 1, the multiplicand is added to the par- tial product. if ASWE is logical 0, 0 is added to the par- tial product, which is the same as passing the partial product. CIN/FCIN can bring the carry-in from the less significant PFUs if the multiplicand is wider than 8 bits, and COUT/FCOUT holds any carry-out from the multi- plication, which may then be used as part of the prod- uct or routed to another PFU in multiplier mode for multiplicand width expansion. Ripple modes fourth submode features equality comparators. The functions that are explicitly available are A> B, A#B, and A<B, where the value for A is input on Kz[0}, and the value for B is input on Kz[1]. A value of 1 on the carry-out signals valid argument. For example, a carry-out equal to 1 in AB submode indi- cates that the value on K2(0] is greater than or equal to the value on Kz[1]. Conversely, the functions A < B, A+ B, and A > B are available using the same functions but with a 0 output expected. For example, A > B with a0 output indicates A < B. Table 5 shows each function and the output expected. If larger than 8 bits, the carry-out signal can be cas- caded using fast-carry logic to the carry-in of any adja- cent PFU. The use of this submode could be shown using Figure 6, except that the CIN/FCIN input for the least significant PFU is controlled via configuration. Table 5. Ripple Mode Equality Comparator Functions and Outputs Equality | ORCA Foundry True, if Function Submode Carry-Out Is: A>B A>B : 1 A<B A<B 1 A#B A#B 1 A<B A>B 0 A>B A<B 0 A=B A#B 0 18 ASWE K7[1] K7[0] Ke[1] Ke[0} Ks{1] Ks{0] Ke{1] Ka{0] Keo[1] K3[0] K2{1] K2{0] Ki[1] K1[0] Kof[1] Ko[0] REGCOUT COUT F7 a7 FG as F5 Qs F4 a4 F3 Q3 F2 Q2 Fi Qt FO Qo 5-S757(F) Key: C = configuration data. Figure 8. Multiplier Submode Lucent Technologies inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs _ Programmable Logic Cells (continued) Memory Mode The Series 3 PFU can be used to implement a 32 x 4 (128-bit) synchronous, dual-port random access memory (RAM). A block diagram of a PFU in memory mode is shown in Figure 9. This RAM can also be configured to work as a single-port memory and because initial values can be loaded into the RAM during configuration, it can also be used as a read-only memory (ROM). FS5[A:D] READ K2ia0) 4 ADDRESS{4:0] cinewas){p al % ADDRESS(4:0} pIN7(WA3) +p al F6 | F4 F2 DINS(WA2) rT Fo [> at a6 DINS(WA1) +4 aL p , bp ak as R DIN1(WAD) +4 al DATAI3.O][~ +h Lb D ak a DING(WD3) 1p Q}p7ey WATE, | piNswwo2) +p at re pinawo1) +p at pD pinowpo) +p al Pp ASWE(WREN) 1p qh] WRITE PE1) + CE(WPE!) an > RAM CLOCK LSRWPE2) |] Figure 9. Memory Mode The PFU memory mode uses all LUTs and latches/FFs including the ninth FF in its implementation as shown in Figure 9. The read address is input at the Kz[3:0] and F5[A:D] inputs where Kz[0] is the LSB and F5[A:D] is the MSB, and the write address is input on CIN (MSB) and DIN[7, 5, 3, 1], with DIN[1] being the LSB. Write data is input on DIN{6, 4, 2, 0], where DIN[6] is the MSB, and read data is available combinatorially on F[6, 4, 2, 0] and registered on QJ6, 4, 2, 0] with F[6] and Q[6] being the MSB. The write enable signal is input at ASWE, and two write port enables are input on CE and LSR. The PFU CLK signal is used to synchronously write the data. The polarities of the clock, write enable, and port enables are all programmable. Write-port enables may be disabled if they are not to be used. Lucent Technologies Inc. 19ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Logic Cells (continued) Data is written to the write data, write address, and write enable registers on the active edge of the clock, but data is not written into the RAM until the next clock edge one-half cycle later. The read port is actually asynchronous, providing the user with read data very quickly after setting the read address, but timing is also provided so that the read port may be treated as fully synchronous for write then read applications. If the read and write address lines are tied together (main- taining MSB to MSB, etc.), then the dual-port RAM operates as a synchronous single-port RAM. If the write enable is disabled, and an initial memory contents is provided at configuration time, the memory acts as a ROM (the write data and write address ports and write port enables are not used). Wider memories can be created by operating two or more memory mode PF Us in parallel, all with the same address and control signals, but each with a different nibble of data. To increase memory word depth above 32, two or more PLCs can be used. Figure 10 shows a 128 x 8 dual-port RAM that is implemented in eight PLCs. This figure demonstrates data path width expan- sion by placing two memories in parallel to achieve an WDI[7:0] WPEi RDf3:0] SLIC RO[?:0] WE WA{6:0] RA{6:0} CLK RE 8-bit data path. Depth expansion is applied to achieve 128 words deep using the 32-word deep PFU memo- ries. In addition to the PFU in each PLC, the SLIC (described in the next section) in each PLC is used for read address decodes and 3-state drivers. The 128 x 8 RAM shown could be made to operate as a single-port RAM by tying (bit-for-bit) the read and write addresses. To achieve depth expansion, one or two of the write address bits (generally the MSBs) are routed to the write port enables as in Figure 10. For 2 bits, the bits select which 32-word bank of RAM of the four available from a decode of two WPE inputs is to be written. Simi- larly, 2 bits of the read address are decoded in the SLIC and are used to control the 3-state buffers through which the read data passes. The write data bus is common, with separate nibbles for width expan- sion, across all PLCs, and the read data bus is com- mon (again, with separate nibbles) to all PLCs at the output of the 3-state buffers. Figure 10 also shows a new optional capability to pro- vide a read enable for RAMs/ROMs in Series 3 using the SLIC cell. The read enable will 3-state the read data bus when inactive, allowing the write data and read data buses to be tied together if desired. RD[3:0] SLIC L 5-5749(F) Figure 10. Memory Mode Expansion Example128 x 8 RAM 20 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) Supplemental Logic and Interconnect Cell (SLIC) Each PLC contains a supplemental logic and intercon- nect cell (SLIC) embedded within the PLC routing, out- side of the PFU. As its name indicates, the SLIC performs both logic and interconnect (routing) func- tions. Its main features are 3-statable, bidirectional buff- ers, and a PAL-like decoder capability. Figure 11 shows a diagram of a SLIC with all of its features shown. All modes of the SLIC are not available at one time. Each SLIC contains ten bidirectional (BIDI) buffers, each buffer capable of driving left and/or right out of the SLIC. These BIDI buffers are twin-quad in nature and are segregated into two groups of four (nibbles) and a third group of two for control. Each of these groups of BIDIs can drive from the left (BLI[9:0]) to the right (BRO[9:0]), the right (BRI[9:0]) to the left (BLO[9:0)), or from the central input (I[9:0]) to the left and/or right. This central input comes directly from the PFU outputs (O[9:0]). Each of the BIDIs in the nibble-wide groups also has a 3-state buffer capability, but not the third group. There is one 3-state control (TRI) for each SLIC, with the capability to invert or disable the 3-state control for each group of four BIDIs. Separate 3-state control for each nibble-wide group is achievable by using the SLICs decoder (DEC) output, driven by the group of two BIDIs, to control the 3-state of one BIDI nibbie while using the TRI signal to control the 3-state of the other BIDI nibble. Figure 12 and Figure 13 show the SLIC in buffer mode with available 3-state control from the TRI and DEC signals. If the entire SLIC is acting in a buffer capacity, the DEC output may be used to gen- erate a constant logic 1 (VHI) or logic 0 (VLO) signal for general use. The SLIC may also be used to generate PAL-like AND- OR with optional INVERT (AOl) functions or a decoder Lucent Technologies Inc. of up to 10 bits. Each group of buffers can feed into an AND gate (4-input AND for the nibble groups and 2- input AND for the other two buffers). These AND gates then feed into a 3-input gate that can be configured as either an AND gate or an OR gate. The output of the 3- input gate is invertible and is output at the DEC output of the SLIC. Figure 16 shows the SLIC in full decoder mode. The functionality of the SLIC is parsed by the two nibble-wide groups and the 2-bit buffer group. Each of these groups may operate independently as BID! buff- ers (with or without 3-state capability for the nibble- wide groups) or as a PAL/decoder. As discussed in the memory mode section, if the SLIC is placed into one of the modes where it contains both buffers and a decode or AOI function (e.g., BUF_BUF_DEC mode), the DEC output can be gated with the 3-state input signal. This allows up to a 6-input decode (e.g., BUF_DEC_DEC mode) plus the 3-state input to control the enable/disable of up to four buffers per SLIC. Figure 12Figure 16 show several configu- rations of the SLIC, while Table 6 shows all of the possi- ble modes. Table 6. SLIC Modes Mode Mode BUF BUF BUF # [3:0] [7:4] [9:8] 1 BUFFER Buffer Buffer Buffer 2 BUF_BUF_DEC}| Buffer Buffer | Decoder 3 BUF_DEC_BUF]| Buffer | Decoder! Buffer 4 BUF_DEC_DEC]|; Buffer | Decoder | Decoder 5 DEC_BUF_BUF || Decoder| Buffer Buffer 6 DEC_BUF_DEC]| Decoder| Buffer | Decoder 7 DEC_DEC_BUF|| Decoder | Decoder! Buffer 8 DECODER Decoder | Decoder | Decoder 21Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Programmable Logic Cells (continued) BRI9__ IN BLog 19 rr = nN BLOg BLIO U | BROS > BROS p els BRIa ~ BLOB BRIS ~ BLos 18 . 2 [Bros BLIB [BROS BLS a =, _ oF e PAIN BLO? BRIZ_ NN BLOT ca > 1 [ror [eer ar an] Se BLOS BRIG N BLOG eo BROS BUC we | BARE i BROS o_O BLIG ee BAIS BLOS ~ 15 ~~ er BRIS BLO5 BLS Ler Lo et N HY oT a 15 DEC BROS BRI > __BUS ot BLOs LY 4 rn, eee BRO4 BL4 Y Ot ee BRI A BLO4 >is BRO4 = = x] o1 oO \ TRI Oe HIGH Z WHEN LOW tht on J { DEC HIGH Z WHEN LOW 0 " magia ue BRIS TOG 3 Pt a td} AVHI OR VLO a] |_ BROS on BUS Bi rh BLO? BRI3 ~~ 8LO3 r4 > ~_S BRO2 13 B2___| > BLS U by BROS BRIM BLO1 "1 S ral sro. BRI2 XN BLo2 it __ Y 2 bt BRO2 BLI2 BRIO BLOO a <_ Y ow Como aRit BLIO p - aC 55744(F) +BBlL___n BLOt BLT bt BRO1 Figure 11. SLIC All Modes Diagram . a BRIO BLOO aN, 10 BLIO BROO TO 5-5745(F) 22 Figure 12. Buffer Mode Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) BRIS ~ BLIS HY BRIS ~ BLIS YY pBRIZ_ NY BLO7 17 BLT U BRO7 is _N BLOG 16 *BLIG B BROG NY BLOS 15 *BLIS y BROS5 tN BLO4 14 BLS y BRO4 1 HIGH Z DEC ek ~ WHEN LOW Hq Le 1 1 HIGH Z WHEN LOW 1 as _N BLOS BLS U a BRO3 oBRI2 UN BLO2 12 4 Tero2 BLD U BRO2 BRH N BLO1 u BRO1 BLI By NN BLOO 10 BLIO p BROO, 5-5746(F) Figure 13. Buffer-Buffer-Decoder Mode Lucent Technologies Inc. BRIS N BLO9 BLIS i, BROO, | = N BLOS BLIS | BROS va BRI7 ~ BLI7 YY BRIG ~ BLIG va BRIS ~ BLIS YY" BRI4 ~ BLI4 TI TRI DEC HIGH Z WHEN LOW ~ BLO3 s Pt l pros BLI3 ce LY BRI2 N BLOZ 2 : l BLi2 - | BRO2 neememmenmnnn Pd BRI1 BLO1 i rr _ BL - LBRO1 Bu BRIO ~ BLOO BLIO - LBRO * a 5-5747(F) Figure 14. Buffer-Decoder-Buffer Mode 23Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Programmable Logic Cells (continued) BRIS ~ BRIS ON BLI9 : BLI9 BRIS N } BRI8 NS pf f BLIS BLIS HY > BRI7 ms BRI7_ Ow. BLI7 BLI7 v YY _ BRIE UN BRIG ar a Ls BLIG | ) va omemmen BRIS ~ - | BRIS Ny Tre _ BLI5 y BLIS > Y BRIG x > BRIAN BLI4 YY = DEC I> TR J> Hef ee 1 HIGH Z WHEN LOW 7 GRIs BLO3 st y ne BROS BRI3 BRI2 \ re BLo2 _ BUS | | 12 BRI BLI2 NX r BLO1 _Btle 4 J BRO1 BLIt p a [ad BRI1 BRIO N BLOO BLI1 }H 10 le . BLIO LBRO BRIO a 5-5750(F) _ BLIO 5-5748(F) Figure 15. Buffer-Decoder-Decoder Mode Figure 16. Decoder Mode 24 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) PLC Latches/Flip-Flops The eight general-purpose latches/FFs in the PFU can be used in a variety of configurations. In some cases, the configuration options apply to all eight latches/FFs in the PFU and some apply to the latches/FFs on a nibbie- wide basis where the ninth FF is considered indepen- dently. For other options, each latch/FF is independently programmable. In addition, the ninth FF can be used for a variety of functions. Table 7 summarizes these latch/FF options. The latches/FFs can be configured as either positive- or negative-level sensitive latches, or positive or negative edge-triggered flip-flops (the ninth register can only be FF). All latches/FFs in a given PFU share the same clock, and the clock to these latches/FFs can be inverted. The input into each latch/FF is from either the corresponding LUT output (F[7:0]) or the direct data input (DIN[7:0]). The latch/FF input can also be tied to logic 1 or to logic 0, which is the default. Table 7. Configuration RAM Controlled Latch/ Flip-Flop Operation Function Options Common to All Latches/FFs in PFU LSR Operation Asynchronous or synchronous Clock Polarity Noninverted or inverted Front-end Select* | Direct(DIN[7:0})orfromLUT (F[7:0]) LSR Priority Either LSR or CE has priority Latch/FF Mode Latch or flip-flop Enable GSRN GSRN enabled or has no effect on PFU latches/FFs Set Individually in Each Latch/FF in PFU Set/Reset Mode | Set or reset By Group (Latch/FF[3:0], Latch/FF[7:4], and FF[8]) Clock Enable CE or ASWE or none LSR Control LSR or none * Not available for FF[8]. Lucent Technologies Inc. The eight latches/FFs in a PFU share the clock (CLK) and options for clock enable (CE), local set/reset (LSR), and front-end data select (SEL) inputs. When CE is dis- abled, each latch/FF retains its previous value when clocked. The clock enable, LSR, and SEL inputs can be inverted to be active-low. The set/reset operation of the latch/FF is controlled by two parameters: reset mode and set/reset value. When the global set/reset (GSRN) and local set/reset (LSR) signals are not asserted, the latch/FF operates normally. The reset mode is used to select a synchronous or asynchronous LSR operation. If synchronous, LSR has the option to be enabled only if clock enable (CE or ASWE) is active or for LSR to have priority over the clock enable input, thereby setting/resetting the FF inde- pendent of the state of the clock enable. The clock enable is supported on FFs, not latches. It is imple- mented by using a 2-input multiplexer on the FF input, with one input being the previous state of the FF and the other input being the new data applied to the FF. The select of this 2-input multiplexer is clock enable (CE or ASWE), which selects either the new data or the previ- ous state. When the clock enable is inactive, the FF out- put does not change when the clock edge arrives. 25ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Logic Cells (continued) The GSRN signal is only asynchronous, and it sets/ resets all latches/FFs in the FPGA based upon the set/ reset configuration bit for each latch/FF. The set/reset value determines whether GSRN and LSR are set or reset inputs. The set/reset vaiue is independent for each latch/FF. A new option is available to disable the GSRN function per PFU after initial device configura- tion. The latch/FF can be configured to have a data front- end select. Two data inputs are possible in the front- end select mode, with the SEL signal used to select which data input is used. The data input into each latch/FF is from the output of its associated LUT, F[7:0], or direct from DIN[7:0], bypassing the LUT. In the front- end data select mode, both signals are available to the latches/FFs. If either or both of these inputs is unused or is unavail- able, the latch/FF data input can be tied to a logic 0 or logic 1 instead (the default is logic 0). CE/ASWE s_set LSR sreset GSRN > CLK isn) SET RESET GSAN ! ry Key: C = configuration data. CEASE SEL F DIN F CE F CE CE DIN D ro) a D a Hess bD ~ abe LOGIC 1 LOGIC 1 DIN LOGIC 0 LOGIC 0 Tre [ana The latches/FFs can be configured in three basic modes: 1. Local synchronous set/reset: the input into the PFUs LSR port is used to synchronously set or reset each latch/FF. 2. Local asynchronous set/reset: the input into LSR asynchronously sets or resets each latch/FF. 3. Latch/FF with front-end select, LSR either synchro- nous or asynchronous: the data select signal selects the input into the latches/FFs between the LUT output and direct data in. For all three modes, each latch/FF can be indepen- dently programmed as either set or reset. Figure 17 provides the logic functionality of the front-end select, global set/reset, and local set/reset operations. The ninth PFU FF, which is generally associated with registering the carry-out signal in ripple mode func- tions, can be used as a general-purpose FF. It is only an FF and is not capable of being configured as a latch. Because the ninth FF is not associated with an LUT, there is no front-end data select. The data input to the ninth FF is limited to the CIN input, logic 1, logic 0, or the carry-out in ripple and half-logic modes. CE/ASWE GSRN > CLK LSR SET RESET > CLK SET RESET Figure 17. Latch/FF Set/Reset Configurations 26 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) PLC Routing Resources Generally, the ORCA Foundry Development System is used to automatically route interconnections. !nterac- tive routing with the ORCA Foundry design editor (EPIC) is also available for design optimization. To use EPIC for interactive layout, an understanding of the routing resources is needed and is provided in this sec- tion. The routing resources consist of switching circuitry and metal interconnect segments. Generally, the metal lines which carry the signals are designated as routing seg- ments. The switching circuitry connects the routing segments, providing one or more of three basic func- tions: signal switching, amplification, and isolation. A net running from a PFU or PIC output (source) to a PLC or PIC input (destination) consists of one or more routing segments, connected by switching circuitry called configurable interconnect points (CIPs). The following sections discuss PLC, PIC, and interquad routing resources. This section discusses the PLC switching circuitry, intra-PLC routing, inter-PLC routing, and clock distribution. Configurable Interconnect Points The process of connecting routing segments uses three basic types of switching circuits: two types of con- figurable interconnect points (CIPs) and bidirectional buffers (BIDIs). The basic element in CIPs is one or more pass transistors, each controlled by a configura- tion RAM bit. The two types of CiPs are the mutually exclusive (or multiplexed) CIP and the independent CIP. A mutually exclusive set of CIPs contains two or more CIPs, only one of which can be on at a time. An inde- pendent CIP has no such restrictions and can be on independent of the state of other CIPs. Figure 18 shows an example of both types of CIPs. Lucent Technologies Inc. INDEPENDENT CIP B A = a_I Lp MULTIPLEXED CIP O 2 A aT B B oO c Cc Key: C = configuration data. 5-5973(C) Figure 18. Configurable Interconnect Point 3-Statable Bidirectional Buffers Bidirectional buffers, previously described in the SLIC section of the programmable logic cell discussion, pro- vide isolation as well as amplification for signals routed a long distance. Bidirectional buffers are also used to route signals diagonally in the PLC (described later in the subsection entitled Intra-PLC Routing), and BIDIs can be used to indirectly route signals through the switching routing (xSW) segments. Any number from zero to ten BIDis can be used in a given PLC. 27Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Programmable Logic Cells (continued) General Routing Structure Routing resources in Series 3 FPGAs generally consist of routing segments in groups of ten, with varying lengths and connectivity to logic and other routing resources. The varying lengths of routing segments provides a hierarchy of routing capability from chip-length routes to routes within a PLC. The hierarchical nature of the routing provides the ORCA Foundry development tools with the necessary resources to route a design completely and to optimize the routing for system speed while reducing the overall power required by the device. Within each group of ten routing segments there is an equivalency of connectivity between pairs of segments. These pairs are segments: [0, 4] and [1, 5] and [2, 6] and [3, 7] and [8, 9]. The equivalency in connectivity ensures that signals on either segment in a pair have the same capability to get to a given destination. This, in turn, allows for signal distribution from a source to varying destinations without using special routing. It also provides for routing flexibility by ensuring that one segment position will not become so congested as to preclude routing a bus or group of signals and allows easy connectivity from either of the twin quads in a source PFU to either of the twin quads in any destination PFU. Having ten segments in a group is significant in that it provides for routing a byte of data and two control signals or parity. Due to the equivalent pairs of segments, this can also be viewed as routing two nibbles each with a control signal. Figure 19 is an overview of the routing for a single PLC. s @ 3s = s 2 S = foce20) hx UI9:0] hCK Fc Fo SuLpe0] sue] x} hxt BI9:0} hx5{9:0] huxL {9:0} BR{9:0} BRIS-0] SULI9:0} SULI9:0] Fo BL{9:0} KEY: CONFIGURABLE SIGNAL LINE BREAKS pee LINE-BY-LINE a 20F5 5 5-5766(F) Figure 19. Single PLC View of Inter-PLC Route Segments 28 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) Intra-PLC Routing The function of the intra-PLC routing resources is to connect the PFUs input and output ports to the routing resources used for entry to and exit from the PLC. This routing provides PFU feedback, corner turning, or switching from one type of routing resource to another. Flexible Input Structure (FINS) The flexible input switching structure (FINS) in each PLC of the ORCA Series 3 provides for the flexibility of a crossbar switch from the routing resources to the PFU inputs while taking advantage of the routability of shared inputs. Connectivity between the PLC routing resources and the PFU inputs is provided in two stages. The primary FINS switch has 50 inputs that connect the PLC routing to the 35 inputs on the sec- ondary switch. The outputs of the second switch con- nect to the 50 PFU inputs. The switches are implemented to provide connectivity for bused signals and individual connections. PFU Output Switching The PFU outputs are switched onto PLC routing resources via the PFU output multiplexer (OMUX). The PFU output switching segments from the output multi- plexer provide ten connections to the PLC routing out of 18 possible PFU outputs (F[7:0], Q[7:0], DOUT, REGCOUT). These output switching segments con- nect segment for segment to the SUR, SUL, SLR, and SLL switching segments described below (e.g., O4 connects only to SUR4, not SURS5). The output switch- ing segments also feed directly into the SLIC on a seg- ment-by-segment basis. This connectivity is also described below. Switching Routing Segments (xSW) There are four sets of switching routing segments in each PLC. Each set consists of ten switching elements: SUL[9:0], SUR[9:0], SLL[9:0], and SLR[9:0], tradition- Lucent Technologies Inc. ally labeled for the upper-left, upper-right, lower-left, and lower-right sections of the PFUs, respectively. The xSW routing segments connect to the PFU inputs and outputs as well as the BID] routing segments, to be described later. They also connect to both the horizon- tal and vertical x1 and x5 routing segments (inter-PLC routing resources, described later) in their specific cor- ner. xSW segments can be used for fast connections between adjacent PLCs or PICs without requiring the use of inter-PLC routing resources. This capability not only increases signal speed on adjacent PLC routing, but also reduces routing congestion on the principal inter-PLC routing resources. The SLL and SUR seg- ments combine to provide connectivity to the PLCs to the left and right of the current PLC; the SLR and SUL segments combine to provide connectivity to the PLCs above and below the current PLC. Fast routes on switching segments to diagonally adja- cent PLCs/PICs are possible using the BID! routing segments (discussed below) and the SLL and SLR switching segments. The BR BIDI routing segments combine with the SUL switching segments of the PLC below and to the right of the current PLC to connect to that PLC. The BL BIDI routing segments combine with the SLL switching segments of the PLC above and to the right of the current PLC to connect to that PLC. These fast diagonal connections provide a great amount of flexibility in routing congested areas of logic and in shifting data on a per-PLC basis such as per- forming implicit multiplications/divisions in routing between functional logic elements. Switching routing segments are also the chief means by which signals are transferred between the inter-PLC routing resources and the PFU. Each set of switching segments has connectivity to the x1 routing segments, and there is varying connectivity to the x5, xH, and xL inter-PLC routing segments. Detailed information on switching segment/inter-PLC routing connectivity is provided fater in this section in the Inter-PLC Routing Resources subsection. 29ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Logic Cells (continued) BIDI Routing and SLIC Connectivity The SLIC is connected to the rest of the PLC by the bidirectional (BIDI) routing segments and the PFU out- put switching segments coming from the PFU output multiplexer. The BIDI routing segments (xBID) are labeled as BL for BIDI-left and BR for BiDI-right. Each set of BR and BL xBID segments is composed of ten bidirectional lines (note that these lines are diagramed as ten input lines to the SLIC and ten output lines from the SLIC that can be used in a mutually exclusive fash- ion). Because the SLIC is connected directly to the out- puts of the PFU, it provides great flexibility in routing via the xBID segments. The PFU routing segments, O[9:0], only connect to their respective line in the SLL, SUL, SUR, and SLR switching segment groups. That is, O9 only connects to SLL9, SUL9, SUR9Y, and SLR9Y. The BIDI fines provide the capability to connect to the other member of the routing set. That means, for example, that O9 can be routed to BR8 or BL8. This connectivity can be used as a means to distribute or gather signals on intra-PLC routing without disturbing inter-PLC resources. As described in the Switching Routing Seg- ments subsection, the BIDI routing segments are also used for routes to a diagonally adjacent PFU. In addition to the intra-PLC connections, the xBID and output switching segments also have connectivity to the x1, x5, and xL inter-PLC routing resources, provid- ing an alternate routing path rather than using PLC xSW segments. These connections also provide a path to the 3-state buffers in the SLIC without encumbering the xSW segments. In this manner, buffering or 3-state control can be added to inter-PLC routing without dis- turbing local functionality within a PFU. 30 Control Signal and Fast-Carry Routing PFU control signal and the fast-carry routing are per- formed using the FINS structure and several dedicated routing paths. The fast-carry (FC) routing resources consist of a dedicated bidirectional segment between each orthogonal pair of PLCs. This means that a fast- carry can go to or come from each PLC to the right or left, above or below the subject PLC. The FINS struc- ture is used to control the switching of these fast-carry paths between the fast-carry input (FCIN) and fast- carry output (FCOUT) ports of the PFU. The PFU control inputs (CE, SEL, LSR, ASWE) and CIN can be reached via the FINS by two special routing segments, E1 and E2. The E1 routing segment pro- vides connectivity between all of the xBID routing seg- ments and the FINS. It is unidirectional from the BIDI routing to the FINS. E1 also provides connectivity to the PFU clock input via FINS for a local clock signal. The E2 segment connects the SLIC DEC output to the FINS and to a group of CIPS that provide bidirectional con- nectivity with all of the BIDI routing segments. This allows the DEC signal to be used in the PFU and/or routed on the BID! segments. It aiso allows signals to be routed to the PFU on the xBID segments if the SLIC DEC output is not used. There is also a dedicated routing segment from the FINS to the SLIC TRI input used for BID! buffer 3-state control. Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) Inter-PLC Routing Resources The inter-PLC routing is used to route signals between PLCs. The routing segments occur in groups of ten, and differ in the numbers of PLCs spanned. The x1 routing segments span one PLC, the x5 routing seg- ments span five PLCs, the xH routing segments span one-half the width (height) of the PLC array, and the xL routing segments span the width (height) of the PLC array, All types of routing segments run in both horizon- tal and vertical directions. Table 8 shows the groups of inter-PLC routing seg- ments in each PLC. In the table, there are two rows/col- umns for x1 lines. They are differentiated by a T for top, B for bottom, L for left, and R for right. In the ORCA Foundry design editor representation, the horizontal x1 routing segments are located above and below the PFU. The two groups of vertical segments are located on the left side of the PFU. The xL and x5 routing seg- ments only run below and to the left of the PFU, while the xH segments only run above and to the right of the PFU. The indexes specify individual routing segments within a group. For example, the vx5[2] segment runs vertically to the left of the PFU, spans five PLCs, and is the third line in the 10-bit wide group. PLCs are arranged like tiles on the ORCA device. Breaks in routing occur at the middle of the tile (e.g., x1 lines break in the middle of each PLC) and run across tiles until the next break. Table 8. Inter-PLC Routing Resources Horizontal Vertical . Routing Routing Spanned Segments Segments hx1U[9:0] vx1R[9:0] One PLC hx1B[9:0] VX1L{[9:0] One PLC hx5[9:0] vx5[9:0] Five PLCs hx5[9:0] vx5[9:0] Five PLCs hxL[9:0] vxL[9:0] PLC Array hxH[9:0] vxH[9:0] 1/2 PLC Array hCLK vCLK PLC Array Figure 20 provides a global view of inter-PLC routing resources across multiple PLCs. Lucent Technologies Inc. x1 Routing Segments. There are a total of 40 x1 rout- ing segments per PLC: 20 vertical and 20 horizontal. Each of these are subdivided into two, 10-bit wide buses: hx1T[9:0], hx1B[9:0], vx1L[9:0], and vx1R[9:0]. An x1 segment is one PLC long. If a signal net is longer than one PLC, an x1 segment can be lengthened to n times its length by turning on n- 1 CIPs. A signal is routed onto an x1 route segment via the switching rout- ing segments or BIDI routing segments which also allows the x1 route segment to be connected to other inter-PLC segments of different lengths. Corner turning between x1 segments is provided through direct con- nections, xSW segments, and xB!D segments. x5 Routing Segments. There are two sets of ten x5 routing segments per PLC. One set (vx5/[9:0]) runs ver- tically, and the other (hx5[9:0]) runs horizontally. Each x5 segment traverses five PLCs before it is broken by a CIP. Two x5 segments in each group break in each PLC. The two that break are in an equivalent pair; for example, x5[0] and x5[4]. The x5 segments that break shift by one at the next PLC. For example, if hx5[0] and hx5[4] are broken at the current PLC, hx5[1] and hx5[5] will be broken at the PLC to the right of the current PLC. There are direct connections to the BIDI routing segments in the PLC at which the x5 segments break, on both sides of the break. Signal corner turning is enabled by CIPs in each PLC that allow the broken x5 segments to directly connect to the broken x5 seg- ments that run in the orthogonal direction. x5 corner turning can also be accomplished via the xSW and xBID segments in a PLC. In addition, the x5 segments are connected to the FINS and PFU outputs on a bit- by-bit basis by the xSW segments. x5 segments can be connected for signal runs in multiples of five PLCs, or they can be combined with x1 and xH routing segments for runs of varying distances. 31Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Programmable Logic Cells (continued) Ses 6 Ss ses 6s = sess 8s s 282 4 = Sef 4= $ee x= & g Ss 5 SF & 5 Qs ge Fe & 5 Qe ' , ' e-o-b J. Jo 4 etd ae pee ge ee Pe a ed EP EEL; ' fe hxH[9:0] 1 i ' 1 L l L 1 L oe mine ole hx1[9:0 1 I i 5 1 i I 18:0] T T T T hCLK ; 10 ' 10 ' 10 ' i] yoy ! ey CY ' Ly 1 (| ok ee Pre ' 2h eee Pre \ 2h are 1 SLIC | 1 Suc 1 i a i at l | L = = hx1{9:0 i > 1 > i i. i {3:0} { I 1 200 ' { 1 a 1 Ts 1 Ts 1 Fxs{:0} 1 ! ' i. T 7 T T hxL {9:0} \ ' t \ -44-4-b-----4-]--+-+-} -bF - -l- --+4-4--- 4-4--4----Fe- \ i | Le hxH[9:0} i 1 1 1 " I 1 ' \ ale ale a! T Pit T + T T* Tom het[9:0} 1 { i 1 I i I i hCLK ; 10 ! 40 I 10 \ 1} Joy ' py \ ey 1 1|2ey PFU 1 2h ay Pre 2h haa | ! suc \ suc 1 Suc \ L SS ee L J 1 al L ; 1 ; ot< ; }-+>< i x0} 2 2 2 1 1 { \ \ 1 1 1 "40 \ Vio 1 Vio yr PxS19:0) 1 { 1 i T T T To bol {:0] 1 \ 1 \ -+ 4 _ a -__ = rm sel - ome om Pe oe fee ee ee - ~ =e el we ee ee fe m- ro 1 1 { 1 1 1 j BxH{9:0] 1 t ! { ale ale i T at al T i* T T T hxt[s:0] ' 1 1 { ! | 1 1 hCLK \ { \ { 1) yoy iv oe ov yoy vi \|2ny y] PFU I 2h Pru \ ah irae \ \ suc \ suc \ SUC \ ot a! | 1 | >} ; f ; =}->}< i hxtf.0] 1 2) \ 2 1 2) 1 hus(e-0} ' ~Nt0 ! "i0 ! "Hi 1 , ! l | I 7 T 1 7 hxl{s:0} { I I Tp a ese ge aac sas ae ede -4arT Tt Orr rrp, t t . | t KEY: CONFIGURABLE SIGNAL-LINE BREAKS: ae }ee-LINE-BY-LINE oe 2 OF 10 10 -------- PLC BOUNDARY 5-5767(F) Figure 20. Multiple PLC View of Inter-PLC Routing 32 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) xL Routing Lines. The xL routing lines run vertically and horizontally the height and width of the array, respectively. There are a total of 20 xL routing lines per PLC: ten horizontal (nxL[9:0]) and ten vertical (vxL{9:0]). Each of the xL lines connects to the PIC routing at either end. The xL lines are intended prima- rily for global signals that must travel long distances and require minimum delay and/or skew, such as clocks or 3-state buses. Each xL line (also called a long line) drives a buffer in each PLC that can drive onto the horizontal and verti- cal local clock routing segments (ICLK) in the PLC. Also, two out of each group of ten xL segments in each PLC can be driven by a buffer attached to a clock spine (described later) allowing local distribution of global clock signals. More general-purpose connections to the long lines can be made through the xBID segments ina PLC. Each long line is connected to an xBID segment on a bit-by-bit basis. These BIDI connections allow cor- ner turning from horizontal to vertical long lines, and connection between long lines and x1 or x5 segmenis. xH Routing Segments. Ten by-half (xH) routing seg- ments run horizontally (hxH[9:0]) and ten xH routing segments run vertically (vxH[9:0]) in each row and col- umn in the array. These routing segments travel a dis- tance of one-half the PLC array before being broken in the middle of the array in the interquad area (discussed later). They also connect at the periphery of the FPGA to the PICs, like the xl lines. xH routing segments con- nect to the PLCs only by switching segments. They are intended for fast signal interconnect. Clock (and Giobal CE and LSR) Routing Segments. For a very fast and low-skew clock (or other global! sig- nal tree), clock routing segments run the entire height and width of the PLC array. There are two clock routing segments per PLC: one horizontal (hCLK) and one ver- tical (VCLK). The source for these clock routing seg- ments can be any of the I/O buffers in the PIC, the Series 3 ExpressCLK inputs, user logic, or the pro- grammable clock manager (PCM). The horizontal clock routing segments (nCLK) are alternately driven by the left and right PICs. The vertical clock routing segments (vCLK) are alternately driven by the top and bottom PICs. Lucent Technologies Inc. The clock routing segments are designed to be a clock spine. In each PLC, there is a fast connection available from the clock segment to a long-line driver (described earlier). With this connection, one of the clock routing segments in each PLC can be used to drive one of the ten xL routing segments perpendicular to it, which, in turn, creates a clock spine tree. This feature is dis- cussed in detail in the Clock Distribution Network sec- tion. Special connectivity is provided in each PLC to connect the clock enable signals (CE and ASWE) and the LSR signal to the clock network for fast global control signal distribution. CE and ASWE have a special connection to the horizontal clock spine, and LSR has a special connection to the vertical clock spine. This allows both signals to be routed globally within the same PLC, if desired; however, this will consume some of the resources available for clock signal routing. If using these spines, the clock enable signal must come from the right or left edge of the device, and the LSR signal must come from the top or bottom of the device due to their horizontal and vertical connectivity, respectively, to the clock network. Minimizing Routing Delay The CIP is an active element used to connect two rout- ing segments. As an active element, it adds signifi- cantly to the resistance and capacitance of a routing network (net), thus increasing the net's delay. The advantage of the x1 segment over an x5 segment is routing flexibility. A net from one PLC to the next is eas- ily routed by using x1 routing segments. As more CIPs are added to a net, the delay increases. To increase speed, routes that are greater than two PLCs away are routed on the x5 routing segments because a CIP is located only in every fifth PLC. A net that spans eight PLCs requires seven x1 routing segments and six CIPs. Using x5 routing segments, the same net uses two routing segments and one CIP. 33ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Logic Cells (continued) PLC Architectural Description Figure 21 is an architectural drawing of the PLC (as seen in ORCA Foundry) that reflects the PFU, the rout- ing segments, and the CIPs. A discussion of each of the letters in the drawing follows. A. These are switching routing segments (xSW) that give the router flexibility. In general switching theory, the more levels of indirection there are in the routing, the more routable the network is. The xSW seg- ments can also connect to the xSW lines in adjacent PLCs. B. These CIPs connect the x1 routing. These are located in the middle of the PLC to allow the block to connect to either the left end of the horizontal x1 segment from the right or the right end of the hori- zontal x1 segment from the left, or both. By symme- try, the same principle is used in the vertical direction. C. This set of C!Ps is used to connect the x1 and x5 nets to the xSW segments or to other x1 and x5 nets. The CIPs on the major diagonal allow data to be transmitted on a bit-by-bit basis frorn x1 nets to the xSW segments and between the x1 and x5 nets. D. This structure is the supplemental logic and inter- connect cell, or SLIC. It contains 3-statable bidirec- tional buffers and logic for building decoders and AND-OR-INVERT type structures. E. These are the primary and secondary elements of the flexible input structure or FINS. FINS is a switch matrix that provides high connectivity while retaining routing capability. FINS also includes feedback paths for softwired LUT implementation. F. This is the PFU output switch matrix. It is a complex switch network which, like the FINS at the input, pro- vides high connectivity and maintains routability. G. This set of CIPs allows an xBID segment to transfer a signal to/from xSW segments on each side. The BIDIs can access the PFU through the xSW seg- ments. These CIPs allow data to be routed through the BIDIs for amplification or 3-state control and continue to another PLC. They also provide an alter- native routing resource to improve routability. H. These CIPs are used to transfer data from/to the xBID segments to/from the x1 and xL routing seg- ments. These CIPs have been optimized to allow the BIDI buffers to drive the loads usually seen when using each type of routing segment. 1. Clock input to PFU. 34 J. These are the ten switched output routing segments from the PFU. They connect to the PLC switching segments and are input to the SLIC. K. These lines deliver the auxiliary signals clock enable (CE), local set/reset (LSR), front-end select (SEL), add/subtract/write enable (ASWE), as well as the carry signais (CIN and FCIN) to the latches/FFs. L. This is the local clock buffer. Any of the horizontal and vertical xL lines can drive the clock input of the PLC latches/FFs. The clock routing segments (vCLK and hCLK) and multiplexers/drivers are used to connect to the xL routing segments for low-skew, low-delay global signals. M. These routing segments are used to route the fast- carry signal to/from the neighboring four PLCs. The carry-out (COUT) and registered carry-out (REG- COUT) can also be routed out of the PFU. N. This is the E2 control routing segment. It runs from the SLIC DEC output to the FINS and also provides connectivity to all xBID segments. O. The xH routing segments run one-half the length (width) of the array before being broken by a CIP. P. These CIPs connect the xH segments to the xSW segments. Q.The xBID segments are used to connect the SLIC to the xSW segments, x1 segments, x5 segments, and xL lines, as well as providing for diagonal PLC to PLC connections. R. These CIPs provide connections from the xBID seg- ments to the E1/E2 routing segments that feed PFU control inputs CE, LSR, CIN, ASWE, SEL, and the clock input. Alternatively, these CIPs connect the BIDI lines to the decoder (DEC) output of the SLIC, for routing the DEC signal. S. These are clock spines (vCLK and hCLk) with the multiplexers and drivers to connect to the xL routing segments. T. These CIPs connect xBID segments to switching segments in diagonally and orthogonally adjacent PFUs. U. These CIPs connect xSW segments to the PFU out- put segments. V. These CIPS connect xSW segments in orthogonally adjacent PFUs. W.This is the SLIC 3-state control routing segment from the FINS to the SLIC 3-state control. X. This is the E41 control routing segment. It provides a PFU input path from all xBID segments. Y. These CIPs are used to select which xBID segments are connected to the E1/E2 signal as described in (R). Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Logic Cells (continued) PRIMARY FINS Figure 21. PLC Architecture Lucent Technologies Inc. a Zz c > & a = 9 oO wl na 5-5758(F) 35ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Input/Output Cells The programmable input/output cells (PICs) are located along the perimeter of the device. The PICs name is represented by a two-letter designation to indi- cate on which side of the device it is located followed by a number to indicate in which row or column it is located. The first letter, P. designates that the cell is a PIC and not a PLC. The second letter indicates the side of the array where the PIC is located. The four sides are left (L), right (R), top (T), and bottom (B). The indi- vidual I/O pad is indicated by a single letter (either A, B, C, or D) placed at the end of the PIC name. As an example, PL10A indicates a pad located on the left side of the array in the tenth row. Each PIC interfaces to four bond pads and contains the necessary routing resources to provide an interface between I/O pads and the PLCs. Each PIC is com- posed of four programmable I/Os (PIOs) and significant routing resources. Each PIO contains input buffers, output buffers, routing resources, latches/FFs, and logic and can be configured as an input, output, or bidirectional 1/O. PICs in the Series 3 FPGAs have significant local rout- ing resources, similar to routing in the PLCs. This new routing increases the ability to fix user pinouts prior to placement and routing of a design and still maintain routability. The flexibility provided by the routing also provides for increased signal speed due to a greater variety of signal paths possible. Included in the PIC routing is a fast path from the input pins to the SLICs in each of the three adjacent PLCs (one orthogonal and two diagonal). This feature allows for input signals to be very quickly processed by the SLIC decoder function and used on-chip or sent back off of the FPGA. Also new to the Series 3 PlOs are latches and FFs and options for using fast, dedicated clocks called ExpressCLKs. These features will all be discussed in subsequent sections. A diagram of a single PIO (one of four in a PIC) is shown in Figure 22. Table 9 provides an overview of the programmable functions in an 1/O cell. PIO LOGIC io AND iO NAND a OR in NOR DB XOR 2 XNOR PMUX PULL-MODE & OUTIOUTREG 0 UP G OUT2Z0OUTREG Oo DOWN _ CLKIN ouT1 ff 5 0 OUTIOUT2 a NONE Cc] DO oS pa D QHp1 IN| z OUT2 ry oO OD NORMAL }4CK z= E ap G INVERTED CK 3 5 9 ISP iv ce Fe 42a o TL SD B sou, If Ck |o Res BUFFER |o CMOS 1 INREGMODE in - a ! = ce fi | | |isn {2 SET Lipo ap! MOdE 0 LATCHFF bo RESET ox | (EES, aft p Ser LSR 0 CE_OVER_LSR ILSR | | SINK IN2 DH LSR_OVER_CE o ~| 0 ASYNG ENABLE_GSR O DISABLE_GSR 5-5805(F).c Figure 22. OR3C/Txxx Programmable Input/Output (PIO) Image from ORCA Foundry 36 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) Table 9. PIO Options Input Option Input Level TTL, OR3Cxx only CMOS, OR3Cxx or OR3Txxx 3.3 V PCI Compliant, OR3Txx 5 V PCI Compliant, ORSTxxx Input Speed Fast, Delayed Float Value Pull-up, Pull-down, None Register Mode Latch, FF, Fast Zero Hold FF, None (direct input) Clock Sense Inverted, Noninverted Input Selection Input 1, Input 2, Clock Input Output Option Output Drive 12 mA/6 mA or 6 mMA/3 MA Current Output Function Normal, Fast Open Drain Output Speed Fast, Slewlim, Sinklim Output Source FF Direct-out, General Routing Output Sense Active-high, Active-low 3-State Sense Active-high, Active-low (3-state) FF Clocking ExpressCLK, System Clock Clock Sense Inverted, Noninverted Logic Options See Table 10. VO Controls Option Clock Enable Active-high, Active-low, Always Enabled Set/Reset Level Active-high, Active-low, No Local Reset Set/Reset Type Synchronous, Asynchronous Set/Reset Priority | CE over LSR, LSR over CE GSR Control Enable GSR, Disable GSR Lucent Technologies Inc. 5 V Tolerant I/O The I/O on the OR3Txxx Series devices allow intercon- nection to both 3.3 V and 5 V devices (selectable ona per-pin basis). The OR3Tx devices will drive the pin to the 3.3 V lev- els when the output buffer is enabled. If the other device being driven by the OR3Txxx device has TTL- compatible inputs, then the device will not dissipate much input buffer power. This is because the OR3Txxx output is being driven to a higher level than the TTL level required. If the other device has a CMOS-compat- ible input, the amount of input buffer power will also be small. Both of these power values are dependent upon the input buffer characteristics of the other device when driven at the OR3Txxx output buffer voltage levels. The OR3Txxx device has internal programmable pull- ups on the I/O buffers. These pull-up voltages are always referenced to Vpp and are always sufficient to pull the input buffer of the ORSTxxx device to a high state. The pin on the OR3Txxx device will be at a level 1.0 V below VoD (minimum of 2.0 V with a minimum VobpD of 3.0 V). This voltage is sufficient to pull the exter- nal pin up to a 3.3 V CMOS high input level (1.8 V, min) or a TTL high input level (2.0 V, min) in a 5 V tolerant system. Therefore, in a 5 V tolerant system using 5 V CMOS parts, care must be taken to evaluate the use of these pull-ups to pull the pin of the OR3Txx device to a typical 5 V CMOS high input level (2.2 V, min). PCI Compliant /O The I/O on the OR3Txxx Series devices allows compli- ance with PCI Local Bus (Rev. 2.2) 5 V and 3.3 V sig- naling environments. The signaling environment used for each input buffer can be selected on a per-pin basis. The selection provides the appropriate I/O clamping diodes for PCI compliance. Choosing an IBT input buffer will provide PCI compliance in OR3Txxx devices. OR3Cxx devices have PCI Local Bus compliant I/Os for 5 V signaling. 37ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Input/Output Cells (continued) Inputs As outlined earlier in Table 9, there are six major options on the PIO inputs that can be selected in the ORCA Foundry tools. For OR3Cxx devices, the inputs and bidirectional buffers can be configured as either TTL or CMOS compatible. OR3Txxx devices support CMOS levels only for input or bidirectional buffers, have 5 V tolerant I/Os as previously explained, but can optionally be selected on a pin-by-pin basis to be PC/ bus 3.3 V signaling compliant (PCI bus 5 V signaling compliance occurs in 5 V tolerant operation). The deiault buffer upon powerup for the unused sites is 5 V tolerant/S5 V PCI compliant. Consult the ORCA macro library, Series 3 I/O cells, for the appropriate buffers. Inputs may have a pull-up or pull-down resistor selected on an input for signal stabilization and power management. Input signals in a PIO can be passed to PIC routing on any of three paths, two general signal paths into PIC routing, and/or a fast route into the clock routing system. There is also a programmable delay available on the input. When enabled, this delay affects the IN1 and IN2 signals of each PIO, but not the clock input. The delay allows any signal to have a guaranteed zero hold time when input. This feature is discussed subsequently. Inputs should have transition times of less than 500 ns and should not be left floating. If any pin is not used, it is 3-stated with an internal pull-up resistor enabled automatically after configuration. 38 Warning: During configuration, all OR3Txx inputs have internal pull-ups enabled. If these inputs are driven to 5 V, they will draw substantial current (=5 mA). This is due to the fact that the inputs are pulled up to 3 V. Floating inputs increase power consumption, produce oscillations, and increase system noise. The OR3Cxx inputs have a typical hysteresis of approximately 280 mV (200 mV for the OR3T200)) to reduce sensitivity to input noise. The PIC contains input circuitry which pro- vides protection against latch-up and electrostatic dis- charge. The other features of the PIO inputs relate to the new latch/FF structure in the input path. As shown in Figure 23, the input is optionally passed to a register or latch/register pair. These structures can operate in the modes listed in Table 9. In latch mode, the input signal is fed to a latch that is clocked by a system clock signal. The clock may be inverted or noninverted from its sense in the PIC routing. There is also a local set/reset signal to the latch from the PIC routing. The senses of these signals are also programmable as well as the capability to enable or disable the global set/reset sig- nal and select the set/reset priority. The same control signals may also be used to control the input latch/FF when it is configured as a FF instead of a latch, with the addition of another control signal used as a clock enable. Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) Zero-Hold Input There are two options for zero-hold input capture in the PiO. If input delay mode is selected to delay the signal from the input pin, data can be either registered or latched with guaranteed zero-hold time in the PIO using a system clock. To guarantee zero hold, the system clock spine structure must be used for clocking, as will be discussed later. The fast zero-hold mode of the PIO input takes advantage of the latch/FF combination and sources the input FF data from a dedicated latch that is clocked by the ExpressCLK from the PIC. The ExpressCLK is a clock from a dedi- cated input pin designed for fast, low-skew operation at the I/Os and is described more fully in the Clock Distribu- tion Network and PIC Interquad (MID) Routing sections that follow. The combination of ExpressCLK latch and system clock FF guarantees a zero-hold capture of input data in the PIO FF, while at the same time reducing input setup time. Figure 23 shows a schematic of the fast-capture latch/FF and a sample timing diagram. FF DATA OUT INPUT DATA dD @ TO PIC ROUTING EXPRESSCLK CE * S/R SYSTEM CLK CLOCK ENABLE LOCAL SET/RESET SYSTEM CLK Sf \ f/f \J/J \J/ \ INPUTDATA A X B x Cc X QULATCH A X B x Cc x D XE Or x A x B x c Xo 5-5974(F) Note: CE and LSR signals not shown. Figure 23. Fast-Capture Latch and Timing Lucent Technologies Inc. 39Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Programmable Input/Output Cells (continued) Input Demultiplexing The combination of input register capability and the two inputs, IN1 and IN2, from each PIO to the internal routing provides for input signal demultiplexing without any additional resources. Figure 24 shows the input configuration and general timing for demultiplexing a multiplexed address and data signal. The PIO input signal is sent to both the input latch and directly to IN2. The signal is latched on the falling edge of the clock and output to routing at IN1. The address and data are then both available at the rising edge of the system clock. These signals may be regis- tered or otherwise processed in the PLCs at that clock edge. Figure 24 also shows the possible use of the SLIC decoder to perform an address decode to enable which registers are to receive the input data. Although the timing shown is for using the input register as a latch, it may also be used in the same way as an FF. Also note that the sig- nals found in PIO inputs IN1 and IN2 can be interchanged. | OTHER ADDRESS ; LINES I PIO , PLC ' I DEC PAD p qPWNu SLic I t STL f i SCLK ; Ina! > ale LCE > PIO INPUT _Xarat Manone DATA KADDAS DATAS KADOR4 DATA4 ADORE K PSurpur ADDR1 X = aDpbR2. =X appr. = XARA ~X_ ADRS ouspur _DATAO Xx DATAt xX DATA2 x DATA X DATA -798(F) Figure 24. PiO Input Demultiplexing 40 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) Outputs The PICs output drivers have programmable drive capability and slew rates. Three propagation delays (fast, slewlim, sinklim) are available on output drivers. The sinklim mode has the longest propagation delay and is used to minimize system noise and minimize power consumption. The fast and slewlim modes allow critical timing to be met. The drive current is 12 mA sink/6 mA source for the slewlim and fast output speed selections and 6 mA sink/3 mA source for the sinklim output. Two adja- cent outputs can be interconnected to increase the out- put sink/source current to 24 mA/12 mA. All outputs that are not speed critical should be config- ured as sinklim to minimize power and noise. The num- ber of outputs that switch simultaneously in the same direction should be limited to minimize ground bounce. To minimize ground bounce problems, locate heavily loaded output buffers near the ground pads. Ground bounce is generally a function of the driving circuits, traces on the printed-circuit board, and loads and is best determined with a circuit simulation. At powerup, the output drivers are in slewlim mode, and the input buffers are configured as TTL-level com- patible (CMOS for OR3Txxx) with a pull-up. !f an output is not to be driven in the selected configuration mode, it is 3-stated. The output buffer signal can be inverted, and the 3-state control signal can be made active-high, active- low, or always enabled. In addition, this 3-state signal can be registered or nonregistered. Additionally, there is a fast, open-drain output option that directly connects the output signal to the 3-state control, allowing the out- put buffer to either drive to a logic 0 or 3-state, but never to drive to a logic 1. Because there is no explicit route required to create the open-drain output, its response is very fast. Like the input side of the PIO, there are two output connections from PIC routing to the output side of the PIO, OUT1, and OUT2. These connections provide for flexible routing and can be used in data manipulation in the PIO as described in subsequent paragraphs. Lucent Technologies Inc. An FF has been added to the output path of the PIO. The register has a local set/reset and clock enable. The LSR has the option to be synchronous or asynchro- nous and have priority set as clock enable over LSR or LSR over clock enable. Clocking to the output FF can come from either the system clock or the ExpressCLK associated with the PIC. The input to the FF can come from either OUT1 or OUT2, or it can be tied to VDD or GND. Additionally, the input to the FF can be inverted. Output Multiplexing The Series 3 PIO output FF can be combined with the new PIO logic block to perform output data multiplexing with no PLC resources required. The PIO logic block has three multiplexing modes: OUT1OUTREG, OUT2OUTREG, and OUT1OUT2. OUTIOUTREG and OUT2OUTREG are equivalent except that either OUT1 or OUT2 is MUXed with the FF, where the FF data is output on the clock phase after the active edge. The simplest multiplexing mode is OUT1OUT2. In this mode, the signal at OUT1 is output to the pad while the clock is low, and the signal on OUT2 is output to the pad when the clock is high. Figure 25 shows a simple schematic of a PIO in OUT1OUT2 mode and a general timing diagram for multiplexing an address and data signal. Often an address will be used to generate or read a data sample from memory with the goal of multiplexing the data onto a single line. In this case, the address often precedes the data by one clock cycle. OUT10OUTREG and OUT2OUTREG modes of the PIO logic can be used to address this situation. Because OUTI1OUTREG mode is equivalent to OUT2OUTREG, only OUTZOUTREG mode is described here. Figure 26 shows a simple PIO sche- matic in OUT2ZOUTREG mode and general timing for multiplexing data with a leading address. The address signal on OUT1 is registered in the PiO FF. This delays the address so that it aligns with the data signal. The PIO logic block then sends the OUTREG signal (address) to the pad when the clock is high and the OUT2 signal (data) to the pad when the clock is low, resulting in an aligned, multiplexed signal. 41Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Programmable Input/Output Cells (continued) ' PLC 1 PIC | ADDRESS ' outs FROM ROUTING i I DATA 1 oUuT2 PIO FROM I PAD ROUTING ; LoGic oJ \S\VSNVSX ouT1 apori X ADDR2 x ADOR3 x ADDR4 Xx ADDAS OUT2 DATA! x DATA2 x DATA3 x DATA4 x DATAS PIC OUTPUT ADDR1 x DATAI X appre X DATA2 X aor X DATA3 X abors x DATA4 x NOTE: PIO LOGIC MODE, OUT10OUT2 -5799(F} Figure 25. Output Multiplexing (OUT1OUT2 Mode) PLC | PIC I pores iour: 15 ROUTING \ ! cLK>++ > 1 J t ' P/O PAD DATA i LOGIC FROM > , OUT2 ROUTING : cur J \Ss/\ S/N SY ADDR aDDRI X ADDR2 xX ADDR x ADDR4 ADDRS5 DATA XXXX DATA! x DATA2 x. DATAS XX DATA4 REG ADDRESS YOOX ADDR Xx ADDR2 x ADDR3 Xx ADDR4 PAD ORO KAD0RI x DATA1 X appr DATAZ ADDS) DATAS KADDRA NOTE: PIO LOGIC MODE, OUT10UT2 5-5797(F) Figure 26. Output Multiplexing (OQUTZOUTREG Mode) 42 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) PIO Logic Function Generator The PIO logic block can also generate logic functions based on the signals on the OUT2 and CLK ports of the PIO. The functions are AND, NAND, OR, NOR, XOR, and XNOR. Table 10 is provided as a summary of the PIO logic options. Table 10. PIO Logic Options PIO Register Control Signals As discussed in the Inputs and Outputs subsections, the PIO latches/FFs have various clock, clock enable (CE), local set/reset (LSR), and global set/reset (GSRN) controls. Table 11 provides a summary of these control signals and their effect on the PIO jatches/FFs. Note that all control signals are optionally invertible. Table 11. PIO Register Control Signals Control Signal Effect/Functionality Option Description OUTIOUTREG | Data at OUT1 output when clock low, data at FF out when clock high. OUT2OUTREG | Data at OUT2 output when clock low, data at FF out when clock high. OUT1OUT2 Data at OUT1 output when clock low, data at OUT2 when clock high. AND Output logical AND of signals on OUT2 and clock. NAND Output logical NAND of signals on OUT2 and clock. OR Output logical OR of signals on OUT2 and clock. NOR Output logical NOR of signals on OUT2 and clock. XOR Output logical XOR of signals on OUT2 and clock. XNOR Output logical XNOR of signals on OUT2 and clock. Lucent Technologies Inc. ExpressCLK Clocks input fast-capture latch; optionally clocks output FF, or 3-state FF. System Clock | Clocks input latch/FF; optionally (SCLK) clocks output FF, or 3-state FF. Clock Enable | Optionally enables/disables input (CE) FF (not available for input latch mode); optionally enables/dis- ables output FF; separate CE inversion capability for input and output. Local Set/Reset (LSR) Option to disable; affects input latch/FF, output FF, and 3-state FF if enabled. Global Set/Reset (GSRN) Option to enable or disable per PIO after initial configuration. Set/Reset Mode The input latch/FF, output FF, and 3-state FF are individually set or reset by both the LSR and GSRN inputs. 43ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Input/Output Cells (continued) PIC Routing Resources The PIC routing borrows many of the concepts and constructs from the PLC routing. It is designed to be able to gather an 8-bit bidirectional bus from any eight consecutive I/O pads and route them to either or both of the two adjacent PLCs. The eight I/O bits do not need to start at a PIC boundary; that is, they may start at one of the middle two P!Os in a PIC and span three PICs. Substantial routing has been added to the PIC to off- load PLC routing from being used to move signals around the PLC array perimeter. This saves PLC rout- ing for logic purposes and provides greater flexibility for locking design pinouts prior to final placement and rout- ing of the device, or allowing a change in the pinout late in the design cycle. The PIC routing has aiso been increased substantially to allow routing to the complex PIO cells that now allow multiple inputs and outputs per device pin, along with new sequential control signals, such as clock enable, LSR, and clock. PICs are grouped in pairs for purposes of discussing PIC routing. On the sides of a device, the PICs in a pair are referred to as top and bottom. On the top or bottom of a device, the PICs in a pair are referred to as left or right. For example, on the top edge of the device, the leftmost PIC, PT1, is the left PIC of a pair, and PIC PT2 is the right PIC of that pair. The next PIC to the right, PTS, is the left PIC of the next pair, and so on. The need for PIC pairs stems from the routing of switching segments and PLC half- and long-line driv- ers. As described below, the connectivity for these types of routing is grouped across pairs of PICs to pro- vide complete and fast routing of I/O signals between a given PIC and the three adjacent PLCs: one orthogonal and two diagonal. PIC routing segments use the same terminology as PLC routing segments, but are prefixed with a p to dis- tinguish them as belonging to the PICs. PIC Switching Segments. Each PIC has two groups of switching segments (pSW), each group having eight lines with connectivity to the PlOs in groups of four. One set of switching segments connects to the PIC to the left (above), and the other set connects to the switching segments of the PIC to the right (below). This means of connectivity between PICs using staggered connections of groups of switching segments allows a given PIC to route signals to both adjacent PICs and all adjacent PLCs efficiently. This provides single signal routing flexibility and routing of multiple buses on groups of I/Os without tying up global routing resources. px1 Routing Segments. There are five px1 routing segments in each PIC that run parallel to the edge of the chip on which the PIC resides, each broken by a CIP in each PIC. The px1 segments have connectivity to the pSW segments and to the x1 routing segments of the two adjacent PLCs. px2 Routing Segments. There are five px2 routing segments in each PIC that run parallel to the edge of the chip on which the PIC resides. To provide greater routing flexibility, the CiPs that break the px2 segments every two PICs are staggered across the two PICs ina pair. One PIC of the pair has break CIPs on the even- numbered px2 segments, and the other has them on the odd-numbered px2 segments. The px2 segments have connectivity to the pSW segments and to the x1 routing segments of the two adjacent PLCs. px5 Routing Segments. There are ten px5 routing segments in each PIC that run parallel to the edge of the chip on which the PIC resides. Two of the ten seg- ments are broken in each PIC so that each segment is broken every five PICs. All ten px5 segments break at the corners of the chip, allowing independent px5 rout- ing on each edge of the chip. The px5 routing seg- ments connect to the pSW segments and the x5 and xH routing segments of the two adjacent PLCs. pxH Routing Segments. Each PIC contains eight pxH routing segments that run parallel to the edge of the chip on which the PIC resides. The pxH segments have connectivity with the xL, xH, and one set of xBID rout- ing segments in the immediately adjacent PLC. pxL Routing Segments. There are ten pxL routing segments in each PIC that run parallel to the edge of the chip on which the PIC resides. Each of the xL lines makes a connection to an xL line from the adjacent PLC. PIC long lines (xL) can be used for global signal distribution just as PLC xL lines can. Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) PIC Architectural Description The PIC architecture as seen in ORCA Foundry is shown in Figure 27. The figure is the left PIC of a PIC pair on the top edge of a Series 3 array. Both PICs ina pair are similar, with the differences mainly lying in the connections between the PIC switching segments (pSW), the IN2 connections across PIC boundaries, and the system clock spine driver residing in only one PIC of a pair. A. This is a programmable input/output (PIO). There are four PlOs per PIC. The PIOs contain the PIC logic and I/O buffers. B. This is the PIC output switching block. It connects the PIC switching segments and local clock lines to the PIO output and control signals. C. This is the system clock spine switching block and buffer. There is only one system clock spine per pair of PICs. Its inputs can come from the PIC switching segments or any of the eight PIO inputs in a PIC pair. D. PIC switching segments (pSW). These routing seg- ments are used to interconnect routing resources within the PIC and to a lesser degree, between PICs. E. px1 routing segments. The PIC x1 routing seg- ments traverse one PIC and break at a CIP in the middle of each PIC. F. px2 routing segments. The PICs have routing that traverses two PICs between breaks. The breaks are staggered among the five px2 segments. G. px5 routing segments. Each of the ten PIC x5 rout- ing segments traverses five PICs in between breaks at a CIP. Two px5 segments break in each PIC. H. pxH routing segments. The eight PIC xH routing segments traverse half of the array and break at CIPs in the interquad routing region that is in the middle of the array. (Not used intentionally for clarity.) J. pxL routing segments. The PIC long lines run the entire length of the side of the array. K. x5 routing segments from the adjacent PLC routing. L. xL routing segments from the adjacent PLC routing. M. x1 routing segments from the adjacent PLC routing. N . Switching segments from the adjacent PLC routing. Lucent Technologies Inc. O. xH routing segments from the adjacent PLC routing. P. BID! routing segments from the adjacent PLC rout- ing. Q. These are the IN2 routing segments. There is one IN2 line from each PIO, and all eight IN2 lines from each PIC pair are present in both PICs of a pair. R. These CiPs connect the IN1 and IN2 routing seg- ments from the PlOs to the PIC switching seg- ments. S. These CIPs break the PIC switching segments at the interface between a PIC pair. T. These CIPs connect adjacent PLC routing resources to the PIC switching segments. U. These CIPs connect inter-PIC routing with the PIC switching segments. V. These CIPs break the px1, px2, and px5 routing at the middle of a PIC. The px2 and px5 CIP place- ment varies depending on the PLC. W. These mutually exclusive buffers can drive one long line signal onto a PIC local clock routing segment. X. These mutually exclusive buffers can select a source from one of the local system clock routes to drive the PIO 3-state control signal. Y. These are the four local system clock routing seg- ments. Two come from connections within the PIC, one from the other PIC in the pair, and one from the adjacent PLC. Z. These mutually exclusive buffers allow a signal on the PIC switching segments to be routed to a sys- tem clock spine or to a PIO system clock. AA. ExpressCLkK routing line. AB. System clock spine. AC. These various groups of CIPs connect routing resources from the adjacent PLC to the inter-PIC routing resources. AD. These buffers provide connectivity between the PLC xl. (xH) lines and the PIC xL (xH) lines or connectivity between one of the IN2 routing seg- ments and the PIC and/or PLC xL (xH) routing segments. AE. These mutually exclusive buffers and CIPs provide connectivity to the PLC xL and xH lines from one of the IN2 input segments. AF. These buffers allow the IN2 signals to drive onto the BIDI routing of the adjacent PLC, or the BIDI routing of the adjacent PLC, and the PIC switching segments and/or PIC half lines may be connected. 45Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Programmable Input/Output Cells (continued) 5-5823(F) Figure 27. PIC Architecture 46 Lucent Technologies inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs High-Level Routing Resources The high-level routing resources in the ORCA Series 3 devices are interquad routing, corner cell routing, and PIC interquad routing. These resources and their related structures are discussed in the following subsections. Interquad Routing In the ORCA Series 3 devices, the PLC array is split into four equal quadrants. In between these quadrants, routing has been added to route signals between the quadrants and distribute clocks. In addition to general routing, there are four specialized clock routing spines. The general routing is discussed below, followed by the special clock rout- ing. One of the main purposes of interquad routing is to distribute internally generated signals, such as clocks and con- trol signals. There are two types of interquad blocks: vertical and horizontal. Vertical interquad blocks (vIQ) run between quadrants on the left and right, while horizontal interquad blocks (hIQ) run between top and bottom quad- rants. Interquad lines begin and end in the MID cells that are discussed later. Since hlQ and vIQ blocks have the same logic, only the hlQ block is described below. The interquad routing connects to x5 and xH segments. It does not affect other local routing (xsw, x1, fast carry), so local routing is the same, whether PLC-PLC connections cross quadrants or not. Figure 28 presents a (not to scale) view of interquad routing. FAST CLOCK L ao x 3 = o 5 z BEESSSDACRELARESESERLAAARRERER RES ERReED SORRAARAAARERRERDSNESRRRRRESEOSE REREAD 5-4538(F) Figure 28. Interquad Routing Lucent Technologies Inc. 47ORCA Series 3C and 3T FPGAs Data Sheet June 1999 High-Level Routing Resources (continued) Figure 29 shows the connections from the interquad routing to the inter-PLC routing for a block of the hori- zontal interquad. The vertical interquad has similar connections. The connections shown in Figure 29 are made with PLCs located above and below the routing shown in the figure. The interquad routing segments, prefixed IH for interquad horizontal, are in ten groups of five lines. Any one line from each group can be routed to one of the xH segments from the top of the device (left for vertical interquad), one of the xH segments from the bottom of the device (right for vertical inter- quag), and one of the x5 segments crossing the inter- quad. Figure 28 shows four fast middle clock (fast clock) sig- nals with the suffixes T (top), B (bottom), R (right), and L (left), respectively. Figure 29 also shows the fast clock R and fast clock L lines; these are dedicated interquad clock spines. They originate in the CLKCN- TRL special function blocks in the middle of each edge of the device, with the name referencing the edge of origin. For example, fast clock R originates in the CLKCNTRL block on the right edge of a device. Fast clock spines traverse the entire PLC array but do not connect to the PICs on the edge of the device opposite to the source. Each fast clock line connects to two of the xL lines in each PLC that run orthogonally to the fast clock. These connections allow the fast clock lines to generate a clock tree that can reach any PLC in the BL[9:0] vxb[9:0] vx5[9:0] vx1[9:0] SUL[9:0] vx1[9:0) FAST CARRY device. Fast clocks and other clock resources are dis- cussed in the Clock Distribution Network section. Programmable Corner Cell Routing Programmable Routing The programmable corner cell (PCC) contains the cir- cuitry to connect the routing of the two PICs in each corner of the device. The PIC px1 and px2 segments and eight PIC switching segments are directly con- nected together from one PIC to another. The px5 lines are all broken with CIPs and the PIC pxL and pxH segments are connected from one block to another through programmable buffers. Corner Cell Special Functions In addition to routing functions, special-purpose func- tions are located in each FPGA corner. The upper-left PCC contains connections to the boundary-scan logic and microprocessor interface. The upper-right PCC contains connections to the readback logic, connectiv- ity to the global 3-state signal (TS_ALL), and a pro- grammable clock manager. The lower-left PCC contains connections to the internal oscillator and a programmable clock manager. The lower-right PCC contains connections to the start-up and global reset logic. These functions are all more completely described in the Special Function Blocks section of this data sheet. IHO[4:0] 1H1 [4:0] 1H2[4:0] 1H3(4:0) 1H4[4:0] FAST CLOCK R FAST CLOCK L 1H5[4:0] IH6[4:0} 1H7[4:0] IH8[4:0} 1H9{4:0} vek vxH[9:0] BL{9:0] 5-5821(F) Figure 29. hiQ Block Detail 48 Lucent Technologies Inc.Data Sheet June 1999 High-Level Routing Resources (continued) PIC Interquad (MID) Routing There is also connectivity between the PICs in each quadrant, as well as a clock control (CLKCNTRL) mod- ule (discussed in the Special Function Blocks section) between the PIC routing and the interquad routing. These blocks are called LMID (left), TMID (top), RMID (right), and BMID (bottom). The TMID routing is shown in Figure 30. As with the hIQ and viQ blocks, the only connectivity to the PIC routing is to the global pxH and px5 segments. ORCA Series 3C and 3T FPGAs The pxH segments from the one quadrant can be con- nected through a CIP to its counterpart in the opposite quadrant, providing a path that spans the array of PiCs. Since a passive CIP is used to connect the two pxH segments, a 3-state signal can be routed on the two pxH segments in the opposite quadrants, and then connected through this CIP. As with the hiQ and viQ blocks, CIPs and buffers allow nibble-wide connections between the interquad segments, the xH segments, and the x5 segments. SHUTOFF EXPRESSCLK LEFT = = Seon ae = 2 Moen NS a a a3 a7 Jo x x x =x KX x x a o KR 6S oO > > >> >> >> > 2 2222 22 FAST CLOCK EXPRESSCLK RIGHT PIC LOCAL CLOCKS FROM RIGHT PIC LOCAL CLOCKS FROM LEFT pxL[9-0] pxH[7:0] px5{9:0} px2[4:0] pxt[4:0] pSWI7:4] pSWI3:0] pSWI7:4] pSW(3:0] in2[A:D] FROM LEFT infA:D] FROM RIGHT CORNER ExpressCLK a2- OH NOOK NS jes ZIT StI 73T7 T7 x KR xXx X x * zl ae Ande = 66 2= 22 2222 2? + -5822(F) Figure 30. Top (TMID) Routing Lucent Technologies Inc. 49ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Clock Distribution Network The Series 3 FPGAs provide three types of high- speed, low-skew clock distributions: system clock, fast middle clock (fast clock), and ExpressCLK. Because of the great variety of sources and distribution for clock signals in the ORCA Series 3, the clock mechanisms will be described here from the inside out. The clock connections to the PFU will be described, followed by clock distribution to the PLC array, clock sources to the PLC array, and finally ending with clock sources and distribution in the PICs. The ExpressCLK inputs are new, dedicated clock inputs in Series 3 FPGAs. They are mentioned in several of the clock network descrip- tions and are described fully later in this section. PFU Ciock Sources Within a PLC there are five sources for the clock signal of the latches/FFs in the PFU. Two of the signals are generated off of the jong lines (xL) within the PLC: one from the set of vertical long lines and one from the set of horizontal long lines. For each of these signals, any one of the ten long lines of each set, vertical or horizon- tal, can generate the clock signal. Two of the five PFU clock sources come from neighboring PLCs. One clock is generated from the PLC to the left or right of the cur- rent PLC, and one is generated from the PLC above or below the current PLC. The selection decision as to where these signals come from, above/below and left/ right, is based on the position of the PLC in the array and has to do with the alternating nature of the source of the system clock spines (discussed later). The last of the five clock sources is also generated within the PLC. The E1 control signai, described in the PLC Routing Resources section, can drive the PFU clock. The E1 signal can come from any xBID routing resource in the PLC. The selection and switching of clock signals ina PLC is performed in the FINS. Figure 31 shows the PFU clock sources for a set of four adjacent PLCs. Global Control Signals The four clock signals in each PLC that are generated from the long lines (xL) in the current PLC or an adja- cent PLC can also be used to drive the PFU clock enable (CE), local set/reset (LSR) and add/subtract/ write enable (ASWE) signals. The clock signals gener- ated from vertical long lines can drive CE and ASWE, and the clocks generated from horizontal long lines can drive LSR. This allows for low-skew global distribution of two of these three contro! signals with the clock rout- ing while still allowing a global clock route to occur. vxL[9:0] | PFU P I mr | E1 ' : hxL[9:0] | Pic | P I L, ye I I E1 | t hxL[9:0] 5-6054(F) Figure 31. PFU Clock Sources 50 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Clock Distribution Network (continued) Clock Distribution in the PLC Array System Clock (SCLK) The clock distribution network, or clock spine network, within the PLC array is designed to minimize clock skew while maximizing clock flexibility. Clock flexibility is expressed in two ways: the ease with which a single clock is routed to the entire array, and the capability to provide multiple clocks to the PLC array. There is one horizontal and one vertical clock spine passing through each PLC. The horizontal clock spine is sourced from the PIC in the same row on either the left- or right-hand side of the array, with the source side (left or right) alternating for each row. The vertical clock spines are similarly sourced from the PICs alternating from the top or bottom of a column. Each clock spine is capable of driving one of the ten xL routing segments that run orthogonal to it within each PLC. Full connec- tivity to all PFUs is maintained due to the connectivity from the xL lines to the PFU clock signals described in the previous section; however, only an xL line in every other row (column) needs to be driven to allow the given clock signal to be distributed to every PFU. Figure 32 is a high-level diagram of the Series 3 system clock spine network with sample xL line connections for a 4 x 4 array of PLCs. The clock spine structure previously described pro- vides for complete distribution of a clock from any I/O pin to the entire PLC array by means of a single clock spine and long lines (xL). This distribution system also provides a means to have many different clocks routed to many different and dispersed locations in the PLC array. Each spine can carry a different clock signal, so for the OR3C/T55 (which has an 18 x 18 array of PLCs, implying nine clock spines per side), 36 input clock sig- nals can be supported using the system clock network. Fast Clock Fast clocks are high-speed, low-skew clock spines that originate from the CLKCNTRL special function blocks (described later). There are four fast clock spinesone originating on the middle of each edge of the array. The spines run in the interquad region of the PLC array from their source side of the device to the last row or column on the opposite side of the device. The fast clocks connect to two long lines, xL[8] and xL[9], that run orthogonal to the spine direction in each PLC. These long lines can then be connected to the PFU clock input in the same manner as the general system clocks, and, like the system clock connections, xL lines are only needed in every other row (column) to distrib- ute a clock to every PFU. The limited number of long- line connections and the low skew of the CLKCNTRL source combine to make the fast clocks a very robust, low-skew clock source. UNUSED VERTICAL UNUSED SCLK SPINE SCLK SPINE SCLK SPINE UNUSED a 4 ) 4 4 SCLK SPINE (xt) vy v 4 HORIZONTAL SCLK SPINE A 4 A ot) scik SPINE >> _ t t UNU: + SO SPINE od) soe see - (kL) y y (xt) UNUSED UNUSED SCLK SPINE SCLK SPINE -5801(F).a Figure 32. ORCA Series 3 System Clock Distribution Overview Lucent Technologies Inc. 51ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Clock Distribution Network (continued) Clock Sources to the PLC Array The source of a clock that is globally available to the PLC array can be from any user I/O pad, any of the ExpressCLK pads, or an internally generated source. System Clock As described in the Programmable Input/Output Cells section, PICs are grouped in adjacent pairs. Any one of the eight pads in a PIC pair can drive a clock spine ina row or column. For PIC pairs on the top of the chip, the column associated with the left PIC has the clock spine, for pairs on the bottom, the right PIC column has the spine. The top PIC of the pair sources the spine from the left side of the array, and the bottom PIC of the pair sources the spine from the right side of the array. Clock delay and skew are minimized by having a single clock buffer per pair of PICs. The clock spine for each pair can also be driven by one of the four PIC switching segments (pSW) in each PIC of the pair. This allows a signal generated in the PLC array to be routed onto the global clock spine network. The system clock output of the programmable clock manager (PCM) may also be routed to the global system clock spines via the pSW segments. Figure 33 shows the clock spine multiplex- ing structure for a pair of PICs on the top of the array. Fast Clock The fast clock spines are sourced to the PLC array from each side of the device by the ExpressCLK pads via the CLKCNTRL function block (described in the Special Function Blocks section). The ExpressCLK and fast clock source from the pads is shown in Figure 34 and will be described further in the ExpressCLK Inputs subsection. | pswi4] 1 pSwis] I pSwi] I "7 t TO LOCAL CLOCKS | TO LOCAL CLOCKS 1 SPINE t TRHICL | TRICR 5-5800(F) Figure 33. PIC System Clock Spine Generation 52 Clocks in the PICs Because the Series 3 FPGAs have latches and FFs in the I/Os, it is necessary to have clock signal distribution to the PlOs as well as in the PLC array. The system clock, the fast clock, and the ExpressCLK are available for PIO clocking. PIC System Clock There are five local system clock lines in each PIC. Much like the sources for a clock in the PFU, two of the local PIC clocks are generated within the PIC from long lines. One is generated from the set of ten PIC long lines (pxL) that runs parallel to the PICs on a side, and the other is generated from the set of ten long lines (xL) from the PLC array that terminate in the PIC. Another local PIC system clock route comes from the set of ten xL lines in the adjacent PLC that is parallel to the side of the array on which the PIC resides. The fourth local PIC system clock route comes from the set of ten long lines (xL) from the PLC array that terminate in the adja- cent PIC that is not part of the same PIC pair. Much like the E1 signals in the PLCs that are used to distribute a local clock to the PFU source, the fifth local clock fine in each PIC comes from local pSW signals. This clock signal for each PIC is shown in Figure 33. One of these five local PIC system clocks is selected for the system clock signal in the PIO. It is used as the PIO system clock for both input and output clocking as selected within the PIO. All PIOs in a PIC share the same sys- tem clock. PIC ExpressCLK The ExpressCLK signal used at the PIC latches/FFs comes from the CLKCNTRL function block that resides in the middle of the side on which the PIC resides. A single signal comes from the CLKCNTRL and is driven by separate buffers onto two ExpressCLK long wires. One of these ExpressCLK signals goes to the PICs on the right of (above) the CLKCNTRL block, and the other ExpressCLK signal goes to the PICs on the left of (below) the CLKCNTRL block on that side. Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Clock Distribution Network (continued) ExpressCLK Inputs There are four dedicated ExpressCLK pads on each Series 3 device: one in the middle of each side. Two other user I/O pads can also be used as corner ExpressCLK inputs, one on the lower-left corner, and one on the upper-right corner. The corner ExpressCLK pads feed the ExpressCLK to the two sides of the array that are adjacent to that corner, always driving the same signal in both directions. The ExpressCLK route from the middle pad and from the corner pad associ- ated with that side are multiplexed and can be glitch- lessly stopped/started under user control using the StopCLK feature of the CLKCNTRL function block (described under Special Function Blocks) on that side. The ExpressCLK output of the programmable clock manager (PCM) is programmably connected to the cor- ner ExpressCLK routes. PCM blocks are found in the same corners as the corner ExpressCLK signals and are described in the Special Function Blocks section. The ExpressCLK structure is shown in Figure 34 (PCM blocks are not shown). bX ie _y_. | CLKCNTRI BLOCK EXPRESSCLK PADS \ nts = Hx i xX EXPRESSCLKS TO PlOs 5-5802(F) Note: All multiplexers are set during configuration. Figure 34. ExpressCLK and Fast Clock Distribution Selecting Clock Input Pins Any user {/O pin on an ORCA FPGA can be used as a fast, low-skew system clock input. Since the four dedi- cated ExpressCLK inputs can only be used to distribute global signals into the FPGA, these pins should be selected first as clock pins. Within the interquad region of the device, these clocks sourced by the ExpressCLK inputs are called fast clocks. Choosing the next clock Lucent Technologies Inc. pin is completely arbitrary, but using a pin that is near the center of an edge of the device will provide the low- est skew system clock network. The pin-to-pin timing numbers in the Timing Characteristics section assume that the clock pin is in one of the PICs at the center of any side of the device next to an ExpressCLK pad. For actual timing characteristics for a given clock pin, use the timing analyzer results from ORCA Foundry. To select subsequent clock pins, certain rules should be followed. As discussed in the Programmable Input/ Output Cells section, PICs are grouped into adjacent pairs. Each of these pairs contains eight I/Os, but only one of the eight I/Os in a PIC pair can be routed directly onto a system clock spine. Therefore, to achieve top performance, the next clock input chosen should not be one of the pins from a PIC pair previously used for a clock input. If it is necessary to have a second input in the same PIC pair route onto global system clock rout- ing, the input can be routed to a free clock spine using the PIC switching segment (pSW) connections to the clock spine network at some small sacrifice in speed. Alternatively, if global distribution of the secondary clock is not required, the signal can be routed on long lines (xL) and input to the PFU clock input without using a clock spine. Another rule for choosing clock pins has to do with the alternating nature of clock spine connections to the xL and pxL routing segments. Starting at the left side of the device, the first vertical clock spine from the top connects to hxL[0] (horizontal xL[0]), and the first verti- cal clock spine from the bottom connects to hxL{[5] in all PLC rows. The next vertical clock spine from the top connects to hxL[1], and the next one from the bottom connects to hxL[6]. This progression continues across the device, and after a spine connects to hxL[9], the next spine connects to hxL[0] again. Similar connec- tions are made from horizontal clock spines to vxL (ver- tical xL) lines from the top to the bottom of the device. Because the ORCA Series 3 clock routing only requires the use of an xL line in every other row or col- umn, even two inputs chosen 20 PLCs apart on the same xL line will not conflict, but it is always better to avoid these choices, if possible. The fast clock spines in the interquad routing region also connect to xL[8] and xL[9] for each set of xL lines, so it is better to avoid user I/Os that connect to xL[8] or xL[9] when a fast clock is used that might share one of these connec- tions. Another reason to use the fast clock spines is that since they use only the xL[9:8] lines, they will not conflict with internal data buses which typically use xL{7:0]. For more details on clock selection, refer to application notes on clock distribution in ORCA Series 3 devices. 53ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Special Function Blocks Special function blocks in the Series 3 provide extra capabilities beyond general FPGA operation. These blocks reside in the corners and MIDs (middle inter- quad areas) of the FPGA array. Single Function Blocks Most of the special function blocks perform a specific dedicated function. These functions are data/configura- tion readback control, global 3-state control (TS_ALL), internal oscillator generation, global set/reset (GSRN), and start-up logic. Readback Logic The readback logic is located in the upper right corner of the FPGA and can be enabled via a bit stream option or by instantiation of a library readback component. Readback is used to read back the configuration data and, optionally, the state of the PFU outputs. A read- back operation can be done while the FPGA is in nor- mal system operation. The readback operation cannot be daisy-chained. To use readback, the user selects options in the bit stream generator in the ORCA Foundry Development System. Table 12 provides readback options selected in the bit stream generator tool. The table provides the number of times that the configuration data can be read back. This is intended primarily to give the user control over the security of the FPGAs configuration program. The user can prohibit readback (0), allow a single readback (1), or allow unrestricted readback (U). Table 12. Readback Options Option Function 0 Prohibit Readback 1 Allow One Readback Only U Allow Unrestricted Number of Readbacks 54 Readback can be performed via the Series 3 micropro- cessor interface (MPI) or by using dedicated FPGA readback controls. If the MPI is enabled, readback via the dedicated FPGA readback logic is disabled. Read- back using the MPI is discussed in the Microprocessor Interface (MPI) section. The pins used for dedicated readback are readback data (RD_DATA), read configuration (RD_CFG), and configuration clock (CCLK). A readback operation is ini- tiated by a high-to-low transition on RD_CFG. The RD_CFG input must remain low during the readback operation. The readback operation can be restarted at frame 0 by driving the RD_CFG pin high, applying at least two rising edges of CCLK, and then driving RD_CFG low again. One bit of data is shifted out on RD_DATA at the rising edge of CCLK. The first start bit of the readback frame is transmitted out several cycles after the first rising edge of CCLK after RD_CFG is input low (see the Readback Timing Characteristics table in the Timing Characteristics section). To be certain of the start of the readback frame, the data can be monitored for the 01 frame start bit pair. Readback can be initiated at an address other than frame 0 via the new microprocessor interface (MPI) control registers (see the Microprocessor Interface (MPI) section for more information). In all cases, read- back is performed at sequential addresses from the start address. It should be noted that the RD_DATA output pin is also used as the dedicated boundary-scan output pin, TDO. If this pin is being used as TDO, the RD_DATA output from readback can be routed internally to any other pin desired. The RD_CFG input pin is also used to control the global 3-state (TS_ALL) function. Before and during configuration, the TS_ALL signal is always driven by the RD_CFG input and readback is disabled. After con- figuration, the selection as to whether this input drives the readback or global 3-state function is determined by a set of bit stream options. If used as the RD_CFG input for readback, the internal TS_ALL input can be routed internally to be driven by any input pin. Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) The readback frame contains the configuration data and the state of the internal logic. During readback, the value of all registered PFU and PIC outputs can be captured. The following options are allowed when doing a capture of the PFU outputs. 1. Do not capture data (the data written to the RAMs, usually 0, will be read back). 2. Capture data upon entering readback. 3. Capture data based upon a configurable signal internal to the FPGA. If this signal is tied to logic 0, capture RAMs are written continuously. 4, Capture data on either options 2 or 3 above. The readback frame has an identical format to that of the configuration data frame, which is discussed later in the Configuration Data Format section. If LUT memory is not used as RAM and there is no data capture, the readback data {not just the format) will be identical to the configuration data for the same frame. This eases a bitwise comparison between the configuration and readback data. The configuration header, including the length count field, is not part of the readback frame. The readback frame contains bits in locations not used in the configuration. These locations need to be masked out when comparing the configuration and readback frames. The development system optionally provides a readback bit stream to compare to readback data from the FPGA. Also note that if any of the LUTs are used as RAM and new data is written to them, these bits will not have the same values as the original configuration data frame either. Global 3-State Control (TS_ALL) To increase the testability of the ORCA Series FPGAs, the global 3-state function (TS_ALL) disables the device. The TS_ALL signal is driven from either an external pin or an internal signal. Before and during configuration, the TS_ALL signal is driven by the input pad RD_CFG. After configuration, the TS_ALL signal can be disabled, driven from the RD_CFG input pad, or driven by a general routing signal in the upper right cor- ner. Before configuration, TS_ALL is active-low; after configuration, the sense of TS_ALL can be inverted. Lucent Technologies Inc. The following occur when TS_ALL is activated: +. All of the user I/O output buffers are 3-stated, the user I/O input buffers are pulled up (with the pull- down disabled), and the input buffers are configured with TTL input thresholds (OR3Cxx only). 2. The TDO/RD_DATA output buffer is 3-stated. 3. The RD_CFG, RESET, and PRGM input buffers remain active with a pull-up. 4. The DONE output buffer is 3-stated, and the input buffer is pulled up. Internal Oscillator The internal oscillator resides in the lower left corner of the FPGA array. It has output clock frequencies of 1.25 MHz and 10 MHz. The internal oscillator is the source of the internal CCLK used for configuration. It may also be used after configuration as a general- purpose clock signal. Global Set/Reset (GSRN) The GSRN logic resides in the lower right corner of the FPGA. GSRN is an invertible, default, active-low signal that is used to reset all of the user-accessible latches/ FFs on the device. GSRN is automatically asserted at powerup and during configuration of the device. The timing of the release of GSRN at the end of config- uration can be programmed in the start-up logic described below. Following configuration, GSRN may be connected to the RESET pin via dedicated routing, or it may be connected to any signal via normal routing. Within each PFU and PIO, individual FFs and latches can be programmed to either be set or reset when GSRN is asserted. A new option in Series 3 allows indi- vidual PFUs and P1tOs to turn off the GSRN signal to its latches/FFs after configuration. The RESET input pad has a special relationship to GSRN. During configuration, the RESET input pad always initiates a configuration abort, as described in the FPGA States of Operation section. After configura- tion, the global set/reset signal (GSRN) can either be disabled (the default), directly connected to the RESET input pad, or sourced by a lower-right corner signal. If the RESET input pad is not used as a global reset after configuration, this pad can be used as a normal input pad. 55ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Special Function Blocks (continued) Start-Up Logic The start-up logic block is located in the lower right cor- ner of the FPGA. This block can be configured to coor- dinate the relative timing of the release of GSRN, the activation of all user I/Os, and the assertion of the DONE signal at the end of configuration. If a start-up clock is used to time these events, the start-up clock can come from CCLK, or it can be routed into the start- up block using lower right corner routing resources. These signals are described in the Start-Up subsection of the FPGA States of Operation section. Clock Control (CLKCNTRL) and StopCLK There is one CLKCNTRL block in the MID section of the interquad routing on each side of the FPGA. This block is used to selectively distribute the fast clock to the PLC array and the left (top) and right (bottom) ExpressCLKs (ECKL and ECKR) to the side of the array on which the CLKCNTRL block resides. The source clock for the CLKCNTRL block comes either from the ExpressCLK pad at the middle of the side of the FPGA or from the corner ExpressCLK route that comes from the corner ExpressCLK pad (at the lower left or upper right of the device, whichever is closer). The programmable clock manager ExpressCLK output can also be sourced to this corner routing for distribution at the two closest CLKCNTRL blocks. Each CLKCNTRL block also features an invertible StopCLK shutoff input that is available from local rout- ing. This feature may be used to glitchlessly stop and start the clock at the three outputs of each CLKCNTRL block and has the option of doing so on either the rising or falling edge of the clock. When the clock is halted based on its rising edge, it stops and stays at Vop. When it is stopped based on its falling edge, it stops and stays at GND. If the StopCLK shutoff signal meets the CLKCNTRL setup and hold times, the clock is stopped on the second clock cycle after the shutoff sig- nal. A diagram of the bottom CLKCNTRL block and StopCLK timing is shown in Figure 35. y ++- CORNER EXPRESSCLK CLOCK SHUTOFF EXPRESSCLK LEFT lop ole EXPRESSCLK RIGHT FAST CLOCK OFF_SET. < OFFHLD ~ CLOCK SHUTOFF / \ An CLKCNTRL OUTPUT CLOCKS Notes: CLKCNTARL output clocks are ExpressCLK left and right and fast clock. Clock shutoff shown active-high acting on clock falling edge. rs -N rn . a c s . ? ng x t. dont, den al 2 5-5981(F) Figure 35. Top CLKCNTRL Function Block 56 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) Boundary Scan The increasing complexity of integrated circuits (ICs) and IC packages has increased the difficulty of testing printed-circuit boards (PCBs). To address this testing problem, the /EEE standard 1149.1/D1 (/EEE Standard Test Access Port and Boundary-Scan Architecture) is implemented in the ORCA series of FPGAs. It allows users to efficiently test the interconnection between integrated circuits on a PCB as well as test the inte- grated circuit itself. The /EEE 1149.1/D1 standard is a well-defined protocol that ensures interoperability among boundary-scan (BSCAN) equipped devices from different vendors. The /EEE 1149.1/D1 standard defines a test access port (TAP) that consists of a four-pin interface with an optional reset pin for boundary-scan testing of inte- grated circuits in a system. The ORCA Series FPGA provides four interface pins: test data in (TDI), test mode select (TMS), test clock (TCK), and test data out (TDO). The PRGM pin used to reconfigure the device also resets the boundary-scan logic. The user test host serially loads test commands and test data into the FPGA through these pins to drive out- puts and examine inputs. In the configuration shown in Figure 36, where boundary scan is used to test ICs, test data is transmitted serially into TDI of the first BSCAN device (U1), through TDO/TDI connections between BSCAN devices (U2 and U3), and out TDO of the last BSCAN device (U4). In this configuration, the TMS and TCK signals are routed to all boundary-scan ICs in paralle! so that all boundary-scan components operate in the same state. In other configurations, mul- tiple scan paths are used instead of a single ring. When multiple scan paths are used, each ring is indepen- dently controlled by its own TMS and TCK signals. Figure 37 provides a system interface for components used in the boundary-scan testing of PCBs. The three major components shown are the test host, boundary- scan support circuit, and the devices under test (DUTs). The DUTs shown here are ORCA Series FPGAs with dedicated boundary-scan circuitry. The test host is normally one of the following: automatic test equipment (ATE), a workstation, a PC, or a micropro- cessor. Lucent Technologies Inc. B29 ENLARGED VIEW BELOW 5-5972(F) Key: BSC = boundary-scan cell, BDC = bidirectional data cell, and DCC = data control cell. Figure 36. Printed-Circuit Board with Boundary- Scan Circuitry 57Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Special Function Blocks (continued) D{7:0] #4 D[7:0] TDO TDI TDO TDI TDO LUCENT ORCA ORCA BOUNDARY- SERIES eee SERIES SCAN FPGA FPGA __ MASTER MICRO- CE TMSO TMS (DUT) TMS (DUT) PROCESSOR | RA TCK >| TCK TCK RW [I DAV INTR iNT (BSM) Tol F fl TDI TDO}+ ORCA SERIES FPGA TMS (DUT) TCK 5-6765(F) Figure 37. Boundary-Scan Interface The boundary-scan support circuit shown in Figure 37 is the 497AA Boundary-Scan Master (BSM). The BSM off-loads tasks from the test host to increase test throughput. To interface between the test host and the DUTs, the BSM has a general microprocessor interface and provides parallel-to-serial/serial-to-parallel conver- sion, as well as three 8K data buffers. The BSM also increases test throughput with a dedicated automatic test-pattern generator and with compression of the test response with a signature analysis register. The PC- based boundary-scan test card/software allows a user to quickly prototype a boundary-scan test setup. Boundary-Scan Instructions The ORCA Series boundary-scan circuitry is used for three mandatory /EEE 1149.1/D1 tests (EXTEST, SAMPLE/PRELOAD, BYPASS), the optional /EEE 1149.1/D1 IDCODE instruction, and five ORCA-defined instructions. The 3-bit wide instruction register sup- ports the nine instructions listed in Table 13, where the use of PSR1 or USERCODE is selectable by a bit stream option. 58 Table 13. Boundary-Scan Instructions Code Instruction 000 EXTEST 001 PLC Scan Ring 1 (PSR1)/USERCODE 010 RAM Write (RAM_W) 011 IDCODE 100 SAMPLE/PRELOAD 101 PLC Scan Ring 2 (PSR2) 110 RAM Read (RAM_R) 111 BYPASS Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) The external test (EXTEST) instruction allows the inter- connections between ICs in a system to be tested for opens and stuck-at faults. lf an EXTEST instruction is performed for the system shown in Figure 36, the con- nections between U1 and U2 (shown by nets a, b, and c) can be tested by driving a value onto the given nets from one device and then determining whether the same value is seen at the other device. This is deter- mined by shifting 2 bits of data for each pin (one for the output value and one for the 3-state value) through the BSR until each one aligns to the appropriate pin. Then, based upon the value of the 3-state signal, either the I/O pad is driven to the value given in the BSR, or the BSR is updated with the input value from the I/O pad, which allows it to be shifted out TDO. The SAMPLE/PRELOAD instruction is useful for sys- tem debugging and fault diagnosis by allowing the data at the FPGAs '/Os to be observed during normal Table 14. Boundary-Scan ID Code operation or written during test operation. The data for all of the I/Os is captured simultaneously into the BSR, allowing them to be shifted-out TDO to the test host. Since each I/O buffer in the PICs is bidirectional, two pieces of data are captured for each I/O pad: the value at the I/O pad and the value of the 3-state control sig- nal. For preload operation, data is written from the BSR to all of the I/Os simultaneously. There are five ORCA-defined instructions. The PLC scan rings 1 and 2 (PSR1, PSR2) allow user-defined internal scan paths using the PLC latches/FFs. The RAM_Write Enable (RAM_W) instruction allows the user to serially configure the FPGA through TDI. The RAM_Read Enable (RAM_R) allows the user to read back RAM contents on TDO after configuration. The IDCODE instruction allows the user to capture a 32-bit identification code that is unique to each device and serially output it at TDO. The IDCODE format is shown in Table 14. Device Version Part* Family Manufacturer LSB (4 bits) (10 bits) | (6 bits) (11 bits) (1 bit) OR3T20 0000 0011000000; 110000} 00000011101 1 OR3T30 0000 0111000000! 110000 00000011101 1 OR3C/T55 0000 0100100000} 110000} 00000011101 1 OR3C/T80 0000 0110100000] 110000} 00000011101 1 OR3T125 0000 0011100000] 110000} 00000011101 1 OR3T165 0000 0000010000| 110000 00000011101 1 * PLC array size of FPGA, reverse bit order. Note: Table assumes version 0. Lucent Technologies Inc. 59ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Special Function Blocks (continued) ORCA Boundary-Scan Circuitry The ORCA Series boundary-scan circuitry includes a test access port controller (TAPC), instruction register (IR), boundary-scan register (BSR), and bypass regis- ter. It also includes circuitry to support the four pre- defined instructions. Figure 38 shows a functional diagram of the boundary- scan circuitry that is implemented in the ORCA Series. The input pins (TMS, TCK, and TDI) locations vary depending on the part, and the output pin is the dedi- cated TDO/RD_DATA output pad. Test data in (TDI) is the serial input data. Test mode select (TMS) controls the boundary-scan test access port controller (TAPC). Test clock (TCK) is the test clock on the board. The BSR is a series connection of boundary-scan cells (BSCs) around the periphery of the IC. Each I/O pad on the FPGA, except for CCLK, DONE, and the boundary- scan pins (TCK, TDI, TMS, and TDO), is included in the BSR. The first BSC in the BSR (connected to TDI) is located in the first PIC 1/O pad on the left of the top side of the FPGA (PTA PIC). The BSR proceeds clock- wise around the top, right, bottom, and left sides of the array. The last BSC in the BSR (connected to TDO) is located on the top of the left side of the array (PL1D). The bypass instruction uses a single FF, which resyn- chronizes test data that is not part of the current scan operation. In a bypass instruction, test data received on TDI is shifted out of the bypass register to TDO. Since the BSR (which requires a two FF delay for each pad) is bypassed, test throughput is increased when devices that are not part of a test operation are bypassed. The boundary-scan logic is enabled before and during configuration. After configuration, a configuration option determines whether or not boundary-scan logic is used. The 32-bit boundary-scan identification register con- tains the manufacturer's ID number, unique part num- ber, and version (as described earlier). The identification register is the default source for data on TDO after RESET if the TAP controller selects the shift- data-register (SHIFT-DR) instruction. If boundary scan is not used, TMS, TDI, and TCK become user I/Os, and TDO is 3-stated or used in the readback operation. An optional USERCODE is available if the boundary- scan PSR1 instruction is not used. The selection between PSR1 and USERCODE is a configuration option and can be performed in ORCA Foundry. The USERCODE is an 11-bit value that the user can set during device configuration and can be written to and read from the FPGA via the boundary-scan logic. The USERCODE value replaces the manufacturer fieid of the boundary-scan ID code when the USERCODE instruction is issued, allowing users to have configured devices identified in a user-defined manner. The manu- facturer ID field remains available when the IDCODE instruction is issued. DATAREGISTERS ** Yosyvy BOUNDARY-SCAN REGISTER IDCODE REGISTER PSA1 REGISTER (PLCs) PSR2 REGISTER (PLCs) MUX DATA UL] Vpo CONFIGURATION REGISTER, (RAM_R, RAM_W) RESET CLOCK DR SHIFT-DR UPDATE-DR} iS 2 ifs TCK TAP CONTROLLER g UPDATE-IR Vgo PUR SELECT ENABLE 5-5768(F) Figure 38. ORCA Series Boundary-Sean Circuitry Functional Diagram 60 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) ORCA Series TAP Controller (TAPC) The ORCA Series TAP controller (TAPC) is a 1149.1/ D1 compatible test access port controller. The 16 JTAG state assignments from the /EEE 1149.1/D1 specifica- tion are used. The TAPC is controlled by TCK and TMS. The TAPC states are used for loading the IR to allow three basic functions in testing: providing test stimuli (Update-DR), test execution (Run-Test/Idle), and obtaining test responses (Capture-DR). The TAPC allows the test host to shift in and out both instructions and test data/results. The inputs and outputs of the TAPC are provided in the table below. The outputs are primarily the control signals to the instruction register and the data register. Table 15. TAP Controller Input/Outputs Symbol VO Function TMS | | Test Mode Select TCK 1 | Test Clock PUR | | Powerup Reset PRGM | | BSCAN Reset TRESET O | Test Logic Reset Select | Select IR (High); Select-DR (Low) Enable O | Test Data Out Enable Capture-DR | O | Capture/Parallel Load-DR Capture-IR { O | Capture/Parallel Load-IR Shift-DR | Shift Data Register Shift-IR O | Shift Instruction Register Update-DR | O | Update/Parallel Load-DR Update-IR | O | Update/Parallel Load-IR Lucent Technologies Inc. The TAPC generates control signals that allow capture, shift, and update operations on the instruction and data registers. in the capture operation, data is loaded into the register. In the shift operation, the captured data is shifted out while new data is shifted in. In the update operation, either the instruction register is loaded for instruction decode, or the boundary-scan register is updated for control of outputs. The test host generates a test by providing input into the ORCA Series TMS input synchronous with TCK. This sequences the TAPC through states in order to perform the desired function on the instruction register or a data register. Figure 39 provides a diagram of the state transitions for the TAPC. The next state is deter- mined by the TMS input value. TEST-LOGIC-|_ 1@ RESET 0 oC) RUN-TEsT/ [1 IDLE 7 5-53704F) Figure 39. TAP Controller State Transition Diagram 61ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Special Function Blocks (continued) Boundary-Scan Cells Figure 40 is a diagram of the boundary-scan cell (BSC) in the ORCA series PICs. There are four BSCs in each PIC: one for each pad, except as noted above. The BSCs are connected serially to form the BSR. The BSC controls the functionality of the in, out, and 3-state signals for each pad. The BSC allows the I/O to function in either the normal or test mode. Normal mode is defined as when an out- put buffer receives input from the PLC array and pro- vides output at the pad or when an input buffer provides input from the pad to the PLC array. In the test mode, the BSC executes a boundary-scan operation, such as shifting in scan data from an upstream BSC in the BSR, providing test stimuli to the pad, capturing test data at the pad, etc. The primary functions of the BSC are shifting scan data serially in the BSR and observing input (p_in), output (p_out), and 3-state (p_ts) signals at the pads. The BSC consists of two circuits: the bidirectional data cell is used to access the input and output data, and the SCAN IN direction control cell is used to access the 3-state value. Both cells consist of a flip-flop used to shift scan data which feeds a flip-flop to control the I/O buffer. The bidirectional data cell is connected serially to the direc- tion control cell to form a boundary-scan shift register. The TAPC signals (capture, update, shiftn, treset, and TCK) and the MODE signal control the operation of the BSC. The bidirectional data cell is also controlled by the high out/low in (HOLI) signal generated by the direction control cell. When HOLL is low, the bidirec- tional data cell receives input buffer data into the BSC. When HOLI is high, the BSC is loaded with functional data from the PLC. The MODE signal is generated from the decode of the instruction register. When the MODE signal is high (EXTEST), the scan data is propagated to the output buffer. When the MODE signal is low (BYPASS or SAMPLE), functional data from the FPGAs internal logic is propagated to the output buffer. The boundary-scan description language (BSDL) is provided for each device in the ORCA Series of FPGAs on the ORCA Foundry CD. The BSDL is generated from a device profile, pinout, and other boundary-scan information. VO BUFFER PAD_IN p_in ~ <] BIDIRECTIONAL DATA CELL PAD_OUT Ly } NS L 0 8) D a Da 1 a 1 a lL PAD_TS p_out 1 > reo HOLI ) 0 [o) DB Q DB. (a 1 p_ts 1 > Pp > q DIRECTION CONTROL CELL SHIFTN/CAPTURE TCK SCAN OUT UPDATE/TCK MODE 5-2844(F Figure 40. Boundary-Scan Cell 62 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Special Function Blocks (continued) Boundary-Scan Timing To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on the rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum fre- quency allowed for TCK is 10 MHz. Figure 41 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is clocked into the DUT on the rising edge. TEST-LOGIC-RESET RUN-TESTADLE SELECT-DR-SCAN SELECT-IR-SCAN CAPTURE-IR } SHIFT-IR EXIT1-IR UPDATE-IR | RUN-TEST/DLE EXIT1-IR SHIFT-IR EXIT2-IR | PAUSE-IR TCK TMS 1 87 TDI XXX) Figure 41. Instruction Register Scan Timing Diagram 5-5971(F) Lucent Technologies Inc. 63ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Microprocessor Interface (MPI) The Series 3 FPGAs have a dedicated synchronous microprocessor interface function block (see Figure 42). The MPI is programmable to operate with PowerPC MPC800 series microprocessors and Inie* i960* J core processors; see Table 16 and Table 17, respectively, for compatible processors. The MPI imple- ments an 8-bit interface to the host processor (Pow- erPC or i960) that can be used for configuration and readback of the FPGA as well as for user-defined data processing and general monitoring of FPGA function. In addition to dedicated-function registers, the micro- processor interface allows for the control of up to 16 user registers (RAM or flip-flops) in the FPGA logic. A synchronous/asynchronous handshake procedure is used to control transactions with user logic in the FPGA array. There is also capability for the FPGA logic to DECODE/CONTAOL CLK ADS ALE wr RD/WR CLKOUT TA DEVICE PAD {] VO BUFFER 2 POWERPCLOGIC interrupt the host processor either by a hard interrupt or by having the host processor poll the microprocessor interface. The control portion of the microprocessor interface is available following powerup of the FPGA if the mode pins specify MPI mode, even if the FPGA is not yet con- figured. The mode pin (M[2:0]) settings can be found in the FPGA Configuration Modes section of this data sheet, and the setup and use of the MPI for configura- tion is discussed in the MPI Setup and Control subsec- tion. For postconfiguration use, the MPI must be included in the configuration bit stream by using an MPI library element in your design from the ORCA macro library, or by setting the MP_USER bit of the MPI con- figuration contro! register prior to the start of configura- tion (MPI registers are discussed later). * Intel and i960 are registered trademarks of Intel Corporation. TO FPGA ROUTING SCRATCHPAD REGISTER READBACK ADOR REGISTER CONTROL REGISTERS TO GSR BLOCK TO FPGA ROUTING 5-5806(F) Figure 42. MPI Block Diagram 64 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) PowerPC System In Figure 43, the ORCA FPGA is a memory-mapped peripheral to the PowerPC processor. The PowerPC interface uses separate address and data buses and has several control lines. The ORCA chip select lines, CSO and CS1, are each connected to an address line coming from the PowerPC. In this manner, the FPGA is capable of a transaction with the PowerPC whenever the address line connected to CS0 is low, the address line for CS1 is high, and there is a valid address on PowerPC address lines A[27:31]. Other forms of selec- tion are possible by using the FPGA chip selects ina different way. For example, PowerPC address bits A[0:26] could be decoded to select CSO and CS1, or if the FPGA is the only peripheral to the PowerPC, CSO and CS1 could be tied low and high, respectively, to cause them to always be selected. If the MPI is not used for FPGA configuration, decoding logic can be implemented internal or external to the FPGA. If logic internal to the FPGA is used, the chip selects must be routed out on an output pin and then connected exter- nally to CSO and/or CS1. If the MPI is to be used for configuration, any decode logic used must be imple- mented external to the FPGA since the FPGA logic has not been configured yet. TO DAISY- BOL Le CHAINED 8, DEVICES D[7:0] > D[7:0] A{27:31] A[4:0] CLKOUT MPI_CLK RD/WR MPI_RW TA MPILACK ORCA Powerrc 4 MEILACK SERIES 3 Bi MPI_Bi PGA iRtQx MPLIRO TS MPI_STRB A26 cso DONE -- A25 cs! iNT > HDC |-> LDC }-> 5-5761(F) Note: FPGA shown as a memory-mapped peripheral using CSO and CS1. Other decoding schemes are possible using CSO and/or CS1. Figure 43. PowerPC/MPI The basic flow of a transaction on the PowerPC/MPI interface is given below. Pin descriptions are shown in Table 16 and timing is shown in the Timing Characteris- tics section of this data sheet. For both read and write transactions, the address, chip select, and read/write Lucent Technologies Inc. (read high, write low) signals are set up at the FPGA pins by the PowerPC. The PowerPC then asserts its transfer start signal (TS) low. Data is available to the MPI during a write at the rising clock edge after the clock cycle during which TS is low. The transfer is acknowledged to the PowerPC by the low assertion of the TA signal. The MP! PowerPC interface does not support burst transfers, so the burst inhibit signal, Bi, is also asserted low during the transferacknowledge. The same process applies to a read from the MPI except that the read data is expected at the FPGA data pins by the PowerPC at the rising edge of the clock when TA is low. The MPI only drives TA low for one clock cycle. Interrupt requests can be sent to the PowerPC asyn- chronously to the read/write process. Interrupt requests are sourced by the user-logic in the FPGA. The MPI will assert the request to the PowerPC as a direct interrupt signal and/or a pollable bit in the MP! status register (discussed in the MPI Setup and Control section). The MPI will continue to assert the interrupt request until the user-logic deasserts its interrupt request signal. Table 16. PowerPC/MPI Configuration PowerPC ORCA Pin MPI Function Signal Name vO D[0:7] D[7:0] VO | 8-bit data bus A(27:31] A[4:0] | 5-bit MP! address bus TS RD/MPI_STRB| 1 | Transfer start signal _ cso 1 Active-low MPI select CS1 | Active-high MPI select CLKOUT | A7/MPILCLK l PowerPC interface clock RO/WR | AS/MPI_RW I Read (high)/write (low) signal! TA AQ/MPI_ACK | O | Active-low transfer acknowledge signal BI A10/MPI_BI O | Active-low burst transfer inhibit signal _Any of A11/MPI_IRQ oO Active-low interrupt IRQ[?:0] request signal 65ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Microprocessor Interface (MPI) (continued) i960 System Figure 44 shows a schematic for connecting the ORCA MPI to supported /960 processors. In the figure, the FPGA is shown as the only peripheral, with the FPGA chip select lines, CSO and CS1, tied low and high, respectively. The (960 address and data are multi- plexed onto the same bus. This precludes memory mapping of the FPGA in the i960 memory space of a multiperipheral system without some form of address latching to capture and hold the address signals to drive the CSO and/or CS1 signals. Multiple address sig- nals could also be decoded and latched to drive the CSO and/or CS1 signals. If the MPI is not used for FPGA configuration, decoding/latching logic can be implemented internal or external to the FPGA. If logic internal to the FPGA is used, the chip selects must be routed out an output pin and then connected externally to CSO and/or CS1. If the MPI is to be used for configu- ration, any decode/latch logic used must be imple- mented external to the FPGA since the FPGA logic has not been configured yet. i960 SYSTEM CLOCK, 8 TO DAISY- ADI7:0] #4 17:0) DOUTT CHAINED CCLK [> Devices CLKIN / MPI_CLK wk >| MPI_RW RDYACV MPI_ACK XINTX MPI_IRG = ORCA i960 ALE MPILALE _ SERIES 3 ADS |MPILSTRE FPGA BEO MPI_BEO BEI >| MPI_BE1 Vpp DONE [--> | INIT [> cSt HDC [> oie myo 5-5762(F) Note: FPGA shown as only system peripheral with fixed-chip select signals. For multiperipheral systems, address decoding and/ or latching can be used to implement chip selects. Figure 44. i960/MPI The basic flow of a transaction on the i960/MP1 inter- face is given below. Pin descriptions are shown in Table 17, and timing is shown in the ORCA Timing Characteristics section of this data sheet. For both read and write transactions, the address latch enable (ALE) is set up by the i960 at the FPGA to the falling edge of the clock. The address, byte enables, chip selects, and read/write (read low, write high) signals are normally 66 set up at the FPGA pins by the /960 at the next rising edge of the clock. At this same rising clock edge, the i960 asserts its address/data strobe (ADS) low. Data is available to the MPI during a write at the rising clock edge of the following clock cycle. The transfer is acknowledged to the i960 by the low assertion of the ready/recover (RDYRCV) signal. The same process applies to a read from the MPI except that the read data is expected at the FPGA data pins by the i960 at the rising edge of the clock when RDYRCV is low. The MPI only drives RDYRCV low for one clock cycle. Interrupts can be sent to the i960 asynchronously to the read/write process. Interrupt requests are sourced by the user-logic in the FPGA. The MPI will assert the request to the /960 as a direct interrupt signal and/or a pollable bit in the MP! status register (discussed in the MPI Setup and Control section). The MPI will continue to assert the interrupt request until the user-logic deas- serts its interrupt request signal. Table 17. i960/MPI Configuration i960 ORCA Pin | MPI Function Signal Name vO AD{[7:0} D[7:0] VO. |Multiplexed 5-bit address/ 8-bit data bus. The address appears on D[4:0]. ALE RDY/RCLK/| | |Address latch enable used MPI_ALE to capture address from AD[4:0] on falling edge of clock. ADS RD/ | |Address/data strobe to MPi_STRB indicate start of transac- tion. _ cso | |Active-low MPI select. _ cs1 | |Active-high MPI select. System A7/ | {i960 system clock. This Clock MPI_CLK clock is sourced by the system and not the i960. W/R |A8/MPILRW] |__| Write (high)/read (low) signal. RDYRCV AQ/ OQ |{Active-low ready/recover MPI_ACK signal indicating acknowl- edgment of the transac- tion. Any of Al1/ O_ |Active-low interrupt XINT[?7:0] | MPI_IRQ request signal. BEO AO/ | |Byte-enable 0 used as MPI_BEO address bit 0 in (960 8-bit mode. BE1 Al/ | |Byte-enable 1 used as MPI_BE1 address bit 1 in (960 8-bit mode. Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) MPI Interface to FPGA The MP! interfaces to the user-programmable FPGA logic using a 4-bit address, read/write control signal, interrupt request signal, and user start and user end handshake signals. Timing numbers are provided so that the user-logic data transfers can be performed syn- chronously with the host processor (PowerPC or i960) interface clock or asynchronously. Table 18 shows the internal interface signals between the MPI and the FPGA user-programmable logic. All of the signals are connected to the MPI in the upper-left corner of the device except for the D[7:0] and CLK signals that come directly from the I/O pin. The 4-bit addressing from the MPI to the PLCs allows for up to 16 locations to be addressed by the host pro- cessor. The user address space of the MPI does not address any hard register. Rather, the user is free to construct registers from FFs, latches, or RAM that can be selected by the addressing. Alternately, the decoded address signals may be used as control signals for other functions such as state machines or timers. The transaction sequence between the MPI and the user-logic is as follows. When the host processor ini- tiates a transaction as discussed in the preceding sec- tions, the MPI outputs the 4-bit user address (UA[3:0]) and the read/write control signal (URDWR, which is read-high, write-low regardless of host processor), and then asserts the user start signal, USTART. During a write from the host processor, the user logic can accept Table 18. MPI Internal Interface Signals data written by the host processor from the D[7:0] pins once the USTART signal is asserted. The user logic ends a transaction by asserting an active-high user end (UEND) signal to the MPI. The MPI will insert wait-states in the host processor bus cycles, holding the host processor until the user- logic completes its task and returns a UEND signal, upon which the MPI generates an acknowledge signal. If the host processor is reading from the FPGA, the user logic must have the read data available on the D[7:0] pins of the FPGA when the UEND signal is asserted. If the user logic is fast or if the MPI user address is being decoded for use as a control signal, the MPI transaction time can be minimized by routing the USTART signal directly to the UEND input of the MPI. The timing section of this data sheet contains a parameter table with delay, setup, and hold timing requirements to operate the user-logic either synchro- nously or asynchronously with the MPI host interface clock. The user-logic may also assert an active-low interrupt request (UIRQ) to the MPI, which, in turn, asserts an interrupt to the host processor. Assertion of an inter- rupt request is asynchronous to the host processor clock and any read or write transaction occurring in the MPI. The user-logic is responsible for providing any required interrupt vectors for the host processor, and the user-logic must deassert the interrupt request once serviced. If the interrupt request is not deasserted in the user logic, it will continue to be asserted to the host processor via the MPI_IRQ pin. Signal MPI VO Function UA[3:0] oO User Logic Address. Addresses up to 16 unique user registers or use as control signals. URDWRN Oo User Logic Read/Write Control Signal. High indicates a read from user logic by the host processor, low indicates a write to user-logic by the host processor. USTART oO Active-High User Start Signal. indicates the start of an MPI transaction between the host processor and the user logic. UEND I Active-High User End Signal. indicates that the user-logic is finished with the current MPI transaction. UIRQ I Active-Low Interrupt. Sends request from the user-logic to the host processor. D[7:0] FPGA I/O |User Data. Eight data bits come directly from the FPGA pinsnot through the MPI. MPI_CLK FPGA! |MPI Clock. The MPI clock is sourced by the host processor and comes directly from the FPGA pinnot through the MPI. Lucent Technologies Inc. 67Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Microprocessor Interface (MPI) (continued) MPI Setup and Control The MP! has a series of addressable registers that provide MPI control and status, configuration and readback data transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 bits wide. The address map for these registers and the user-logic address space are shown in Table 19, followed by descriptions of the register and bit functions. Note that for all registers, the most significant bit is bit 7, and the least significant bit is bit 0. Table 19. MPI Setup and Control Registers Hex) Register 00 Control Register 1. 01 Control Register 2. 02 Scratchpad Register. 03 Status Register. 04 Configuration/Readback Data Register. 05 Readback Address Register 1 (bits [7:0]). 06 Readback Address Register 2 (bits [15:8]). 07 Device ID Register 1 (bits [7:0]). 08 Device ID Register 2 (bits [15:8]}. 09 Device ID Register 3 (bits [23:16]). OA Device ID Register 4 (bits [31:24]). OBOF Reserved. 101F User-definable Address Space. Control Register 1 The MPI control register 1 is a read/write register. The host processor writes a contro! byte to configure the MPI. It is readable by the host processor to verify the status of control bits previously written. Table 20. MPI Setup and Control Registers Descriptions Bit # Description BitO | GSR Input. Setting this bit to a 1 invokes a global set/reset on the FPGA. The host processor must return this bit to a 0 to remove the GSR signal. GSR does not affect the registers at MPI addresses 0 through F hexadecimal! or any configuration registers. Default state = 0. Bit1 | Reserved. Bit2 | Reserved. Bit3 | Reserved. Bit4 | Reserved. Bit5 |AD_CFG Input. Changing this bit to a O after configuration will initiate readback. The host processor must return this bit to a 1 to remove the RD_CFG signal. Since this bit works exactly like the RD_CFG input pin, please see the FPGA pin descriptions for more information on this signa!. Default state = 1. Bit6 | Reserved. Bit7 | PRGM Input. Setting this bit to a 0 causes the FPGA to begin configuration and resets the boundary- scan circuitry. The host processor must return this bit to a 1 to remove the PRGM signal. Since this bit works exactly like the PRGM input pin (except that it does not reset the MPI), please see the FPGA pin descriptions for more information on this signal. Default state = 1. 68 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) Scratchpad Register The MPI scratchpad register is an 8-bit read/write register with no defined operation. It may be used for any user- defined function. Control Register 2 The MPI control register 2 is a read/write register. The host processor writes a control byte to configure the MPI. It is readable by the host processor to verify the status of control bits it had previously written. Table 21. MPI Control Register 2 Bit # Bit Name Description Bit 0 EN_IRQ_CFG Enable iRQ for Configuration Data Request in Daisy-Chain Configuration Mode. Setting this bit to a 1 prior to configuration enables the IRQ signal to go active when new data is requested for configuration writes or is available for configuration reads to/from the configuration data register. A 0 clears the IRQ enable. This bit is only valid for daisy-chain configuration. Default = 0. Bit 1 EN_iIRQ_ERR Enable IRQ for Bit Stream Error. Setting this bit to a 1 prior to configuration enables the IRQ signal to go active on the occurrence of a bit stream error during configuration. A 0 clears the IRQ enable. This bit only has effect while in configura- tion mode. Default = 0. Bit 2 EN_IRQ_USR Enable IRQ from the User FPGA Space. Setting this bit to a 1 allows user-defined circuitry in the FPGA to generate an interrupt to the host processor by sourcing a logic low on the UIRQ signal in the user logic. Default = 0. Bit 3 MP_DAISY MPI Daisy-Chain Output Enable. Setting this bit to a 1 enables daisy-chain output of the configuration data. See the Configuration section of this data sheet for daisy- chain configuration details. Default = 0. Bit 4 MP_HOLD_BUS Enable Bus Holding During Daisy-Chain Configuration Mode. Setting this bit to a 1 will cause the MPI to wait until the FPGA configuration logic has serialized a byte of configuration data before acknowledging the transaction. The data is only serialized if the MP_DAISY (bit 3 above) contro! bit is set to 1. If MP_HOLD_BUS is set to 0, the MPI will immediately acknowledge a configuration data byte transfer. Immediate acknowledgment allows the host processor to perform other tasks during FPGA configuration by polling the MPI status register (or by interrupt) and only write configuration data when the FPGA is ready. Default = 0. Bit 5 MP_USER MPI User Mode Enable. Setting this bit to a 1 will enable the MPI for user mode operation. MP_USER must be set prior to the FPGA DONE signal going high during configuration. The MPI may also be enabled for user operation via the configuration bit stream. Default = 0. Bit 6 Reserved Bit 7 Reserved Lucent Technologies Inc. 69Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Microprocessor Interface (MPI) (continued) Status Register The microprocessor interface status register is a read-only register, providing information to the host processor. Table 22. Status Register Bit # Description BitO | Reserved. Bit1 | Data Ready. Set by the MPI, a 1 on this bit during configuration alerts the host processor that the FPGA is ready for another byte of configuration data. During byte-wide readback, the MPI sets this bit to a 1 to tell the host processor that a byte of configuration data is available for reading. This bit is cleared by a host processor access (read or write) to the configuration data register. Bit2 | IRQ Pending. The MPI sets this bit to 1 to indicate to the host processor that the FPGA has a pending interrupt request. This bit may be used for the host processor to poll for interrupts if the MPI_IRQ pin out- put of the FPGA has been masked at the host processor. This bit is set to 0 when the status register is read. Interrupt requests from the FPGA user space must be cleared in FPGA user logic in addition to reading this bit. Bits | Bit Stream Error Flags. Bits 3 and 4 are set by the MPI to indicate any error during FPGA configura- [4:3] | tion. See bit 2 of control register 2 for the capability to alert the host processor of an error via the IRQ signal during configuration. In the truth table below, bit 3 is the LSB (bit on right). These bits are cleared to 0 when PRGM goes active: 00 = No error 01 = ID error 10 = Checksum error 11 = Stop-bit/alignment error BitS | Reserved. Bit 6 | INIT. This bit reflects the binary value of the FPGA INIT pin. Bit 7 | DONE. This bit reflects the binary value of the FPGA DONE pin. Configuration Data Register The MPI configuration data register is a writable register in configuration mode and a readable register in readback mode. For FPGA configuration, this is where the configuration data bytes are sequentially written by the host pro- cessor. Similarly, for readback mode, the MPI provides the readback data bytes in this register for the host proces- sor. Readback Address Register 1 The MPI readback address register 1 is a writable register used to accept the least significant address byte (bits [7:0]) of the configuration data location to be read back. Readback Address Register 2 The MPI readback address register 2 is a writable register used to accept the most significant address byte (bits [15:8]) of the configuration data location to be read back. 70 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) (continued) Device ID Registers The MPI device ID is broken into four registers holding 1 byte each. The device ID that is available through the MPI is the same as the boundary-scan ID code, except that the device ID in the MPI has a reverse bit order. There is no means to overwrite any of the device ID as can be done with the boundary-scan ID, but the MPI scratchpad register can be used as a personalization register. The format for the entire device ID is shown below followed by family and device values and the partitioning of the device ID into the four device !D registers. Table 23. Device ID Code Version Part* Family Manufacturer MSB 4 bits 10 bits 6 bits 11 bits 1 bit Example: (First version of Lucents OR3C55) 0000 0100100000 110000 00000011101 1 * PLC array size of FPGA. Table 24 shows the family and device values for all parts covered by this data sheet. Table 24. Series 3 Family and Device ID Values Family ID Device ID Part Name (Hex) (Hex) OR3T20 03 oc OR3T30 03 OE ORSC/T55 03 12 OR3C/T80 03 16 OR3T125 03 1c Table 25 describes the device IDs for all parts covered by this data sheet as they are partitioned into the four regis- ters found in the MPI. Table 25. ORCA Series 3 Device ID Descriptions Device ID Register 1 Bit 0 Logic 1. This bit is always a one. Bits [7:1] 0011101, the 7 least significant bits of the Lucent Technologies manufacturer ID. Device ID Register 2 Bits [3:0] 0000, the 4 most significant bits of the Lucent Technologies manufacturer ID. Bits [7:4] The 4 least significant bits of the 10-bit part number. Device ID Register 3 Bits [5:0] The 6 most significant bits of the 10-bit part number. Bits [7:6] The 2 least significant bits of the device family code. Device ID Register 4 Bits [3:0] The 4 most significant bits of the device family code. Bits [7:4] The 4-bit device version code. Lucent Technologies Inc. 71ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Clock Manager (PCM) The ORCA programmable clock manager (PCM) is a special function block that is used to modify or condi- tion clock signals for optimum system performance. Some of the functions that can be performed with the PCM are clock skew reduction (both internal and board level), duty-cycle adjustment, clock delay reduction, clock phase adjustment, and clock frequency multipli- cation/division. Due to the different capabilities required by customer application, each PCM contains both a PLL (phase-locked loop) and a DLL (delayed-locked loop) mode. By using PLC logic resources in conjunc- tion with the PCM, many other functions, such as fre- quency synthesis, are possible. There are two PCMs on each Series 3 device, one in the lower left corner and one in the upper right corner. Each can drive two different, but interrelated clock net- works inside the FPGA. Each PCM can take a clock input from the ExpressCLK pad in its corner or from general routing resources. There are also two input sources that provide feedback to the PCM from the PLC array. One of these is a dedicated corner Express- CLK feedback, and the other is from general routing. Each PCM sources two clock outputs, one to the corner ExpressCLK that feeds the CLKCNTRL blocks on the two sides adjacent to the PCM, and one to the system clock spine network through general routing. Figure 45 shows a high-level block diagram of the PCM. Functionality of the PCM is programmed during opera- tion through a read/write interface internal to the FPGA array or via the configuration bit stream. The internal FPGA interface comprises write enable and read enable signals, a 3-bit address bus, an 8-bit input (to the PCM) data bus, and an 8-bit output data bus. There is also a PCM output signal, LOCK, that indicates a sta- ble output clock state. These signals are used to pro- gram a series of registers to configure the PCM functional core for the desired functionality. Operation of the PCM is divided into two modes, delay- locked loop (DLL) and phase-locked loop (PLL). Some operations can be performed by either mode and some are specific to a particular mode. These will be described in each individual mode section. In general, DLL mode is preferable to PLL mode for the same func- tion because it is less sensitive to input clock noise. In the discussions that follow, the duty cycle is the per- cent of the clock period during which the output clock is high. USER CONTROL SIGNALS h PCM-FPGA INTERFACE H CORNER EXPRESSCLK IN GENERAL CLOCKIN (FROM GENERAL ROUTING) PCM CORE FUNCTIONS * EXPRESSCLK OUT SYSTEM CLOCK OUT (TO GENERAL ROUTING) ff N\ y FEEDBACK ExpressCLK FEEDBACK CLOCK FROM ROUTING 5-5828(F} Figure 45. PCM Block Diagram 72 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) PCM Registers The PCM contains eight user-programmable registers used for configuring the PCMs functionality. Table 26 shows the mapping of the registers and their functions. See Figure 46 for more information on the location of PCM ele- ments that are discussed in the table. The PCM registers are referenced in the discussions that follow. Detailed explanations of all register bits are supplied following the functional description of the PCM. Table 26. PCM Registers Address Function 0 Divider 0 Programming. Programmable divider, DIVO, value and DIVO reset bit. DIVO can divide the input clock to the PCM or can be bypassed. 1 Divider 1 Programming. Programmable divider, DIV1, value and DIV1 reset bit. DIV1 can divide the feedback clock input to the PCM or can be bypassed. Valid only in PLL mode. Divider 2 Programming. Programmable divider, DIV2, value and DIV2 reset bit. DIV2 can divide the output of the tapped delay line or can be bypassed and is only valid for the ExpressCLK output. ow DLL 2x Duty-Cycle Programming. DLL mode clock doubler (2x) duty-cycle selection. DLL 1x Duty-Cycle Programming. Depending on the settings in other registers, this regis- ter is for: a. PLL mode phase/delay selection; b. DLL mode 1x duty cycle selection; and c. DLL mode programmable delay. Mode Programming. DLL/PLL mode selection, DLL 1x/2x clock selection, phase detector feedback selection. Clock Source Status/Output Clock Selection Programming. Input clock selection, feed- back clock selection, ExpressCLK output source selection, system clock output source selec- tion. PCM Control Programming. PCM power, reset, and configuration control. Lucent Technologies Inc. 73ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Clock Manager (PCM) (continued) EXPRESSCLK PAD FROM ROUTING REGISTER 7 REGISTER 6 REGISTER 5 REGISTER 4 3 REGISTER 2 REGISTER 1 REGISTER 0 FPGA-PCM INTERFACE DATA_INI7:0] ADDR_IN[2:0] DATA_OUTI7:0] WE RE LOCK CHARGE PUMP AND LOW-PASS FILTER COMBINATORIAL LOGIC PHASE DETECTOR FEEDBACK CLOCK EXPRESSCLK PROGRAMMABLE FEEDBACK DIVIDER FROM bivt ROUTING EXPRESSCLK OUTPUT DIVIDER DiIVv2 SYSTEM CLOCK OUTPUT 5-5829(F) Figure 46. PCM Functional Block Diagram 74 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) Delay-Locked Loop (DLL) Mode DLL mode is used for implementing a delayed clock (phase adjustment), clock doubling, and duty cycle adjustment. All DLL functions stem from a delay line with 32 taps. The delayed input clock is pulled from var- ious taps and processed to implement the desired result. There is no feedback clock in DLL mode, provid- ing a very stable output and a fast lock time for the out- put clock. DLL mode is selected by setting bit 0 in PCM register five to a 0. The settings for the various submodes of DLL mode are described in the following paragraphs. Divider DIVO may be used with any of the DLL modes to divide the input clock by an integer factor of 1 to 8 prior to implementation of the DLL process. Delayed Clock A delayed version of the input clock can be constructed in DLL mode. The output clock can be delayed by increments of 1/32 of the input clock period. Express CLK and system CLK outputs in delay modes are selected by setting register six, bits [5:4] to 10 or 11 for ExpressCLK output, and/or bits [7:6] to 10 for system clock output. The delay value is entered in register four. See register four programming details for more infor- mation. Delay values are also shown in the second col- umn of Table 27. Note that when register six, bits [5:4] are set to 11, the ExpressCLK output is divided by an integer factor from 1 to 8 while the system clock cannot be divided. The ExpressCLK divider is provided so that the I/O clocking provided by the ExpressCLK can operate slower than the internal system clock. This allows for very fast inter- nal processing while maintaining slower interface speeds off-chip for improved noise and power perfor- mance or to interoperate with slower devices in the sys- tem. The divisor of the ExpressCLK frequency is selected in register two. See the register two program- ming details for more information. Lucent Technologies Inc. 1x Clock Duty-Cycle Adjustment A duty-cycle adjusted replica of the input clock can be constructed in DLL mode. The duty cycle can be adjusted in 1/32 (3.125%) increments of the input clock period. DLL 1x clock mode is selected by setting bit 4 of register five to a 1, and output clock source selection is selected by setting register six, bits [5:4] to 01 for ExpressCLK output, and/or bits [7:6] to 01 for system clock output. The duty-cycle percentage value is entered in register four. See register four programming details for more information. Duty cycle values are also shown in the third column of Table 27. Table 27. DLL Mode Delay/1x Duty Cycle Programming Values Register 4 [7:0] Delay Duty Cycle 76543210 (CLK_IN/32) | (% of CLK_IN) OOXXX000 1 3.125 OOXXX001 2 6.250 OOXXX010 3 9.375 OOXXX011 4 12.500 OOXXX100 5 15.625 OOXXX101 6 18.750 OOXXX110 7 21.875 OOXXX111 8 25.000 01XXX000 9 28.125 01XXX001 10 31.250 01XXX010 11 34.375 01XXX011 12 37.500 01XXX100 13 40.625 Oi1XXX101 14 43.750 01XXX110 15 46.875 01111XXX 16 50.000 10000XXX 17 53.125 10001XXX 18 56.250 10010XXX 19 59.375 10011XXX 20 62.500 10100XXX 21 65.625 10101XXX 22 68.750 10110XXX 23 71.875 10111XXX 24 75.000 11000XXX 25 78.125 11001XXX 26 81.250 11010XXX 27 84.375 11011XXX 28 87.500 11100XXX 29 90.625 11101XXX 30 93.750 11110XXX 31 96.875 75ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Clock Manager (PCM) (continued) 2x Clock Duty-Cycle Adjustment A doubled-frequency, duty-cycle adjusted version of the input clock can be constructed in DLL mode. The first clock cycle of the 2x clock output occurs when the input clock is high, and the second cycle occurs when the input clock is low. The duty cycle can be adjusted in 1/32 (6.25%) increments of the input clock period. Additionally, each of the two doubled-clock cycles that occurs in a single input clock cycle may be adjusted to have different duty cycles. DLL 2x clock mode is selected by setting bit 4 of register five to a 1, and by setting register six, bits [5:4] to 01 for ExpressCLK out- put, and/or bits [7:6] to 01 for system clock output. The duty-cycle percentage value is entered in register three. See register three programming details for more information. Duty-cycle values where both cycles of the doubled clock have the same duty cycle are also shown in Table 28. Table 28. DLL Mode Delay/2x Duty Cycle Programming Values Register 3 [7:0] Duty Cycle 76543210 (%) 00000000 6.25 00001001 12.50 00010010 18.75 00011011 25.00 00100100 31.25 00101101 37.50 00110110 43.75 00111111 50.00 11000000 56.25 11001001 62.50 11010010 68.75 11011011 75.00 11100100 81.25 11101101 87.50 11110110 93.75 Phase-Locked Loop (PLL) Mode The PLL mode of the PCM is used for clock multiplica- tion (1/8x to 64x) and clock delay minimization func- tions. PLL functions make use of the PCM dividers and use feedback signals, often from the FPGA array. The use of feedback is discussed with each PLL submode. PLL mode is selected by setting bit 0 of register five to 1. 76 Clock Delay Minimization PLL mode can be used to minimize the effects of the input buffer and input routing delay on the clock signal. PLL mode causes a feedback clock signal to align in phase with the input clock (refer back to the block dia- gram in Figure 45) so that the delay between them is effectively eliminated. There is a dedicated feedback path from an adjacent middle CLKCNTRL block to the PCM. Using the corner ExpressCLK pad as the input to the PCM and using this dedicated feedback path, the clock from the Express- CLK output of the PCM, as viewed at the CLKCNTRL block, will be phase-aligned with the ExpressCLK input to the PCM. These relationships are diagrammed i in Figure 47. A feedback clock can also be input to the PCM from general routing. This allows for compensating for delay between the PCM input and a point in the general rout- ing. The use of this routed-feedback path is not gener- ally recommended. Because compensation is based on the programmable routing, the amount of clock delay compensation can vary between FPGA lots and fabrication processes, and will vary each time that the feedback line is routed using different resources. Con- tact Lucent Technologies for application notes regard- ing the use of routed-feedback delay compensation. DELAY jcourensaron EQUALS DELAY EXPRESSCLK sf a | ; |} Lot | ecieeumet OUTPUT WITHOUT LJ! LJ | USING PCM DELAY IS COMPENSATED GLKCNTRL EXPRESSCLK LP LI-L. OUTPUT USING PCM 5-5SBQ(F) Figure 47. ExpressCLK Delay Minimization Using the PCM Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Ciock Manager (PCM) (continued) Clock Multiplication An output clock that is a multiple (not necessarily an integer multiple) of the input clock can be generated in PLL mode. The multiplication ratio is programmed in the division registers DIVO, DIV1, and DIV2. Note that DIV2 applies only to the ExpressCLK output of the PCM and any reference to DiV2 is implicitly 1 for the system clock output of the PCM. The clock multiplica- tion formulas when using ExpressCLK feedback are: DIV1 FeExpressCLK_OUT = FINPUT_CLOCK * DIVO FSYSTEM_CLOCK_OUT = FExpressCLK_OUT DIV2 Where the values of DIVO, DIV1, and DIV2 range from 1 to 8. The ExpressCLK multiplication range of output clock frequencies is, therefore, from 1/8x up to 8x, with the system clock range up to 8x the ExpressCLK frequency or 64x the input clock frequency. If system clock feed- back is used, the formulas are: DIV1 FSYSTEM_CLOCK_OUT = FINPUT_CLOCK DIvo FExpressCLK_OUT = FSYSTEM_CLOCK/DIV2 The divider values, DIVO, DIV1, and DIV2 are pro- grammed in registers zero, one, and two, respectively. Lucent Technologies Inc. The multiplied output is selected by setting register six, bits [5:4] to 10 or 11 for ExpressCLK output and/or bits [7:6] to 10 for system clock output. Note that when reg- ister six, bits [5:4] are set to 11, the ExpressCLK output is divided by DIV2, while the system clock cannot be divided. The ExpressCLK divider is provided so that the /O clocking provided by the ExpressCLK can operate slower than the internal system clock. This allows for very fast internal processing while maintaining slower interface speeds off-chip for improved noise and power performance or to interoperate with slower devices in the system. It is also necessary to configure the internal PCM oscil- lator for operation in the proper frequency range. Table 29 and Table 30 show the settings required for register four for a given frequency range for Series 3C and 3T devices. In addition, the acquisition time is shown for each frequency range. This is the time that is required for the PCM to acquire LOCK. The PCM oscil- lator frequency range is chosen based on the desired output frequency at the system clock output. If using the ExpressCLK output, the equivalent system clock frequency can be selected by multiplying the expected ExpressCLK output frequency by the value for DIV2. Choose the nominal frequency from the table that is closest to the desired frequency, and use that value to program register four. Minor adjustments to match the exact input frequency are then performed automatically by the PCM. 77ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Clock Manager (PCM) (continued) Table 29. PCM Oscillator Frequency Range 3Txxx Table 30. PCM Oscillator Frequency Range 3Cxx System System Clock Clock Output Output Frequency T Frequency T Register 4) Min (MHz) Max | Acquisition| | Register 4} Min (MHz) Max | Acquisition 76543210 | (MHz) NOM (MHz) (us) 76543210 | (MHz)| NOM (MHz) (Hs) OOXXX010 | 17.00 58.50 | 100.00 36.00 OOXXX010] 10.50; 73.00 | 135.00 36.00 OOXXX011 | 16.10 52.50 89.00 37.00 0OXXX011 | 10.00 68.00 | 126.00 37.00 OOXXX100 | 15.17 49.00 82.80 38.00 0OXXX100| 9.50 63.00 117.00 38.00 OOXXX101 | 14.25 45.00 76.50 39.00 OOXXX101] 9.10 58.50 | 108.00 39.00 0OXXX110 | 13.33 41.50 70.30 40.00 OOXXX110} 8.60 53.80 99.00 40.00 OOXXX111 | 12.40 38.00 64.00 41.00 OOXXX111| 8.10 49.00 90.00 41.00 01XXX000 | 12.20 36.75 61.30 43.75 01XXX000| 7.80 47.70 87.50 43.80 01XXX001 | 12.10 35.00 58.00 46.50 O1XXX001| 7.60 46.30 85.00 46.50 01XXX010 | 11.90 33.00 54.30 49.25 01XXX010] 7.30 45.00 82.50 49.30 01XXX011 | 11.70 31.30 51.00 52.00 01XXX011| 7.10 43.60 80.00 52.00 01XXX100 | 11.10 30.00 49.40 54.75 01XXX100| 6.80 42.10 77.50 55.00 01XXX101 | 10.50 29.15 47.80 57.50 01XXX101| 6.50 40.75 75.00 57.50 01XXX110 | 10.00 28.10 46.20 60.25 01XXX110} 6.30 39.40 72.50 60.30 01XXX111 |} 9.40 27.00 44.60 63.00 01XXX111| 6.00 38.00 70.00 63.00 10000XXX | 9.20 26.25 43.30 65.40 10000XXX} 5.90 37.40 68.80 65.40 10001XXX | 9.00 25.65 42.30 67.80 10001XXX} 5.90 36.70 67.50 67.80 10010XXX | 8.80 25.00 41.30 70.10 10010XXX} 5.80 36.00 66.30 70.10 10011XXX | 8.60 24.45 40.30 72.50 10011XXX| 5.80 35.40 65.00 72.50 10100XXX | 8.40 23.70 39.00 74.90 10100XXXj 5.70 35.00 63.80 74.90 10101XXX | 8.10 22.90 37.70 77.30 10101XXX| 5.60 34.10 62.50 77.30 10110XXX | 7.90 22.20 36.50 79.60 10110XXX/| 5.60 33.50 61.30 79.60 10111XXX | 7.70 21.50 35.20 82.00 10111XXX} 5.50 32.80 60.00 82.00 11000XXX | 7.60 20.80 34.00 84.30 11000XXX| 5.40 32.10 58.80 84.30 11001XXX | 7.45 20.10 32.80 86.50 11001XXX| 5.40 31.50 57.50 86.50 11010XXX | 7.30 19.45 31.60 88.80 11010XXX| 5.30 30.70 56.30 88.80 11011XXX | 7.20 18.85 30.50 91.00 11011XXX} 5.30 30.10 55.00 91.00 11100XXX |} 6.60 18.30 30.00 93.30 11100XXX} 5.20 29.50 53.80 93.30 11101XXX | 6.00 17.70 29.40 95.50 11101XXXj} 5.10 28.80 52.50 95.50 19140XXX | 5.50 17.10 28.60 97.80 11110XXX} 5.10 28.20 51.30 97.80 11111XXX | 5.00 16.50 28.00 100.00 11114XXX | 5.00 27.50 50.00 100.00 Note: Use of settings in the first three rows is not recommended. X means dont care. 78 Note: Use of settings in the first three rows is not recommended. X means don't care. Lucent Technologies Inc.Data Sheet June 19899 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) PCM/FPGA Internal Interface Writing and reading the PCM registers is done through a simple asynchronous interface that connects with the FPGA routing resources. Reads from the PCM by the FPGA logic are accomplished by setting up the 3-bit address, A[2:0], and then applying an active-high read enable (RE) pulse. The read data will be available as long as RE is held high. The address may be changed while RE is high, to read other addresses. When RE goes low, the data output bus is 3-stated. Writes to the PCM by the FPGA logic are performed by applying the write data to the data input bus of the PCM, applying the 3-bit address to write to, and assert- ing the write enable (WE) signal high. Data will be writ- ten by the high-going transition of the WE pulse. The read enabie (RE) and write enable (WE) signals may not be active at the same time. For detailed timing information and specifications, see the Timing Charac- teristics section of this data sheet. The LOCK signal output from the PCM to the FPGA routing indicates a stable output clock signal from the PCM. The LOCK signal is high when the PCM output clock parameters fall within the programmed values and the PCM specifications for jitter. Due to phase cor- rections that occur internal to the PCM, the LOCK sig- nal might occasionally pulse low when the output clock is out of specification for only one or two clock cycles (high jitter due to temperature, voltage fluctuation, etc.) To accommodate these pulses, it is suggested that the user integrate the LOCK signal over a period suitable to their application to achieve the desired usage of the LOCK signal. The LOCK signal will also pulse high and low during the acquisition time as the output clock stabilizes. True LOCK is only achieved when the LOCK signal is a solid high. Again, it is suggested that the user integrate the LOCK signal over a time period suitable to the subject application. Lucent Technologies Inc. PCM Operation Several features are available for the control of the PCMs overall operation. The PCM may be programma- bly enabled/disabled via bit 0 of register 7. When dis- abled, the analog power supply of the PCM is turned off, conserving power and eliminating the possibility of inducing noise into the system power buses. Individual bits (register 7, bits [2:1]) are provided to reset the DLL and PLL functions of the PCM. These resets affect only the logic generating the DLL or PLL function; they do not reset the divider values (DIVO, DIV1, DIV2) or reg- isters [7:0]. The global set/reset (GSRN) is also pro- grammably controlled via register 7, bit 7. If register 7, bit 7 is set to 1, GSRN will have no effect on the PCM logic, allowing the clock to operate during a global set/reset. This function allows the FPGA to be reset without affecting a clock that is sent off-chip and used elsewhere in the system. Bit 6 of register 7 affects the functionality of the PCM during configuration. If set to 1, this bit enables the PCM to operate during configura- tion, after the PCM has been configured. The PCM functionality is programmed via the bit stream. If regis- ter 7, bit 6 is 0, the PCM cannot function and its power supply is disabled until after the configuration DONE signal goes high. When the PCM is powered up via register 7, bit 0, there is a wake-up time associated with its operation. Follow- ing the wake-up time, the PCM will begin to fully func- tion, and, following an acquisition time during which the output clock may be unstable, the PCM will be in steady-state operation. There is also a shutdown time associated with powering off the PCM. The output clock will be unstable during this period. Waveforms and timing parameters can be found in the Timing Characteristics section of this data sheet. 79Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Programmable Clock Manager (PCM) (continued) PCM Detailed Programming Descriptions of bit fields and individual control bits in the PCM control registers are provided in Table 31. Refer to Figure 46 for more information on the location of the PCM elements that are discussed. In the following discussion, the duty cycle is in the percentage of the clock period where the clock is high. Table 31. PCM Control Registers Bit # Function Register 0ODivider 0 Programming Bits [3:0] 4-Bit Divider, DIVO, Value. This value enables the input clock to immediately be divided by a value from 1 to 8. A 0 value (the default) indicates that DIVO is bypassed (no division). Bypass incurs less delay than dividing by 1. Hexadecimal values greater than 8 for bits [3:0] yield their modulo 8 value. For example, if bits [8:0] are 1001 (9 hex), the result is divide by 1 (remainder 9/8 = 1). Bits [6:4] Reserved. Bit 7 DIV 0 Reset Bit. DIVO may not be reset by GSRN depending on the value of register 7, bit 7. This bit may be set to 1 to reset DIVO to its default value. Bit 0 must be set to 0 (the default) to remove the reset. Register 1Divider 1 Programming Bits [3:0] 4-Bit Divider, DIV1, Value. This value enables the feedback clock to be divided by a value from 1 to 8. A 0 value (the default) indicates that DIV1 is bypassed (no division). Bypass incurs less delay than dividing by 1. Hexadecimal values greater than 8 for bits [3:0] yield their modulo 8 value. For example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder 9/8 = 1). Bits [6:4] Reserved. Bit 7 DIV1 Reset Bit. DIV1 may not be reset by GSRN, depending on the value of register 7, bit 7. This bit may be set to 1 to reset DIV1 to its default value. Bit O must be set to O (the default) to remove the reset. Register 2Divider 2 Programming Bits [3:0] 4-Bit Divider, DIV2, Value. This value enables the tapped delay line output clock driven onto ExpressCLK to be divided by a value from 1 to 8. A 0 value (the default) indicates that DIV2 is bypassed (no division). Bypass incurs less delay than dividing by 1. Hexadecimal values greater than 8 for bits [3:0] yield their modulo 8 value. For example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder 9/8 = 1). Bits [6:4] Reserved. Bit 7 DiV2 Reset Bit. DIV2 may not be reset by GSRN, depending on the value of register 7, bit 7. This bit may be set to 1 to reset DIV2 to its default value. Bit 7 must be set to 0 (the default) to remove the reset. Register 3DLL 2x Duty-Cycle Programming Bits [2:0] Duty-cycle selection for the doubled clock period associated with the input clock high. The duty cycle is (value of bit 6) * 50% + ((value of bits [2:0]) + 1) * 6.25%. See the description for bit 6. Bits [5:3] Duty-cycle selection for the doubled clock period associated with the input clock low. The duty cycle is (value of bit 7) * 50% + ((value of bits [2:0]) + 1) * 6.25%. See the description for bit 7. Bit 6 Master duty-cycle control for the first clock period of the doubled clock: 0 = less than or equal to 50%, 1 = greater than 50%. Bit 7 Master duty-cycle control for the second clock period of the doubled clock: 0 = less than or equal to 50%, 1 = greater than 50%. Example: Both clock periods having a 62.5% duty cycle, bits [7:0] are 11 001 001. 80 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) Table 31. PCM Control! Registers (continued) Bit # Function Register 4DLL 1x Duty-Cycle Programming Bits [2:0] Duty-Cycle/Delay Selection for Duty Cycle/Delays Less Than or Equal to 50%. The duty- cycle/delay is (value of bits [7:6]) * 25% + ((value of bits [2:0]) + 1) * 3.125%. See the description for bits [7:6]. Bits [5:3] Duty-Cycle/Delay Selection for Duty Cycle/Delays Greater Than 50%. The duty-cycle/delay is (value of bits [7:6]) * 25% + ((value of bits [5:3]) + 1) * 3.125%. See the description for bits [7:6]. Bits [7:6] Master Duty Cycle Control: 00: duty cycle 3.125% to 25% 01: duty cycle 28.125% to 50% 10: duty cycle 53.125% to 75% 11: duty cycle 78.125% to 96.875% Example: A 40.625% duty cycle, bits [7:0] are 01 XXX 100, where X is a don't care because the duty cycle is not greater than 50%. Example: The PCM output clock should be delayed 96.875% (31/32) of the input clock period. Bits [7:0] are 11110XXX, which is 78.125% from bits [7:6] and 18.75% from bits [5:3]. Bits [2:0] are dont care (X) because the delay is greater than 50%. Register 5Mode Programming Bit O DLL/PLL Mode Selection Bit. 0 = DLL, 1 = PLL. Default is DLL mode. Bit 1 Reserved. Bit 2 PLL Phase Detector Feedback Input Selection Bit. 0 = feedback signal from routing/ ExpressCLK, 1 = feedback from programmable delay line output. Default is 0. Has no effect in DLL mode. Bit 3 Reserved. Bit 4 1x/2x Clock Selection Bit for DLL Mode. 0 = 1x clock output, 1 = 2x clock output. Default is 1x clock output. Has no effect in PLL mode. Bits [7:5] Reserved. Lucent Technologies Inc. 81Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Programmable Clock Manager (PCM) (continued) Table 31. PCM Control Registers (continued) Bit # Function Bits [5:4] | ExpressCLK Output Source Selector. Default is 00. 00: PCM input clock, bypass path through PCM 01: DLL output 10: tapped delay line output 11: divided (DIV2) delay line output Bits [7:6] System Clock Output Source Selector. Default is 00. 00: PCM input clock, bypass path through PCM 01: DLL output . 10: tapped delay line output 11: reserved Register 7PCM Control Programming Bit 0 PCM Analog Power Supply Switch. 1 = power supply on, 0 = power supply off. Bit 1 PCM Reset. A value of 1 resets all PCM logic for PLL and DLL modes. Bit 2 DLL Reset. A value of 1 resets the clock generation logic for DLL mode. No dividers or user reg- isters are affected. Bits [5:3] Reserved. Bit 6 PCM Configuration Operation Enable Bit. 0 = normal configuration operation. During configu- ration (DONE = 0), the PCM analog power supply will be off, the PCM output data bus is 3-stated, and the LOCK signal is asserted to logic 0. The PCM will power up when DONE = 1. 1 = PCM operation during configuration. The PCM may be powered up (see bit 0) and begin operation, or continue operation. The setup of the PCM can be performed via the configuration bit stream. Bit 7 PCM GSRN Enable Bit. 0 = normal GSRN operation. 1 = GSRN has no effect on PCM logic, so clock processing will not be interrupted by a chip reset. Default is 0. 82 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) PCM Applications The applications discussed below are only a small sampling of the possible uses for the PCM. Check the Lucent Technologies ORCA FPGA Internet website (listed at the end of this data sheet) for additional appli- cation notes. Clock Phase Adjustment The PCM may be used to adjust the phase of the input clock. The result is an output clock which has its active edge either preceding or following the active edge of the input clock. Clock phase adjustment is accom- plished in DLL mode by delaying the clock. This is dis- cussed in the Delay-Locked Loop (DLL) Mode section. Examples of using the delayed clock as an early or late phase-adjusted clock are outlined in the following para- graphs. An output clock that precedes the input clock can be used to compensate for clock delay that is largely due to excessive loading. The preceding output clock is really not early relative to the input clock, but is delayed b DLL DELAY > almost a full cycle. This is shown in Figure 48A. The amount of delay that is being compensated for, plus clock setup time and some margin, is the amount less than one full clock cycle that the output clock is delayed from the input clock. In some systems, it is desirable to operate logic from several clocks that operate at different phases. This technique is often used in microprocessor-based sys- tems to transfer and process data synchronously between functional areas, but without incurring exces- sive delays. Figure 48B shows an input clock and an output clock operating 180 out of phase. !t also shows a version of the input clock that was shifted approxi- mately 180 using logic gates to create an inverter. Note that the inverted clock is really shifted more than 180 due to the propagation delay of the inverter. The PCM output clock does not suffer from this delay. Addi- tionally, the 180 shifted PCM output could be shifted by some smaller amount to effect an early 180 shifted clock that also accounts for loading effects. In terms of degrees of phase shift, the phase of a clock is adjustable in DLL mode with resolution relative to the delay increment (see Table 27): Phase Adjustment = (Delay)* 11.25, Phase Adjustment = ((Delay)* 11.25) 360, Delay < 16 Delay > 16 Iq. CLOCK DELAY AND SETUP 7 BEING COMPENSATED INPUT CLOCK | | | | OUTPUT CLOCK | | | | | | | A. Generating an Early Clock UNINTENDED PHASE SHIFT DUE TO _ r INVERTER DELAY rT DLL DELAY INPUT CLOCK | | | | | PCM OUTPUT CLOCK | | | | | | | INVERTED INPUT CLOCK | | | | | | B. Multiphase Clock Generation Using the DLL 5-5979(F) Figure 48. Clock Phase Adjustment Using the PCM Lucent Technologies Inc. 83ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Programmable Clock Manager (PCM) (continued) High-Speed Internal Processing with Slow /Os The PCM PLL mode provides two outputs, one sent to the global system clock routing of the FPGA and the other to the ExpressCLK(s) that serve the FPGA I/Os. The ExpressCLK output of the PCM has a divide capa- bility (DIV2) that the system clock output does not. This feature allows an input clock to be multiplied up to a higher frequency for high-speed internal processing, and also allows the ExpressCLK output to be divided down to a lower frequency to accommodate off-FPGA data transfers. For example, a 10 MHz input clock may be multiplied (see Clock Multiplication in the Phase- Locked Loop (PLL) Mode subsection) to 25 MHz (DIVO = 4, DIV1 = 5, DIV2 = 2) and output to the FPGA ExpressCLK. This allows the I/Os of the circuit to run at 25 MHz ((2 * 5)/4 * 10 MHz). The system clock will run at DIV2 times the ExpressCLK rate, which is 2 times 25 MHz, or 50 MHz. This setup allows for internal pro- cessing to occur at twice the rate of on/off device 1/O transfers. PCM Cautions Cautions do apply when using the PCM. There are a number of configurations that are possible in the PCM that are theoretically valid, but may not produce viable results. This section describes some of those situa- tions, and should leave the user with an understanding of the types of pitfalls that must be avoided when modi- fying clock signals. 84 Resultant signals from the PCM must meet the FPGA timing specifications. It is possible to specify pulses by using duty-cycle adjustments that are too narrow to function in the FPGA. For instance, if a 40 MHz clock is doubled to 80 MHz and a 6.25% duty cycle is selected, the result will be a 780 ps pulse that repeats every 12.5 ns. This pulse falls outside of the clock pulse width specification and is not valid. Using divider DIV2, it is possible to specify a clock mul- tiplication factor of 64 between the input clock and the output system clock. As mentioned above, the resultant frequency must meet all FPGA timing specifications. The input clock must also meet the minimum specifica- tions. An input clock rate that is below the PCM clock minimum cannot be used even if the multiplied output is within the allowable range. The use of the PCM to tweak a clock signal to eliminate a particular problem, such as a single setup time viola- tion, is discouraged. A small shift in delay, duty cycle, or phase to correct a single-point problem is in essence an asynchronous patch to a synchronous system, mak- ing the system less stable. This type of local problem, as opposed to a global clock contro! issue like device- wide clock delay, can usually be eliminated through more robust design practices. If this type of change is made, the designer must be aware that depending on the extent of the change made, the design may fail to operate correctly in a different speed grade or voltage grade (e.g., 3C vs. 37), or even in a different production lot of the same device. Divider DIV2 is available in DLL mode for the Express- CLK output, but its use is not recommended with duty- cycle adjusted clocks. Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs FPGA States of Operation Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configura- tion, and start-up. Figure 49 outlines these three FPGA states. POWERUP POWER-ON TIME DELAY t INITIALIZATION wi - CLEAR CONFIGURATION _MEMORY __ ~ INIT LOW, HDC HIGH, LDC LOW CONFIGURATION M[3:0] MODE IS SELECTED ~ CONFIGURATION DATA FRAME WRITTEN - INIT HIGH, HDC HIGH, LDC LOW -DOUT ACTIVE START-UP - ACTIVE VO ~ RELEASE INTERNAL RESET ~ DONE GOES HIGH OPERATION 5-4529(F) Figure 49. FPGA States of Operation Lucent Technologies Inc. initialization Upon powerup, the device goes through an initialization process. First, an internal power-on-reset circuit is trig- gered when power is applied. When Vpp reaches the voltage at which portions of the FPGA begin to operate (2.5 V to 3 V for the OR3Cxx, 2.2 V to 2.7 V for the ORS3Txxx), the I/Os are configured based on the con- figuration mode, as determined by the mode select inputs M[2:0]. A time-out delay is initiated wnen Vpp reaches between 3.0 V and 4.0 V (OR3Cxx) or 2.7 V to 3.0 V (OR3Txxx) to allow the power supply voltage to stabilize. The INIT and DONE outputs are low. At pow- erup, if VDD does not rise from 2.0 V to VoD in less than 25 ms, the user should delay configuration by inputting a low into INIT, PRGM, or RESET until Vop is greater than the recommended minimum operating voltage (4.75 V for OR3Cxx commercial devices and 3.0 V for OR3Txxx devices). At the end of initialization, the default configuration option is that the configuration RAM is written to a low state. This prevents shorts prior to configuration. As a configuration option, after the first configuration (i.e., at reconfiguration), the user can reconfigure without clearing the internal configuration RAM first. The active-low, open-drain initialization signal INIT is released and must be pulled high by an external resis- tor when initialization is complete. To synchronize the configuration of multiple FPGAs, one or more INIT pins should be wire-ANDed. If INIT is held low by one or more FPGAs or an external device, the FPGA remains in the initialization state. INIT can be used to signal that the FPGAs are not yet initialized. After INIT goes high for two internal clock cycles, the mode lines (M[3:0]) are sampled, and the FPGA enters the configuration state. The high during configuration (HDC), low during config- uration (LDC), and DONE signals are active outputs in the FPGAs initialization and configuration states. HDC, LDC, and DONE can be used to provide control of external logic signals such as reset, bus enable, or PROM enable during configuration. For parallel master configuration modes, these signals provide PROM enable control and allow the data pins to be shared with user logic signals. 85ORCA Series 3C and 3T FPGAs Data Sheet June 1999 FPGA States of Operation (continued) If configuration has begun, an assertion of RESET or PRGM initiates an abort, returning the FPGA to the ini- tialization state. The PRGM and RESET pins must be pulled back high before the FPGA will enter the config- uration state. During the start-up and operating states, only the assertion of PRGM causes a reconfiguration. In the master configuration modes, the FPGA is the source of configuration clock (CCLK). In this mode, the initialization state is extended to ensure that, in daisy- chain operation, all daisy-chained slave devices are ready. Independent of differences in clock rates, master mode devices remain in the initialization state an addi- tional six internal clock cycles after INIT goes high. When configuration is initiated, a counter in the FPGA is set to 0 and begins to count configuration clock cycles applied to the FPGA. As each configuration data frame is supplied to the FPGA, it is internally assern- bled into data words. Each data word is loaded into the internal configuration memory. The configuration load- ing process is complete when the internal length count equals the loaded length count in the length count field, and the required end of configuration frame is written. All OR3Cxx I/Os operate as TTL inputs during configu- ration (OR3Txxx I/Os are CMOS-only). All I/Os that are not used during the configuration process are 3-stated with internal pull-ups. Warning: During configuration, all OR3Txxx inputs have internal pull-ups enabled. If these inputs are driven to 5V, they will draw substantial current (=5 ma). This is due to the fact that the inputs are pulled up to 3V. During configuration, the PIC and PLC latches/FFs are held set/reset and the internal BIDI buffers are 3- stated. The combinatorial logic begins to function as the FPGA is configured. Figure 50 shows the general waveform of the initialization, configuration, and start- up states. Configuration The ORCA Series FPGA functionality is determined by the state of internal configuration RAM. This configura- tion RAM can be loaded in a number of different modes. In these configuration modes, the FPGA can act as a master or a slave of other devices in the sys- tem. The decision as to which configuration mode to use is a system design issue. Configuration is dis- cussed in detail, including the configuration data format and the configuration modes used to load the configu- ration data in the FPGA, following a description of the start-up state. DONE user KXKXKXKKKKAXKAKKKAKA KAKA | INTERNAL RESET (gsm) | INITIALIZATION | | CONFIGURATION START-UP OPERATION NS 5-4482(F) Figure 50. Initialization/Configuration/Start-Up Waveforms 86 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs FPGA States of Operation (continued) Start-Up After configuration, the FPGA enters the start-up phase. This phase is the transition between the config- uration and operational states and begins when the number of CCLKs received after INIT goes high is equal to the value of the length count field in the configuration frame and when the end of configuration frame has been written. The system design issue in the start-up phase is to ensure the user I/Os become active without inadvertently activating devices in the system or caus- ing bus contention. A second system design concern is the timing of the release of global set/reset of the PLC latches/FFs. There are configuration options that control the relative timing of three events: DONE going high, release of the set/reset of internal FFs, and user I/Os becoming active. Figure 51 shows the start-up timing for ORCA FPGAs. The system designer determines the relative timing of the I/Os becoming active, DONE going high, and the release of the set/reset of internal FFs. In the ORCA Series FPGA, the three events can occur in any arbitrary sequence. This means that they can occur before or after each other, or they can occur simulta- neously. There are four main start-up modes: CCLK_NOSYNC, CCLK_SYNC, UCLK_NOSYNC, and UCLK_SYNC. The only difference between the modes starting with CCLK and those starting with UCLK is that for the UCLK modes, a user clock must be supplied to the start-up logic. The timing of start-up events is then based upon this user clock, rather than CCLK. The dif- ference between the SYNC and NOSYNC modes is that for SYNC mode, the timing of two of the start-up events, release of the set/reset of internal FFs, and the /Os becoming active is triggered by the rise of the external DONE pin followed by a variable number of ris- ing clock edges (either CCLK or UCLK). For the NOSYNC mode, the timing of these two events is based only on either CCLK or UCLK. Lucent Technologies Inc. DONE is an open-drain bidirectional pin that may include an optional (enabled by default) pull-up resistor to accommodate wired ANDing. The open-drain DONE signais from multiple FPGAs can be tied together (ANDed) with a pull-up (internal or external) and used as an active-high ready signal, an active-low PROM enable, or a reset to other portions of the system. When used in SYNC mode, these ANDed DONE pins can be used to synchronize the other two start-up events, since they can all be synchronized to the same external signal. This signal will not rise until all FPGAs release their DONE pins, allowing the signal to be pulled high. The default for ORCA is the CCLK_SYNC synchro- nized start-up mode where DONE is released on the first CCLK rising edge, C1 (see Figure 51). Since this is a synchronized start-up mode, the open-drain DONE signal can be held low externally to stop the occurrence of the other two start-up events. Once the DONE pin has been released and pulled up to a high level, the other two start-up events can be programmed individu- ally to either happen immediately or after up to four ris- ing edges of CCLK (Di, Di + 1, Di+ 2, Di+ 3, Di + 4). The default is for both events to happen immediately after DONE is released and pulled high. A commonly used design technique is to release DONE one or more clock cycles before allowing the I/O to become active. This allows other configuration devices, such as PROMs, to be disconnected using the DONE signal so that there is no bus contention when the /Os become active. In addition to controlling the FPGA during start-up, other start-up techniques that avoid contention include using isolation devices between the FPGA and other circuits in the system, reassigning I/O locations, and maintaining I/Os as 3- stated outputs until contentions are resolved. Each of these start-up options can be selected during bit stream generation in ORCA Foundry, using Advanced Options. For more information, please see the ORCA Foundry documentation. 87ORCA Series 3C and 3T FPGAs Data Sheet June 1999 FPGA States of Operation (continued) CCLK_NOSYNC Fi DONE Ci C2 C3 C4 vO T i T | ] | 27 C2 Cs t4 GSRN ] | | | ACTIVE Ci Cz C3 C4 CCLK_SYNC DONE IN k DONE C1, G2, C3, OR C4 F vO | 7 i Dil _Di+1 Di+2 Died Di+4 1 i 2 1 GSRN | i ACTIVE OF Di+7 Di+ 2 Dies Di+4 UCLK UCLK_NOSYNC F i DONE [ T cr [ui U2 U3 U4 vo { i Tt I L tT Ui U2 U3 4 GSRN | l ACTIVE ui U2 U3 4 UCLK_SYNC DONE IN ! DONE | C1 | U1, U2,U3, OR U4 F vO f t | l Di Diet Di+2 Di+3 Di+4 GSRN | ACTIVE Di] Diet Dit2 Di+3 UCLK PERIOD SYNCHRONIZATION UNCERTAINTY Note: F = finished, no more CLKs required. -2761(F) Figure 51. Start-Up Waveforms 88 Reconfiguration To reconfigure the FPGA when the device is operating in the system, a low pulse is input into PRGM. The con- figuration data in the FPGA is cleared, and the I/Os not used for configuration are 3-stated. The FPGA then samples the mode select inputs and begins reconfigu- ration. When reconfiguration is complete, DONE is released, allowing it to be pulled high. Partial Reconfiguration All ORCA device families have been designed to allow a partial reconfiguration of the FPGA at any time. This is done by setting a bit stream option in the previous configuration sequence that tells the FPGA to not reset all of the configuration RAM during a reconfiguration. Then only the configuration frames that are to be modi- fied need to be rewritten, thereby reducing the configu- ration time. Other bit stream options are also available that allow one portion of the FPGA to remain in operation while a partial reconfiguration is being done. If this is done, the user must be careful to not cause contention between the two configurations (the bit stream resident in the FPGA and the partial reconfiguration bit stream) as the second reconfiguration bit stream is being loaded. Other Configuration Options There are many other configuration options available to the user that can be set during bit stream generation in ORCA Foundry. These include options to enable boundary scan and/or the microprocessor interface (MPI) and/or the programmable clock manager (PCM), readback options, and options to control and use the internal oscillator after configuration. Other useful options that affect the next configuration (not the current configuration process) include options to disable the global set/reset during configuration, dis- able the 3-state of I/Os during configuration, and dis- able the reset of internal RAMs during configuration to allow for partial configurations (see above). For more information on how to set these and other configuration options, please see the ORCA Foundry documenta- tion. Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Configuration Data Format The ORCA Foundry Development System interfaces with front-end design entry tools and provides tools to produce a fully configured FPGA. This section dis- cusses using the ORCA Foundry Development System to generate configuration RAM data and then provides the details of the configuration frame format. The ORCA OR3Cxx and OR3Txxx Series FPGAs are bit stream compatible. Using ORCA Foundry to Generate Configuration RAM Data The configuration data bit stream defines the I/O func- tionality, logic, and interconnections within the FPGA. The bit stream is generated by the development sys- tem. The bit stream created by the bit stream genera- tion tool is a series of 1s and Os used to write the FPGA configuration RAM. It can be loaded into the FPGA using one of the configuration modes discussed later. In the bit stream generator, the designer selects options that affect the FPGAs functionality. Using the output of the bit stream generator, circuit_name.bit, the development system's download tool can load the configuration data into the ORCA series FPGA evalua- tion board from a PC or workstation. Alternatively, a user can program a PROM (such as a Serial ROM or a standard EPROM) and load the FPGA from the PROM. The development systems PROM programming tool produces a file in .mks or .exo for- mat. Lucent Technologies Inc. Configuration Data Frame Configuration data can be presented to the FPGA in two frame formats: autoincrement and explicit. A detailed description of the frame formats is shown in Figure 52, Figure 53, and Table 32. The two modes are similar except that autoincrement mode uses assumed address incrementation to reduce the bit stream size, and explicit mode requires an address for each data frame. in both cases, the header frame begins with a series of 1s and a preamble of 0010, followed by a 24-bit length count field representing the total number of configuration clocks needed to complete the loading of the FPGAs. Following the header frame is a mandatory !D frame. (Note that the ID frame was optional in the ORCA 2C and 2C/TxxA Series.) The ID frame contains data used to determine if the bit stream is being loaded to the correct type of ORCA FPGA (i.e., a bit stream generated for an OR3C55 is being sent to an OR3C55). Error checking is always enabled for Series 3 devices, through the use of an 8-bit checksum. One bit in the ID frame also selects between the autoincrement and explicit address modes for this load of the configuration data. A configuration data frame follows the ID frame. A data frame starts with a 01-start bit pair and ends with enough 1-stop bits to reach a byte boundary. If using autoincrement configuration mode, subsequent data frames can follow. If using explicit mode, one or more address frames must follow each data frame, telling the FPGA at what addresses the preceding data frame is to be stored (each data frame can be sent to multiple addresses). Following all data and address frames is the postam- ble. The format of the postamble is the same as an address frame with the highest possible address value with the checksum set to all ones. 89Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Configuration Data Format (continued) LZ Le oF ad CONFIGURATION DATA | CONFIGURATION DATA Le Le. 0010 O1 a 01 a a0 Ye A A. A J Vv a a Vv PREAMBLE LENGTH ID FRAME CONFIGURATION CONFIGURATION POSTAMBLE K COUNT -, DATA FRAME 1 DATA FRAME 2 Ww CONFIGURATION HEADER -5759(F) Figure 52. Serial Configuration Data FormatAutoincrement Mode L Le ad a CONFIGURATION DATA CONFIGURATION DATA LL Le. 0010 01 as 00 O1 va 00 00 Aw. JA. Ad... A. A. JS LENGTH i CONFIGURATION ADDRESS CONFIGURATION ADDRESS . PREAMBLE count = |D FRAME DATA FRAME 1 FRAME 1 DATA FRAME 2 FRAME2 POSTAMBLE a CONFIGURATION HEADER 5-S760(F) Figure 53. Serial Configuration Data FormatExplicit Mode Table 32. Configuration Frame Format and Contents 11110010 Preamble Header 24-bit Length Count | Configuration frame length. 11119111 Trailing header8 bits. 0104 1141 1141 1111 ID frame header. Configuration Mode 00 = autoincrement, 01 = explicit. ID Frame Reserved [41:0] Reserved bits set to 0. ID 20-bit part ID. Checksum 8-bit checksum. 41991911 Eight stop bits (high) to separate frames. 01 Data frame header. Configuration Data Bits Number of data bits depends upon device. eae Alignment Bits = 0 amng ot ha byt boundary stream to make frame header, plus data (repeated for each - - data frame) Checksum 8-bit checksum. 11111111 Eight stop bits (high) to separate frames. ; ; 00 Address frame header. Configuration 14 Address Bits 14-bit address of location to start data storage. Address - Frame Checksum 8-bit checksum. 14111111 Eight stop bits (high) to separate frames. 00 Postamble header. Postamble 499491191 1141111 Dummy address. 1449499191191111 16 stop bits.* * In MPI configuration mode, the number of stop bits = 32. Note: For slave parallel mode, the byte containing the preamble must be 11110010. The number of leading header dummy bits must be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where nis any positive integer. The number of stop bits/frame for slave parallel mode must be (x 8), where x is a positive integer. Note also that the bit stream generator tool supplies a bit stream that is compatible with all configuration modes, including slave parallel mode. 90 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Configuration Data Format (continued) The length and number of data frames and information on the PROM size for the Series 3 FPGAs are given in Table 33. Table 33. Configuration Frame Size Devices OR3T20 OR3T30 ORSC/TS5S OR3C/T80 ORST125 # of Frames 856 984 1240 1496 1880 Data Bits/Frame 202 232 292 352 442 Configuration Data (# of frames x # of data 172,912 228,288 362,080 526,592 830,960 bits/frame) Maximum Total # Bits/Frame (align bits, 01 224 256 312 376 464 frame start, 8-bit checksum, 8 stop bits) Maximum Configuration Data (# bits/frame 191,744 251,904 386,880 562,496 872,320 x # of frames) Maximum PROM Size (bits) 191,912 252,072 387,048 562,664 872,488 (add configuration header and postamble) Bit Stream Error Checking There are three different types of bit stream error checking performed in the ORCA Series 3 FPGAs: iD frame, frame alignment, and CRC checking. The ID data frame is sent to a dedicated location in the FPGA. This ID frame contains a unique code for the device for which it was generated. This device code is compared to the internal code of the FPGA. Any differences are flagged as an ID error. This frame is automatically created by the bit stream generation program in ORCA Foundry. Each data and address frame in the FPGA begins with a frame start pair of bits and ends with eight stop bits set to 1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame align- ment error. Error checking is also done on the FPGA for each frame by means of a checksum byte. If an error is found on eval- uation of the checksum byte, then a checksum/parity error is flagged. The checksum is the XOR of all the data bytes, from the start of frame up to and including the bytes before the checksum. It applies to the ID, address, and data frames. When any of the three possible errors occur, the FPGA is forced into an idie state, forcing INIT low. The FPGA will remain in this state until either the RESET or PRGM pins are asserted. If using either of the MPI modes to configure the FPGA, the specific type of bit stream error is written to one of the MPI registers by the FPGA configuration logic. The PGRM bit of the MPI control register can also be used to reset out of the error condition and restart configuration. Lucent Technologies Inc. 91ORCA Series 3C and 3T FPGAs Data Sheet June 1999 FPGA Configuration Modes There are eight methods for configuring the FPGA. Seven of the configuration modes are selected on the MO, M1, and M2 inputs. The eighth configuration mode is accessed through the boundary-scan interface. A fourth input, M3, is used to select the frequency of the internal oscillator, which is the source for CCLK in some configuration modes. The nominal frequencies of the internal oscillator are 1.25 MHz and 10 MHz. The 1.25 MHz frequency is selected when the M3 input is unconnected or driven to a high state. There are three basic FPGA configuration modes: master, slave, and peripheral. The configuration data can be transmitted to the FPGA serially or in parallel bytes. As a master, the FPGA provides the control sig- nals out to strobe data in. As a slave device, a clock is generated externally and provided into the CCLK input. In the three peripheral modes, the FPGA acts as a microprocessor peripheral. Table 34 lists the functions of the configuration mode pins. Note that two configura- tion modes previously available on the OR2Cxx and OR2C/TxxA devices (master parallel down and syn- chronous peripheral) have been removed for Series 3 devices. Table 34. Configuration Modes Configuration M2|M1| MO} CCLK de Data 0 | O | O j Output | Master Serial Serial Oo} O07}; 1 {Input Slave Parallel Parallel Oo| 1 0 | Output | Microprocessor: | Parailel Motorola* Pow- erPC 0 1 1 | Output | Microprocessor: j Parallel Intel i960 1 O | O | Output | Master Parallel Parallel 1 O | 1 | Output | Async Peripheral | Parallel 1 1] 0 Reserved 1 | 1] 1 [Input | Slave Serial | Serial * Motorola is a registered trademark of Motorola, Inc. 92 Master Parallel Mode The master parallel configuration mode is generally used to interface to industry-standard, byte-wide mem- ory, such as the 2764 and larger EPROMs. Figure 54 provides the connections for master parallel mode. The FPGA outputs an 18-bit address on A[17:0] to memory and reads 1 byte of configuration data onthe rising edge of RCLK. The parallel bytes are internally serial- ized starting with the least significant bit, DO. D[7:0] of the FPGA can be connected to D[7:0] of the micropro- cessor only if a standard prom file format is used. If a .bit or .rbt file is used from ORCA Foundry, then the user must mirror the bytes in the .bit or .rbt file OR leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the microprocessor. DOUTF-To DAsyY- , CHAINED AU17:0] f+ " Al17:0] CCLK + DEVICES D[?7:0] he D[7:0] ORCA EPROM SERIES == A pone CE PROGRAM ___->] PRGM Vo0 O-] M2 HOC Vop OR GND ~] M1 LOC Re oo MO RCLK Figure 54. Master Parallel Configuration Schematic In master parallel mode, the starting memory address is OOOO0 Hex, and the FPGA increments the address for each byte loaded. One master mode FPGA can interface to the memory and provide configuration data on DOUT to additional FPGAs in a daisy-chain. The configuration data on DOUT is provided synchronously with the falling edge of CCLK. The frequency of the CCLK output is eight times that of RCLK. Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes (continued) Master Serial Mode In the master serial mode, the FPGA loads the configu- ration data from an external serial ROM. The configura- tion data is either loaded automatically at start-up or on a PRGM command to reconfigure. The ATT1700A Series Serial PROMs can be used to configure the FPGA in the master serial mode. This provides a sim- ple 4-pin interface in a compact package. Configuration in the master serial mode can be done at powerup and/or upon a configure command. The sys- tem or the FPGA must activate the serial ROM's RESET/OE and CE inputs. At powerup, the FPGA and serial ROM each contain internal power-on reset cir- cuitry that allows the FPGA to be configured without the system providing an external signal. The power-on reset circuitry causes the serial ROM's internal address pointer to be reset. After powerup, the FPGA automati- cally enters its initialization phase. The serial ROM/FPGA interface used depends on such factors as the availability of a system reset pulse, avail- ability of an intelligent host to generate a configure command, whether a single serial ROM is used or mul- tiple serial ROMs are cascaded, whether the serial ROM contains a single or multiple configuration pro- grams, etc. Because of differing system requirements and capabilities, a single FPGA/serial ROM interface is generally not appropriate for all applications. | Data is read in the FPGA sequentially from the serial ROM. The DATA output from the serial ROM is con- nected directly into the DIN input of the FPGA. The CCLK output from the FPGA is connected to the CLK input of the seria! ROM. During the configuration pro- cess, CCLK clocks one data bit on each rising edge. Since the data and clock are direct connects, the FPGA/serial ROM design task is to use the system or FPGA to enable the RESET/OE and CE of the serial ROM(s). There are several methods for enabling the serial ROMs RESET/OE and CE inputs. The serial ROMs RESET/OE is programmable to function with RESET active-high and OE active-low or RESET active- low and OE active-high. In Figure 55, serial ROMs are cascaded to configure multiple daisy-chained FPGAs. The host generates a 500 ns low pulse into the FPGA's PRGM input. The FPGAs INIT input is connected to the serial ROMs RESET/OE input, which has been programmed to function with RESET active-low and OE active-high. The FPGA DONE is routed to the CE pin. The low on DONE enables the serial ROMs. At the completion of Lucent Technologies Inc. configuration, the high on the FPGA's DONE disables the serial ROM. Serial ROMs can also be cascaded to support the con- figuration of multiple FPGAs or to load a single FPGA when configuration data requirements exceed the capacity of a single serial ROM. After the last bit from the first serial ROM is read, the serial ROM outputs CEO low and 3-states the DATA output. The next serial ROM recognizes the low on CE input and outputs con- figuration data on the DATA output. After configuration is complete, the FPGAs DONE output into CE disables the serial ROMs. This FPGA/serial ROM interface is not used in applica- tions in which a serial ROM stores multiple configura- tion programs. In these applications, the next configuration program to be loaded is stored at the ROM location that follows the last address for the previ- ous configuration program. The reason the interface in Figure 55 will not work in this application is that the low output on the INIT signal would reset the serial ROM address pointer, causing the first configuration to be reloaded. In some applications, there can be contention on the FPGA's DIN pin. During configuration, DIN receives configuration data, and after configuration, it is a user V/O. If there is contention, an early DONE at start-up (selected in ORCA Foundry) may correct the problem. An alternative is to use LDC to drive the serial ROM's CE pin. In order to reduce noise, it is generally better to run the master serial configuration at 1.25 MHz (M3 pin tied high), rather than 10 MHz, if possible. TO DAISY- CHAINED DATA DIN DOUTT* DEVICES CLK CCLK ATT1700A CE b- DONE RESET/OE INT CEO ORCA tL____ SERIES DATA FPGA CLK ATT1700A PRGM CE p M2 RESET/OE Mi CEO Mo | = SERIAL ROR AL ROMs PROGRAM AS NEEDED PROGRAM -4456.1(F) Figure 55. Master Serial Configuration Schematic 93ORCA Series 3C and 3T FPGAs Data Sheet June 1999 FPGA Configuration Modes (continued) Asynchronous Peripheral Mode Figure 56 shows the connections needed for the asyn- chronous peripheral mode. In this mode, the FPGA system interface is similar to that of a microprocessor- peripheral interface. The microprocessor generates the control signals to write an 8-bit byte into the FPGA. The FPGA control inputs include active-low CSO and active- high CS1 chip selects and WR and RD inputs. The chip selects can be cycled or maintained at a static level during the configuration cycle. Each byte of data is writ- ten into the FPGAs D[7:0] input pins. D[7:0] of the FPGA can be connected to D[7:0] of the microproces- sor only if a standard prom file format is used. If a .bit or tht file is used from ORCA Foundry, then the user must mirror the bytes in the .bit or .rbt file OR leave the .bit or .tbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the microprocessor. The FPGA provides an RDY/BUSY status output to indi- cate that another byte can be loaded. A low on RDY/ BUSY indicates that the double-buffered hold/shift reg- isters are not ready to receive data, and this pin must be monitored to go high before another byte of data can be written. The shortest time RDY/BUSY is low occurs when a byte is loaded into the hold register and the shift register is empty, in which case the byte is immediately transferred to the shift register. The long- est time for RDY/BUSY to remain low occurs when a byte is loaded into the holding register and the shift register has just started shifting configuration data into configuration RAM. The RDY/BUSY status is also available on the D7 pin by enabling the chip selects, setting WR high, and apply- ing RD low, where the RD input provides an output enable for the D7 pin when RD is low. The D{6:0] pins are not enabled to drive when RD is low and, therefore, only act as input pins in asynchronous peripheral mode. Optionally, the user can ignore the RDY/BUSY status and simply wait until the maximum time it would take for the RDY/BUSY line to go high, indicating the FPGA is ready for more data, before writing the next data byte. 94 DOUT[-- TO DAISY- CHAINED > -] PRG CCLK + DEVICES > >) D170) RDY/BUSY INIT DONE MICRO- PROCESSOR | appress bedcso ORCA DECODE LOGIc| -slcs; SERIES FPGA BUS -CHRD | |CONTROLLER | aiwg Vop M2 HDC M1 MO LDC}. Figure 56. Asynchronous Peripheral Configuration Microprocessor Interface (MPI) Mode The built-in MPt in Series 3 FPGAs is designed for use in configuring the FPGA. Figure 57 and Figure 58 show the glueless interface for FPGA configuration and read- back from the PowerPC and i960 processors, respec- tively. When enabled by the mode pins, the MPI handles all configuration/readback control and hand- shaking with the host processor. For single FPGA con- figuration, the host sets the configuration control register PRGM bit to zero then back to a one and, after reading that the INIT signal is high in the MPI status register, transfers data 8 bits at a time to the FPGAs D[7:0] input pins. If configuring multiple FPGAs through daisy-chain operation is desired, the MP_DAISY bit must be set in the configuration contro! register of the MPI. Because of the latency involved in a daisy-chain configuration, the MP_HOLD_BUS bit may be set to zero rather than one for daisy-chain operation. This allows the MPI to acknowledge the data transfer before the configuration information has been serialized and transferred on the FPGA daisy-chain. The early acknowledgment frees the host processor to perform other system tasks. Con- figuring with the MP_HOLD_BUS bit at zero requires that the host microprocessor poll the RDY/BUSY bit of the MPI status register and/or use the MPI interrupt capability to confirm the readiness of the MP! for more configuration data. Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes (continued) There are two options for using the host interrupt request in configuration mode. The configuration con- trol register offers control bits to enable the interrupt on either a bit stream error or to notify the host processor when the FPGA is ready for more configuration data. The MPI status register may be used in conjunction with, or in place of, the interrupt request options. The status register contains a 2-bit field to indicate the bit stream error status. As previously mentioned, there is also a bit to indicate the MPIs readiness to receive another byte of configuration data. A flow chart of the MPI configuration process is shown in Figure 59. The MPI status and configuration register bit maps can be found in the Special Function Blocks section and MPI configuration timing information is available in the Tim- ing Characteristics section of this data sheet. Configuration readback can also be performed via the MPI when it is in user mode. The MPI is enabled in user mode by setting the MP_USER bit to 1 in the configura- tion control register prior to the start of configuration or through a configuration option. To perform readback, the host processor writes the 14-bit readback start address to the readback address registers and sets the RD_CFG bit to 0 in the configuration control register. Readback data is returned 8 bits at a time to the read- back data register and is valid when the DATA_RDY bit of the status register is 1. There is no error checking during readback. A flow chart of the MP! readback operation is shown in Figure 60. The RD_DATA pin used for dedicated FPGA readback is invalid during MPI readback. POWER ON WITH VALID M[3:0] y WRITE CONFIGURATION CONTROL REGISTER BITS TO DAISY- ne [> CHAINED 8, DEVICES D{7:0] a Df7:0] A{27:31] A[4:0] CLKOUT MPI_CLK RO/WR MPI_RW TA MPI_ACK ORCA Powerec 1A MACK SERIES 3 ot MP\_BI_ FPGA TROXx MPI_iRG Ts >| MPI_STRB A26 cso DONE /-> A25 csi INIT }> HDC > tC +> 5-5761(F) Note: FPGA shown as a memory-mapped peripheral using CSO and CS1. Other decoding schemes are possible using CSO and/or CS1. Figure 57. PowerPC/MPI Configuration Schematic i960 SYSTEM CLOCK 8 TO DAISY- ADI7:0] 74-> DI7:0] DOUT F-* CHAINED CLKIN MPI_CLK DEVICES wa MPL_RW RDYACV MPI_ACK XINTE MPLIRQ oa, weo 0 EE MPLALE _ SERIES 3 ADS MPLLSTRS FPGA BEO MPI_BEO BEI MPI_BE1 voo DONE [ | INIT [> cst HOC |-= 5 __ =F 5-5762(F) Note: FPGA shown as only system peripheral with fixed chip select signals. For multiperipheral systems, address decoding and/ or latching can be used to implement chip selects. Figure 58. i96Q/MPI Configuration Schematic Lucent Technologies Inc. Y READ STATUS REGISTER NO INIT = 1? READ STATUS REGISTER NO BIT STREAM ERROR? NO DATA_RDY = 1? YES WRITE DATA TO CONFIGURATION DATA REG 5-5763(F) Figure 59. Configuration Through MPI 95ORCA Series 3C and 3T FPGAs Data Sheet June 1999 FPGA Configuration Modes (continued) ENABLE MICROPROCESSOR INTERFACE IN USER MODE t SET READBACK ADDRESS y WRITE RD_CFG TO 0 IN CONTROL REGISTER 1 Y WRITE RD_CFG TO 11N CONTROL REGISTER 1 READ STATUS REGISTER DATA_RDY = 1? READ DATA REGISTER DATA = OxFF? READ DATA REGISTER DATA = OxFF? READ DATA REGISTER START OF FRAME FOUND? READ UNTIL END OF FRAME FINISHED READBACK? Figure 60. Readback Through MPI 96 5-5764(F) Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes (continued) Slave Serial Mode The slave serial mode is primarily used when multiple FPGAs are configured in a daisy-chain (see the Daisy- Chaining section). It is also used on the FPGA evalua- tion board that interfaces to the download cable. A device in the slave serial mode can be used as the lead device in a daisy-chain. Figure 61 shows the connec- tions for the slave serial configuration mode. The configuration data is provided into the FPGAs DIN input synchronous with the configuration clock CCLK input. After the FPGA has loaded its configuration data, it retransmits the incoming configuration data on DOUT. CCLK is routed into all slave serial mode devices in parallel. Multiple slave FPGAs can be loaded with identical con- figurations simultaneously. This is done by loading the configuration data into the DIN inputs in parallel. waa nem TO DAISY- CHAINED DOUT }- DEVICES INIT MICRO- ORCA PROCESSOR PAGM SERIES OR DOWNLOAD DONE CABLE CCLK DIN Vop = M1 MO (DG be Figure 61. Slave Serial Configuration Schematic y 5-4485(F) Lucent Technologies Inc. Slave Parallel Mode The slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins D[7:0] for each CCLK cycle. Due to 8 bits of data being input per CCLK cycle, the DOUT pin does not contain a valid bit stream for slave parallel mode. As a result, the lead device cannot be used in the slave parallel mode in a daisy-chain configuration. Figure 62 is a schematic of the connections for the slave parallel configuration mode. WR and CSO are active-low chip select signals, and CS1 is an active- high chip select signal. These chip selects allow the user to configure multiple FPGAs in slave parallel mode using an 8-bit data bus common to all of the FPGAs. These chip selects can then be used to select the FPGA(s) to be configured with a given bit stream. The chip selects must be active for each valid CCLK cycle until the device has been completely pro- grammed. They can be inactive between cycles but must meet the setup and hold times for each valid pos- itive CCLK. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ORCA Foundry, then the user must mirror the bytes in the .bit or .rbt file OR leave the -bit or .rbt file unchanged and connect D[7:0] of the FPGA to D{0:7] of the microprocessor. 8 Y D[7:0] DONE : cok eee MICRO- PROCESSOR leRam FPGA SYSTEM veo csi CSO WR M2 HDC rk M1 LOCH +| mo 5-4487(F) Figure 62. Slave Parallel Configuration Schematic 97ORCA Series 3C and 3T FPGAs Data Sheet June 1999 FPGA Configuration Modes (continued) Daisy-Chaining Multiple FPGAs can be configured by using a daisy- chain of the FPGAs. Daisy-chaining uses a lead FPGA and one or more FPGAs configured in slave serial mode. The lead FPGA can be configured in any mode except slave parallel mode. (Daisy-chaining is available with the boundary-scan ram_w instruction discussed later.) All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on positive CCLK and out on negative CCLK edges. An upstream FPGA that has received the preamble and length count outputs a high on DOUT until it has received the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After loading and retransmitting the preamble and length count to a daisy-chain of slave devices, the lead device loads its configuration data frames. The loading of configuration data continues after the lead device has received its configuration data if its internal frame bit counter has not reached the length count. When the configuration RAM is full and the num- ber of bits received is less than the length count field, the FPGA shifts any additional data out on DOUT. The configuration data is read into DIN of slave devices on the positive edge of CCLK, and shifted out DOUT on the negative edge of CCLK. Figure 63 shows the connections for loading multiple FPGAs in a daisy- chain configuration. The generation of CCLK for the daisy-chained devices that are in slave serial mode differs depending on the configuration mode of the lead device. A master paral- lel mode device uses its internal timing generator to produce an internal CCLK at eight times its memory address rate (RCLK). The asynchronous peripheral mode device outputs eight CCLKs for each write cycle. If the lead device is configured in slave mode, CCLK must be routed to the lead device and to all of the daisy-chained devices. LL CCLK CCLK CCLK A[17:0] jue ~ A[17:0] DOUT DIN DOUT DIN DOUT -. . ZL el pr. E IES ERIES 017:0} 7 0170) FPGA FPGA FPGA OE A. pone MASTER SLAVE #1 SLAVE #2 Voo cE DONE DONE z PRGM _ PRGM PREM { , Vi iNIT PROGRAM Voo o-|M2 woe e ne . vi M2 M2 HDC pp Mo RCLK Mo RCLK MO RCLK : 5-4488(F Figure 63. Daisy-Chain Configuration Schematic As seen in Figure 63, the INIT pins for all of the FPGAs are connected together. This is required to guarantee that powerup and initialization will work correctly. In general, the DONE pins for all of the FPGAs are also connected together as shown to guarantee that all of the FPGAs enter the start-up state simultaneously. This may not be required, depending upon the start-up sequence desired. 98 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs FPGA Configuration Modes (continued) Daisy-Chaining with Boundary Scan Multiple FPGAs can be configured through the JTAG ports by using a daisy-chain of the FPGAs. This daisy-chain- ing operation is available upon initial configuration after powerup, after a power-on reset, after pulling the program pin to reset the chip, or during a reconfiguration if the EN_JTAG RAM has been set. All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on the positive TCK and out on the negative TCK edges. An upstream FPGA that has received the preamble and length count outputs a high on TDO until it has received the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After load- ing and retransmitting the preamble and length count to a daisy-chain of downstream devices, the lead device loads its configuration data frames. The loading of configuration data continues after the lead device had received its configuration read into TDI of downstream devices on the positive edge of TCK, and shifted out TDO on the negative edge of TCK. Figure 63 shows the connections for loading multiple FPGAs in a JTAG daisy-chain configuration. Lucent Technologies Inc. 99Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. The ORCA Series FPGAs include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. Table 35. Absolute Maximum Ratings Parameter Symbol! Min Max Unit Storage Temperature Tstg 65 150 C Supply Voltage with Respect to Ground Vpp 0.5 7.0 Vv Input Signal with Respect to Ground 0.5 VDD + 0.3 Vv Signal Applied to High-impedance Output _ 0.5 VbbD + 0.3 Vv Maximum Package Body Temperature _ 220 C Recommended Operating Conditions Table 36. Recommended Operating Conditions OR3Cxx ORSTXxx Mode Temperature Supply Voltage Temperature Supply Voltage Range (Vop) Range (VoD) (Ambient) (Ambient) Commercial 0 C to 70 C 5V+5% 0C to 70C 3.0 V to 3.6 V Industrial 40 C to +85 C 5V+10% 40 C to +85 C 3.0 V to 3.6 V Note: The maximum recommended junction temperature (Ts) during operation is 125 C. 100 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Electrical Characteristics Table 37. Electrical Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, 40 C < TA < +85 C. OR3STxxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Sym- . OR3Cxx ORSTXxx . Parameter bol Test Conditions Unit Min Max Min Max input Voltage: Input configured as CMOS High VIH (includes OR3Txxx) 50% VDD | VOD +0.5| 50% VDD| VDD+0.5} V Low ViL GND - 0.5] 20% VDD | GND-0.5} 30% VoD Vv Input Voltage: OR3Txx 5 V Tolerant High VIH _ -_ 50% VDD 5.8V Vv Low VIL _ _ GND -0.5| 30% VoD V input Voltage: Input configured as TTL High VIK (not valid for OR3Txxx) 2.0 VoD +0.3 _ _ V Low Vit ~0.5 0.8 _ ~ Vv Output Voltage: High , VOH VbD = min, loH = 6 mMAor3 mA 2.4 2.4 _ Vv Low VoL | VoD =min, loL.=12mAor6mA _ 0.4 _ 0.4 V Input Leakage Current IL VDD = max, VIN = VSS or VDD -10 10 10 10 HA Standby Current: IDDSB OR3Cxx (TA = 25 C, ORST20 VDD = 5.0 V) _ _ _ 4.70 mA OR3T30 ORSTxx (TA = 25 C, _ _ _ 4.90 mA ORSC/T55 VoD = 3.3 V) 4.06 _ 5.30 mA OR3C/T80 internal oscillator running, no out- _ 4.56 _ 5.80 mA OR3T125 put loads, inputs VDD or GND _ _ _ 6.70 mA (after configuration) Standby Current: IpDsB OR3Cxx (TA = 25 C, OR3T20 VoD = 5.0 V) _ 3.52 mA OR3T30 OR3Txxx (TA = 25 C, _ _ 3.68 mA OR3C/T55 Vbp = 3.3 V) _ 3.05 3.98 mA OR3C/T80 internal oscillator stopped, no _ 3.42 _ 4.35 mA OR3T125 output loads, inputs VDD or GND _ ~~ _ 5.02 mA (after configuration) Powerup Current: Ipp Power supply current @ approxi- OR3T20 mately 1 V, within a recommended _ _ 1.2 _ mA OR3T30 power supply ramp rate of _ _ 1.6 _ mA ORSC/T55 1 ms200 ms 2 2.7 _ mA ORS3C/T80 5.4 _ 4.0 _ mA OR3T125 _ 6.5 _ mA Data Retention Voltage} Vor TA = 25 C 2.3 _ 2.3 V Input Capacitance CIN OR3Cxx (TA = 25 C, _ 9 _ 8 pF VbD = 5.0 V) OR3Txxx (TA = 25 C, VDD = 3.3 V) Test frequency = 1 MHz Output Capacitance Cout OR3Cxx (TA = 25 C, 9 _ 8 pF Vppb = 5.0 V) ORSTxxx (TA = 25 C, VbpD = 3.3 V) Test frequency = 1 MHz Lucent Technologies Inc. 101Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Electrical Characteristics (continued) Table 37. Electrical Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VoD = 3.0 V to 3.6 V, -40 C < TA < +85 C. _ ORSCxx OR3STxxx Parameter Symbol Test Conditions Unit Min Max Min Max DONE Pull-up RDONE _ 100 100 kQ Resistor M[3:0] Pull-up Rm _ 100 _ 100 _ kQ Resistors /O Pad Static Pull-up Ipu OR3Cxx (VoD = 5.25 V, 14.4 50.9 14.4 50.9 pA Current* VIN = Vss, TA = 0 C) ORS3Txxx (VDD = 3.6 V, VIN = Vss, TA = 0 C) 1/O Pad Static IPD OR3Cxx (VbD = 5.25 V, 26 103 26 103 pA Pull-down Current VIN = Vss, TA = 0 C) OR3Txxx (VDD = 3.6 V, VIN = VSS, TA = 0 C) VO Pad Pull-up RPu VbD = all, VIN = Vss, TA=0 C 100 100 _ kQ Resistor* VO Pad Pull-down Rep VDD = all, VIN = VDD, TA =0 C 50 _ 50 _ ko2 Resistor * On the OR3Tx devices, the pull-up resistor will externally pull the pin to a level 1.0 V below Vop. Note: For 3T devices driven to 5 V. 102 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics Description To define speed grades, the ORCA Series part number designation (see Ordering Information) uses a single- digit number to designate a speed grade. This number is not related to any single ac parameter. Higher num- bers indicate a faster set of timing parameters. The actual speed sorting is based on testing the delay ina path consisting of an input buffer, combinatorial delay through all PLCs in a row, and an output buffer. Other tests are then done to verify other delay parameters, such as routing delays, setup times to FFs, etc. The most accurate timing characteristics are reported by the timing analyzer in the ORCA Foundry Develop- ment System. A timing report provided by the develop- ment system after layout divides path delays into logic and routing delays. The timing analyzer can also pro- vide logic delays prior to layout. While this allows rout- ing budget estimates, there is wide variance in routing delays associated with different layouts. The logic timing parameters noted in the Electrical Characteristics section of this data sheet are the same as those in the design tools. In the PFU timing given in Table 41Table 48, symbol names are generally a concatenation of the PFU operating mode (as defined in Table 3) and the parameter type. The setup, hold, and propagation delay parameters, defined below, are designated in the symbol name by the SET, HLD, and DEL characters, respectively. The values given for the parameters are the same as those used during production testing and speed bin- ning of the devices. The junction temperature and sup- ply voltage used to characterize the devices are listed in the delay tables. Actual delays at nominal tempera- ture and voltage for best-case processes can be much better than the values given. It should be noted that the junction temperature used in the tables is generally 85 C. The junction temperature for the FPGA depends on the power dissipated by the device, the package thermal characteristics (Qua), and the ambient temperature, as calculated in the following equation and as discussed further in the Package Thermal Characteristics section: TJmax = TAmax + (P * Qua) C Note: The user must determine this junction tempera- ture to see if the delays from ORCA Foundry should be derated based on the following derat- ing tables. Table 38 and Table 39 provide approximate power sup- ply and junction temperature derating for OR3Cxx com- Lucent Technologies Inc. mercial and industrial devices. Table 40 provides the same information for the OR3Txxx devices (both com- mercial and industrial). The delay values in this data sheet and reported by ORCA Foundry are shown as 1.00 in the tables. The method for determining the maximum junction temperature is defined in the Pack- age Thermal Characteristics section. Taken cumula- tively, the range of parameter values for best-case vs. worst-case processing, supply voltage, and junction temperature can approach 3 to 1. Table 38. Derating for Commercial Devices (OR3Cxx) Tu Power Supply Voltage (C) 4.75V 5.0V 5.25V 0 0.81 0.79 0.77 25 0.85 0.83 0.81 85 1.00 0.97 0.95 100 1.05 1.02 1.00 125 1.12 1.09 1.07 Table 39. Derating for Industrial Devices (OR3Cxx) TJ Power Supply Voltage (CC) | 45V | 4.75V) 5.0V | 5.25V| 5.5V 40 0.71 0.70 0.68 0.66 0.65 0 0.80 0.78 0.76 0.74 0.73 25 0.84 0.82 0.80 0.78 0.77 85 1.00 0.97 0.94 0.93 0.91 100 1.05 1.01 0.99 0.97 0.95 125 1.12 1.09 1.06 1.04 1.02 Table 40. Derating for Commercial/industrial Devices (OR3Txxx) TJ Power Supply Voltage (C) 3.0 V 3.3V 3.6 V 40 0.73 0.66 0.61 0 0.82 0.73 0.68 25 0.87 0.78 0.72 85 1.00 0.90 0.83 100 1.04 0.94 0.87 125 1.10 1.00 0.92 Note: The derating tables shown above are for a typical critical path that contains 33% logic delay and 66% routing delay. Since the routing delay derates at a higher rate than the logic delay, paths with more than 66% routing delay will derate at a higher rate than shown in the table. The approximate derating values vs. temperature are 0.26% per C for logic delay and 0.45% per C for routing delay. The approximate derating values vs. voltage are 0.13% per mV for both logic and routing delays at 25 C. 103ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Timing Characteristics (continued) In addition to supply voltage, process variation, and operating temperature, circuit and process improve- ments of the ORCA Series FPGAs over time will result in significant improvement of the actual performance over those listed for a speed grade. Even though lower speed grades may still be available, the distribution of yield to timing parameters may be several speed grades higher than that designated on a product brand. Design practices need to consider best-case timing parameters (e.g., delays = 0), as well as worst-case timing. The routing delays are a function of fan-out and the capacitance associated with the CIPs and metal inter- connect in the path. The number of logic elements that can be driven (fan-out) by PFUs is unlimited, although the delay to reach a valid logic level can exceed timing requirements. It is difficult to make accurate routing delay estimates prior to design compilation based on fan-out. This is because the CAE software may delete redundant logic inserted by the designer to reduce fan- out, and/or it may also automatically reduce fan-out by net splitting. PFU Timing Table 41. Combinatorial PFU Timing Characteristics The waveform test points are given in the Input/Output Buffer Measurement Conditions section of this data sheet. The timing parameters given in the electrical characteristics tables in this data sheet follow industry practices, and the values they reflect are described below. Propagation DelayThe time between the specified reference points. The delays provided are the worst case of the tphh and tpll delays for noninverting func- tions, tplh and tphl for inverting functions, and tphz and tplz for 3-state enable. Setup TimeThe interval immediately preceding the transition of a clock or latch enable signal, during which the data must be stable to ensure it is recognized as the intended value. Hold TimeThe interval immediately following the transition of a clock or latch enable signal, during which the data must be held stable to ensure it is recognized as the intended value. 3-State EnableThe time from when a 3-state contro! signal becomes active and the output pad reaches the high-impedance state. OR3Cxx Commercial: VDD = 5.0 V+ 5%, 0C < TA< 70 C; Industrial: VOD = 5.0 V + 10%, -40 C < TA < +85 C. OR3Txx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter Symbol -4 5 6 -7 Unit Min | Max | Min | Max | Min | Max | Min | Max Combinatorial Delays (TJ = +85 C, VDD = min): Four-input Variables (Kz{3:0] to F[z])* F4_DEL |2.34) |180} | 1.32] | 1.05] ns Five-input Variables (F5[A:D] to F[0O, 2, 4, 6]) F5_DEL | 2.11; | 1.57] | 1.23] | 0.99] ns Two-level LUT Delay (Kz[3:0] to F w/feedbk)* SWL2_DEL | | 4.87) | 3.66] | 258| | 2.03] ns Two-level LUT Delay (F5{A:D] to F w/feedbk) SWL2F5_DEL}| | 4.69) | 3.51} | 2.48/ | 1.94] ns Three-level LUT Delay (Kz[3:0] to F w/feedbk)* | SWL3_DEL | | 6.93] | 5.15; | 3.63} | 2.82] ns Three-level LUT Delay (F5[A:D] to F w/feedbk) | SWL3F5_DEL] | 6.89] | 5.08/ | 3.54}; | 2.75] ns CIN to COUT Delay (logic mode) CO_DEL } 3.47) ) 265) | 1.79} } 1.43) ns * Four-input variables (KZ[3:0]) path delays are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes. 104 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) FDBK-DEL PFU :0 P$~ Kz3:0] - F4 DEL Bz FI7:0), K23:0], FS[A:D] FI7:0) K2{3:0] F4_DEL/ FI7:0] OMUX_DEL = O[9:0] KZ3:0} ~| tur FT7:0} FS[A:D] SWL2F5 DEL F4_DEL/ FI7:0] F4_DEL/ mm] F5_DEL f~ LUT F4_DEU/ FS[A:D) FS_DEL | SWL3E5_DEL Note: See Table 46 for an explanation of FDBK_DEL and OMUX_DEL. 5-5751(F) Figure 64. Combinatorial PFU Timing Lucent Technologies Inc. 105Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Timing Characteristics (continued) Table 42. Sequential PFU Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, ~40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter Symbol 4 5 -6 -7 Unit Min | Max | Min | Max| Min | Max] Min | Max Input Requirements Clock Low Time CLKL_MPW | 3.361 12.07} | 0.94 | 0.72] | ns Clock High Time CLKH_MPW | 1.61) | 1.06] | 0.54) | 0.45) | ns Global S/R Pulse Width (GSRN) GSR_MPW {| 3.36) | 2.07| | 0.94} | 0.72} | ns Local S/R Pulse Width LSR_MPW {3.36; | 2.07] | 0.94) | 0.72] j ns Combinatorial Setup Times (TJ = +85 C, VoD = min): Four-input Variables to Clock (Kz[3:0] to CLK)* F4_SET 1.99] | 1.47} | 1.08] | 0.85] | ns Five-input Variables to Clock (F5[A:D] to CLK) F5_SET 1.79| | 1.33} | 1.03] |0.81] | ns Data In to Clock (DIN{7:0] to CLK) DIN_SET | 0.47) | 0.32} | 0.18] |0.16] | ns Carry-in to Clock, DIRECT to REGCOUT (CIN to CLK) | CINDIR_SET | 1.25] | 0.99) | 0.71] | 0.58] | ns Clock Enable to Clock (CE to CLK) CE1_LSET | 2.86) | 2.15) | 1.80] | 1.387] | ns Clock Enable to Clock (ASWE to CLK) CE2_SET 1.68; | 1.30} |0.95| | 0.77] | ns Local Set/Reset to Clock (SYNC) (LSR to CLK) LSR_SET 1.86) | 1.36) } 0.86} | 0.68] | ns Data Select to Clock (SEL to CLK) SEL_SET 1.37} | 1.00} | 0.92] |0.70} | ns Two-level LUT to Clock (Kz[3:0] to CLK w/eedbk)* SWL2_SET | 3.98] | 2.991 |2.13] | 1.63] | ns Two-level LUT to Clock (F5[A:D] to CLK w/feedbk) SWL2F5_SET | 4.06] | 2.97] | 2.29] | 1.68] | ns Three-level LUT to Clock (Kz[3:0] to CLK w/feedbk)* SWL3_SET {| 6.49] | 4.81] |3.42| |2.64]| | ns Three-level LUT to Clock (F5[A:D] to CLK w/feedbk) SWL3F5_SET | 6.39] | 4.731 |3.34| {2.571 | ns Combinatorial Hold Times (TJ = all, VDD = all): Data In (DIN[7:0] from CLK) DIN_HLD 0.00; | 0.00} ; 0.00; |0.00] | ns Carry-in from Clock, DIRECT to REGCOUT (CIN from | CINDIR_LHLD | 0.00} | 0.00; | 0.00] |0.00/ | ns CLK) Clock Enable (CE from CLK) CE1_HLD |0.00} | 0.00] | 0.00! ~ | 0.00] | ns Clock Enable from Clock (ASWE from CLK) CE2.HLD j|0.00} | 0.00| | 0.00} | 0.00) | ns Local Set/Reset from Clock (sync) (LSR from CLK) LSR_HLD {0.00} | 0.00] | 0.00} |0.00); | ns Data Select from Clock (SEL from CLK) SEL_HLD {0.00} | 0.00) [0.00] |0.00/ | ns All Others _ 0.00] | 0.00} | 0.00] |0.00/ | ns Output Characteristics Sequential Delays (TJ = +85 C, VDD = min): Local S/R (async) to PFU Out (LSR to Q[7:0], REG- LSR_DEL | 7.02} | 5.29) | 3.64) | 2.90] ns COUT) Global S/R to PFU Out (GSRN to Q[7:0], REGCOUT) GSR_DEL | 5.21) 13.90] | 2.55) | 2.00) ns Clock to PFU OutRegister (CLK to Q[7:0], REG- REG_DEL | 2.38) | 1.75) | 1.26} | 0.97) ns COUT) Clock to PFU OutLatch (CLK to Q[7:0]) LTCH_DEL 2.51); | 1.88) | 1.21] | 0.96] ns Transparent Latch (DIN[7:0] to Q{[7:0]) LTCHD_DEL | | 2.73] | 2.10) | 1.38] | 1.12] ns * Four-input variables (KZ[3:0]) setup times are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes. Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing the same timing parameter and may accurately report delays that are less than those listed. 106 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 43. Ripple Mode PFU Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter (Ts = +85 C, VoD = min) Symbol ~4 5 4 -7 | Unit Min |Max| Min |Max) Min |Max| Min |Max Full Ripple Setup Times (byte wide): Operands to Clock (Kz[1:0] to CLK) RIP_SET 3.50] | 2.50; | 1.96] | 1.48] | ns Bitwise Operands to Clock (Kz[1:0] to CLK at F[z]} FRIP_SET 1.99} | 1.47) | 1.08] |0.85| j ns Fast Carry-in to Clock (FCIN to CLK) FCIN_SET 2.55] | 1.87) | 1.34) | 1.04) ] ns Carry-in to Clock (CIN to CLK) CIN_SET 3.80] | 2.79} | 1.97] | 1.56; ]| ns Add/Subtract to Clock (ASWE to CLK) AS_SET 8.82] | 6.18] | 4.68) | 3.50! | ns Operands to Clock (Kz[1:0] to CLK at REGCOUT) RIPRC_SET | 2.09] | 1.61) |1.19/ ]|0.93/ ] ns Fast Carry-in to Clock (FCIN to CLK at REGCOUT) FCINRC_SET | 2.29} | 1.76] | 1.28] |1.02} ] ns Carry-in to Clock (CIN to CLK at REGCOUT) CINRC_SET | 3.09] | 2.36] | 1.73} | 1.35} ] ns Add/Subtract to Clock (ASWE to CLK at REGCOUT) ASRC_SET 8.14) | 5.73] | 4.54) 13.39) ] ns Full Ripple Hold Times (Ty = all, VbD = all): Fast Carry-in from Clock (FCIN from CLK at REG- FCINRC_HLD } 0.00} | 0.00] | 0.00; | 0.00] ] ns COUT) All Others GENERIC_HLD | 0.00] | 0.00} | 0.00} {0.00} | ns Half Ripple Setup Times (nibble wide): Operands to Clock (Kz[1:0] to CLK) HRIP_SET 3.91| | 2.81; | 2.21; | 1.66] ] ns Bitwise Operands to Clock (Kz[1:0] to CLK at F[z]) HFRIP_SET 1.99} | 1.47) | 1.08; |0.85| | ns Fast Carry-in to Clock (FCIN to CLK) HFCIN_SET | 2.55| | 1.87] | 1.34; |] 1.04] ] ns Carry-in to Clock (CIN to CLK) HCIN_SET 3.80| | 2.79) | 1.97| |1.56) | ns Add/Subtract to Clock (ASWE to CLK) HAS_SET 8.82| | 6.18] | 4.68] | 3.50] ]| ns Operands to Clock (Kz[1:0] to CLK at REGCOUT) HRIPRC_SET | 3.03] | 2.31; | 1.68] | 1.32) ] ns Fast Carry-in to Clock (FCIN to CLK at REGCOUT) | HFCINRC_SET | 2.29} | 1.76) | 1.28} | 1.02; | ns Carry-in to Clock (CIN to CLK at REGCOUT) HCINRC_SET | 3.09} | 2.36] | 1.73] | 1.35) 1] ns Add/Subtract to Clock (ASWE to CLK at REGCOUT) | HASRC_SET | 8.14] | 5.73] | 4.54] |3.39} ]| ns Half Ripple Hoid Times (Ty = all, VOD = all): Fast Carry-in from Clock (HFCIN from CLK at REG- | HFCINRC_HLD | 0.00| | 0.00} |0.00] | 0.00] ] ns COUT) All Others GENERIC_HLD } 0.00| ~ | 0.00] | 0.00] | 0.00} ] ns Note: The table shows worst-case delay for the ripple chain. ORCA Foundry reports the delay for individual paths within the ripple chain that will be less than or equal to those listed above. Lucent Technologies Inc. 107ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Timing Characteristics (continued) Table 43. Ripple Mode PFU Timing Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VOD = 5.0 V + 10%, 40 C < Ta < +85 C. OR3Txxx Commercial: VoD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < Ta < +85 C. Speed Parameter (TJ = +85 C, Vob = min) Symbol 4 5 6 7 Unit Min | Max | Min) Max| Min | Max | Min | Max Full Ripple Delays (byte wide): Operands to Carry-out (Kz[1:0] to COUT) RIPCO_DEL | 532 | ]411) | 298] | 2.32] ns Operands to Carry-out (Kz[1:0] to FCOUT) RIPFCO_DEL ; | 5.30 | |4.10); | 298] | 2.32] ns Operands to PFU Out (Kz[1:0] to F[7:0]) RIP_DEL | 7.37 | |560| | 4.18; ; 3.10] ns Bitwise Operands to PFU Out (Kz/[1:0] to F[z]) FRIP_DEL | 2.34 | |1.80] | 1.32; | 1.05] ns Fast Carry-in to Carry-out (FCIN to COUT) FCINCO_DEL | | 259 | 1/1.99} | 1.43] | 1.14] ns Fast Carry-in to Fast Carry-out (FCIN to FCOUT)| FCINFCO_DEL | | 2.57 | | 1.98} | 1.41] - | 1.13] ns Carry-in to Carry-out (CIN to COUT) CINCO_DEL | 3.47} |2.65| | 1.79] | 1.43] ns Carry-in to Fast Carry-out (CIN to FCOUT) CINFCO_DEL | | 3.46 | /|2.64) | 1.78] | 1.43] ns Fast Carry-in PFU Out (FCIN to F[7:0]) FCIN_DEL | 6.03 | | 4.55] | 3.21; | 2.51] ns Carry-in PFU Out (CIN to F[7:0]) CIN_DEL | 691 | |5.21| | 3.53} | 3.05] ns Add/Subtract to Carry-out (ASWE to COUT) ASCO_DEL | 828 | |5.89; | 458); | 3.45} ns Add/Subtract to Carry-out (ASWE to FCOUT) ASFCO_DEL | 8.11 | {5.78} | 448; | 3.38] ns Add/Subtract to PFU Out (ASWE to F[7:0]) AS_DEL | 10.66] |7.55| | 5.85; | 4.38] ns Half Ripple Delays (nibble wide): Operands to Carry-out (Kz[1:0] to COUT) HRIPCO_DEL | | 5.32 | ] 4.11] | 298); | 2.32] ns Operands to Fast Carry-out (Kz[1:0] to FCOUT) | HRIPFCO_DEL | | 5.30 | /| 4.10; | 2.98; | 2.32] ns Operands to PFU Out (Kz[1:0] to F[3:0]) HRIP_DEL | 550 | | 4.07} | 3.20| | 2.40] ns Bitwise Operands to PFU Out (Kz[1:0] to F[z]) HFRIP_DEL | 2.34 | |1.80; | 1.32) | 1.05] ns Fast Carry-in to Carry-out (FCIN to COUT) HFCINCO_DEL | | 2.59 | 11.99) | 1.43) | 1.14] ns Fast Carry-in to Fast Carry-out (FCIN to FCOUT) |HFCINFCO_DEL} | 2.57 | {/1.98;) | 1.41} | 1.13] ns Carry-in to Carry-out (CIN to COUT) HCINCO_DEL | | 3.47 | 12.65; | 1.79} | 1.43] ns Carry-in to Carry-out (CIN to FCOUT) HCINFCO_DEL | | 3.46 | 12.64] | 1.78}; | 1.43] ns Fast Carry-in PFU Out (FCIN to F[3:0]) HFCIN_DEL | 3.76 | |2.84| | 2.01| | 1.58] ns Carry-in PFU Out (CIN to F[3:0]) HCIN_DEL | 4.65 3.50| | 2.33] | 2.12] ns Add/Subtract to Carry-out (ASWE to COUT) HASCO_DEL | | 8.28 | |5.89| | 4.58] | 3.45] ns Add/Subtract to Carry-out (ASWE to FCOUT) HASFCO_DEL | | 8.11 5.78| |} 448) | 3.38] ns Add/Subtract to PFU Out (ASWE to F[3:0]) HAS_DEL | 912 | |649} | 486] | 3.69] ns Note: The table shows worst-case delay for the ripple chain. ORCA Foundry reports the delay for individual paths within the ripple chain that will be less than or equal to those fisted above. 108 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 44. Synchronous Memory Write Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, 40 C < TA < +85 C. Speed Parameter Symbol 4 5 6 -7 Unit Min | Max | Min; Max | Min | Max | Min | Max Write Operation for RAM Mode: Maximum Frequency SMCLK_FRQ | 7151.00! |197.00); | 254.00} | 315.00] MHz Clock Low Time SMCLKL_MPW] 2.34 _ 1.80 _ 1.32 _ 1.05 ns Clock High Time SMCLKH_MPW} 3.79 2.77 _ 2.13 _ 1.62 ns Clock to Data Valid (CLK to F[6, 4, 2, 0])* MEM_DEL | 10.00}; 7.14 5.00 _ 4.08 | ns Write Operation Setup Time: Address to Clock (CIN to CLK) WA4_SET 1.25 0.99 _ 0.71 _ 0.58 _ ns Address to Clock (DIN[7, 5, 3, 1] to CLK) WA_SET 0.72 _ 0.52 0.35 0.28 ns Data to Clock (DIN(6, 4, 2, 0] to CLK) WD_SET 0.02 _ 0.06 _ 0.00 _ 0.00 | ns Write Enable (WREN) to Clock (ASWE to CLK)) wWeE_SET 0.18 0.16 0.14 _ 0.12 _ ns Write-port Enable 0 (WPEO) to Clock (CE to WPEO_SET | 2.25} | 1.69/ | 1.16) | O84] ns CLK) Write-port Enable 1 (WPE1) to Clock (LSRto | wpei set | 2.79 213 1.58 1.31 ns CLK) ~ Write Operation Hold Time: Address from Clock (CIN from CLK) WA4_HLD 0.00 _ 0.00 _ 0.00 _ 0.00 _ ns Address from Clock (DIN[7, 5, 3, 1] from CLK) WA_HLD 0.00 0.00 _ 0.00 _ 0.00 _ ns Data from Clock (DIN[6, 4, 2, 0] from CLK) WD_HLD 0.59| | 042; | 040, | 032) ns Write Enable (WREN) from Clock (ASWE from} =WE_HLD 0.03 0.00 0.08 _ 0.06 _ ns CLK) Write-port Enable 0 (WPEO) from Clock (CE WPEO_HLD 0.00 _ 0.00 0.00 0.00 ns from CLK) Write-port Enable 1 (WPE1) from Clock (LSR | wpe, Hip | 0.00 _ 0.00| 0.00 _ 0.00 _ ns from CLK) ~ * The RAM is written on the inactive clock edge following the active edge that latches the address, data, and control signals. Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing the same timing parameter and may accurately report delays that are less than those listed. WA4_SET WA4_HLD ps WALSET {+> WA_HLD cn ome. 5 3:1 XXRRXKRXXKRK ___ XXXXXXKXXXKKXXXKKKXE he WD_SET efe-} WD_HLD DING, 4.2.01 KXXXXXXXXXXK KX XXXKXXXXXAAAKKAKKKK WE_SET} >| WE_HLD ASWE (WREN) / | \ WPEO_SET-+ >}<>1- WPEO_HLD WPE1_SET WPE1_HLD CE (WPEO), 4 \ LSR (WPE1) ___ A TSCH Tser | ox TN nn a2.0 SEXXEXEXERXEKXRXERKERXEKO 5-4621(F)} Figure 65. Synchronous Memory Write Characteristics Lucent Technologies Inc. 109ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Timing Characteristics (continued) Table 45. Synchronous Memory Read Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VOD = 5.0 V + 10%, -40 C < TA < +85 C. ORSTxxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. p ' Speed arameter . (TJ = 85 C, VOD = min) Symbol 4 5 6 7 Unit Min | Max | Min} Max} Min} Max] Min | Max Read Operation: Data Valid After Address (Kz[3:0] to F[6, 4, 2, 0]) RA.DEL | | 234) / 1.80} | 1.32} | 1.05] ns Data Valid After Address (F5[A:D] to F[6, 4, 2, 0]) RA4_DEL | | 2.41 | | 1.57} | 1.23} | 0.99] ns Read Operation, Clocking Data into Latch/FF: Address to Clock Setup Time (Kz[3:0] to CLK) RA_SET | 1.99] | 1.47) | 1.08] | 0.85] | ns Address to Clock Setup Time (F5[A:D] to CLK) RA4_SET | 1.79] {1.33) | 1.03} | 0.81} | ns Address from Clock Hold Time (Kz[3:0] from CLK) RA_HLD | 0.00| [0.00] | 0.00} | 0.00| | ns Address from Clock Hold Time (F5{A:D} from CLK) RA4_HLD | 0.00| | 0.00; {| 0.00! | 0.00; | ns Clock to PFU OutputRegister (CLK to Q[6, 4, 2, 0])} REG_DEL | | 238} | 1.75] | 1.26] -- | 0.97] ns Read Cycle Delay SMRD_CYC) | 10.48} | 7.66] | 7.53; | 5.78] ns Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing the same timing parameter and may accurately report delays that are less than those listed. Kz[3:0), FSD] X X XX XXAXAKN RA_| DEL a RA4_DEL RA_SET _,! - RA4_SET ~ | CLK | j SMRD_CYC <_$__ RA_HLD RA4_HLD REG_DEL > aso] XXXAXXAXXXKXXKAXAKKKKAKAK KKK AA 110 Figure 66. Synchronous Memory Read Cycle -4622(F) Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) PLC Timing Table 46. PFU Output MUX and Direct Routing Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, 40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VOD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter . U (Ty = 85 C, VoD = min) Symbol ~4 5 6 7 nit Min | Max| Min | Max | Min | Max | Min | Max PFU Output MUX (Fan-out = 1) Output MUX Delay (F[7:0]/Q[7:0] to O[9:0]) OMUX_DEL | | 0.50] | 0.39; | 0.35) | 0.28] ns Carry-out MUX Delay (COUT to 09) Coos_DEL |} | 0.34; | 0.26! | 0.24] | 0.18] ns Registered Carry-out MUX Delay (REGCOUT | RCOO8_DEL| | 0.34) | 0.26; | 0.24; |} 0.18] ns to 08) Direct Routing PFU Feedback (xSW)* | FOBK_DEL | | 1.74; | 1.41] | 148] | 1.14] ns PFU to Orthogonal PFU Delay (xSW to xSW) | ODIR_DEL | 2.21; | 1.77) | 1.75) | 1.39] ns PFU to Diagonal PFU Delay (xBID to xSW) DDIR_DEL | 269); |219} | 253} | 1.98] ns * This is general feedback using switching segments. See the combinatorial PFU timing table for softwired look-up table feedback timing. SLIC Timing Table 47. Supplemental Logic and Interconnect Cell (SLIC) Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, ~40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, ~40 C < TA < +85 C. p Speed arameter * Unit (Ty = 85 C, VoD = min) Symbol 4 5 6 7 n Min | Max| Min | Max| Min | Max| Min | Max 3-Statable BIDis BID! Delay (BRx to BLx, BLx to BRx} BUF_DEL | 084, |0.70| | 0.94) | 0.77) ns BID! Delay (Ox to BRx, Ox to BLx) OBUF_DEL | | 0.72] | 0.61| | 0.87} | 0.70] ns BID] 3-state Enable/Disable Delay (TRI to BL, BR) TRI_DEL |2.55; | 1.90} | 1.31} | 1.01] ns BIDI 3-state Enable/Disable Delay DECTRILDEL) | 3.59} | 265; | 1.91] | 1.48] ns (BL, BR via DEC, TRI to BL, BR) Decoder Decoder Delay (BR[9:8], BL[9:8] to DEC) DEC98_DEL| {|2.39| -- | 1.85} | 1.27] | 1.02] ns Decoder Delay (BR[7:0], BL[7:0] to DEC) DEC_DEL | 235) | 182} | 1.23) | 0.99! ns Lucent Technologies Inc. 111ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Timing Characteristics (continued) PlO Timing Table 48. Programmable V/O (PIO) Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, 40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, 40 C < TA < +85 C. Speed Parameter Symbol 4 5 6 -7 Unit Min | Max | Min | Max | Min | Max | Min [| Max Input Delays (TJ = 85 C, Voo = min) Input Rise Time IN_RIS | 500; | 500]; 500 | 500 | ns Input Fall Time IN_FAL _ 500 | 500 | 500 | 500 | ns PIO Direct Delays: Pad to In (pad to CLK IN) CKIN_DEL }/141/ 1126} | 064} | 0.41] ns Pad to In (pad to IN1, IN2) IN_DEL |216| | 1.87] | 1.28] | 090] ns Pad to In Delayed (pad to IN1, IN2) IND_DEL (905) | 783} | 664) |7.27)] os PIO Transparent Latch Delays: Pad to In (pad to IN1, IN2) LATCH_DEL | | 4.11] |325/ | 252] | 1.82] ns Pad to In Delayed (pad to IN1, IN2) LATCHD_DEL j; |1058| |9.05| | 7.67] | 7.65| ns Input Latch/FF Setup Timing: Pad to ExpressCLK (fast-capture latch/FF) INREGE_SET | 5.93, | 4.82; | 363] | 323] | ns Pad Delayed to ExpressCLK INREGED_SET 12.86 11.03 ~ 9.18 9.68 _ ns (fast-capture latch/FF) Pad to Clock (input latch/FF) INREG_SET | 1.62] |142) ~ |0.71j, | 050] ns Pad Delayed to Clock (input latch/FF) INREGD_SET | 8.57} | 7.36/ | 591] | 7.06] | ns Clock Enable to Clock (CE to CLK) INCE_SET | 203) | 164) | 1.29] | 1.00} | ngs Loca! Set/Reset (sync) to Clock (LSR to CLK)| !NLSR_SET | 1.79] | 145] | 1.14] | 089} | ng Input FF/Latch Hold Timing: Pad from ExpressCLK (fast-capture latch/FF) | INREGE_HLD | 0.00; |0.00; | 0.00} {0.00} | ns Pad Delayed from ExpressCLK INREGED_HLD 0.00 0.00 _ 0.00 _ 0.00 ns (fast-capture latch/FF) Pad from Clock (input latch/FF) INREG_HLD | 0.00; | 000] | 000) | 0.00; | ns Pad Delayed from Clock (input latch/FF) INREGD_HLD | 0.00); | 0.00}; | 0.00} | 0.00} | ns Clock Enable from Clock (CE from CLK) INCE_HLD | 0.00; | 0.00; {000} | 0.00) | ns Local Set/Reset (sync) from Clock INLSR_HLD {| 0.00) | 0.00} | 0.00} | 0.00} | ns (LSR from CLK) Clock-to-in Delay (FF CLK to IN1, IN2) INREG_DEL |405) |314)/ | 253|/ | 2.05] ns Clock-to-in Delay (latch CLK to IN1, IN2) INLTCH_DEL | | 408] |319| | 262] | 2.14] ns Local S/R (async) to IN (LSR to IN1, IN2) INLSR_DEL {6.11 |] | 476}; | 381 | | 3.17] ns Local S/R (async) to IN (LSR to IN1, IN2) INLSRL_DEL | | 589! | 466|/ | 357] ; 298] ns LatchFF in Latch Mode Global S/R to In (GSRN to IN1, IN2) INGSR_DEL |} | 5.38| | 422] |344] | 288] ns Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns. 112 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 48. Programmable I/O (PIO) Timing Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter Symbol 4 5 6 -7 Unit Min | Max | Min | Max | Min | Max | Min | Max Output Delays (Ty = 85 C, Vop = min, CL = 50 pF) Output to Pad (OUT2, OUT1 direct to pad): Fast OUTF_DEL |509| |421] | 263] | 2.17] ns Slewlim OUTSL_DEL |7.86| |649] |349| | 291] ns Sinklim OUTSI!_DEL |941/ | 7.98] | 8.08} | 7.32] ns 3-state Enable/Disable Delay (TS to pad): Fast TSF_DEL |493| | 409] |233|] | 1.88] ns Slewlim TSSL_DEL |7.70| |637} | 3.00] | 2.41] ns Sinklim TSSI_DEL {925| |7.86| |7.95| | 7.23) ns Local Set/Reset (async) to Pad (LSR to pad): Fast OUTLSRF_DEL | /|9.03; | 7.25} |496| | 3.94] ns Slewlim OUTLSASL_DEL| [11.791 |9.53| | 5.82] | 4.67] ns Sinklim OUTLSRSI_DEL| {13.35]} {11.02} |10.38; | 9.10] ns Global Set/Reset to Pad (GSRN to pad): Fast OUTGSRF_DEL | | 8.30 6.69 4.39 | |3.46| ns Slewlim OUTGSRSL_DEL}] /|11.06) | 897; |5.07| {3.99] ns Sinklim OUTGSRSILDEL| |12.62) |10.46] |10.02/ | 8.81] ns Output FF Setup Timing: Out to ExpressCLK (OUT[2:1] to ECLK) OUTE_SET 0.00} |; 0.00}; | 0.00} |0.00| ns Out to Clock (OUT[2:1] to CLK) OUT_SET 0.00} |0.00; | 0.00} |0.00! j ns Clock Enable to Clock (CE to CLK) OUTCE_SET |0.91/ {0.67} |056}| {045}; | ns Local Set/Reset (sync) to Clock (LSR to CLK) | OUTLSR_SET |0.41} | 0.32] |0.26] | 0.24] | ns Output FF Hold Timing: Out from ExpressCLK (OUT[2:1] from ECLK) OUTE_HLD 0.73| |058; | 036} | 0.29} ns Out from Clock (OUT[2:1] from CLK) OUT_HLD 0.73; | 058) |036/ | 0.29) ns Clock Enable from Clock (CE from CLK) OUTCE_HLD 10.00} |0.00} }0.00/| | 0.00}; ns Local Set/Reset (sync) from Clock (LSR from | OUTLSR_HLD | 0.00} {0.00} | 0.00! | 0.00; ns CLK) Clock to Pad Delay (ECLK, SCLK to pad): Fast OUTREGF_DEL | | 6.71] | 5.44) [3.56] | 2.78] ns Slewlim OUTREGSL_DEL| |9.47] | 7.71| |442) |3.52| ns Sinklim OUTREGSI_DEL| [11.03] {9.20} |898|] | 7.94] ns Additional Delay If Using Open Drain OD_DEL | 0.20); | 0.16) | 0.10} | 0.08] ns Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns. Lucent Technologies Inc. 113Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Timing Characteristics (continued) Table 48. Programmable W/O (PIO) Timing Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V+ 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < Ta < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter Symbol 4 5 -6 -7 Unit Min | Max | Min | Max | Min | Max | Min | Max PIO Logic Block Delays Out to Pad (OUT[2:1] via logic to pad): Fast OUTLF_DEL |5.09| |421| |263) | 2.17] ns Slewlim OUTLSL_DEL |7.86| | 649; |3.49; |2.91] ns Sinklim OUTLSI_DEL |9.41| |7.98}| | 808| |7.32] ns Outreg to Pad (OUTREG via logic to pad): Fast OUTRF_DEL |6.71|; | 544] 13.56] | 2.78] ns Slewlim OUTRSL_DEL |9.47| |7.71| |442/ | 3.52] ns Sinklim OUTRSI_DEL /11.03; |920} |898/ | 7.94| ns Clock to Pad (ECLK, CLK via logic to pad): Fast OUTCF_DEL 6.97; | 5.68! | 3.71) | 2.91] ns Slewlim OUTCSL_DEL |9.74| | 7.961 | 4.57] | 3.64] nos Sinklim OUTCSI_DEL |11.29} |945/ 19.13 | | 8.07] ns 3-State FF Delays 3-state Enable/Disable Delay (TS direct to pad): Fast TSF_DEL 1493] | 409/ |233| | 71.88] ns Slewlim TSSL_DEL |7.70| |637 |] |3.00; | 2.41 ns Sinklim TSSI_DEL |925| |786) |7.95| | 7.23] ns Local Set/Reset (async) to Pad (LSR to pad): Fast TSLSRF_DEL |825! {665} | 424] | 3.39] ns Slewlim TSLSRSL_DEL |/11.01; | 892! | 4.92} |3.92]/ ns Sinklim TSLSRSI_DEL |12.57; |10.41] |9.87| | 8.74] ns Global Set/Reset to Pad (GSRN to pad): Fast TSGSRF_DEL |7.52; |6.09! | 3.88 3.11 ns Slewlim TSGSRSL_DEL | |10.28] | 836] | 4.55| | 3.64] ns Sinklim TSGSRSI_DEL |11.84; |985); |9.51] | 845] ns 3-State FF Setup Timing: TS to ExpressCLK (TS to ECLK) TSE_SET 0.00} |0.00] | 0.00} | 0.00} ns TS to Clock (TS to CLK) TS_SET 0.00} | 0.00] | 0.00} | 0.00} ns Local Set/Reset (sync) to Clock (LSR to TSLSR_SET 0.28) 10.21} |0.17/ 10.18} ns CLK) 3-State FF Hold Timing: TS from ExpressCLK (TS from ECLK) TSE_HLD 085} |068| |044); |034/ ns TS from Clock (TS from CLK) TS_HLD 0.85; |0.68| [044] 10.34) ns Local Set/Reset (sync) from Clock TSLSR_HLD 0.00; |} 0.00] {0.00} | 0.00} ns (LSR from CLK) Clock to Pad Delay (ECLK, SCLK to pad): Fast TSREGF_DEL |594!1 |482]) 12.84) | 2.23] ns Slewlim TSREGSL_DEL |870| | 7.10} |} 3.52| | 2.76] ns Sinklim TSREGSI_DEL /10.26) |859! | 847] | 7.58} ns Note: The delays for all input buffers assume an input rise/fall time of <1 Vins. 114 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Special Function Blocks Timing Table 49. Microprocessor Interface (MPI) Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, 40 C < TA < +85 C. Speed Parameter Symbol 4 +5 -6 7 Unit Min | Max} Min} Max} Min | Max| Min | Max PowerPC Interface Timing (TJ = 85 C, VDD = min) Transfer Acknowledge Delay (CLK to TA) TA_DEL |11.6]) |} 93} | 80; | 68] ns Burst Inhibit Delay (CLK to BIN) BILDEL 111.6) | 93] | 80] | 6.8] ns Transfer Acknowledge Delay to High Impedance TA_DELZ | @)/}| @]/_| @}] ] @] ns Burst Inhibit Delay to High impedance BI_DELZ {|@]/| @]/]|] @i] OI ns Write Data Setup Time (data to TS) WD_SET 0.0}; | 00}; }| 0.0; | 0.0/ j ns Write Data Hold Time (data from CLK while MPI_ACK low) WD_HLD 0.0|/ !00} | 00] | 00}; ]| ns Address Setup Time (addr to TS) A_SET 0.0| | 00; | 00} ] 00] | ns Address Hold Time (addr from CLK while MPI_ACK low) A_HLD 0.0; | 00} } 00; ]|00] ] ns Read/Write Setup Time (R/W to TS) RW_SET 0.0} { 00] }| 00} | 00] ] ns Read/Write Hold Time (R/W from CLK while MPI_ACK low) RW_HLD 0.0; | 00); | 00; | 00| ] ns Chip Select Setup Time (CSO, CS1 to TS) CS_SET | 03] ] 25] | .14| | 12) | ns Chip Select Hold Time (CSO, CS1 from CLK) CS_HLD 0.0} | 00) | 00}; }| 00; ] ns User Address Delay (pad to UA[3:0]} UA_DEL | 3.3! !26) /| 23) | 1.9] ns User Read/Write Delay (pad to URDWR_DEL) URDWR_DEL | | 7.0| | 54] | 42] | 3.6] ns i960 Interface Timing (TJ = 85 C, VDD = min) Addr/Data Select to ALE (ADS, to ALE low) ADSN_SET | 2.0} | 1.8] | 1.6] | 1.4] | ns Addr/Data Select to ALE (ADS, from ALE low) ADSN_HLD | 0.0] |0.0|/ j| 00} ] 00] ] ns Ready/Receive Delay (CLK to RDYRCV) RDYRCV_DEL | | 11.6} | 9.3] | 8.0); | 6.8] ns Ready/Receive Delay to High Impedance RDYRCV_DELZ} | @ | /] @ | | @ | | | ns Write Data Setup Time WD_SET 6}; | @&) | @ | | |) ] ns Write Data Hold Time WD_HLD 4) ~| M)| M}| |] @) ] ns Address Setup Time (addr to ALE low) A_SET 20/ |1.8] |0.50] | | 0.42] ns Address Hold Time (addr from ALE low) A_HLD 2.0] | 1.8) |0.51) | | 0.441 ns Byte Enable Setup Time (BEO, BE1 to ALE low) BE_SET 20} | 1.8] |0.50] | | 0.42] ns Byte Enable Hold Time (BEO, BE1 from ALE low) BE_HLD 20] |]18] 10.51; | | 0.44! ns Read/Write Setup Time RW_SET @)| |] j; @;} | | 1] ns Read/Write Hold Time RW_HLD a) | 4M) | OM) j|] M] ] ns Chip Select Setup Time (CSO, CS1 to CLK) CS_SET | 20; | 1.8} |0.45| | | 0.38] ns Chip Select Hold Time (CSO, CS1 from CLK)" CS_HLD 0.0} |oo0| | 00] | 00} ]{ ns User Address Delay (CLK low to UA[3:0]) UA_DEL | 66)/ |] 43) | 41) | 3.5] ns User Read/Write Delay (pad to URDWR_DEL) URDWR_DEL | | 7.0}; | 54] | 42] | 3.6] ns 1. For user system flexibility, CSO and CS1 may be set up to any one of the three rising clock edges, beginning with the fising clock edge when MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CSO and CS1 may go inactive before the end of the read/write cycle. 2.0.5MPILCLK. _ __ __ 3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CSO and CS1 are recognized. 4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV. Notes: Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA. PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK). Lucent Technologies Inc. 415ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Timing Characteristics (continued) Table 49. Microprocessor Interface (MP1) Timing Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, ~40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter Symbol 4 5 -6 7 Unit Min; Max| Min | Max| Min | Max! Min | Max User Logic Delay) User Logic Delay| {| | | / | ! ] T ns User Start Delay (MPI_CLK falling to USTART) USTART_DEL |36/ |34/ } 33}; |] 28] ns User Start Clear Delay (MPI_CLK to USTART) USTARTCLR_DEL| | 7.5| | 7.3) | 7.1} | 6.0] ns User End Delay (USTART low to UEND low) 7) UEND_DEL ;}}]}-jy-t-{]- ns Synchronous User Timing: User End Setup (UEND to MPI_CLk) UEND_SET 0.00; | 0.00} {0.00} 10.00; | ns User End Hold (UEND to MPI_CLK) UEND_HLD 1.0; |0.95| |0.88| |0.75| 1] ns Data Setup for Read (D[7:0] to MPI_CLK) RDS_SET }|{]]/|]|!|j]I ns Data Hold for Read (D{[7:0] from MPI_CLK)) RDS_HLD |}!-|]| |]| ns Asynchronous User Timing: User End to Read Data Delay (UEND to RDA_DEL -}o-l]-}y} oy | om] Yd Cos D[7:0})"1 Data Hold from User Start (low)? RDA_HLD {|-;--!]!--!}!]|]]] ns interrupt Request Pulse Width) TUIRQ_PW {;|-]-]-!|]]] ns 1. For user system flexibility, CSO and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when MPI_STRB is low. If both chip selects are valid and the setup time is met, the MP! will latch the chip select state, and CSO and CS1 may go inactive before the end of the read/write cycle. . 0.5 MPI_CLK. . USTART_DEL is based on the falling clock edge. DON OAhON . This should be at least one MPI_CLK cycle. 10. Notes: Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA. . There is no specific time associated with this delay. The user must assert UEND low to complete this cycle. . The user must assert interrupt request low until a service routine is executed. User should set up read data so that RDS_SET and RDS_HLD can be met for the microprocessor timing. . Write data and wk have to be valid starting from the clock cycle after both ADS and CSO and CS1 are recognized. . Write data and W/R have to be held until the microprocessor receives a valid RDYRCV. . User Logic Delay has no predefined value. The user must generate a UEND signal to complete the cycle. PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK). 116 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) MPI_CLK N40) MPI_RW (RO/WA) Gs0, cs1 TPi_STAB (TS) UA3:0] URDWRN USTART_DEL USER LOGIC DELAY UEND MPI_AGR (TA) MPI_BI Gi) 5-5832(F) Figure 67. MP! PowerPC User Space Read Timing MPI_CLK Al4:0] MPI_AW (RDAWR) CSO, cst D(7-0} MPi_STRE (TS) UA_DEL>} UAI3:0} k x_ ke vows pe UROWRN l USTART_DEL #4 al - USTARTCLR_DEL USTART \ USER LOGIC DELAYS} ft | VEND_DEL UEND TA_DELZ LT TA_DEL) i - = MPI_LACK (TA) PLE ee) B_DELP op >} et 81_DEL. ~ Le 5-5840(F) Figure 68. MPI PowerPC User Space Write Timing Lucent Technologies Inc. 117Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Timing Characteristics (continued) UEND_SET RDS_HLD CS_SET CS_HLD RW_SET ASET RW_ ROS_SET MPI_CLK A{4:0] eraweone l| | itt TSO, cs1 J | A 1 | | RDA_DEL jt-{p> | >| /RDA_HLD | | bea UA_DEL>| | 5 fl MPI_ACK (TA) MPI_BI (Bl) BLDEL>| Tf -5832(F).c Figure 69. MPI PowerPC Internal Read Timing MPI_CLK Al4:0] MPI_RW (RO/WR) S06, cs1 D{7:0] MPI_STRB (TS) | e UA_DELo be URDWR_DEL> URDWAN \ UAL3:0] a fo TA_DEL > MPI_ACK (TA) MPLS Bi) BI_DEL >} >| he BI_DEL A Lt _ |_DELZ Figure 70. MP! PowerPC Internal Write Timing Tt 5-5840(F).e 118 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) USTART_DEL USER LOGIC DELAY RDYRCV. -5831(F).b Figure 71. MPI {960 User Space Read Timing ADSN. MPI_CLK Of7:0} MPI_RW (W/A) So, cs1 MPI_ALE (ALE) MP(_STRE (ADS) UAj3:0] URDWR_DEL URDWRN USTART_DEL USTARTCLR_DEL USTART USER LOGIC DELAY UEND_DEL UEND RDYRCV_DEL RDYRGV_DEL MPI_ACK (RDYACV) LL RDYRCV_DELZ 5-5830(F).b Figure 72. MPI i960 User Space Write Timing Lucent Technologies Inc. 119Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Timing Characteristics (continued) 5-5831(F).c Figure 73. MPI i960 internal Read Timing MPI_CLK D?:0] MPI_RW (W/A) So, cs1 MPI_ALE (ALE) MPI_STRB (ADS) UAI3:0) URDWR_OEL URDWAN ADYRCV_peL-m| ROYRCV_DEL MPI_ACK (ADYRCV) LL ROYRCV_DELZ 5-5830(F).c Figure 74. MPI i960 Internal Write Timing 120 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 50. Programmable Clock Manager (PCM) Timing Characteristics (Preliminary Information) OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C STA < 70 C; Industrial: VDD = 5.0 V + 10%, -40 C < TA < +85 C. OR3STxxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Speed Parameter Symbol -4 -5 6 -7 Unit Min | Max | Min | Max | Min | Max | Min | Max Input Clock Frequency: FPCMI OR3Cxx 5 133 5 133 _ _ | MHz OR3T xxx _ 5 133 5 133 5 133 | MHz Output Clock Frequency: FPCMO ORSCxx 5 135 5 135 _ _ _ |MHz ORSTxx _ _ 5 100 5 100 5 100 | MHz Input Clock Duty Cycle PCMI_DUTY | 30.00] 70.00] 30.00} 70.00] 30.00} 70.00 | 30.00] 70.00] % Output Clock Duty Cycle PCMO_DUTY | 3.13 | 96.90] 3.13 | 96.90] 3.13 | 96.90] 3.13 | 96.90] % Input Frequency Tolerance FTOL |26400; | 26400} { 26400; | 26400] ppm PCM Acquisition Time (CLK In to PCM_ACQ?t 36 100 36 100 36 100 36 100 | us LOCK) PCM Off Delay (config. Done-L, WE to | PCMOFF_DEL {| | 100.0|] | 100.0] | 100.0; | 100.0) ns PCM power off) PCM Delay in DLL Mode (propagation PCMDLL-DEL _ 1.95 _ 1.82 _ 1.63 _ 1.50 | ns delay) PCM Delay in PLL Mode (propagation PCMPLL_DEL _ 0.00 _ 0.00 _ 0.00 _ 0.00 | ns delay) PCM Clock In to PCM Clock Out PCMBYE_DEL| 0.47 _ 0.36 _ 0.26 _ 0.24 | ns (CLK In to ECLK)* PCM Clock In to PCM Clock Out PCMBYS_DEL| 0.47 _ 0.36 | 0.26 _ 0.24 | ns (CLK In to SCLK)* Routed Clock-in Delay (routing to PCM RTCKD_DEL _ 1.30 _ 1.10 _ 0.90 _ TBD | ns phase detect, using DIVO) System Clock-out Delay (PCM oscilla-] PCMSCK_DEL| | 2.70} - |; 220; | 190; | TBD] ns tor to SCLK output at PCM) Parameter Symbol fouT (MHz) PLL Mode | DLL Mode Unit Output Jitter OUTJIT 520 250 200 ps 2130 210 170 ps 3140 180 145 ps 41-50 155 123 ps 5160 130 105 ps 6170 110 90 ps 7180 95 75 ps 8190 80 65 ps 91100 70 55 ps * Input frequency tolerance is the allowed input clock frequency change in parts per million. t+ See Table 29 and Table 30 for acquisition times for individual frequencies. + PLL mode, divider reg = 1111111 (input freq. = output freq.). Note: All timing values for the PCM are preliminary information. Lucent Technologies Inc. 121ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Timing Characteristics (continued) Table 51. Boundary-Scan Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, -40 C < TA < +85 C. ORSTxxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA <+85C. Parameter Symbol Min Max Unit TDI/TMS to TCK Setup Time Ts 25.0 _ ns TDI/TMS Hold Time from TCK TH 0.0 ns TCK Low Time TCL 50.0 _ ns TCK High Time TCH 50.0 _ ns TCK to TDO Delay TD _ 20.0 ns TCK Frequency TTCK 10.0 MHz TCK Ts TH TS \ TDI x x. x Top too Xx x xX a Xx x 5-6764(F) 122 Figure 75. Boundary-Scan Timing Diagram Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Clock Timing Table 52. ExpressCLK (ECLK) and Fast Clock (FCLK) Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, 40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Device Speed (Ts = 85C, VoD = min) Symbol 4 5 6 7 Unit Min | Max | Min | Max | Min | Max | Min | Max Clock Control Timing Delay Through ECLKC_DEL| 0.31 | 0.31; | O31] | 0.31 _ ns CLKCNTRL (input from corner) Delay Through CLKCNTAL (input from inter- | ECLKM_DEL}| 1.54) {| 1.17] | 100] | 092]; ns nal clock controller PAD) Clock Shutoff Timing: Setup from Middle ECLK (shut off to CLK) OFFM_SET | 0.77| | 0.51) | 044] | 041] ns Hold from Middle ECLK (shut off from CLK) }| OFFM_HLD } 0.00/ | 0.00}; | 0.00] | 0.00); ns Setup from Corner ECLK (shut off to CLK) OFFC_SET | 0.77} | 0.51) | 044] | 0.41) ns Hold from Corner ECLK (shut off from CLK) | OFFC_LHLD | 0.00; | 0.00; | 0.00; | 0.00; ns ECLK Delay (middle pad): ECLKM_DEL OR3T20 _ _ | 256; 2.05| 1.78] ns OR3T30 _ | 262| | 208; | 1.80] ns ORSC/T55 | 350} | 274) | 2.13] | 1.85] ns OR3C/T80 | 367/ | 286] | 2.19] | 1.90] ns OR3T125 _ _ | 306; | 229] | 1.98) ns ECLK Delay (corner pad): ECLKC_DEL OR3T20 _ _ | 448] | 3.85} | 3.36] ns OR3T30 _ _ ;453| | 3.97} | 3.47] ns ORSC/T55 | 547) | 464] | 422] | 3.69] ns OR3C/T80 | 564) | 4.77) | 447); | 3.92] ns OR3T125 _ _ | 496| | 485) | 4.27] ns FCLK Delay (middle pad): FCLKM_DEL OR3T20 _ _ | 591) | 459} | 3.81] ns OR3T30 _ _ | 612; | 466] | 3.89] ns OR3C/T55 | 824; | 659] | 483] | 4.06] ns OR3C/T80 | &87| | 7.11} | 5.01! | 4.26] ns OR3T125 _ _ | 7.98| | 533} | 459] ns FCLK Delay (comer pad): FCLKC_DEL OR3T20 _ _ | 7.88] | 641] | 5.40] ns OR3T30 _ _ | 811} | 658); |} 5.58| ns OR3C/T55 | 10.34 | 860] | 6.95) | 5.94] ns OR3C/T80 {11.01} | 915] | 7.34) | 6.33] ns OR3T125 _ _ |10.07] | 796| | 6.94] ns Notes: The ECLK delays are to all of the PICs on one side of the device for middle pin input, or two sides of the device for comer pin input. The delay includes both the input buffer delay and the clock routing to the PIC clock input. The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used. Lucent Technologies Inc. 123Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Timing Characteristics (continued) Table 53. General-Purpose Clock Timing Characteristics (Internally Generated Clock) OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, -40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Devi Speed (Ts = 85 C, VOD = min) | Smbol 4 5 6 7 Unit Min Max Min Max Min Max Min Max OR3T20 CLK_DEL _ _ _ 4.22 _ 3.46 _ 2.84 ns OR3T30 CLK_DEL _ _ _ 4.29 _ 3.48 _ 2.87 ns ORS3C/T55 CLK_DEL _ 5.34 _ 4.41 _ 3.53 _ 2.93 ns OR3C/T80 CLK_DEL _ 5.49 _ 4.52 _ 3.57 2.98 ns OR3T125 CLK_DEL _ _ _ 4.80 _ 3.71 _ 3.13 ns Notes: This table represents the delay for an internally generated clock from the clock tree input in one of the four middle PICs (using pSW routing) on any side of the device which is then distributed to the PFU/PIO clock inputs. If the clock tree input used is located at any other PIC, see the results reported by ORCA Foundry. This clock delay is for a fully routed clock tree that uses the general clock network. The delay will be reduced if any of the clock branches are not used. See pin-to-pin timing in Table 56 for clock delays of clocks input on general I/O pins. 124 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 54. OR3Cxx ExpressCLK to Output Delay (Pin-to-Pin) OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA< 70 C; Industrial: VDD = 5.0 V + 10%, 40 C < TA < +85 C; CL = 50 pF. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, 40 C < TA < +85 C;CL = 50 pF. D tio Speed escription . . (Ta = 85 C, VoD = min) Device ~4 5 7 Unit Min | Max | Min | Max | Min | Max | Min | Max ECLK Middle Input Pin->OUTPUT Pin OR3T20 _ _ |7.78| | 540}! | 4.38 | ns (Fast) OR3T30 _ _ | 7.84| | 543] | 440] ns OR3C/T55 |993 |} | 796 | | 548 | | 444] ns OR3C/T80 |10.40; | 808 | | 554] | 4.49 | ns OR3T125 _ |828|; | 564) | 4.58] ns ECLK Middle Input Pin-OUTPUT Pin OR3T20 _ ~ | 9.77 | | 607 | | 4.91] ns (Slewlim) OR3T30 _ _ |983); | 610; | 4.93] ns OR3C/T55 |12.37] |995| | 615 | | 4.97 | ns OR3C/T80 112.54, |10.07}| | 6.21 | 5.02 | ns ORST125 _ _ |10.27; | 6.31 | 5.11 | ns ECLK Middle Input Pin-OUTPUT Pin OR3T20 _ _ |11.12; |1092} | 9.65 | ns (Sinklim) OR3T30 _ _ |11.18] |1095} | 9.67 | ns OR3C/T55 |13.73; | 11.30} {11.00} | 9.71 | ns OR3C/T80 |13.90) |11.42| |11.06) | 9.76 | ns OR37T125 _ _ {1162}; |11.16] | 9.85 | ns Additional Delay if ECLK Corner Pin Used OR3T20 _ _ _ 1.91 _ 1.80 1.58 | ns OR3T30 _ _ | 1.91 | 1.90 | | 1.67 | ns OR3C/T55 | 1.97 | | 1.91 | 209 | | 1.84 ] ns OR3C/T80 | 1.97] | 1.91 | 228] | 2.02 ] ns OR3T125 _ _ |190] | 257} | 2.29] ns Notes: Timing is without the use of the programmable clock manager (PCM). This clock delay is for a fully routed clock tree that uses the ExpressCLK network. !t includes both the input buffer delay, the clock routing to the PIO CLK input, the clockQ of the FF, and the delay through the output buffer. The given timing requires that the input clock pin be located at one of the six ExpressCLK inputs of the device, and that a PIO FF be used. PIO FF D Q|~P] ouTPuT (60 pF LOAD) CLKCNTAL ecLK [>_> ECLK Lucent Technologies Inc. Figure 76. ExpressCLK to Output Delay S-4846(F).a 125ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Timing Characteristics (continued) Table 55. OR3Cxx Fast Clock (FCLK) to Output Delay (Pin-to-Pin) OR3Cxx Commercial: VOD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, -40 C < TA < +85 C; CL = 50 pF. ORSTxxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C: CL = 50 pF. Descriptio Speed tiption . : (Ts = 85 C, VoD = min) Device 4 5 6 7 Unit Min | Max | Min | Max | Min | Max | Min | Max Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs) ECLK Middle Input Pin ~OUTPUT Pin OR3T20 _ |11.13| | 7.94] | 6.40 | ns (Fast) OR3T30 _ _ |11.35; | 8.01 | 6.48 | ns OR3C/T55 11468) |11.81/ | 8.18 | | 666] ns OR3C/T80 115.30} |12.33|; | 836 | | 685] ns OR3T125 _ _ 7138.20] | 868} | 7.19 | ns ECLK Middle Input Pin ~OUTPUT Pin OR3T20 _ _ |13.12| | 8.61 | 693 | ns (Stewlim) OR3T30 _ _ {13833] | 868} | 7.01 | ns ORSC/T55 |17.41f |13.80) | 885 | | 7.19} ns ORS3C/T80 117.74, |1432; | 9.04) | 7.38] ns OR3T125 _ _ |15.19]| | 9.35] | 7.72 | ns ECLK Middle Input Pin OUTPUT Pin OR3T20 _ _ |14.47| 113.46) | 11.67] ns (Sinklim) OR3T30 _ _ 41468] |1353] | 11.75] ns OR3C/T55 |18.47) |15.15) |13.70] | 11.93] ns OR3C/T80 119.10; |]15.67); |13.88] | 12.12] ns OR3T125 _ _ |16.54) |14.20| | 12.46] ns Additional Delay if ECLK Comer Pin OR3T20 _ _ _ 1.97) 1.82 _ 1.60 | ns Used OR3T30 _ _ |199| | 1.92] | 1.69 | ns OR3C/T55 | 210) | 2.01 | 212] | 1.88] ns OR3C/T80 1214) | 204) | 233 | | 2071] ns OR38T125 _ _ |209|/ | 263] | 239 | ns Notes: Timing is without the use of the programmable clock manager (PCM). This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the PIO CLK input, the clockQ of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not used. The given timing requires that the input clock pin be located at one of the six ExpressCLK inputs of the device and that a PIO FF be used. 126 PIO FF D Q CLKCNTRL ECLK [}->-1p> FCLK LIS] OUTPUT (50 pF LOAD) Figure 77. Fast Clock to Output Delay 5-4846(F).b Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 56. OR3Cxx General System Clock (SCLK) to Output Delay (Pin-to-Pin) OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA<. 70 C; Industrial: VDD = 5.0 V + 10%, -40 C < TA < +85 C; CL = 50 pF. ORSTxxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C; CL = 50 pF. Description Speed i ; A (Ts = 85 C, VoD = min) Device ~4 5 6 7 Unit Min | Max | Min | Max | Min | Max | Min | Max Output On Same Side of Device As Input Clock (System Clock Delays Using General User /O inputs) Clock Input Pin (mid-PIC} ~OUTPUT Pin (Fast)| OR3T20 _ _ (11.35) | 7.74; | 610] ns OR3T30 _ {11.63) | 7.93 | | 627] ns ORSC/T55 | 114.91; [1217] | 828 | | 659] ns ORSC/T80 | |15.71/ |1280) | 866] | 6.95] ns OR3T125 | {13.69} | 9.24) | 7.49) ns Clock Input Pin (mid-PIC) OUTPUT Pin OR3T20 _ |13.341 | 842)! | 663] ns (Stewlim) OR3T30 _ _ |13.62| | 860; | 6.80) ns ORSC/T55 | |17.34) [1416] | 895] | 7.12} ns OR3C/T80 | |18.14) [14.79] | 9.34] | 7.48] ns OR3T125 | _ {15.68} | 991 | | 802] ns Clock Input Pin (mid-PIC) ~OUTPUT Pin OR3T20 _ _ |1469}; |13.26) | 11.37] ns (Sinklim) OR3T30 _ _ |14.97] |13.45}| | 11.54] ns ORSC/T55 | |18.70; [15.51] [13.80] | 11.86) ns OR3C/T8O0 | |19.51) |[16.14) |[14.18| |12.22) ns OR3T125 | |17.03} |14.76; {12.76) ns Additional Delay if Non-mid-PIC Used as Clock | OR3T20 _ _ |}016) | 018} | 0.17] ns Pin OR3T30 _ _ {020| | 0.21) | 0.201 ns ORSC/T55 | |041| | 036) | 0.37} | 0.35] ns OR3C/T80 |} | 063| | 055} | 057] | 0.55] ns OR3T125 | | 1.41] | 1.05 | | 1.02] ns Output Not on Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs) Additional Delay if Output Not on Same Side as | OR3T20 _ _ {0.16/ {018} | 0.17] ns Input Clock Pin ORS3T30 _ _ | 020} {0.21} | 0.201] ns ORSC/T55 +; | 0.41} | 036}; | 037; | 035] ns ORSC/T80 |} | 063} |0.55| 10571 | 055] ns OR3T125 | _ | 1.417) | 1.05 | | 1.02] ns Note: This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the PIO CLK input, the clock>Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the device and that a PIO FF be used. For clock pins located at any other PIO, see the results reported by ORCA Foundry. sc.k (}-{>_p PIO FF D Q +{>(] OuTPUT (50 pF LOAD) 5-4846(F) Figure 78. System Clock to Output Delay Lucent Technologies Inc. 127Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Timing Characteristics (continued) Table 57. OR3C/Txxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin) OR3Cxx Commercial: Vop = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: Vop = 5.0 V + 10%, 40 C < TA < +85 C. OR3Txxx Commercial: Vob = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: Vop = 3.0 V to 3.6 V, -40 C < Ta < +85 C. a Speed Description : (Ta = 85 C, VoD = min) Device 4 5 6 7 Unit Min | Max | Min | Max | Min Max | Min | Max Input to ECLK Setup Time (middle | oOR3T20 ~ _ 1.34 0.88 0.83 ns ECLK pin) ORST30 |} 130; | 086 | | o82/ ns OR3C/T55 | 1.36 _ 1.22 _ 0.83 _ 0.80 _ ns OR3C/T80 | 1.25 _ 1.14 0.80 _ 0.77 ns OR3T125 _ 1.03 0.76 _ 0.74 ns input to ECLK Setup Time (middie | oOR3T20 6.30 5.32 5.98 ns ECLK pin, delayed data input) OR3T30 _ {| 627/ | 530/ | 597; ns OR3C/T55 | 6.91 _ 6.19 _ 5.27 _ 5.95 _ ns OR3C/T80 | 6.79 _ 6.11 5.24 _ 5.93 _ ns OR3T125 _ 6.00 _ 5.20 _ 5.90 _ ns Input to ECLK Setup Time (corner OR3T20 0.00 0.00 0.00 _ ns ECLK pin) OR3T30 | 000} | 000} | 000; ns ORS3C/T55 | 0.00 _ 0.00 _ 0.00 _ 0.00 _ ns OR3C/T80 | 0.00 _ 0.00 0.00 _ 0.00 ns OR38T125 _ _ 0.00 _ 0.00 _ 0.00 _ ns Input to ECLK Setup Time (comer | oOR3T20 _ 4.39 3.51 441 ns ECLK pin, delayed data input) OR3T30 4.35 3.40 4.31 ns ORSC/T55 | 494) | 428] | 318; | 4.11 ns ORS3C/T80 | 4.82 _ 4.21 2.98 _ 3.91 _ ns OR3T125 _ _ 4.10 _ 2.63 3.61 _ ns Input to ECLK Hold Time (middle OR3T20 _ 0.00 0.00 0.00 ns ECLK pin) OR3T30 _ | 000} | 000} | 000; ns OR3C/T55 | 0.00 _ 0.00 _ 0.00 _ 0.00 _ ns OR3C/T80 | 0.00 _ 0.00 _ 0.00 _ 0.00 _ ns OR3T125 _ _ 0.00 _ 0.00 _ 0.00 _ ns Input to ECLK Hold Time (middle OR3T20 0.00 0.00 0.00 ns ECLK pin, delayed data input) OR3T30 _ 0.00 0.00 0.00 _ ns OR3SC/T55 | 0.00} | 0.00/ | 000/ | ooo | ns ORS3C/T80 | 0.00 _ 0.00 _ 0.00 _ 0.00 _ ns OR3T125 | | 000| | 000] | ooo | ns Note: The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry. The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay includes both the input buffer delay and the clock routing to the PIO clock input. 128 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 57. OR3C/Txxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin) (continued) OR3Cxx Commercial: VoD = 5.0 V+ 5%, 0 C < TA< 70 C; Industrial: Vob = 5.0 V + 10%, 40 C < TA < +85 C. OR3Txxx Commercial: VoD = 3.0 V to 3.6 V, 0 C < Ta < 70 C; Industrial: VoD = 3.0 V to 3.6 V, ~-40 C < TA < +85 C. eg Speed Description . ; (Tu = 85 C, VoD = min) Device 5 -7 Unit Min | Max | Min | Max | Min | Max | Min Max Input to ECLK Hold Time (comer OR3T20 _ 0.00 0.00 0.00 ns ECLK pin) OR3T30 | 000] | 000} | Oooo | ns ORSC/T55 | 0.00 _ 0.00 _ 0.80 _ 1.10 ns OR3C/T80 | 0.00 _ 0.00 ~~ 0.00 _ 0.00 _ ns OR3T125 _ _ 0.00 _ 0.00 _ 0.00 _ ns input to ECLK Hold Time (corner OR3T20 _ 0.00 0.00 0.00 ns ECLK pin, delayed data input) OR3T30 | 000|/ | 000} | 000] ns ORSC/T55 | 0.00 _ 0.00 _ 0.00 _ 0.00 _ ns OR3C/T80 | 0.00 0.00 _ 0.00 _ 0.00 _ ns ORST125 _ _ 0.00 _ 0.00 _ 0.00 _ ns Notes: The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry. The ECLK delays are to all of the PlOs on one side of the device for middie pin input, or two sides of the device for comer pin input. The delay includes both the input buffer delay and the clock routing to the PIO clock input. Lucent Technologies Inc. PIO ECLK LATCH INPUT _ [}>p_ a CLKCNTRL CLK ECLK Figure 79. Input to ExpressCLK Setup/Hold Time 5-4847(F).b 129ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Timing Characteristics Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) (continued) ORSCxx Commercial: Vop = 5.0 V+ 5%, 0C <TA< 70 C; Industrial: VoD = 5.0 V + 10%, 40 C < TA < +85 C. ORS3STxxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VoD = 3.0 V to 3.6 V, -40 C < TA < +85 C. _ Speed Description . . (Ts = 85 C, VoD = min) Device 4 5 6 7 Unit Min | Max | Min | Max | Min | Max | Min | Max Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs) Input to FCLK Setup Time (middie OR3T20 _ _ 0.00 0.00 0.00 _ ns ECLK pin) OR3T30 | 000} | 000} | 000] ns OR3C/T55 | 0.00 _ 0.00 _ 0.00 0.00 ns OR3C/T80 | 0.00 _ 0.00 0.00 0.00 _ ns OR3T125 _ 0.00 _ 0.00 _ 0.00 ns Input to FCLK Setup Time (middie OR3T20 _ 0.80 ~ 0.58 _ 2.20 _ ns ECLK pin, delayed data input) OR3T30 _ | 074); | 055] | 217] ns ORSC/T55 | 0.29 0.62 _ 0.51 _ 2.11 _ ns ORSC/T80 | 0.14 _ 0.50 _ 0.46 2.06 ns OR3T125 _ 0.22 _ 0.33 _ 1.90 _ ns Input to FCLK Setup Time (comer OR3T20 0.00 0.00 0.00 ~~ ns ECLK pin) OR3T30 _ _ 0.00 _ 0.00 _ 0.00 ns OR3C/T55 | 0.00 _ 0.00 _ 0.00 _ 0.00 _ ns ORSC/T8O } 0.00 _ 0.00 _ 0.00 _ 0.00 ns OR3T125 _ 0.00 _ 0.00 0.00 _ ns Input to FCLK Setup Time (corner OR3T20 _ 0.00 _ 0.00 0.00 ns ECLK pin, delayed data input) OR3T30 _ 0.00 0.00 _ 0.00 ns ORS3C/T55 | 0.00 _ 0.00 _ 0.00 0.00 ns ORSC/T80 | 0.00 _ 0.00 _ 0.00 _ 0.00 _ ns OR3T125 _ _ 0.00 _ 0.00 _ 0.00 _ ns Input to FCLK Hold Time (middle OR3T20 _ 4.29 3.72 3.27 ns ECLK pin) OR3T30 _ | 450; | 380] | 335] ns OR3C/T55 | 6.33 _ 4.97 ~~ 3.96 _ 3.52 ns OR3C/T80 | 6.95 _ 5.49 _ 4.15 _ 3.72 _ ns OR3T125 _ _ 6.36 _ 4.47 _ 4.05 ns Notes: The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry. The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used. 130 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) (continued) OR3Cxx Commercial: Vop = 5.0 V + 5%, 0 C <TA< 70 C; Industrial: VoD = 5.0 V + 10%, -40 C < TA < +85 C. OR3Txxx Commercial: Vop = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VoD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Description Speed (Ty = 85 C, VoD = min) Device 5 7 Unit Min | Max | Min | Max | Min | Max | Min | Max Input to FOLK Hold Time (middle OR3T20 _ 0.00 0.00 ~_ 0.00 ns ECLK pin, delayed data input) OR3T30 0.00 0.00 0.00 ns ORSC/T55 | 0.00 _ 0.00 0.00 _ 0.00 _ ns ORSC/T80 | 0.00 _ 0.00 _ 0.00 _ 0.00 _ ns OR3T125 _ _ 0.00 _ 0.00 _ 0.00 _ ns Input to FCLK Hold Time (comer OR3T20 6.26 5.54 4.88 ns ECLK pin) OR3T30 | 649} | 572); | 504) ns ORSC/T55 | 8.43 _ 6.98 _ 6.09 _ 5.40 _ ns OR3C/T80 | 9.09 _ 7.53 _ 6.47 _ 5.79 _ ns OR8T125 _ _ 8.45 _ 7.10 _ 6.40 _ ns Input to FOLK Hold Time (corner OR3T20 _ 0.00 0.00 0.00 ns ECLK pin, delayed data input) OR3T30 0.00 0.00 0.00 ns ORSC/T55 } 0.00 _ 0.00 0.00 _ 0.00 ns ORS3C/T80 | 0.00 _ 0.00 _ 0.00 _ 0.00 ns OR3T125 _ _ 0.00 _ 0.00 _ 0.00 _ ns Notes: The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry. The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used. Lucent Technologies Inc. INPUT _ [+-{>__ PIO FF D 6@Q CLKCNTRL Fou? Figure 80. Input to Fast Clock Setup/Hold Time 5-4847(F).a 131ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Timing Characteristics (continued) Table 59. OR3C/Txxx Input to General System Clock (SCLK) Setup/Hold Time (Pin-to-Pin) OR3Cxx Commercial: VoD = 5.0 V + 5%, 0 C < TA< 70 C; Industrial: VoD = 5.0 V + 10%, 40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VoD = 3.0 V to 3.6 V, -40 C < TA < +85 C. sas Speed Description . . (Ty = 85C, Yop = min) Device 5 6 7 Unit Min Max | Min Max |, Min Max | Min Max Input to SCLK Setup Time OR3T20 {| 000} | 000/ | 000] ns OR3T30 _ | 000}; | 000; | 000]; ns ORSC/T55 | 0.00 | | 000} | 000}; | 000} ns orsc/rso | 0.00 | | 000} | 000/ | 000] ns OR3T125 _ | 000; | 000; | 000] ns Input to SCLK Setup Time OR3T20 _ 133} 147} | 309) ns (delayed data input) OR3T30 _ 122} 140| | 303} ns OR3C/T55 | 099} | 109} | 133]; | 297] ns orsc/Tso | 0.79! | 093} | 126] | 2.91 ~ ns OR3T125 _ | 078) | 119| | 286, ns Input to SCLK Hold Time OR3T20 4.74 ~ 3.64 _ 3.04 ns OR3T30 _ | 5.01 | 383/ | 322) ns OR3C/T55 | 6.82} | 556] | 418 | | 354] ns OR3SC/T80 | 7.62} | 619} | 456] | 389; ns OR3T125 | 707}; | 514] | 444], ns input to SCLK Hold Time OR3T20 _ 0.00 0.00 0.00 ns (delayed data input) OR3T30 _ | 000} | 000; | Ooo; ns OR3C/T55 | 0.00} | 0.00} | 000] | 000; ns OR3C/T80 | 0.00} | 000} | 000; | ooo | ns OR3T125 | 000} | 000| | 000; ns Additional Hold Time if Non- OR3T20 _ _ 0.16 _ 0.18 0.17 ns mid-PIC Used as SCLK Pin OR3T30 _ 0.20 _ 0.21 0.20 ns (no delay on data input) OR3C/T55 | 0.41 | 036) | 037{ | 035; ns oRsc/Tso | 063 | | 055| | 057/ | O55] ns OR3T125 | 1441 | 105! | 102}; ns Notes: The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry. This clock delay is for a fully routed clock tree that uses the clock network. It includes both the input buffer delay and the clock routing to the PiO FF CLK input. The delay will be reduced if any of the clock branches are not used. The given setup (delayed and no delay) and hold (delayed) timing allows the input clock pin to be located in any PIO on any side of the device, but a PIO FF must be used. The hold (no delay) timing assumes the clock pin is located at one of the four middle PICs on any side of the device and that a PIO FF is used. If the clock pin is located elsewhere, then the last parameter in the table must be added to the hoid (no delay) timing. 132 INPUT _ E+->_p__ qi ScLK [-{>_D PIO FF 5-4847(F) Figure 81. Input to System Clock Setup/Hold Time Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Configuration Timing Table 60. General Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, 40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Parameter Symbol Min Max Unit All Configuration Modes M[3:0] Setup Time to INIT High TSMODE 0.00 _ ns M[3:0] Hold Time from INIT High THMODE 600.00 _ ns RESET Pulse Width Low to Start Reconfiguration TRW 50.00 _ ns PRGM Pulse Width Low to Start Reconfiguration TPGW 50.00 _ ns Master and Asynchronous Peripheral Modes Power-on Reset Delay TPO 15.70 52.40 ms CCLK Period (M3 = 0) TCCLK 60.00 200.00 ns (M3 = 1) 480.00 1600.00 ns Configuration Latency (autoincrement mode): TCL OR3T20 (M3 = 0) 11.50 38.40* ms (M3 = 1) 92.10 307.00* ms OR3T30 (M3 = 0) 15.10 50.40* ms (M3 = 1) 121.00 403.30* ms ORS3C/T55 (M3=0) 23.20 77.40* ms (M3 = 1) 185.00 619.00* ms ORS3C/T80 (M3 =0) 33.70 113.00* ms (M3 = 1) 270.00 900.00* ms OR3T125 (M3 = 0) 52.30 175.00" ms (M3 = 1) 418.00 1395.00* ms Microprocessor (MPI) Mode Power-on Reset Delay TPO 15.70 52.40 ms Configuration Latency (autoincrement mode): TCL OR3T20 27413 _ write cycles OR3T30 35445 _ write cycles OR3C/T55 53341 _ write cycles OR3C/T80 76317 _ write cycles OR3T125 116581 _ write cycles Partial Reconfiguration (explicit mode): TPR OR3T20 32 _ write cycles OR3T30 36 _ write cycles OR3C/T55 43 _ write cycles OR3C/T80 51 _ write cycles OR3T125 62 _ write cycles Slave Serial Mode Power-on Reset Delay TPO 3.90 13.10 ms CCLK Period TCCLK OR3Cxx 40 _ ns OR3Txxx 15 _ ns Configuration Latency (autoincrement mode): TCL OR3T20 2.80 _ ms OR3T30 3.80 _ ms OR3C55 15.50 _ ms OR3T55 5.80 ms OR3C80 22.50 _ ms OR3T80 8.40 ms OR3T125 13.09 _ ms * Not applicable to asynchronous peripheral mode. Lucent Technologies Inc. 133ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Timing Characteristics (continued) Table 60. General Configuration Mode Timing Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V + 5%, 0C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, 40 C < TA < +85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Parameter Symbol Min Max Unit Slave Parallel Mode Power-on Reset Delay TPO 3.90 13.10 ms CCLK Period: TCCLK OR3Cxx 40.00 _ ns OR3Txxx 15.00 _ ns Configuration Latency (normal mode): TCL OR3T20 0.36 _ ms OR3T30 0.47 ms OR3C55 1.94 ms OR3T55 0.72 _ ms OR3C80 2.81 ms OR3T80 1.05 ms OR3T125 1.64 _ ms Partial Reconfiguration (explicit mode): TPR OR3T20 0.48 _ ys/frame OR3T30 0.54 _ ps/frame OR3C55 1.72 _ us/frame ORS3T55 0.65 _ us/frame OR3C80 2.04 _ us/frame OR3T80 0.77 _ ps/frame OR3T125 0.93 _ us/frame INIT Timing INIT High to CCLK Delay: TINIT_CCLK Slave Parallel 1.00 _ pS Slave Serial 1.00 _ ys Master Serial: (M3 = 1) 1.00 3.40 us (M3 = 0) 0.50 2.00 ys Master Parallel: (M3 = 1) 4.80 16.20 ys (M3 = 0) 1.00 3.60 us Initialization Latency (PRGM high to INIT high): TIL OR3T20 0.21 0.68 ms OR3T30 0.24 0.79 ms ORSC/T55 0.30 1.00 ms OR3C/T80 0.36 1.20 ms OR3T125 0.45 1.50 ms INIT High to WR, Asynchronous Peripheral TINIT_WR 2.00 Us Note: TPO is triggered when Voo reaches between 3.0 V to 4.0 V for the OR3Cxx and between 2.7 V and 3.0 V for the OR3Txxx. 134 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Vpb TPO + TIL __ PRGM = > TeGw nT t TINIT_CLK > . + TCCLK CCLK 7 Pr a THMODE TSMODE M[3:0] f ~t Tet | 5-4531(F) Figure 82. General Configuration Mode Timing Diagram Lucent Technologies Inc. 135ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Timing Characteristics (continued) Table 61. Master Serial Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, 40 C < TA < +85 C. OR3STxxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Parameter Symbol Min Max Unit DIN Setup Time Ts 60.00 ns DIN Hold Time TH 0.00 _ ns CCLK Frequency (M3 = 0) Fe 5.00 16.67 MHz CCLK Frequency (M3 = 1) Fc 0.63 2.08 MHz CCLK to DOUT Delay To _ 5.00 ns * Data gets clocked out from an external serial ROM. The clock to data delay of the serial ROM must be less than the CCLK frequency since the data available out of the serial ROM must be setup and waiting to be clocked into the FPGA before the next CCLK rising edge. Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN. 136 CCLK \ / Ts TH Lt oe 6 ) ( ar DIN BITN To LC. oF DOUT BITN 5-4592(F) Figure 83. Master Serial Configuration Mode Timing Diagram Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 62. Master Parallel Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, 40 C < TA < +85 C, OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VOD = 3.0 V to 3.6 V, 40 C < TA < +85 C. Parameter Symbol Min Max Unit RCLK to Address Valid TAV _ 60.00 ns D[7:0] Setup Time to RCLK High Ts 60.00 _ ns D{7:0] Hold Time to RCLK High TH 0.00 ns RCLK Low Time (M3 = 0) TCL 7.00 7.00 CCLK cycles RCLK High Time (M3 = 0) TCH 1.00 1.00 CCLK cycles RCLK Low Time (M3 = 1) Te. 7.00 7.00 CCLK cycles RCLK High Time (M3 = 1) TCH 1.00 1.00 CCLK cycles CCLK to DOUT Tb 5.00 ns Notes: The RCLK period consists of seven CCLKs for RCLK low and one CCLK for RCLK high. Serial data is transmitted out on DOUT 1.5 CCLK cycles after the byte is input on D[7:0]. rs X x > TcH L { Te. 1K ~< Ts TH D[7:0] v BYTE N BYTEN+1 x CCLK DOUT 5-6764(F) Figure 84. Master Parallel Configuration Mode Timing Diagram Lucent Technologies Inc. 137ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 63. Asynchronous Peripheral Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, 40 C < TA <+85 C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Data Sheet June 1999 Parameter Symbol Min Max Unit WR, CSO, and CS1 Pulse Width TWR 50.00 _ ns D[7:0] Setup Time: Ts 30x 20.00 _ ns 3Txx 10.50 ns D[7:0] Hold Time TH 0.00 _ ns RDY Delay TRDY _ 40.00 ns RDY Low TB 1.00 8.00 CCLK Periods Earliest WR After RDY Goes High" TwR2 0.00 _ ns RD to D7 Enable/Disable TDEN 40.00 ns CCLK to DOUT TD 5.00 ns * This parameter is valid whether the end of not RDY is determined from the RDY pin or from the D7 pin. Notes: Serial data is transmitted out on DOUT on the falling edge of CCLK after the byte is input on D[7:0]. D{6:0] timing is the same as the write data portion of the D7 waveform because D{6:0] are not enabled by RAD. 35 XXXXXXXXXA AXXXXXXA AXXXA 01 XXXXKXKAKY NAXXXXKY XAXXY TwR WR J j |} } Ts at TH >| Twre o SRKXEREK woe RRO TDEN |< TDEN -*+ RD RDY \ 7 < TB 21 TRDY be CCLK To DOUT PREVIOUS BYTE D7 Do x D1 \ p2 xX D3 x -4533(F) Figure 85. Asynchronous Peripheral Configuration Mode Timing Diagram 138 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 64. Slave Serial Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, -40 C < TA < +85 C. OR3Tx0x Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA< 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Parameter Symbol Min Max Unit DIN Setup Time: Ts 3C0xx 20.00 _ ns 3TXXX 10.50 ns DIN Hold Time TH 0.00 _ ns CCLK High Time: TCH 3Cxx 20.00 _ ns 3TxXX 7.00 ns CCLK Low Time: TCL 3Cxx 20.00 _ ns 3TXxx 7.00 _ ns CCLK Frequency: Fe 3Cxx _ 25.00 MHz STXXX _ 66.00 MHz CCLK to DOUT TD _ 20.00 ns Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN. DIN CCLK N DOUT | x BIT N x 5-4535(F). Figure 86. Slave Serial Configuration Mode Timing Diagram Lucent Technologies Inc. 139Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Timing Characteristics (continued) Table 65. Slave Parallel Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0 C < TA < 70 C; Industrial: VDD = 5.0 V + 10%, 40 C < TA < +85 C. ORSTxx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, -40 C < TA < +85 C. Parameter Symbol Min Max Unit CSO, CS1, WR Setup Time Ts1 40.00 ns CS0, CS1, WR Hold Time TH1 20.00 ns D[7:0] Setup Time: Ts2 3Cxx 20.00 _ ns 3TXxx 7.00 _ ns Df[7:0] Hold Time TH2 0.00 _ ns CCLK High Time: TCH 3Cxx 20.00 ns ST Xxx 7.00 ns CCLK Low Time: TCL 3Cxx 20.00 _ ns 3TXXX 7.00 _ ns CCLK Frequency: Fe 3Cxx 25.00 MHz STXxx _ 66.00 MHz Note: Daisy-chaining of FPGAs is not supported in this mode. os XXX X XK KXXXA Ts2 Pt THe a> D{7:0} Y Figure 87. Slave Parallel Configuration Mode Timing Diagram 5-2848(F) 140 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Microprocessor Interface (MPI) Configuration Timing Characteristics For configuration timing using the MPI, consult Table 49. See Figures 67 through 74 for MPI timing diagrams. Lucent Technologies Inc. 141ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Timing Characteristics (continued) Readback Timing Table 66. Readback Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V + 5%, 0C < TA < 70 C; Industrial VDD = 5.0 V + 10%, -40 C < TA < +85 C. OR3Txx Commercial: VDD = 3.0 V to 3.6 V, 0 C < TA < 70 C; Industrial: VDD = 3.0 V to 3.6 V, 40 C < TA < +85 C. Parameter Symbol Min Max Unit RD_CFG to CCLK Setup Time Ts 50.00 _ ns RD_CFG High Width to Abort Readback TRBA 2 CCLK cycles CCLK Low Time TeL 40.00 _ ns CCLK High Time TCH 40.00 _ ns CCLK Frequency Fe _ 12.50 MHz CCLK to RD_DATA Delay To _ 40.00 ns RD_CFG \ Tei n{TS e cox J \ if VF \VS\S VSI VSN | TCH iw TD el | no.oata YXYYXYX, Karo Figure 88. Readback Timing Diagram 5-4536(F) 142 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Input/Output Buffer Measurement Conditions Voc GND TO THE OUTPUT UNDER TEST T. pF TO THE OUTPUT UNDER TEST l A. Load Used to Measure Propagation Delay B. Load Used to Measure Rising/Falling Edges Note: Switch to Voo for TPLz/TPzt; switch to GND for TPHZ/TPZH. 50 pF -3234(F) Figure 89. ac Test Loads tsfil outfi} go ac TEST LOADS (SHOWN ABOVE) Vbb out{i] voore fh PAD i5y =a OUT gov TPLL _ ol rows -3233.a(F) Figure 90. Output Buffer Delays PAD +H > inf] 3.0V PADIN 1.5V 0.0V Vop in{i] Voo/2 Vss >|TPHH 5-3235(F)} Figure 91. Input Buffer Delays Lucent Technologies Inc. 143Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Output Buffer Characteristics OR3Cxx 70 T T T T 50 T T T I ef i boot | ky TTT 41 e Ter int i | Ai & oe ~L Ie LJ es 5 oF - -A------ Fe iw | | | | & | | | c ceenoe tft E 20 Loe HS + 4 E 6 | | o pw AL ~L ro - i 0 A | | | 0 1 l L l 0 l l i l 0 1 2 3 4 0 1 2 3 4 5 OUTPUT VOLTAGE, Vo (V) OUTPUT VOLTAGE, Vo (V) 5-4634(F) 5-4635(C) Figure 92. Sinklim (Tu = 25 C, Vpp = 5.0 V) Figure 95. Sinklim (Ty = 125 C, Vob = 4.5 V) 250 7 T T T 150 T T T T 2 - tT mh = -4 oe PTT le TT wt LF _LTTe Li < 7 T | | | | | oe ne nn 8 10 + ++--4+4 ot Y_1 |__| @toiZAl bil. S | | | 5 | | | Co 10k f-- - - - - 2 ash StS ed 2 9 ~+-+- = 7 5 lon 3 50+ te } 4 Oo | | | ar ee __ = at/ + |l I H A] | | | 0 l i L ! 0 l | ! i 0 1 2 3 4 0 1 2 3 4 OUTPUT VOLTAGE, Vo (V) OUTPUT VOLTAGE, Vo (V) 5-4636(F) -4637(F) Figure 93. Slewlim (Ty = 25 C, Vop = 5.0 V) Figure 96. Siewlim (TJ = 125 C, Vpp = 4.5 V) 250 T T T I 175 T T T T 2st ++s = + + x wot - !__I__L | g MrF- +t Y-+t-+7-7 z | | ; E we-+A-+-+-- E 1st + |- Fr 4 a ns E ot 1A _I-_L | & wp Yo to to to 3 Ale 2 _ __ i _f ~ tor ~ta-t +74 0 75- 7 | [- Fp ft tO RS TT E sok -|-_L. Op f+ + ~ + KR 7 3 1 md at/-+-+-+-+ 5 ap faa aN o t t 1 L 0 ! ! ! l 0 1 2 3 4 5 0 1 2 3 4 OUTPUT VOLTAGE, Vo (V) oO 5-4638(F) OUTPUT VOLTAGE, Vo (V) 46205 Figure 94. Fast (Ti = 25 C, Vpp = 5.0 V) Figure 97. Fast (Tu = 125 C, Vp = 4.5 V) 144 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Output Buffer Characteristics (continued) OR3Txxx o ' ' ' ' o i ' a a ' t t ' t 1 1 a , 2 = ate we ole ee ee he wie = He ame w t t t ' 1 d u ' N 13 1 . ' 1 t t t ' ' ' 1 t t -~< = she = ete eb we he le ste ewe tee a 4 1 a, 1 ' ' ' ' 1 2 ' 1 1 1 ' ' ' 1! eek ce we tw et dw eh afte @ eho we te we wy ' ' . t t ' ' 5 7 a a t 1 ' ' ' ' a t ' a ee ee -- en i= ' ' ' ' 7 t t t t ' 1 t a t i} i ' t wk ah te oe fe ow CI ee ee FD 1 ' ' t ' o 1 t 1 1 ' ' ' ' ' ' 4 ' i 1 ' QoQ 1 : 1 1 : So 88R @BFBAR SS (vw) 4 LNAYYND LNdLNO 0 ' ' 1 t t i ' - ' ' ' ' 4 Joe ck be ho Lk al lt fo ' ' ' ' ' ' ' ' 1 oO 19) ' ' ' ' free A tee 8 ' ' a a) Gi ' 1 ' ' ' 12 ' t ' ' Peete eb be tf be te ee SD ' ' 1 1 ' N ' ' ' ' t 1 t rarer iefiece crac ce [8 ' + , ' ! , ' ' a ' ' ' t t ' ete ele ne be Waele eh ew de ete et HPO ' ' ' 1 1 ' - ' ' ' ' ' ' oye fescce Magee or 18 ' ' ' ' ' t ' ' 1 ' ' ' ' ' ' ' ' o 1 1 1 2 . o egegsesageaRaee (vw) 0} LNAYYND LNdLNO 5-6866(F) 125 C, Vop = 3.0 V) OUTPUT VOLTAGE, Vo (V) 5-6865(F) 3.3 V) OUTPUT VOLTAGE, Vo (V) Figure 101. Sinklim (Ty 25 C, VoD = Figure 98. Sinklim (Ty t ' ' ' ' 0 ' ' t ' ' ' t t wo ode te ww nt ete tb we - Fj ' ' ' 3 ' 1 5: 1 ' ' ia a we ee ew te ee ete ew few bee ed SO ' ' ' 4 N ' ' ' wee ae Note ee ete Je eee eee PO 1 1 ' ' - t ' ' ' ' ' t ' eee de ew lee pee ee ee ee ee LO ' ' ' r ' ' t ' 1 ' t ' a ee Penn woh ee FO t ' ' ' ' ' 1 ' ' t t 1 1 . o gs 8 8 & (yuu) ] LNAYYND LNdLNO in ' t ' ' ' 36 1 ' ' ' 1 o 3B ' 15 ' , ' 1 1 ' wn emer ae cere corsets tha ' ' ' ' t ' ' ' A ete eee f-- 4 See eben tee fe 1 N 1 1 ' ' ' ' ' se ee 9 crew r er ger rr TT t a ' ' 1 ' ' ee te PP ON ee eee te PS ' 1 4 ' ' - ' ' t 1! a ' t wn cepa err rt ae TAT mds ' 1 ' i 1 t ' ' ' o 1 rs + 4 2 o e2 88 8 Rk O (yi) Of LNAYYND LNdLAO 5-6868(F) OUTPUT VOLTAGE, Vo (V) 3.0 V) 5-6967(F) 3.3 V) OUTPUT VOLTAGE, Vo (V) 125 C, VDD = Figure 102. Slewlim (Ts 25 C, VDD = Figure 99. Slewlim (TJ 9 ' ' ' om 1 ' ' 1 t ' ' 1 w ele rer rrr tr rte mola Byi tk BS ~o Noe. tee bee feed 1 9 ' 4 1 N v i ' i ' ' 1 ' i ' eee ee eee et efow see eae tO ' ' ' 7 v ' ' ' we eteret Xe ctee tee [2 , ro 1 ' wn Te TR TT NS TTT LS 1 t ' 1 i v 1 ' fo] amnion 4 L 4 1 o ge 8 8 &@ @ & (vu) OF LNAYYND LNdLNO 9 ' 1 ' ', ' oO t a ' ' ' ' pete be ee ee et eT. S gi Be ' 1 ' ' wo Tyr TTP TT aS mgt yr nN ' 1 ' i t ' ' 1 ' ' ' elif gee eee | ' i ' t ' 1 Tr ' t 1 ' ' we tee Pee ee bet ef ' ' i ' c ' ' 1 ' t ' wee eph ede e PEN ee [8 ' i , ' d ' ' ' t Oo _ 1 1 1 . o #8 8 8 8 @< & (vu) 0) INAHHNO LAdLNO OUTPUT VOLTAGE, Vo (V) OUTPUT VOLTAGE, Vo (V) 5-6868(F) 3.0 V) 5-6867(F} Figure 103. Fast (TJ = 125 C, Vop 3.3 V) Figure 100. Fast (Ty = 25 C, Vop Lucent Technologies Inc. 145ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Estimating Power Dissipation OR3Cxx The total operating power dissipated is estimated by summing the standby (!DDsB), internal, and external power dissipated. The internal and external power is the power consumed in the PLCs and PICs, respec- tively. In general, the standby power is smail and may be neglected. The total operating power is as follows: PT = 2 PPLC + = PPiC The internal operating power is made up of two parts: clock generation and PFU output power. The PFU out- put power can be estimated based upon the number of PFU outputs switching when driving an average fan-out of two: PPFU = 0.186 mW/MHz For each PFU output that switches, 0.186 mW/MHz needs to be multiplied times the frequency (in MHz) that the output switches. Generally, this can be esti- mated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. The power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/clock branch row or column, the clock power dis- sipated in each PFU that uses this particular clock, and the power from the subset of those PFUs that are con- figured as synchronous memory. Therefore, the clock power can be calculated for the four parts using the fol- lowing equations: OR3C55 Clock Power P = [0.183 mW/MHz + (0.235 mW/MHz/Branch) (# Branches) + (0.083 mW/MHz/PFU) (# PFUs) + (0.008 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3C55 clock power = 14.64 mW/MHz. OR3C80 Clock Power P = [0.224 mW/MHz + (0.288 mW/MHz/Branch) (# Branches) + (0.033 mW/MHz/PFU) (# PFUs) + (0.008 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3C80 clock power = 21.06 mW/MHz. The power dissipated in a PIC is the sum of the power dissipated in the four PlOs in the PIC. This consists of power dissipated by inputs and ac power dissipated by outputs. The power dissipated in each PIO depends on whether it is configured as an input, output, or input/ 146 output. If a PIO is operating as an output, then there is a power dissipation component for P!n, as well as Pout. This is because the output feeds back to the input. The power dissipated by a TTL input buffer is estimated as: PTTL = 2.2 mW + 0.17 mW/MHz The power dissipated by an input buffer is estimated as: PCMOS = 0.17 mW/MHz The ac power dissipation from an output or bidirec- tional is estimated by the following: PouT = (CL + 8.8 pF) x VoD? x F Watts where the unit for CL is farads, and the unit for F is Hz. As an example of estimating power dissipation, sup- pose that a fully utilized OR3C55 has an average of six outputs for each of the 324 PFUs, that 10 clock branches are used so that the clock is driven to the entire PLC array, that 150 of the 324 PFUs have FFs clocked at 40 MHz, and that the PFU outputs have an average activity factor of 20%. Twenty TTL-configured inputs, 20 CMOS-configured inputs, 32 outputs driving 30 pF loads, and 16 bidirec- tional 1/Os driving 50 pF loads are also generated from the 40 MHz clock with an average activity factor of 20%. Ali of the output PlOs are registered, and 30 of the input PlOs are registered. The worst-case (VDD = 5.25 V) power dissipation is estimated as follows: 324 x 6 (0.136 mW/MHz x 20 MHz x 20%) 1057.54 mW = [0.183 MW/MHz + (0.235 mW/MHz Branch) (10 Branches) + (0.033 mW/MHz PFU) (150 PFUs) + (0.008 mW/MHz/PIO (58 PIOs)] = 317.88 mW = 20 x [2.2 mW + (0.17 mW/MHz x 20 MHz x 20%)] = 57.6 mW Pcmos = 20 x [0.17 mW x 20 MHz x 20%] = 13.6 mW = 32 x [(30 pF + 8.8 pF) x (5.25)* x 20 MHz x 20%] = 136.89 mW PBip == 16 x [(50 pF + 8.8 pF) x (5.25)* x 20 MHz x 20%] = 103.72 mW Tota =1.69W PPFu PCLK PTTL PouT Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Estimating Power Dissipation (continued) OR3Txxx (Preliminary Information) The total operating power dissipated is estimated by summing the standby (!opss), internal, and external power dissipated. The internal and external power is the power consumed in the PLCs and PICs, respec- tively. In general, the standby power is small and may be neglected. The total operating power is as follows: PT == PPLc + = PPIC The internal operating power is made up of two parts: clock generation and PFU output power. The PFU out- put power can be estimated based upon the number of PFU outputs switching when driving an average fan-out of two: PPFU = 0.068 mW/MHz For each PFU output that switches, 0.068 mW/MHz needs to be multiplied times the frequency (in MHz) that the output switches. Generally, this can be esti- mated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. The power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/clock branch row or column, the clock power dis- sipated in each PFU that uses this particular clock, and the power from the subset of those PFUs configured as synchronous memory. Therefore, the clock power can be calculated for the four parts using the following equations. OR3T20 Clock Power P = [0.38 mW/MHz + (0.045 mW/MHz/Branch) (# Branches) + (0.015 mW/MHz/PFU) (# PFUs) + (0.004 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3T20 clock power = 2.92 mW/MHz. OR3T30 Clock Power P = [0.53 mW/MHz + (0.061 mW/MHz/Branch) (# Branches) + (0.015 mW/MHz/PFU) (# PFUs) + (0.004 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3T30 clock power = 3.98 mW/MHz. Lucent Technologies Inc. OR3T55 Clock Power P = [0.88 mW/MHz + (0.102 mW/MHz/Branch) (# Branches) + (0.015 mW/MHz/PFU) (# PFUs) + (0.004 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) ORS8T55 clock power = 6.58 mW/MHz. OR3T80 Clock Power P = [0.107 mW/MHz + (0.124 mW/MHz/Branch) (# Branches) + (0.015 MW/MHz/PFV) (# PFUs) + (0.004 mW/MHz/PIO (# PiOs)] For a quick estimate, the worst-case (typical circuit) ORS8T80 clock power = 9.47 mW/MHz. OR3T125 Clock Power P = [0.167 mW/MHz + (0.193 mW/MHz/Branch) (# Branches) + (0.015 mW/MHz/PFU) (# PFUs) + (0.004 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3T125 clock power = 15.44 mW/MHz. The power dissipated in a PIC is the sum of the power dissipated in the four PlOs in the PIC. This consists of power dissipated by inputs and ac power dissipated by outputs. The power dissipated in each PIO depends on whether it is configured as an input, output, or input/ output. If a PIO is operating as an output, then there is a power dissipation component for PIN, as well as Pout. This is because the output feeds back to the input. The power dissipated by an input buffer (ViIH = VDD 0.3 V or higher) is estimated as: PIN = 0.09 mW/MHz The ac power dissipation from an output or bidirec- tional is estimated by the following: Pout = (CL + 8.8 pF) x VDD? x F Watts where the unit for CL is farads, and the unit for F is Hz. 147Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Estimating Power Dissipation (continued) As an example of estimating power dissipation, suppose that a fully utilized OR3T80 has an average of six outputs for each of the 484 PFUs, that 12 clock branches are used so that the clock is driven to the entire PLC array, that 250 of the 484 PFUs have FFs clocked at 40 MHz, and that the PFU outputs have an average activity factor of 20%. Eighty inputs, 40 of them used as 5 V tolerant inputs, 50 outputs driving 30 pF loads, and 30 bidirectional I/Os driving 50 pF loads are also generated from the 40 MHz clock with an average activity factor of 20%. All of the output PlOs are registered, and 30 of the input PlIOs are registered. The worst-case (VDD = 3.6 V) power dissipation is estimated as follows: PpFu = 484x 6 (0.068 mW/MHz x 20 MHz x 20%) = 789.9 mW PctK = [0.107 mW/MHz + (0.09 mW/MHz Branch) (12 Branches) + (0.015 mW/MHz PFU) (250 PFUs) + (0.004 mW/MHz/PIO) (110 PIOs)} = 230.43 mW PIN = 80 x [0.09 mW/MHz x 20 MHz x 20%] = 28.8 mW Pout =50 x [(30 pF + 8.8 pF) x (3.6)? x 20 MHz x 20%] = 100.57 mw PaID == 30 x [(50 pF + 8.8 pF) x (3.6)? x 20 MHz x 20%] = 91.45 mW TOTAL = 1.241 W 148 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin information Pin Descriptions This section describes the pins found on the Series 3 FPGAs. Any pin not described in this table is a user-program- mable 1/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled after configuration. Table 67. Pin Descriptions Symbol! VO Description Dedicated Pins VDD | Positive power supply. GND | Ground supply. Vpp5 | 5 V tolerant select. VDD5 pin locations are shown for package compatibility with OR2TxxA devices. Connections to 5 V power sources are not used for 5 V tolerant /Os in the OR3Txxx devices. RESET | | During configuration, RESET forces the restart of configuration and a pull-up is enabled. After configuration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC latches/FFs to be asynchronously set/reset. CCLK | | In the master and asynchronous peripheral modes, CCLK is an output which strobes configuration data in. In the slave or synchronous peripheral mode, CCLK is input synchronous with the data on DIN or D[7:0]. In microprocessor mode, CCLK is used internally and output for daisy-chain operation. DONE | | As an input, a low level on DONE delays FPGA start-up after configuration (see Note). O | Asan active-high, open-drain output, a high level on this signal indicates that config- uration is complete. DONE has an optional pull-up resistor. PRGM | | PRGM is an active-low input that forces the restart of configuration and resets the boundary-scan circuitry. This pin always has an active pull-up. RD_CFG | | This pin must be held high during device initialization until the INIT pin goes high. This pin always has an active pull-up. During configuration, RD_CFG is an active-low input that activates the TS_ALL func- tion and 3-states all of the I/O. After configuration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on RD_CFG will initiate readback of the configuration data, including PFU output states, starting with frame address 0. RD_DATA/TDO O | RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides con- figuration data out. if used in boundary scan, TDO is test data out. Special-Purpose Pins MoO, M1, M2 | | During powerup and initialization, MOM2 are used to select the configuration mode with their values latched on the rising edge of INIT; see Table 34 for the config- uration modes. During configuration, a pull-up is enabled. /O | After configuration, these pins are user-programmable I/O (see Note). Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options. Lucent Technologies Inc. 149Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Pin Information (continued) Table 67. Pin Descriptions (continued) Symbol vO Description Special-Purpose Pins (continued) M3 | | During powerup and initialization, M3 is used to select the speed of the internal oscillator dur- ing configuration with their values latched on the rising edge of INIT. When M3 is low, the oscillator frequency is 10 MHz. When M3 is high, the oscillator is 1.25 MHz. During configura- tion, a pull-up is enabled. \/O | After configuration, this pin is a user-programmable I/O pin (see Note). TDI, TCK, | | If boundary scan is used, these pins are test data in, test clock, and test mode select inputs. If TMS boundary scan is not selected, all boundary-scan functions are inhibited once configuration is complete. Even if boundary scan is not used, either TCK or TMS must be held at logic 1 dur- ing configuration. Each pin has a pull-up enabled during configuration. V/O | After configuration, these pins are user-programmable 1/O (see Note). RDY/RCLK/ | O | During configuration in peripheral mode, RDY/RCLK indicates another byte can be written to MPI_ALE the FPGA. If a read operation is done when the device is selected, the same status is also available on D7 in asynchronous peripheral mode. | During the master parallel configuration mode, RCLK is a read output signal to an external memory. This output is not normally used. 1 | In 960 microprocessor mode, this pin acts as the address latch enable (ALE) input. 1/O | After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). HDC O | High During Configuration is output high until configuration is complete. It is used as a control output, indicating that configuration is not complete. \/O | After configuration, this pin is a user-programmable I/O pin (see Note). LDC | Low During Configuration is output low until configuration is complete. It is used as a control out- put, indicating that configuration is not complete. V/O | After configuration, this pin is a user-programmable I/O pin (see Note). INIT V/O | INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is enabled, but an external pull-up resistor is recommended. As an active-low open-drain out- put, INIT is held low during power stabilization and internal clearing of mernory. As an active- low input, INIT holds the FPGA in the wait-state before the start of configuration. /O | After configuration, this pin is a user-programmable I/O pin (see Note). Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options. 150 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 67. Pin Descriptions (continued) Symbol | I/O Description Special-Purpose Pins (continued) CS0, CS1 | | CSO and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During config- uration, a pull-up is enabled. \/O | After configuration, these pins are user-programmable I/O pins (see Note). RD/ |_| RD is used in the asynchronous peripheral configuration mode. A low on RD changes D7 into MPI_STRB a Status output. As a status indication, a high indicates ready, and a low indicates busy. WR and RD should not be used simultaneously. If they are, the write strobe overrides. | | This pin is also used as the microprocessor interface (MPI) data transfer strobe. For PowerPC, it is the transfer start (TS). For (960, it is the address/data strobe (ADS). I/O | After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). WR | | WR is used in the asynchronous peripheral configuration mode. When the FPGA is selected, a low on the write strobe, WR, loads the data on D[7:0] inputs into an internal data buffer. WR and RD should not be used simultaneously. If they are, the write strobe overrides. (/O | After configuration, this pin is a user-programmabie I/O pin (see Note). A[17:0] | During master parallel configuration mode, A[17:0] address the configuration EPROM. In microprocessor interface (MPI) mode, many of the A[n] pins have alternate uses as described below. See the Special Function Blocks section for more MPI information. During configura- tion, if not in master parallel or an MPI configuration mode, these pins are 3-stated with a pull- up enabled. I/O | After configuration, the pins are user-programmable I/O pins (see Note). Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options. Lucent Technologies Inc. 151ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Pin Information (continued) Table 67. Pin Descriptions (continued) Symbol vO Description Special-Purpose Pins (continued) A11/MPI_IRQ O VO MP! active-low interrupt request output. After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). A10/MPI_BI O VO PowerPC mode MPI burst inhibit output. After configuration, if the MPI is not used, this pin is a user-programmablie VO pin (see Note). AQ/MPI_ACK O VO In PowerPC mode MPI operation, this is the active-high transfer acknowledge (TA) output. For i960 MPI operation, it is the active-low ready/record (RDYRCV) output. After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). A8/MPI_RW VO In PowerPC mode MPI operation, this is the active-low write/active-high read control signals. For i960 operation, it is the active-high write/active-low read control signal. After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). A7/MPI_CLK VO This is the clock used for the synchronous MP! interface. For PowerPC, it is the CLKOUT signal. For i960, it is the system clock that is chosen for the i960 external bus interface. After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). A[4:0] VO For PowerPC operation, these are the PowerPC address inputs. The address bit mapping (in PowerPC/FPGA notation) is A[31/A[0], A[SOVA[1], A[29/A[2], A[28V/A[3], A[27V/A[4]. Note that A[27]//A[4] is the MSB of the address. The A[4:2] inputs are not used in i960 MPI mode. After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note). A[1:0)/ MP1_BE[1:0] vO For i960 operation, MPI_BE[1:0] provide the {960 byte enable signals, BE[1:0], that are used as address bits A[1:0] in i960 byte-wide operation. After configuration, if the MPI is not used, this pin is a user-programmable V/O pin (see Note). D[7:0] VO During master parallel, peripheral, and slave parallel configuration modes, D[7:0] receive configuration data, and each pin has a pull-up enabled. During serial configuration modes, DO is the DIN input. D[7:0] are also the data pins for PowerPC microprocessor mode and the address/data pins for i960 microprocessor mode. After configuration, the pins are user-programmable I/O pins (see Note). DIN vO During slave serial or master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the DO input. Dur- ing configuration, a pull-up is enabled. After configuration, this pin is a user-programmable I/O pin (see Note). DOUT oO Vo During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained slave LCA devices. Data out on DOUT changes on the falling edge of CCLK. After configuration, DOUT is a user-programmabile I/O pin (see Note). Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user [/Os) is controlled by a second set of options. 152 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Package Compatibility Table 68 provides the number of user I/Os available for the ORCA Series 3 FPGAs for each available package. Each package has six dedicated configuration pins. Tables 7075 provide the package pin and pin function for the ORCA Series 3 FPGAs and packages. The bond pad name is identified in the PIC nomenclature used in the ORCA Foundry design editor. When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device pad column for the FPGA. The tables provide no information on unused pads. Table 68. ORCA I/Os Summary Device 208-Pin 240-Pin 256-Pin 352-Pin 432-Pin 600-Pin SQFP/SQPF2 | SQFP/SQFP2 PBGA PBGA EBGA EBGA OR3T20 User i/Os* 171 192 192 192 _ VDD/VSs 31 40 26 48 _ Configuration 6 6 6 6 _ _ Unused 0 2 32 106 _ OR3T30 User V/Os* 171 192 221 224 _ VDD/VSS 31 40 26 48 _ Configuration 6 6 6 6 _ _ Unused 0 2 3 74 _ ORSC/T55 User 1/Os* 171 192 223 288 _ _ VDD/Vss 31 42 26 48 _ Configuration 6 6 6 6 _ _ Unused 0 0 1 10 _ OR3C/T80 User /Os* 171 192 _ 298 342 _ VDD/VSS 31 42 _ 48 84 _ Configuration 6 6 _ 6 6 _ Unused 0 0 _ 0 0 OR3T125 User I/Os* 171 192 _ 298 342 448 VDD/VSS 31 42 _ 48 84 140 Configuration 6 6 _ 6 6 6 Unused 0 0 _ 0 0 6 *User I/O count includes four ExpressCLK inputs. Lucent Technologies Inc. 153Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Pin Information (continued) Compatibility with OR2C/TxxA Series The pinouts shown for the OR3Cxx and OR3T devices are consistent with the OR2C/TxxA Series for all devices offered in the same packages. This includes the following pins: VpD, Vss, VOD5 (OR2TxxA Series only), and all configuration pins. The following restrictions apply: 1. There are two configuration modes supported in the OR2C/TxxA Series that are not supported in Series 3: mas- ter parallel down and synchronous peripheral modes. The Series 3 FPGAs have two new microprocessor inter- face (MPI) configuration modes that are unavailable in the OR2C/TxxA Series. . There are four pinsone per each device sidethat are user I/O in the OR2C/TxxA Series which can only be used as fast dedicated clocks or global inputs in Series 3. These pins are also used to drive the ExpressCLK to the I/O FFs on their given side of the device. These four middle ExpressCLK pins should not be used to connect to a programmable clock manager (PCM). A comer ExpressCLK input should be used instead (see item 3 below). See Table 69 for a list of these pins in each package. . There are two other pins that are user 1/O in both the OR2C/TxxA and Series 3 but also have optional added functionality. Each of these pins drives the ExpressCLKs on two sides of the device. They also have fast connec- tivity to the programmable clock manager (PCM). See Table 69 for a list of these pins in each package. Table 69. Series 3 ExpressCLK Pins Pin Name/ 208-Pin 240-Pin 256-Pin 352-Pin 432-Pin 600-Pin Package SQFP/SQFP2| SQFP/SQFP2 PBGA PBGA EBGA EBGA I-ECKL 22 26 K3 N2 R29 U33 1l-ECKB 80 91 wii AE14 AH16 AM18 I-ECKR 131 152 K18 N23 T2 V2 |-ECKT 178 207 B11 B14 C15 C17 //O-SECKLL 49 56 wi AB4 AG29 AK34 /O-SECKUR 159 184 A19 A25 D5 D5 154 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Tabie 70. OR3T20, OR3T30, OR3SC/T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout OR3T20 OR3T30 OR3C/T55 OR3C/T80 OR3T125 Pin Pad Pad . Pad Pad Pad Function 1 Vss Vss Vss Vss Vss Vss 2 Vss Vss Vss Vss Vss Vss 3 PL1D PL1D PL1iD PLiD PLID vO 4 PLIA PL2D PL2D PL2D PL2D 1/O-A0/MPI_BEO 5 PL2D PL4D PL3D PL4D PL4D VO 6 PL2C PL5D PL3A PL4A PL5D vO 7 PL2A PL7D PL4A PL5A PL7D V/O-A1/MPI_BE1 8 PL3D PL8A PL5A PL6A PL8A VO-A2 9 PL3C PLOD PL6D PL7D PL9D vO 10 PL3B PLOB PL6B PL7B PL9B vO 11 PL3A PLOA PL6A PL7A PL9A /O0-A3 12 Vpp Vop VoD Vpp Vpp Vppb 13 PL4D PL10D PL7D PL8D PL10D vO 14 PL4C PLi0A PL7C PL8A PL10A vO 15 PL4B PL11D PL7B PL9D PL11D vO 16 PL4A PL11A PL7A PL9B PLI1A VO-A4 17 PL5D PL12D PL8D PL9A PL12D VO-A5 18 PL5C PL12A PL8C PL10C PL12A vO 19 PL5B PL13D PL8B PL10B PL13D vO 20 PL5A PL13A PL8A PL10A PL13A 1/0-A6 21 Vss Vss Vss Vss Vss vss 22 PECKL PECKL PECKL PECKL PECKL I-ECKL 23 PL6C PL14C PL9C PL11C PL14C vO 24 PL6B PL14B PL9B PL11B PL14B vO 25 PL6A PL14A PLOA PLI1A PL14A 1/O-A7/MPI_CLK 26 VDD Vobb Vpb VDD Vppb VoD 27 PL7D PL15D PLiOD PL12D PL15D VO 28 PL7C PL15C PL10C PL12C PL15C vO 29 PL7B PL15B PL10B PL12B PLi5B VO 30 PL7A PL15A PLIOA PL12A PL15A i/0-A8/MPI_RW 31 Vss Vss Vss Vss Vss Vss 32 PL8D PL16D PL11D PL13D PL16D 1/O-A9/MPI_ACK 33 PL8C PLI6A PL11C PL13B PLI6A VO 34 PL8B PL17D PL11B PLI3A PL17D vO 35 PL8A PL17A PLI1A PL14C PL17A VYO-A10/MPI_BI 36 PL9D PL18D PL12D PL14B PL18D vO 37 PL9C PL18A PL12C PL15C PL18A vO 38 PL9OB PL19D PL12B PL15B PL19D vO 39 PL9A PL19A PL12A PL15A PL19A /O-A11/MPI_IRQ Lucent Technologies Inc. 155ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Pin Information (continued) Table 70. OR3T20, OR3T30, ORSC/T55, ORSC/T80, and OR3T125, 208-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 ORSC/T55 OR3C/T80 OR3T125 Pin Pad Pad Pad Pad Pad Function 40 Vob VpD VDD VbbD Vpb Vpp 41 PL10D PL20D PL13D PL16D PL20D V/O-A12 42 PL10C PL20B PL13B PL16B PL20B 1/0 43 PL10B PL21D PL14D PL17D PL21D 1/0 44 PL10A PL21B PL14B PL17B PL21B V/O-A13 45 PL11D PL22D PL15D PL18D PL22D /O 46 PL1I1A PL24A PL16D PL19D PL24A /O-A14 47 PL12D PL26D PL17D PL20D PL26D VO 48 PL12C PL27D PLI7A PL21D PL27D 1/0 49 PL12B PL27A PL18C PL21A PL27A /O-SECKLL 50 PL12A PL28A PL18A PL22A PL28A VO-A15 51 Vss Vss Vss Vss Vss Vss 52 PCCLK PCCLK PCCLK PCCLK PCCLK CCLK 53 Vss Vss Vss Vss Vss Vss 54 Vss Vss Vss Vss Vss Vss 55 PBIA PBIA PB1IA PBIA PB1A V/O-A16 56 PB1iB PB2A PB1iD PB2A PB2A VO 57 PB1C PB2D PB2A PB2D PB2D VO 58 PB1D PB3D PB2D PB3D PB3D VO 59 PB2A PB4D PB3D PB4D PB4D /O-A17 60 PB2D PB5D PB4D PB5D PB5D 0 61 PB3A PB6D PB5B PB6B PB6D 0 62 PB3B PB7D PB5D PB6D PB7D VO 63 PB3C PB8D PB6B PB7B PB8D VO 64 PB3D PB9D PB6D PB7D PBSD /O 65 Vbb Vpp Vop Vop VpD VDD 66 PB4A PB10A PB7A PB8A PB10A vO 67 PB4B PB10D PB7B PB8D PB10D VO 68 PB4C PB11A PB7C PB9A PB11A VO 69 PB4D PB11D PB7D PB9C PB11D /O 70 PB5A PB12A PB8A PB9D PB12A vO 71 PB5B PB12D PB8B PB10A PB12D @) 72 PB5C PB13A PB8C PB10B PB13A VO 73 PB5D PB13D PB8D PB10D PB13D vO 74 Vss Vss Vss Vss Vss Vss 75 PB6A PB14A PB9A PB11A PB14A VO 76 PB6B PB14B PB9B PB11B PB14B VO 77 PB6C PB14C PBSC PB11C PB14C 9) 78 PB6D PB14D PBSD PB11D PB14D VO 156 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 70. OR3T20, OR3T30, ORSC/T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 ORSC/T55 OR3C/T80 OR3T125 Pin Pad Pad Pad Pad Pad Function 79 Vss Vss Vss Vss Vss Vss 80 PECKB PECKB PECKB PECKB PECKB l-ECKB 81 PB7B PB15B PB10B PB12B PB15B V/O 82 PB7C PB15C PB10C PB12C PB15C vO 83 PB7D PB15D PB10D PB12D PB15D VO 84 Vss Vss Vss Vss Vss Vss 85 PB8A PBi6A PBI1A PBi3A PB16A vO 86 PB8B PB16D PB11B PB13B PBi6D /O 87 PB8C PB17A PB11C PB13C PB1I7A VO 88 PB8D PB17D PB11D PB14A PB17D 0 89 PB9A PB18A PB12A PB14B PB18A V/O-HDC 90 PB9B PB18D PB12B PB14D PB18D /O 91 PB9C PB19A PB12C PB15A PB1i9A VO 92 PBSD PB19D PB12D PB15D PB19D VO 93 VDD Vob Vob VDD VDD VoD 94 PB10A PB20A PB13A PBi6A PB20A i/O-LDC 95 PB10B PB21D PB13D PB16D PB21D VO 96 PB10C PB22A PB14A PBi7A PB22A 0 97 PB10D PB23D PBi4D PB17D PB23D VO 98 PB11A PB24A PB15A PB18A PB24A VO-INIT 99 PB11C PB25A PB16A PBi9A PB25A /O 100 PB11D PB26A PB17A PB20A PB26A VO 101 PB12A PB27D PB18A PB21D PB27D vO 102 PB12D PB28D PB18D PB22D PB28D VO 103 Vss Vss Vss Vss Vss Vss 104 PDONE PDONE PDONE PDONE PDONE DONE 105 Vss Vss Vss Vss Vss Vss 106 PRESEIN PRESEIN PRESEIN PRESETN PRESETN RESET 107 PPRGMN PPRGMN PPRGMN PPRGMN PPRGMN PRGM 108 PR12A PR28A PR1I8A PR22A PR28A VO-MO 109 PR12D PR27A PR18D PR21A PR27A iO 110 PRI1A PR26A PR17B PR20A PR26A VO 111 PR11B PR25A PRi6A PR19A PR25A /O 112 PR10A PR22D PR15D PR18D PR22D /O-M1 113 PR10B PR21A PR14A PR17A PR21A /O 114 PR10C PR2iD PR14D PR17D PR21D /O 115 PR10D PR20A PR13A PR1I6A PR20A 1/0 116 VDD Vop Vpb VDD VbD VbD 117 PR9A PR19A PRi2A PR1I5A PR1I9A V/O-M2 Lucent Technologies Inc. 157ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Pin Information (continued) Table 70. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout (continued) OR3T20 ORST30 ORSC/T55 ORSC/T80 OR3T125 Pin Pad Pad Pad Pad Pad Function 118 PR9B PR19D PR12B PR15D PR19D /O 119 PROC PR18A PR12C PR14A PR18A VO 120 PR9D PR18D PR12D PR14C PR18D VO 121 PR8A PRI7A PRITA PR14D PRI7A VO-M3 122 PR8B PR17D PR11B PR13A PR17D VO 123 PR8C PR16A PR11C PR13B PR16A /O 124 PR8D PR16D PR1iD PR13D PR16D VO 125 Vss Vss Vss Vss Vss Vss 126 PR7A PR1I5A PR10A PR12A PR15A vO 127 PR7B PR15B PR10B PR12B PR15B vO 128 PR7C PR15C PR10C PR12C PR15C vO 129 PR7D PR15D PR10D PR12D PR15D VO 130 Vpp Vop Vpb VDD VDD VDD 131 PECKR PECKR PECKR PECKR PECKR l-ECKR 132 PR6B PR14B PR9B PR11B PR14B /O 133 PR6C PR14C PROC PR11C PR14C vO 134 PR6D PR14D PR9D PR11D PR14D VO 135 Vss Vss Vss Vss Vss Vss 136 PR5A PR13A PR8A PR10A PR13A VO 137 PR5B PR13D PR8B PR10C PR13D VO 138 PR5C PR12A PR8C PR10D PR12A VO 139 PR5D PR12D PR8D PROB PR12D /O 140 PR4A PRIA PR7A PR9IC PR11A /O-CS1 144 PR4B PR11D PR7B PR9D PR11D vO 142 PR4C PR10A PR7C PR8A PR10A VO 143 PR4D PR10D PR7D PR8D PR10D vO 144 Vop Vop VpD VoD VDD Vppb 145 PR3A PRIA PR6A PR7A PR9A V/O-CSO 146 PR3B PR9B PR6B PR7B PROB VO 147 PR3C PR8B PR5B PR6B PR8B /O 148 PR3D PR8D PR5D PR6D PR8D VO 149 PR2A PR7A PR4A PR5A PR7A /O-RD/MPI_STRB 150 PR2C PR5A PR4D PR5D PR5A /O 151 PR2D PR4A PR3A PR4A PR4A /O 152 PRIA PR3A PR2A PR3A PR3A O-WR 153 PRiC PR2A PR2C PR2A PR2A vO 154 PR1D PRIA PRIA PRIA PRIA V/O 155 Vss Vss Vss Vss Vss Vss 156 PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN RD_CFG 158 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 70. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout (continued) OR3T20 ORS3T30 ORS3C/T55 OR3C/T80 OR3T125 Pin Pad Pad Pad Pad Pad Function 157 Vss Vss Vss Vss Vss Vss 158 Vss Vss Vss Vss Vss Vss 159 PT12D PT28D PT18D PT22D PT28D /O-SECKUR 160 PT12A PT27A PT17D PT21A PT27A VO-RDY/RCLK/MPI_ALE 161 PT11D PT25D PT16D PT19D PT25D 1/0 162 PT11C PT25A PT16A PT19A PT25A VO 163 PTIIA PT24D PT15D PT18D PT24D /0-D7 164 PT10D PT23D PT14D PT17D PT23D VO 165 PT10C PT22D PT14A PT17A PT22D VO 166 PT10B PT21D PT13D PT16D PT21D V/O 167 PT10A PT20D PT13B PT16B PT20D V/O-D6 168 VoD VppD VbD VbD Vpb Vbp 169 PT9D PT19D PT12D PT15D PT19D /O 170 PTSC PT19A PT12C PT15B PT19A Vo 171 PT9B PT18D PT12B PT15A PT18D @) 172 PT9A PT18A PT12A PT14C PT18A VO-D5 173 PT8D PT17D PT11D PT14B PT17D ie) 174 PT8C PT17A PT11C PT13D PT17A 0 175 PT8B PT16D PT11B PT13C PT16D 1/0 176 PT8A PT16A PTA PT13A PT16A 1/0-D4 177 Vss Vss Vss Vss Vss Vss 178 PECKT PECKT PECKT PECKT PECKT I-ECKT 179 - PT7C PT15C PT10C PT12C PT15C VO 180 PT7B PT15B PT10B PT12B PT15B VO 181 PT7A PT15A PT10A PT12A PT15A /O-D3 182 Vss Vss Vss Vss Vss Vss 183 PT6D PT14D PT9D PT11D PT14D VO 184 PT6C PT14C PT9C PT11C PT14C VO 185 PT6B PT14B PT9B PT11B PT14B /O 186 PT6A PT14A PT9A PTA PT14A /O-D2 187 Vss Vss Vss Vss Vss Vss 188 PT5D PT13D PT8D PT10D PT13D /O-D1 189 PT5C PTI3A PT8C PT10B PT13A VO 190 PT5B PT12D PT8B PT10A PT12D vO 191 PT5A PT12A PT8A PT9C PT12A /O-D0/DIN 192 PT4D PT11D PT7D PT9B PT11D He) 193 PT4C PT11A PT7C PT8D PT11A VO 194 PT4B PT10D PT7B PT8C PT10D VO 195 PT4A PT10A PT7A PT8A PT10A /O-DOUT 196 Vppb Vpb Vob VoD Vpb Vop Lucent Technologies Inc. 159Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Pin Information (continued) Table 70. OR3T20, OR3T30, ORSC/T55, ORSC/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 ORSC/T55 OR3C/T80 OR3T125 Pin Pad Pad Pad Pad Pad Function 197 PT3D PT9D PT6D PT7D PT9D 1/0 198 PT3C PT8A PT6A PT7A PT8A ie) 199 PT3B PT7A PT5C PT6C PT7A 1/0 200 PT3A PT6A PT5A PT6A PT6A /O-TDI 201 PT2D PT5A PT4A PT5A PT5A 0 202 PT2A PT4A PT3A PT4A PT4A V/O-TMS 203 PT1D PT3A PT2C PT3A PT3A vO 204 PT1C PT2A PT2A PT2A PT2A iO 205 PT1B PT1D PT1D PT1D PT1D VO 206 PT1A PT1A PT1A PTIA PT1A /O-TCK 207 Vss Vss Vss Vss Vss Vss 208 PRD_DATA PRD_DATA PRD_DATA PRD_DATA PRD_DATA RD_DATA/TDO 160 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 71. OR3T20, OR3T30, OR3C/T55, ORSC/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout OR3T20 OR3T30 ORSC/T55 OR3C/T80 OR3T125 Pin Pad Pad Pad Pad Pad Function 1 Vss Vss Vss Vss Vss Vss 2 VDD Vop Vopb Vpb Vpb Vbb 3 PL1D PL1D PLiD PL1D PL1D vo 4 PLIC PL1B PLiC PLIC PL1C ie) 5 PL1B PLIA PL1B PLiB PL1B Vo 6 PL1IA PL2D PL2D PL2D PL2D 1/O-A0/MPI_BEO 7 Vss Vss Vss Vss Vss Vss 8 PL2D PL3D PL3D PL4D PL4D VO 9 PL2C PL3C PL3A PL4A PL5D vO 10 PL2B PL3B PL4D PL5D PL6D vO 11 PL2A PL3A PL4A PL5A PL7D /O-A1/MPI_BE1 12 PL3D PL4D PL5A PL6A PL8A VO-A2 13 PL3C PL4C PL6D PL7D PL9D VO 14 PL3B PL4B PL6B PL7B PL9B /O 15 PL3A PL4A PL6A PL7A PL9A VO-A3 16 Vop Vob VoD Vop Vpp VoD 17 PL4D PL5D PL7D PL8D PL10D VO 18 PL4C PL5C PL7C PL8A PL10A 10) 19 PL4B PL5B PL7B PL9D PL11D Te) 20 PL4A PL5A PL7A PL9OB PL11A V/0-A4 21 PL5D PL6D PL8D PL9OA PL12D /0-AS 22 PL5C PL6C PL8C PL10C PL12A VO 23 PL5B PL6B PL8B PL10B PL13D /O 24 PL5A PL6A PL8A PL10A PL13A //O-A6 25 vss Vss Vss Vss Vss Vss 26 PECKL PECKL PECKL PECKL PECKL I-ECKL 27 PL6C PL7C PL9OC PL1iC PL14C 1/0 28 PL6B PL7B PL9OB PL11B PL14B VO 29 PL6A PL7A PL9OA PLI1A PL14A 1/0-A7/MPI_CLK 30 VoD Vpb VDD Vob Vop VoD 31 PL7D PL8D PL10D PL12D PL15D vO 32 PL7C PL8C PL10C PL120 PL15C vO 33 PL7B PL8B PL10B PL12B PL15B VO 34 PL7A PL8A PLi0A PL12A PLIi5A /O-A8/MPI_RW 35 Vss Vss Vss Vss Vss Vss 36 PL8D PL9D PL11D PL13D PL16D /O-A9/MPI_ACK 37 PL8C PL9C PL11C PL13B PL1I6A vO 38 PL8B PL9B PL11B PL1I3A PL17D oO 39 PL8A PL9OA PLIiA PL14C PL1I7A VO-A10/MPI_Bt Lucent Technologies Inc. 161ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Pin Information (continued) Table 71. OR3T20, OR3T30, OR3C/T55, ORSC/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30O ORSC/T55 OR3C/T80 OR3T125 Pin Pad Pad Pad Pad Pad Function 40 PL9D PL10D PL12D PL14B PL18D /O 41 PL9C PL1i0C PL12C PL15C PL18A 1/0 42 PL9B PL10B PL12B PL15B PL19D /O 43 PL9A PL10A PL12A PL15A PL19A V/O-A11/MPI_IRQ 44 VppD VDD VbD VDD VDD Vpb 45 PL10D PL11D PL13D PLi6D PL20D V/O-A12 46 PL10C PL11C PL13B PL16B PL20B VO 47 PL10B PL11B PL14D PL17D PL21D 1/0 48 PL10A PL11A PL14B PL17B PL21B V/O-A13 49 PL11D PL12D PL14A PL17A PL21A VO 50 PL11C PL12C PL15D PL18D PL22D /O 51 PL11B PL12B PL15B PL18B PL23D 1/0 52 PLI1A PL12A PL16D PL19D PL24A /O-A14 53 Vss Vss Vss Vss Vss Vss 54 PL.12D PL13D PL17D PL20D PL26D 1/0 55 PL12C PL13A PLI7A PL21D PL27D 1/0 56 PL12B PL14C PL18C PL21A PL27A /O-SECKLL 57 PL12A PL14A PL18A PL22A PL28A 1/0-A15 58 Vss Vss Vss vss Vss Vss 59 PCCLK PCCLK PCCLK PCCLK PCCLK CCLK 60 Vpp VDD VDD VDD Vppb VoD 61 Vss Vss Vss Vss Vss Vss 62 Vss Vss Vss Vss Vss Vss 63 PBIA PBiA PBIA PBIA PB1A V/O-A16 64 PBiB PB1D PB1D PB2A PB2A /O 65 PB1C PB2A PB2A PB2D PB2D VO 66 PB1D PB2D PB2D PB3D PB3D 1/0 67 Vss Vss Vss Vss Vss Vss 68 PB2A PB3A PB3D PB4D PB4D VO-A17 69 PB2B PB3B PB4D PB5D PBSD /O 70 PB2C PB3C PB5A PB6A PB6A 0 71 PB2D PB3D PB5B PB6B PB6D /O 72 PB3A PB4A PB5D PB6D PB7D VO 73 PB3B PB4B PB6A PB7A PB8A VO 74 PB3C PB4C PB6B PB7B PB8D VO 75 PB3D PB4D PB6D PB7D PB9D VO 76 VDD Vbb VDD Vpb Vpb VbD 77 PB4A PB5A PB7A PB8A PB10A /O 78 PB4B PB5B PB7B PB8D PB10D /O 162 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 71. OR3T20, OR3T30, ORSC/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 ORSC/T55 OR3C/T80 ORS3T125 Pin Pad Pad Pad Pad Pad Function 79 PB4C PB5C PB7C PB9A PBI1A vo 80 PB4D PB5D PB7D PB9C PB11D vo 81 PB5A PB6A PB8A PBSD PB12A vO 82 PB5B PB6B PB8B PB10A PB12D vO 83 PB5C PB6C PB8C PB10B PB13A ie) 84 PB5D PB6D PB8D PB10D PB13D VO 85 vss Vss Vss Vss Vss Vss 86 PB6A PB7A PB9A PB11A PB14A VO 87 PB6B PB7B PB9B PB11B PB14B ie) 88 PB6C PB7C PB9C PB11C PB14C /O 89 PB6D PB7D PB9D PB11D PB1i4D vO 90 Vss Vss -Vss Vss Vss vss 91 PECKB PECKB PECKB PECKB PECKB |-ECKB 92 PB7B PB8B PB10B PB12B PB15B 0 93 PB7C PB8C PB10C PB12C PB15C VO 94 PB7D PBsD PB10D PB12D PB15D vo 95 Vss Vss Vss Vss Vss Vss 96 PB8A PB9A PBIIA PB13A PBI6A V/O 97 PB8B P89B PB11B PB13B PB16D ie) 98 PB8C PBSC PB11C PB13C PBI7A O 99 PB8D PB9D PB11D PB14A PB17D vO 100 PB9A PB10A PB12A PB14B PB18A /O-HDC 101 PB9B PB10B PB12B PB14D P818D VO 102 PB9C PB10C PB12C PBI5A PB19A VO 103 PB9D PB10D PB12D PBi5D PB19D vO 104 Vop Vpb Vop Vppb Vpb Vob 105 PB10A PBI1TA PB13A PB16A PB20A /O-LDC 106 PB10B PB11D PB13D PB1i6D PB21D VO 107 PB10C PBi2A PB14A PBI7A PB22A VO 108 PB10D PB12B PB14D PB17D PB23D VO 109 PB11A PB12C PB15A PBi8A PB24A VO-INIT 110 PB11B PB12D PB15D PB18D PB24D vO 111 PB11C PB13A PB16A PB19A PB25A VO 112 PB11D PB13B PB16D PB19D PB25D VO 113 Vss Vss Vss Vss Vss 114 PB12A PB13D PB17A PB20A PB26A vO 115 PB12B PB14A PB17D PB21A PB27A VO 116 PB12C PB14B PB18A PB21D PB27D VO 117 PB12D PB14D PB18D PB22D PB28D vO Lucent Technologies Inc. 163ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Pin Information (continued) Table 71. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 OR3C/T55 OR3C/T80 OR3T125 Pin Pad Pad Pad Pad Pad Function 118 Vss Vss Vss Vss Vss Vss 119 PDONE PDONE PDONE PDONE PDONE DONE 120 VDD VDD VDD VDD Vpb VpD 121 Vss Vss Vss Vss Vss Vss 122 PRESETN PRESETN PRESETN PRESETN PRESETN RESET 123 PPRGMN PPRGMN PPRGMN PPRGMN PPRGMN PRGM 124 PR12A PR1I4A PR18A PR22A PR28A 1/O-MO 125 PR12B PR14D PR18C PR22D PR28D 2) 126 PR12C PRI3A PR18D PR21A PR27A VO 127 PR12D PR13D PR17B PR20A PR26A VO 128 Vss Vss Vss Vss Vss Vss 129 PR11A PR12A PRI6A PR19A PR25A 1/0 130 PR11B PR12B PR16D PR19D PR24A VO 131 PR11C PR12C PR15A PR18A PR23A VO 132 PR11D PR12D PR15C PRi8C PR23D VO 133 PR10A PRIIA PR15D PR18D PR22D VO-M1 134 PR10B PR11B PR1I4A PR17A PR21A VO 135 PR10C PR11C PR14D PR17D PR21D VO 136 PR10D PR11D PR13A PRI6A PR20A VO 137 Vbp Vop Vpp Vpp VpD VbD 138 PR9A PRI0A PR12A PRI5A PRI9A /O-M2 139 PRSB PR10B PR12B PR15D PR19D vO 140 PR9C PR10C PR12C PR14A PR18A VO 141 PROD PR10D PR12D PR14C PR18D fe) 142 PR8A PR9A PR11A PR14D PRI7A VO-M3 143 PR8&B PROB PR11B PR13A PR17D Vo 144 PR8C PR9C PR11C PR13B PR16A /O 145 PR8D PROD PR11D PR13D PRi6D 0 146 Vss Vss Vss Vss Vss Vss 147 PR7A PR8A PR10A PR12A PR15A 1/0 148 PR7B PR8B PR10B PR12B PR15B VO 149 PR7C PR8C PR10C PR12C PR15C /O 150 PR7D PR8D PR10D PR12D PR15D VO 151 VDD Vbp Vbpb VbD Vpp VppD 152 PECKR PECKR PECKR PECKR PECKR |-ECKR 153 PR6EB PR7B PR9B PR11B PR14B VO 154 PR6C PR7C PR9C PR11C PR14C VO 155 PR6D PR7D PR9D PR11D PR14D /O 156 Vss Vss Vss vss Vss Vss 164 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Tabie 71. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 OR3C/T55 OR3C/T80 OR3T125 Pin Pad Pad Pad Pad Pad Function 157 PR5A PR6A PR8A PR10A PR13A vO 158 PR5B PR6B PR8&B PR10C PR13D 1/0 159 PR5C PR6C PR8&C PR10D PR12A VO 160 PR5D PR6D PR8D PROB PR12D ie) 161 PR4A PR5A PR7A PROC PRI1A V/O-CS1 162 PR4B PR5B PR7B PR9D PR11iD VO 163 PR4C PR5C PR7C PR8A PR10A VO 164 PR4D PR5D PR7D PR8D PR10D Vo 165 VDD Vpb VDD VpD VpD Vpp 166 PR3A PR4A PR6A PR7A PR9A V/O-CSO 167 PR3B PR4B PR6B PR7B PR9B vO 168 PR3C PR4C PR5B PR6B PR8B /O 169 PR3D PR4D PR5D PR6D PR8D /O 170 PR2A PR3A PR4A PR5A PR7A 1/O-RD/MPI_STRB 171 PR2B PR3B PR4B8 PR5B PR6A /O 172 PR2C PR3C PR4D PR5D PR5A /O 173 PR2D PR3D PR3A PR4A PR4A vo 174 Vss Vss Vss Vss vss Vss 175 PRIA PR2A PR2A PR3A PR3A V/O-WR 176 PR1B PR2D PR2C PR2A PR2A /O 177 PR1IC PRIA PRIA PRIA PR1A VO 178 PR1D PR1D PR1D PR1D PR1D VO 179 Vss Vss Vss Vss Vss Vss 180 PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN RD_CFG 181 Vss Vss Vss Vss Vss Vss 182 VppD Vop VoD Vop VoD Vop 183 Vss Vss Vss Vss Vss Vss 184 PT12D PT14D PT18D PT22D PT28D VO-SECKUR 185 PT12C PT14C PT18B PT22A PT28A vO 186 PT12B PT14A PT18A PT21D PT27D ie) 187 PT12A PT13D PT17D PT21A PT27A VO-RDY/RCLK/MPI_ALE 188 Vss Vss Vss Vss Vss 189 PT11D PT13B PTi6D PT19D PT25D /O 190 PT11C PT13A PT16C PT19C PT25C vO 191 PT11B PT12D PT16A PTI9A PT25A VO 192 PT1I1A PT12C PT15D PT18D PT24D V/O-D7 193 PT10D PT12A PT14D PT17D PT23D VO 194 PT10C PT11D PT14A PT17A PT22D VO 195 PT10B PT11C PT13D PT16D PT21D VO Lucent Technologies Inc. 165ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Pin Information (continued) Table 71. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 OR3C/T55 OR3C/T80 OR3T125 Pin Pad Pad Pad Pad Pad Function 196 PT10A PT11B PT13B PT16B PT20D /O-D6 197 VppD VDD VpD VoD VpD Vpb 198 PT9D PT10D PT12D PT15D PT19D VO 199 PT9C PT10C PT12C PT15B PT19A VO 200 PT9B PT10B PT12B PT15A PT18D vo 201 PT9A PT10A PT12A PT14C PT18A V/O-D5 202 PT8D PT9D PT11D PT14B PT17D VO 203 PT8C PT9C PT11C PT13D PT17A ie) 204 PT8B PT9B PT11B PT13C PT16D vO 205 PT8A PT9A PT11A PT13A PT16A /O-D4 206 Vss Vss Vss Vss Vss Vss 207 PECKT PECKT PECKT PECKT PECKT l-ECKT 208 PT7C PT8C PT10C PT12C PT15C vO 209 PT7B PT8B PT10B PT12B PT15B VO 210 PT7A PT8A PT10A PT12A PT15A /O-D3 211 Vss Vss Vss Vss Vss Vss 212 PT6D PT7D PTSD PT11D PT14D VO 213 PT6C PT7C PT9C PTC PT14C vO 214 PT6B PT7B PT9B PT11B PT14B 0 215 PT6A PT7A PT9A PTI1A PT14A /O-D2 216 Vss Vss Vss Vss Vss Vss 217 PT5D PT6D PT8D PT10D PT13D VO-D1 218 PT5C PT6C PT8C PT10B PT13A VO 219 PT5B PT6B PT8B PT10A PT12D vO 220 PT5A PT6A PT8A PT9C PT12A /O-DO/DIN 221 PT4D PT5D PT7D PT9B PT11D VO 222 PT4C PT5C PT7C PT8D PT1I1A /O 223 PT4B PT5B PT7B PT8C PT10D vO 224 PT4A PT5A PT7A PT8A PT10A /O-DOUT 225 VDD VoD VpD VpD Vpp VoD 226 PT3D PT4D PT6D PT7D PTSD VO 227 PT3C PT4C PT6A PT7A PT8A ie) 228 PT3B PT4B PT5C PT6C PT7A /O 229 PT3A PT4A PT5A PT6A PT6A /O-TDI 230 PT2D PT3D PT4D PT5D PT5D 1/0 231 PT2C PT3C PT4A PTSA PT5A vO 232 PT2B PT3B PT3D PT4D PT4D /O 233 PT2A PT3A PT3A PT4A PT4A /O-TMS 234 Vss Vss Vss Vss Vss Vss 166 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 71. OR3T20, OR3T30, ORSC/T55, ORSC/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout (continued) ORST20 OR3T30 OR3C/T55 ORSC/T80 OR3T125 Pin Pad Pad Pad Pad Pad Function 235 PT1D PT2D PT2C PT3A PT3A VO 236 PT1C PT2A PT2A PT2A PT2A 1@) 237 PT1B PTiD PT1D PT1D PT1D VO 238 PT1A PT1A PT1A PT1A PT1A /0-TCK 239 Vss Vss Vss Vss Vss Vss 240 PRD_DATA PRD_DATA PRD_DATA PRD_DATA PRD_DATA RD_DATA/TDO Lucent Technologies Inc. 167Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Pin Information (continued) Table 72. OR3T20, OR3T30, and OR3C/T55 256-Pin PBGA Pinout OR3T20 | OR3T30 | OR3C/T55 OR3T20 | OR3ST30 | OR3C/T55 Pin Pad Pad Pad Function Pin Pad Pad Pad Function B1 Vop VbD Vpp Vpb T1 PL10B PL11B PL14D VO C2 PL1D PL1D PL1D vO P4 PL10A PLIIA PL14B VO-A13 D2 PL1C PL1B PLiC vO R3 PL11D PL12D PLI4A VO D3 PL1B PLIA PL1B VO T2 PL11C PL12C PL15D /O E4 PLIA PL2D PL2D VO-AO/MPI_BEO | U1 PL11B PL12B PL15B VO Ci PL2C PL2C VO T3 PLI1A PL12A PL16D VO-A14 D1 PL2B PL2B vO U2 PL13D PL17D VO E3 PL2A PL2A VO V1 PL12D PL13C PLI7C /O E2 PL2D PL3D PL3D /O T4 PL12C PL13B PL17B VO E1 PL2C PL3C PL3A /O U3 _ PL13A PLI7A VO F3 PL2B PL3B PL4D vO V2 PL14D PL18D VO G4 PL2A PL3A PL4A VO-A1/MPI_BE1 | W1 PL12B PL14C PL18C 1/O-SECKLL F2 PL5D vO V3 PL14B PL18B VO FA PL3D PL4D PL5A VO-A2 We PL12A PL14A PL18A V/O-A15 G3 PL3C PL4C PL6D VO Y1 PCCLK PCCLK PCCLK CCLK G2 PL3B PL4B PL6B VO W3 _ NC G1 PL3A PL4A PL6A /0-A3 Y2 PBIA PBIA PBIA /0-A16 H3 PL4D PL5D PL7D VO W4 _ PB1C PB1C VO H2 PL4C PL5C PL7C 0 V4 PB1B PB1D PB1D VO H1 PL4B PL5B PL7B VO U5 PBiC PB2A PB2A /O J4 PL4A PL5A PL7A /0-A4 Y3 PBiD PB2B PB2B VO J3 PL5D PL6D PL8D /0-A5 Y4 PB2C PB2c /O J2 PL5C PL6C PL8C VO V5 PB2D PB2D VO J PL5B PL6B PL8B Vo W5 PB2A PB3A PB3D VO-A17 K2 PL5A PL6A PL8A VO-A6 Y5 PB2B PB3B PB4D /O K3 , PECKL PECKL PECKL |-ECKL V6 PB2c PB3C PB5A /O K1 PL6C PL7C PL9C VO U7 PB2D PB3D PB5B 1/0 L1 PL6B PL7B PL9B vO W6 PB3A PB4A PB5D /O L2 PL6A PL7A PL9A_ | VO-A7/MPILCLK] Y6 PB3B PB4B PB6A VO L3 PL7D PL8D PL10D vO V7 PB3C PB4C PB6B VO L4 PL7C PL8C PL10C Vo W7 PB3D PB4D PB6D VO M1 PL7B PL8B PL10B 0 Y7 PB4A PB5A PB7A 0 M2 PL7A PL8A PLIOA | vO-AsMPILRW] V8 PB4B PB5SB PB7B VO M3 PL8D PLSD PL11D | VO-A9/MPI_ACK | W8 PB4C PB5C PB7C VO M4 PL8C PLOC PL1iC VO Y8 PB4D PB5D PB7D i) N1 PL8B PL9B PL11B vo U9 PB5A PB6A PB8A 1/0 N2 PL8A PL9A PLIIA | Vo-A10/MPI_BI | V9 PB5B PB6B PB8B VO N3 PL9D PL.10D PL12D /O wg PB5C PB6C PB8C VO P1 PL9C PL10C PL12C Vo Y9 PB5D PB6D PB8D VO P2 PL9B PL10B PL12B VO W10| PB6A PB7A PB9A 70 Ri PL9OA PLIOA PLI2A | VO-A11/MPIIRO|, V10 PB6B PB7B PB9B /O P3 PL10D PL11D PL13D VO-A12 Y10 PB6C PB7C PB9C /O R2-| PLioc PL11C PL13B. VO Y11 PB6D PB7D PB9D VO 168 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 72. OR3T20, OR3T30, and ORSC/T55 256-Pin PBGA Pinout (continued) OR3T20 | OR3T30 | ORSC/T55 OR3T20 | ORST3O | OR3C/T55 Pin Pad Pad Pad Function Pin Pad Pad Pad Function Wi1| PECKB PECKB PECKB |-ECKB Ri9| PRI1D PR12D PR15C 0 V11 PB7B PB8B PB10B /O R20 | PRIOA PR11A PR15D /O-M1 U11 PB7C PBSC PB10C VO P18} PR10B PR11B PR14A VO Y12 PB7D PB8D PB10D VO P19} PR10C PR11C PR14D VO W112 PB8A PB9SA PBI1A VO P20 | PR10D PR11D PR13A vO V12 PB8B PB9B PB11B VO N18 PR9OA PR10A PR12A /O-M2 U12 PB8C PBSC PB11C VO N19 PR9SB PR10B PR12B /O 13 PB8D PB9D PBi1D vO N20 PRSC PR10C PR12C /O W13 PB9A PB10A PB12A VO-HDC M17 PR9SD PR10D PR12D VO V13 PB9B PB10B PB12B 1/0 M18 PR8A PRSA PRI1TA (/O-M3 Y14 PBSC PB10C PB12C VO M19 PR8B PR9B PR11B VO W114 PBSD PB1i0D PB12D VO M20 PR8C PR9C PR11C VO Y15| PB1I0A PBIIA PB13A /O-LDC L19 PR8D PRSD PR11D VO V14| PB10B PB11B PB13B VO L18 PR7A PR8A PR10A vO W15} PBt10C PB11C PB13C 1/0 L20 PR7B PR8&B PR10B /O Y16j) PB10D PB11D PB13D VO K20 PR7C PR8&C PR10C /O U14 PB12A PBI14A VO K19 PR7D PR8D PR10D /O V15 PB12B PB14D vO K18 | PECKR PECKR PECKR 1-ECKR Wi6| PBIIA PB12C PBI5A VO-INIT K17 PR6B PR7B PROB 1/0 Y17 PB15D VO J20 PR6C PR7C PROC /O V1i6 PB12D PBIt6A /O J19 PR6D PR70D PROD /O W17| PB11B PB13A PBi6D /O J18 PR5A PR6A PR8A /O Y18;} PB11C PB13B PB17A vO J17 PR5B PR6B PR8B 0 U16| PB11D PBi3C PB17C 1/0 H20 PR5C PR6C PR8C VO V17 | PB12A PB13D PB17D VO H19 PR5D PR6D PR8D VO W18| PB12B PB14A PB18A VO H18 PR4A PR5A PR7A V/0-CS1 Y19 | PB12C PB14B PB18B 1/0 G20 PR4B PR5B PR7B /O V18| PB12D PB14C PB18C VO G19 PR4C PR5C PR7C /O W19 PB14D PB18D /0 F20 PR4D PR5D PR7D VO Y20 | PDONE PDONE PDONE DONE G18 PR3A PR4A PR6A VO-CSO W20| PRESETN | PRESETN | PRESETN RESET F19} PR3B PR4B PR6B VO V19 | PPRGMN | PPRGMN | PPRGMN PRGM E20 | PR3C PR4C PR5B /0 UY19} PR12A PR14A PR18A /O-MO G17 PR3D PR4D PR5D VO U18 PR14C PRi8C /O Fi8 PR2A PR3A PR4A VO-RD/MPI_STRB T17 PR14D PR18D VO E19 PR2B PR3B PR4B 1/0 V20 PR13A PRi7A vO D20 PR2C PR3C PR4D VO U20} PR12B PR13B PR17B 1/0 E18 PR2D PR3D PR3A VO T18 PR12C PR13C PR17C VO D19 PRIA PR2A PR2A VO-WR T19 | PR12D PR13D PRi7D VO C20 PR1iB PR2B PR2B /O T20 | PRIIA PR12A PRi6A VO E17 PR1C PR2C PR2C VO R18 PR11B PR12B PR16D vO D18 PR1D PR2D PR2D VO P17 | PR1IIC PR12C PR15A VO C19 PRIA PRIA vO Lucent Technologies Inc. 169ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Pin Information (continued) Table 72. OR3T20, OR3T30, and OR3C/T55 256-Pin PBGA Pinout (continued) OR3T20 | ORST30 | ORSC/T55 OR3T20 | ORST30 | ORSC/T55 Pin Pad Pad Pad Function Pin Pad Pad Pad Function B20 _ PR1B PRiB VO B7 PT4A PT5A PT7A /O-DOUT C18 _ PRiC PRIC V/O AG PT3D PT4D PT6D VO B19 PR1D> PR1D VO C7 PT3C PT4C PT6A VO A20 | PRD_CFGN | PRD_CFGN | PRD_CFGN RD_CFG B6 PT3B PT4B PT5C /O Ai9} PT12D PT14D PTi8D | VO-SECKUR] A5 PT3A PT4A PT5A /O-TDI Bi8 PT14C PT18C VO D7 PT2D PT3D PT4D VO Bi7| PT12C PT14B PT18B VO C6 PT2C PT3C PT4A VO C17| PT12B PT14A PT18A VO B5 PT2B PT3B PT3D vO D16| PT12A PT13D PT17D |voroymeuwmerate] A4 PT2A PT3A PT3A VO-TMS A18 _ PT13C PT17A vO C5 PT2D PT2D VO A17| PT11D PT13B PT16D vO B4 PT1D PT2C PT2C /O Ci6} PT11C PT13A PT16C VO A3 PTiC PT2B PT2B VO Bi6; PT11B PT12D PT16A VO D5 PT1B PT2A PT2A VO A16| PTIIA PT12C PT15D /0-D7 C4 PT1D PT1D VO C15 _ PT12B PT15A VO B3 PT1C PT1C VO Di4| PT10D PT12A PT14D VO B2 _ PT1B PT1B /O B15 | PT10C PT11D PT14A VO A2 PT1A PT1A PT1A VO-TCK A15{ PT10B PT11C PT13D vO C3 | PRD_DATA! PRD_DATA| PRD_DATA | RD_DATA/TDO C14 PT10A PT11B PT13B /O-D6 Al Vss Vss Vss Vss B14 PT9D PT11A PT13A /O D4 Vss Vss Vss Vss A14 PT9C PT10D PT12D VO D8 vss Vss Vss Vss C13 _ PT10C PT12C VO Di3 vss Vss Vss Vss Bi3 PT9B PT10B PT12B VO D17 vss Vss Vss Vss A13 PT9A PT10A PT12A V/O-D5 H4 Vss Vss Vss Vss D12 PT8D ~PT9D PT11D VO H17 Vss Vss Vss Vss Ci2 PT8C PT9C PT11C VO N4 Vss Vss Vss Vss B12 PT8B PTSB PT11B /O N17 Vss Vss Vss Vss Al2 PT8A PT9SA PT11A V/O-D4 U4 Vss Vss Vss vss B11 | PECKT PECKT PECKT 1-ECKT U8 Vss Vss Vss Vss C11 PT7C PT8C PT10C VO U13 Vss Vss Vss Vss Alt PT7B PT8B PT10B /O U17 Vss Vss Vss Vss A10 PT7A PT8A PT10A /O-D3 J9 Vss Vss Vss Vss" B10 PT6D PT7D PT9D VO J10 Vss Vss Vss Vss* C10 PT6C PT7C PT9C VO J11 Vss Vss Vss Vss* D10 PT6B PT7B PT9B VO J12 Vss Vss Vss Vss" AQ PT6A PT7A PT9A /0-D2 K9 Vss Vss Vss Vss* Bg PT5D PT6D PT8D /O-D1 K10 Vss Vss Vss Vss* C9 PT5C PT6C PT8C VO K11 Vss Vss Vss Vss* D9 PT5B PT6B PT8B V/O K12 Vss Vss Vss Vss* A8 PT5A PT6A PT8A 1/O-D0/DIN L9 Vss Vss vss Vss* B8 PT4D PT5D PT7D VO L10 Vss Vss Vss Vss* C8 PT4C PT5C PT7C VO Li Vss Vss Vss Vss* A7 PT4B PT5B PT7B VO L1i2 Vss Vss Vss Vss* 170 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 72. OR3T20, OR3T30, and OR3C/T55 256-Pin PBGA Pinout (continued) OR3T20 | OR3T30 | ORSC/T55 OR3T20 | OR3T30 | ORSC/TS5 Pin Pad Pad Pad Function Pin Pad Pad Pad Function M9 Vss Vss Vss Vss* F17 VDD VoD Vpb VppD M10 Vss Vss Vss Vss* K4 Vob VpD VDD Vpp M11 Vss Vss Vss Vss* L17 VDD VpD VbpD VoD Mi2 Vss Vss Vss Vss" R4 VpD VDD VDD VpD D6 VpD VbD VopD VDD R17 Vbb VDD VbD VDD O11 VoD VDD Vpp Vpp U6 VoD Vob Vbbd VpD Di5 VDD VDD VDD VbD U10 Vob Vob /9)9) VDD F4 VDD VppD VDD VDD U15 VDD VDD VDD Vpp * Thermally enhanced connection. Lucent Technologies Inc. 171Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout . OR3T20 OR3T30 OR3C/T55 RSC/T: OR3T125 . Pin Pad Pad Pad Pad Pad ? Function Bi PL1D PL1iD PL1D PL1iD PLID VO C2 PLiC PL1C PL1IC PLiC /O Ci PL1IC PL1B PL1B PLiB PL1B I/O D2 PL1B PLIA PLiA PLIA PLIA vO D3 PLIA PL2D PL2D PL2D PL2D V/O-A0/MPI_BEO D1 _ PL2C PL2C PL2A PL2A vO E2 _ PL2B PL2B PL3D PL3D ie) E4 PL3B PL3B vO E3 _ PL2A PL2A PL3A PL3A /O E1 PL2D PL3D PL3D PL4D PL4D vO F2 _ _ PL3C PL4C PL4C VO G4 PL2C PL3C PL3B PL4B PL4B VO F3 _ PL3A PL4A PL5D VO F1 PL2B PL3B PL4D PL5D PL6D /O G2 _ _ PL4c PL5C PL6C VO G1 _ PL4B PL5B PL6B VO G3 PL2A PL3A PL4A PLSA PL7D /O-A1/MPI_BE1 H2 _ PL5D PL6D PL8D VO J4 _ _ PL5C PL6C PL8C VO H1 _ _ PL5B PL6B PL8B /O H3 PL3D PL4D PL5A PL6A PL8A V/O0-A2 J2 _ _ PL6D PL7D PL9D /O J1 PL3C PL4c PL6C PL7C PL9OC VO K2 PL3B PL4B PL6B PL7B PLOB (9) J3 PL3A PL4A PL6A PL7A PL9OA /0-A3 K1 PL4D PL5D PL7D PL8D PL10D vO K4 PL4c PL5C PL7C PL8A PL1IOA VO L2 PL4B PL5B PL7B PLOD PL1iD vO K3 PL4A PL5A PL7A PL9B PLIiA VO-A4 L1 PL5D PL6D PL8D PL9A PL12D VO-A5 M2 PL5C PL6C PL8C PL10C PL12A ie) M1 PL58 PL6B PL8B PL10B PL13D VO L3 PL5A PL6A PL8A PL10A PL13A /O-A6 N2 PECKL PECKL PECKL PECKL PECKL I-ECKL M4 PL6C PL7C PL9C PL11C PL14C vO N1 PL6B PL7B PLOB PL11B PL14B vO M3 PL6A PL7A PLOA PLI1A PLI4A VO-A7/MPI_CLK P2 PL7D PL8D PL10D PL12D PL15D VO P4 PL7C PL8C PL10C PL12C PL15C vO P1 PL7B PL8B PL10B PL12B PL15B VO N3 PL7A PL8A PL10A PL1i2A PL15A 1/0-A8/MPI_RW R2 PL8D PL9D PL11D PL13D PL16D /O-A9/MPILACK 172 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T8O, and OR3T125 352-Pin PBGA Pinout (continued) OR3T20 OR3T30. | ORSC/TS55 | ORSC/T8O | OR3T125 Pin Pad Pad Pad Pad . Pad Function Pa PLEC PLOG PLIC PL13B PLI6A V0 Ri PLAB PLOB PLiiB PLI3A PL17D vO T2 PLBA PLOA PLIiA PL14G PLI7A /0-A10/MPL_BI RS PLOD PLIOD PL12D PL14B PLIaD vO TH PLOC PLI0C PLi2c PLISC PL1aA V0 Ra PLOB PLIOB PL12B PL1S5B PL19D 0 U2 PLOA PLI0A PLI2A PLISA PLI9A VO-A11/MPLIRG T3 PL10D PLD PL13D PL16D PL2OD VO-Al12 Ut PLI3C PL16C PL20C v0 U4 PL10C PLC PLISB PLi6B PL20B V0 V2 PL13A PLI6A PL2OA vO U3 PL10B PL1iB PL14D PL17D PL21D vO Vi PL14C PLI7G PL21C vO We PLI0A PLIWA PL14B PLI7B PL21B V0-AT3 Wi PLI4A PLI7A PLO1A vO v3 PL11D PL12D PL15D PL18D PL22D vO Y2 PLC PL12c PL1SC PL18C PL22C vO wa PLB PL12B PLI5B PL1aB PL2SD v0 Yi PLISA PL18A PL24D vO Ww3 PLIA PLI2A PL16D PL19D PLO4A VO-A14 AAD _ PLi6C PL19G PL25C vO Y4 = PL16B PLI9B PLO5B V0 AAI = = PLIGA PLI9A PLO5A v0 Y3 = PL13D PL17D PL20D PL26D vO AB2 PL12D PL13CG PLI7G PL20G PL26C 0 ABI PL12C PL13B PL17B PL2OA PL26A V0 AAS PLI3A PLI7A PL21D PL27D 0 AC2 PL14D PL18D PL21G PL27C vO ABA PL12B PL14G PL1ac PLOIA PLO7A VO-SECKLL ACI PL14B PL18B PL22D PL28D v0 ABS = PL22C PL2BC vO AD2 = -_ PL22B PL2BB vO AG3 PL12A PL14A PLI8A PLO2A PLO8A VO-A15 ADI PCCLK PCCLK PCCLK PGCLK PCCLK GCLK ARS PBIA PBIA PBiA PBIA PBIA VO-A16 AES = PBIB PBIB 10 AF3 _ PBIB PBIB PBIC PBIC V0 AEA = PBIC PBIC PBID PB1D vO ADA PBIB PB1D PBID PB2A PB2A vO AFA PBiC PB2A PB2A PB2D PB2D vO AES = = PB2B PBSA PBSA vO ACS PBID PB2B PB2C PBSC PBSC vO ADS = PB2D PBSD PB3D VO Lucent Technologies Inc. 173ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Pin Information (continued) Table 73. OR3T20, ORST30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) Pin OR3T20 OR3T30 OR3C/T55 OR3C/T80 OR3T125 Function Pad Pad Pad Pad Pad AF5 _~ PB2C PB3A PB4A PB4A VO AE6 _ PB2D PB3B PB4B PB4B VO AC7 _ PB3C PB4C PB4C 0 AD6 PB2A PB3A PB3D PB4D PB4D /O-A17 AF6 _ PB4A PB5A PB5A VO AE7 _ PB4B PB5B PB5B fe) AF7 PB4C PB5C PB5C Vo AD7 _ _ PB4D PB5D PB5D 0 AE8 _ PB5A PB6A PB6A VO AC9 PB2B PB3B PB5B PB6B PB6D VO AF8 PB2Cc PB3C PB5C PB6C PB7A vo AD8 PB2D PB3D PB5D PB6D PB7D VO AE9 PB3A PB4A PB6A PB7A PB8A vO AF9 PB3B PB4B PBSB PB7B PB8D 0 AE10 PB3C PB4C PB6C PB7C PB9A /O AD9 PB3D PB4D PB6D PB7D PB9D VO AF10 PB4A PB5A PB7A PB8A PB10A VO AC10 PB4B PB5B PB7B PB8D PB10D 1/0 AE11 PB4C PB5C PB7C PB9A PBI1A VO AD10 PB4D PB5D PB7D PB9C PB11D /O AF11 PB5A PB6A PB8A PB9D PB12A VO AE12 PB5B PB6B PB8B PB10A PB12D VO AF12 PB5C PB6C PB8C PB10B PB13A 1) AD11 PB5D PB6D PB8D PB1i0D PB13D VO AE13 PB6A PB7A PBSA PBIITA PB14A vO AC12 PB6B PB7B PB9B PB11B PB14B VO AF13 PB6C PB7C PB9C PB11C PB14C VO AD12 PB6D PB7D PBSD PBI1D PB14D vO AE14 PECKB PECKB PECKB PECKB PECKB Il-ECKB AC14 PB7B PB8&B PB10B PB12B PB15B VO AF14 PB7C PB8C PB10C PB12C PB15C VO AD13 PB7D PB8D PB10D PB12D PB15D 0 AE15 PB8A PB9A PB11A PB1I3A PBI6A (/0 AD14 PB8B PBSB PB1i1B PB13B PB16D vO AF15 PB8C PB9C PB11C PB13C PBi7A VO AE16 PB8D PBSD PB11D PBI4A PB17D vO AD15 PB9A PB10A PB12A PB14B PB18A VO-HDC AF16 PBSB PB10B PB12B PB14D PB18D Vo AC15 PB9C PB10C PB12C PB15A PB19A VO AE17 PB9D PB10D PB12D PB1i5D PB19D /O AD16 PB10A PB11A PB13A PB16A PB20A /O-LDC AF17 PB13B PB16B PB20D VO 174 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, ORSC/T80, and OR3T125 352-Pin PBGA Pinout (continued) . OR3T2 OR3T30 OR3C/T55 OR3 OR3T1 . Pin Pad Pad Pad Pad Pad Function ACi7 PB10B PB11B PBi3C PB16C PB21A vO AE18 PB10C PB11C PB13D PB16D PB21D VO AD17 PB10D PB1iD PB14A PB17A PB22A VO AF18 _ PB12A PB14B PB17B PB23A 0 AE19 _ _ PB14C PB17C PB23C /O AF19 _ PB12B PB14D PB17D PB23D VO AD18 PBHIA PB12C PB1i5A PB18A PB24A /O-INIT AE20 _ PB15B PB18B PB24B lO AC19 _ _ PB1i5C PB18C PB24C vO AF20 _ PB15D PB18D PB24D VO AD19 PB12D PBI6A PB19A PB25A /O AE21 _ _ PB16B PB19B PB25B VO AC20 _ _ PB16C PB19C PB25C VO AF21 PB11B PB13A PB16D PB19D PB25D vO AD20 PB11C PB13B PBI7A PB20A PB26A vO AE22 PB11D PBi3C PB17B PB20B PB26B vO AF22 PB12A PB13D PB17C PB20D PB26D VO AD21 PB12B PB14A PB17D PB21A PB27A VO AE23 _ _ PB21B PB27B vO AC22 PB12C PB14B PB1i8A PB21D PB27D vO AF23 PB12D PB14C PBi8B PB22A PB28A 0 AD22 _ PB14D PB18C PB22B PB28B /O AE24 _ _ PB22C PB28C VO AD23 _ _ PB1i8D PB22D PB28D VO AF24 PDONE PDONE PDONE PDONE PDONE DONE AE26 PRESETN PRESETN PRESETN PRESETN PRESETN RESET AD25 PPRGMN PPRGMN PPRGMN PPRGMN PPRGMN PRGM AD26 PR12A PR14A PR18A PR22A PR28A /O-MO AC25 _ PR14B PR18B PR22C PR28C vO AC24 _ PR14C PR18C PR22D PR28D i) AC26 PR14D PR18D PR21A PR27A VO AB25 _ PR13A PRI7A PR21D PR27D /O AB23 PR12B PR13B PR17B PR20A PR26A 1/0 AB24 PR12C PR13C PR17C PR20B PR26B vO AB26 PR12D PR13D PR17D PR20D PR26D VO AA25 PR1I1A PR12A PRIGA PR19A PR25A vO Y23 _ _ PR16B PR19B PR25B vO AA24 PR1iB PR12B PR16C PR19C PR25C VO AA26 _ _ PR16D PR19D PR24A vO Y25 PR11C PR12C PR1I5A PR18A PR23A /O Y26 _ _ PR15B PR18B PR23B VO Y24 PR11D PR12D PR15C PR18C PR23D VO Lucent Technologies Inc. 175ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) R3T20 OR3T30 | ORSC/T55 | ORSC/TEO R3T125 Pin Pad bad Ped. Pad Pad. Function W25 PRI0A PRIA PRI5D PR18D PR22D VO-Mi v23 PR10B PRIIB PRI4A PRI7A PR21A vO W26 = PRI4B PR17B PR21B vO w24 = = PR14C PRI7C PR2IC vO V25 PR10C PRG PR14D PRI7D PR21D vO V26 PR10D PRMD PRI3A PRI6A PR20A vO U25 PR1SB PRIGB PR20B VO V24 = = PRIaC PRIGC PR20C vO U26 = PR1aD PRi6D PR20D vO U23 PROA PRI0A PRI2A PRI5A PRI9A 0-2 T25 PROB PR10B PR12B PRI5D PR19D vO U24 PROC PR10C PRI2ZC PRI4A PRIGA VO T26 PROD PR10D PR12D PRI4C PRISED VO R25 PR8A PROA PRIA PR14D PRI7A V/O-M3 R26 PR8B PROB PRB PRI3A PR17D vO T24 PREC PROG PRC PR13B PRI6A VO P25 PR8D PROD PRD PR13D PRI6D vO R23 PR7A PR8A PRIOA PRI2A PRI5A vO P26 PR7B PR8B PRI0B PR12B PRi5B vO R24 PR7C PREC PR10C PR12C PRI5C VO N25 PR7D PRED PR10D PR12D PRI5D vO N23 PECKR PECKR PECKR PECKR PECKR -ECKR N26 PR6B PR7B PROB PRI1B PR14B v0 P24 PREC PR7C PROC PRIIC PR14C vO M25 PR6D PR7D PROD PRMD PR14D vO NO4 PR5A PRGA PRBA PRI0A PRI3A vO M26 PR5B PRGB PR8B PR10C PR13D vO L25 PRSC PREC PREC PRI0D PRI2A vO M24 PR5D PRED PRED PROB PR12D vO 126 PR4A PR5A PR7A PROC PRIA 0-CS1 M23 PR4B PR5B PR7B PROD PRI1D v0 K25 PR4C PR5C PR7C PRaA PRI0A v0 L24 PR4D PRED PR7D PRED PR10D VO K26 PR3A PR4A PRGA PR7A PROA V/0-CS0 K23 PREB PR7B PROB vO 325 PRB PR4B PREC PR7C PROC v0 K24 PRED PR7D PROD v0 J26 PR3C PR4C PR5SA PRGA PR8A vO H25 PR5B PR6B PREB v0 H26 PR3D PR4D PR5C PREC PREC vO J24 PRSD PRED PRED vO G25 PR2A PR3A PR4A PR5A PR7A /O-RD/MPI_STRB 176 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Tabie 73. OR3T20, OR3T30, OR3C/T55, OR3C/T8O, and OR3T125 352-Pin PBGA Pinout (continued) . OR3T20 OR3T30 ORS3C/T55 OR3C/T80 OR3T125 : Pin ad d Pad Pad Pad Pad Function H23 PR2B PR3B PR4B PR5B PR6A VO G26 _ _ PR4C PR5C PR6C vO H24 PR2C PR3C PR4D PR5D PR5A VO F25 PR2D PR3D PR3A PR4A PR4A 1) G23 _ _ PR3B PR4B PR4B @) F26 _ PR3C PR4C PR4C vO G24 _ PR3D PR4D PR4D V/O E25 PRIA PR2A PR2A PR3A PR3A /O-WR E26 PR1B PR2B PR2B PR3B PR3B /O F24 _ _ _ PR3D PR3D VO D25 PRIC PR2C PR2C PR2A PR2A VO E23 PRiD PR2D PR2D PR2D PR2D vO D26 PRIA PR1IA PRIA PRIA /O E24 PR1B PR1B PR1B PR1B 0 C25 _ PRIC PR1C PRiC PRiC vO D24 _ PR1D PR1D PR1D PR1D VO C26 PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN PRD_CFGN RD_CFG A25 PT12D PT14D PT18D PT22D PT28D V/O-SECKUR B24 PT14C PT18C PT22C PT28C VO A24 _ _ _ PT22B PT28B VO B23 PT12C PT14B PT18B PT22A PT28A VO C23 PT12B PT14A PT18A PT21D PT27D vO A23 PT12A PT13D PT17D PT21A PT27A V/O-RDY/RCLK/ MPI_ALE B22 PT13C PT17C PT20D PT26D VO D22 PT11D PT13B PT17B PT20C PT26C vO C22 PT11C PT13A PT17A PT20A PT26A vO A22 PT11B PT12D PT1i6D PT19D PT25D VO B21 _ PT16C PT19C PT25C vO D20 _ _ PT16B PT19B PT25B vO C21 _ PTi6A PT19A PT25A VO A214 PT11A PT12C PT15D PT18D PT24D /O-D7 B20 _ _ PT15C PT18C PT24C VO A20 PT12B PT15B PT18B PT24B vO C20 _ _ PT15A PTi8A PT24A VO B19 PT10D PT12A PT14D PT17D PT23D VO Dis _ PT14C PT17C PT23C VO A19 PT10C PT11D PT14B PT17B PT23B vO C19 _ _ PT14A PT17A PT22D vO B18 PT10B PT11C PT13D PT16D PT21D 0 Ai8 _ _ PT13C PT16C PT21A /O B17 PT10A PT11B PT13B PT16B PT20D VO-D6 Lucent Technologies Inc. 177ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) . OR3T20 OR3T30 OR3C/T55 OR3C/T80 R3T125 : Pin Pad Pad Pad Pad Ofpad Function C18 PT9D PT11A PT13A PT16A PT20A VO A17 PT9C PT10D PT12D PT15D PT19D /O D17 PT10C PT12C PT15B PT19A VO Bi6 PT9B PT10B PT12B PT15A PT18D VO C17 PT9A PT10A PT12A PT14C PT18A VO-D5 A16 PT8D PT9D PT11D PT14B PT17D VO B15 PT8C PT9C PT11C PT13D PT17A vO A15 PT8B PT9B PT11B PT13C PT16D VO C16 PT8A PT9A PT11A PT13A PT16A VO-D4 B14 PECKT PECKT PECKT PECKT PECKT l-ECKT D15 PT7C PT8C PT10C PT12C PT15C vO Al4 PT7B PT8B PT10B PT12B PT15B 1/0 C15 PT7A PT8A PT10A PT12A PT1S5A /0-D3 B13 PT6D PT7D PT9D PT11D PT14D Vo D13 PT6C PT7C PTSC PT11C PT14C VO A13 PT6B PT7B PT9B PT11B PT14B VO C14 PT6A PT7A PT9A PTH1A PT14A V/O-D2 B12 PT5D PT6D PT8D PT10D PT13D VO-D1 C13 PT5C PT6C PT8C PT10B PT13A 0 Ai2 PT5B PT6B PT8B PT10A PT12D 1/0 B11 PT5A PT6A PT8A PT9C PT12A //O-DO/DIN C12 PT4D PT5D PT7D PT9B PT11D 1/0 All PT4C PT5C PT7C PT8D PT11A vO D12 PT4B PT5B PT7B PT8c PT10D vO B10 PT4A PT5A PT7A PT8A PT10A /0-DOUT Ci1 PT3D PT4D PT6D PT7D PTSD VO A10 _ _ PT6C PT7C PT9A VO D10 _ PT6B PT7B PT8D VO BO PT3C PT4C PT6A PT7A PT8A VO C10 PT3B PT4B PT5D PT6D PT7D /O AQ _ > PT5C PT6C PT7A vO B8 _ _ PT5B PT6B PT6D 1/0 A8 PT3A PT4A PT5A PT6A PT6A /0-TDI cg _ _ PT4D PTSD PT5D 1/0 B7 PT2D PT3D PT4C PT5C PT5C vO De _ PT4B PT5B PT5B VO A7 PT2C PT3C PT4A PT5A PT5A VO C8 PT3D PT4D PT4D ie) B6 PT2B PT3B PT3C PT4C PT4C V/O D7 _ PT3B PT4B PT4B VO AG PT2A PT3A PT3A PT4A PT4A /O-TMS C7 _ PT2D PT2D PT3D PT3D VO 178 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) : OR3T2 OR3T30 ORSC/T55 OR3C/T80 OR3T1 . Pin Pad Pad Pad Pad Pad Function B5 PT1D PT2C PT2C PT3A PT3A vO AS PTiC PT2B PT2B PT2D PT2D VO C6 _ _ PT2C PT2C VO B4 _ _ _ PT2B PT2B /O D5 PT1B PT2A PT2A PT2A PT2A VO A4 _ PT1D PT1D PT1D PT1D VO C5 PT1C PT1C PT1C PT1C VO B3 _ PT1B PT1B PT1B PT1B VO C4 PT1A PT1A PT1A PT1A PT1A V/O-TCK A3 PRD_DATA PRD_DATA PRD_DATA PRD_DATA PRD_DATA RD_DATA/TDO Al Vss Vss Vss Vss Vss Vss A2 Vss Vss Vss Vss Vss Vss A26 Vss Vss Vss Vss Vss Vss AC13 Vss Vss Vss Vss Vss Vss AC18 Vss Vss Vss Vss Vss Vss AC23 Vss Vss Vss Vss Vss Vss AC4 Vss Vss Vss Vss Vss Vss AC8 Vss Vss Vss Vss Vss Vss AD24 Vss vss Vss Vss Vss Vss AD3 Vss Vss Vss Vss Vss Vss AE1 Vss vss Vss Vss Vss Vss AE2 Vss Vss vss vss Vss Vss AE25 Vss Vss Vss Vss Vss Vss AF1 Vss Vss Vss Vss Vss Vss AF25 Vss Vss Vss Vss Vss Vss AF26 Vss Vss Vss Vss Vss Vss B2 Vss Vss Vss Vss Vss Vss B25 Vss Vss Vss Vss Vss Vss B26 Vss Vss Vss Vss Vss Vss C24 Vss Vss Vss Vss Vss Vss C3 Vss Vss Vss Vss Vss Vss D14 Vss Vss vss Vss Vss Vss D19 Vss Vss Vss Vss Vss Vss D23 Vss vss Vss Vss Vss Vss D4 Vss Vss Vss Vss Vss Vss D9 Vss Vss Vss Vss Vss Vss H4 Vss Vss Vss Vss Vss Vss J23 Vss Vss Vss Vss vss Vss N4 Vss Vss Vss Vss Vss Vss P23 Vss Vss Vss Vss Vss Vss V4 Vss Vss Vss Vss Vss Vss W23 Vss vss Vss Vss Vss Vss Lucent Technologies Inc. 179ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, ORSC/T80, and OR3T125 352-Pin PBGA Pinout (continued) . OR3T20 OR3T30 OR3C/T55 3C, . Pin Pad Pad Pad OP Pad pad Function L11 Vss Vss Vss Vss Vss Vss* L12 Vss Vss Vss Vss Vss Vss* L13 vss Vss Vss Vss Vss Vss* L14 Vss Vss Vss Vss Vss Vss* L15 Vss Vss Vss Vss Vss Vss* L16 Vss Vss Vss Vss Vss Vss* M11 Vss Vss Vss Vss Vss Vss" M12 Vss Vss Vss Vss Vss Vss* M13 Vss Vss Vss Vss Vss Vss* M14 Vss Vss Vss Vss Vss Vss* M15 Vss Vss Vss Vss Vss Vss* Mi6 Vss Vss Vss Vss Vss Vss* N11 Vss Vss Vss Vss Vss Vss* N12 Vss Vss Vss Vss Vss Vss" N13 Vss Vss Vss Vss Vss Vss" N14 vss Vss Vss Vss Vss Vss* N15 Vss Vss Vss Vss Vss Vss* N16 Vss Vss Vss Vss Vss Vss* P11 Vss Vss Vss Vss Vss Vss* P12 Vss Vss Vss Vss Vss Vss* P13 Vss Vss Vss Vss Vss Vss* P14 Vss Vss Vss Vss Vss Vss* P15 Vss Vss Vss Vss Vss Vss* P16 Vss Vss Vss Vss Vss Vss* R11 Vss Vss Vss Vss Vss Vss* R12 Vss Vss Vss Vss Vss Vss" R13 Vss Vss Vss Vss Vss Vss* R14 Vss Vss Vss Vss Vss Vss* R15 Vss Vss Vss Vss Vss Vss* R1i6 Vss Vss Vss Vss Vss Vss* T11 Vss Vss Vss Vss Vss Vss* T12 Vss Vss Vss Vss Vss Vss* T13 Vss Vss Vss Vss Vss Vss* T14 Vss Vss Vss Vss Vss Vss" T15 Vss Vss Vss Vss Vss Vss* T16 Vss Vss Vss Vss Vss Vss* AA23 Voo Vop Vpp VDD Vop Vpp AA4 VpD VoD VpD Vpp Vppb VDD AC11 Vop VDD VppD VbD Vpb VbD AC16 VDD VDD Vop Vbb Vob Vbb AC21 VDD VpD Vpp VDD Voo Vpp AC6 VpD VDD Vbb VDD Vpb VDD 180 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T8O, and OR3T125 352-Pin PBGA Pinout (continued) . OR3T20 OR3T30 OR3C/T55 OR3C/T8O OR3T125 . Pin Pad Pad Pad Pad Pad Function D11 VDD Vpp VDD VpD Vpp VDD D16 VbD Vob VDD VDD VpD Vob D21 VDD Vpp VDD VDD VDD VDD D6 VpD VbD VDD VDD VDD VDD F23 VDD VpD VDD VbD VbD VDD F4 Vpp Vbp VDD Vob VpD VDD L23 Vpp Vbb Vpb VpD Vpp Vpp L4 Vob Vob VoD VoD Voo Vob T23 VbD VpD Vpb Vpb VDD VDD T4 Voo Vop VoD VoD Vob VoD *Thermally enhanced connection. Lucent Technologies Inc. 181Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Pin Information (continued) Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout Pin one Teo ons 25 Function Pin onc r8e Re 25 Function E4 | PRD_CFGN | PRD_CFGN RD_CFG U2 PR12A PR15A VO D3 PR1D PRiD VO U3 PR13D PR16D VO D2 PRiC PR1iC VO V1 PR13C PR16B VO D1 PR1B PR1B VO V2 PR13B PR16A VO F4 PRIA PRIA vO V3 PR13A PR17D vO E3 PR2D PR2D vO wW1 PR14D PR17A /O-M3 E2 PR2C PR2C VO V4 PR14C PR18D VO E1 PR2B PR2B V/O we2 PR14B PR18B VO F3 PR2A PR2A /O Ww3 PR14A PR18A VO F2 PR3D PR3D V/O Y2 PR15D PR19D VO F1 PR3C PR3C V/O Ww4 PRI5A PR19A VO-M2 H4 PR3B PR3B VO Y3 PR16D PR20D VO G3 PR3A PR3A /O-WR AA1 PR16C PR20C VO G2 PR4D PR4D VO AA2 PR16B PR20B VO G1 PR4C PR4C /O Y4 PR16A PR20A VO J4 PR4B PR4B /O AAS PR17D PR21D vO H3 PR4A PR4A VO AB1 PR17C PR21C VO H2 PR5D PR5A VO AB2 PR17B PR21B /O J3 PR5C PR6C VO AB3 PR1I7A PR21A 1/0 K4 PR5B PR6A VO AC1 PR18D PR22D VO-M1 J2 PR5A PR7A 1/O-RD/MPI_STRB AC2 PR18C PR23D 1/0 J1 PR6D PR8D /O AB4 PR18B PR23B VO K3 PR6C PR8C VO AC3 PR18A PR23A VO K2 PR6B PR8&B VO AD2 PR19D PR24A VO K1 PR6A PR8A VO AD3 PR19C PR25C VO L3 PR7D PR9D VO AC4 PR19B PR25B vO M4 PR7C PR9C /O AE1 PRI9A PR25A VO L2 PR7B PR9B VO AE2 PR20D PR26D VO L1 PR7A PR9A /O-Cso AES PR20C PR26C VO M3 PR8D PR10D VO AD4 PR20B PR26B /O N4 PR8A PR10A VO AF1 PR20A PR26A VO M2 PR9D PR11D /O AF2 PR21D PR27D /O N3 PR9C PR11A V/O-CS1 AF3 PR21C PR27C VO N2 PR9B PR12D VO AG1 PR21B PR27B V/O P4 PRIA PR12C VO AG2 PR21A PR27A VO N1 PR10D PR12A VO AG3 PR22D PR28D VO P3 PR10C PR13D VO AF4 PR22C PR28C /O P2 PR10B PR13C VO AH1 PR22B PR28B 1/0 P1 PR10A PR13A VO AH2 PR22A PR28A 1/O-MO R3 PR11D PR14D VO AH3 PPRGMN PPRGMN PRGM R2 PR11C PR14C vO AG4 | PRESETN | PRESETN RESET R1 PR11B PR14B /O AH5 PDONE PDONE DONE T2 PECKR PECKR 1-ECKR AJ4 PB22D PB28D /O T4 PR12D PR15D V/O AK4 PB22C PB28C /O T3 PR12C PR15C /O AL4 PB22B PB28B /O U1 PR12B PR15B /O AH6 PB22A PB28A /O 182 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout (continued) Pin Re OR 25 Function Pin oreo mana 25 Function AJ5 PB21D PB27D /O AL19 PB10A PB12D VO AK5 PB21C PB27C VO AHi8 PB9D PB12A VO AL5 PB21B PB27B VO AK19 PB9C PB11D VO AJ6 PB21A PB27A VO AJ19 PB9B PB11B /O AK6 PB20D PB26D /O AK20 PB9A PBITA VO AL6 PB20C PB26C 1/0 AH19 PB8D PB10D VO AH8 PB20B PB26B vO AJ20 PB&B PB10B VO AJ7 PB20A PB26A vO AL21 PB8A PB10A 1/0 AK7 PB19D PB25D VO AK21 PB7D PB9D VO AL7 PB19C PB25C VO AH20 PB7C PB9A VO AH9 PB19B PB25B VO AJ21 PB7B PB8D VO AJ8 PB19A PB25A vO AL22 PB7A PB8A vO AK8 PB18D PB24D VO AK22 PB6D PB7D VO AJS PB18C PB24C Oo AJ22 PB6C PB7A VO AH10 PB18B PB24B 1/0 AL23 PB6B PB6D V/O AK9 PB18A PB24A V/O-INIT AK23 PB6A PB6A VO AL9 PB17D PB23D VO AH22 PB5D PB5D VO AJ10 PB1i7C PB23C /O AJ23 PB5C PBSC /O AK10 PB17B PB23A VO AK24 PB5B PB5B /O AL10 PB17A PB22A /O AJ24 PB5A PB5A VO AJ11 PB16D PB21D VO AH23 PB4D PB4D VO-A17 AH12 PB16C PB21A vO AL25 PB4C PB4C VO AK11 PBi6B PB20D VO AK25 PB4B PB4B V/O AL11 PB16A PB20A /O-LDC AJ25 PB4A PB4A vO AJ12 PB15D PB19D 1/0 AH24 PB3D PB3D /O AH13 PB15B PB19B VO AL26 PB3C PB3C vO AK12 PB15A PB19A iO AK26 PB3B PB3B /O AJ13 PB14D PB18D VO AJ26 PB3A PB3A /O AK13 PB14C PB18B VO AL27 PB2D PB2D VO AH14 PB14B PB18A /O-HDC AK27 PB2C PB2C Vo AL13 PB14A PB17D /O AJ27 PB2B PB2B VO AJ14 PB13D PB17B VO AH26 PB2A PB2A 1/0 AK14 PB1i3C PB17A VO AL28 PB1D PB1D /O AL14 PB13B PB16D VO AK28 PBIC PB1iC vO AJ15 PB13A PBI6A 1/0 AJ28 PBIB PBIB VO AK15 PB12D PBi5D VO AH27 PBIA PBIA /O-A16 AL15 PB12C PB15C VO AG28; PCCLK PCCLK CCLK AK16 PB12B PB15B vO AH29 PL22A PL28A /0-A15 AHi6| PECKB PECKB !-ECKB AH30 PL22B PL28B VO AJ16 PB11D PB14D VO AH31 PL22C PL28C VO AL17 PB11C PB14C /O AF28 PL22D PL28D /O AK17 PB11B PB14B vO AG29 PL21A PL27A /O-SECKLL AJ17 PBI1A PBI4A VO AG30 PL21B PL27B VO AL18 PBi0D PB13D /O AG31 PL21C PL27C /O AK18 PB10C PB13B /O AF29 PL21iD PL27D /O AJ18 PB10B PB13A VO AF30 PL20A PL26A VO Lucent Technologies Inc. 183Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Pin Information (continued) Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout (continued) Pin one Oe 25 Function Pin oneciT80 ons 25 Function AF31 PL20B PL26B VO N28 PL8A PL10A VO AD28 PL20C PL26C VO M29 PL8C PL10C VO AE29 PL20D PL26D VO L31 PL8D PL10D VO AE30 PL19A PL25A VO L30 PL7A PL9A 1/0-A3 AE31 PL19B PL25B VO M28 PL7B PL9B VO AC28 PL19C PL25C VO L29 PL7C PLOC Oo AD29 PLi9D PL24A VO-A14 K31 PL7D PLSD VO AD30 PL18A PL24D VO K30 PL6A PL8A 1/0-A2 AC29 PL18B PL23D VO K29 PL6B PL8B VO AB28 PL18C ~ PL22C VO J31 PL6C PL8C VO AC30 PL18D PL22D VO J30 PL6D PL8D 1/0 AC31 PL17A PL21A VO K28 PL5A PL7D 1//O-A1/MPI_BE1 AB29 PL17B PL21B VO-A13 J29 PL5B PL6B VO AB30 PL17C PL21C VO H30 PL5C PL6C lO AB31 PLi7D PL21D VO H29 PL5D PL6D VO AA29 PL16A PL20A VO J28 PL4A PL5D VO Y28 PL16B PL20B VO G31 PL4B PL4B VO AA30 PLi6C PL20C vO G30 PL4c PL4C VO AA31 PL16D PL20D V/O-A12 G29 PL4D PL4D V/O Y29 PL15A PL19A V/O-A11/MPI_IRQ H28 PL3A PL3A VO W28 PL158 PL19D VO F31 PL3B PL3B /O Y30 PL15C PL18A VO F30 PL3C PL3C VO We29 PLI4A PL18C VO F29 PL3D PL3D VO W30 PL14B PL18D VO E31 PL2A PL2A VO V28 PL14C PL17A 1/0-A10/MPI_BI E30 PL2B PL2B VO Wws31 PL14D PL17C vO E29 PL2C PL2C vO V29 PL13A PL17D VO F28 PL2D PL2D 1/O-A0/MPI_BEO V30 PL13B PLi6A VO D31 PLIA PL1A vO V31 PL13C PLi6C vO D30 PLIB PL1B VO U29 PL13D PL16D 1/0-A9/MPI_ACK D29 PLiC PL1C vO U30 PLi2A PL15A /O-A8/MPI_RW E28 PL1D PL1D vO U31 PL12B PL15B VO D27 | PRD_DATA| PRD_DATA RD_DATA/TDO T30 PL12C PL15C VO C28 PT1A PT1A V/O-TCK T28 PL12D PL15D VO B28 PT1B PTtB VO T29 PLI1A PL14A /0-A7/MPI_CLK A28 PT1C PT1C VO R31 PL11B PL14B vO D26 PT1D PT1D VO R30 PL11C PL14C VO C27 PT2A PT2A VO R29 PECKL PECKL I-ECKL B27 PT2B PT2B V/O P31 PL10A PL13A /O-A6 A27 PT2C PT2C VO P30 PL10B PL13D VO C26 PT2D PT2D /O P29 PL10C PL12A VO B26 PT3A PT3A VO N31 PL10D PL12C VO A26 PT3B PT3B vO P28 PL9OA PL12D 1/0-A5 D24 PT3C PT3C VO N30 PL9OB PL11A 1/0-A4 C25 PT3D PT3D /O N29 PL9C PL11C VO B25 PT4A PT4A 1/0-TMS M30 PLOD PL11D vO A25 PT4B PT4B /O 184 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout (continued) Pin maibsehhee on 25 Function Pin alee on 25 Function D23 PT4C PT4C Vo Ci1 PT16C PT21A /O C24 PT4D PT4D /O A10 PT16D PT21D VO B24 - PT5A PT5A VO B10 PTI7A PT22D /O C23 PT5B PT5B vO C10 PT17B PT23B /O D22 PT5C PT5C VO AQ PT17C PT23C VO B23 PT5D PT5D 0 BO PT17D PT23D VO A23 PT6A PT6A 1/O-TDI D10 PT18A PT24A VO C22 PT6B PT6D VO C9 PT18B PT24B VO B22 PT6C PT7A /O Bs PT18C PT24C Oo A22 PT6D PT7D VO C8 PT18D PT24D /0-D7 C21 PT7A PT8A VO D9 PT19A PT25A V/O D20 PT7B PTSD VO A7 PT19B PT25B VO Bet PT7C PT9SA /O B7 PT19C PT25C Vo A21 PT7D PTSD VO C7 PT19D PT25D VO C20 PT8A PT10A V/O-DOUT D8 PT20A PT26A VO Dig PT8C PT10D V/O A6 PT20B PT26B vO B20 PT8D PT11A vO B6 PT20C PT26C VO C19 PT9A PT11C /O C6 PT20D PT26D VO B19 PT9B PT11D /O A5 PT21A PT27A VO-RDY/RCLK/MP!_ALE D18 PT9C PT12A /(O-DO/DIN B5 PT21B PT27B VO A19 PT9D PT12C VO C5 PT21C PT27C /O C18 PT10A PT12D VO D6 PT21D PT27D VO B18 PT10B PT13A VO A4 PT22A PT28A VO A18 PTi0C PT13C VO B4 PT22B PT28B VO C17 PT10D PT13D VO-D1 C4 PT22C PT28C VO B17 PT11A PT14A VO-D2 D5 PT22D PT28D /O-SECKUR Ai7 PT11B PT14B VO Al2 Vss Vss Vss B16 PT11C PT14C Vo A16 Vss Vss vss D1i6 PT11D PT14D VO A2 Vss Vss Vss C16 PT12A PT15A VO-D3 A20 Vss Vss Vss A15 PT12B PT15B /O A24 Vss Vss Vss B15 PT12C PT15C vO A29 Vss Vss Vss C15 PECKT PECKT 1-ECKT A3 Vss Vss Vss A14 PT13A PTI6A VO-D4 A30 Vss vss Vss B14 PT13B PT16B //O A8& Vss Vss Vss C14 PT13C PT16D 1/0 AD1 Vss Vss Vss A138 PT13D PT17A VO AD31 Vss Vss Vss Di4 PT14A PT17B VO AJ1 Vss Vss Vss B13 PT14B PT17D 0 AJ2 Vss Vss Vss C13 PT14C PT18A /O-D5 AJ30 Vss Vss Vss B12 PT14D PT18B vO AJ31 Vss Vss Vss D13 PT15A PT18D i/O AK1 Vss Vss Vss C12 PT15B PT19A VO AK29 Vss Vss vss A11 PT15D PT19D YO AK3 Vss Vss Vss Bt1 PT16A PT20A vO AK31 Vss vss Vss D12 PT16B PT20D V/O-D6 AL12 Vss Vss Vss Lucent Technologies Inc. 185Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Pin Information (continued) Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout (continued) Pin OR on 25 Function Pin Onecirb0 Ore 25 Function AL16 Vss Vss Vss AH17 VDD VDD VpD AL2 Vss Vss Vss AH21 VbD VbbD VDD AL20 Vss Vss Vss AH25 Vbb VDD VDD AL24 Vss Vss Vss AH28 VpD VDD Vob AL29 Vss Vss Vss AH4 VbbD VbbD VoD AL3 Vss Vss Vss AH7 VpD VpbD VoD AL30 Vss Vss Vss AJ29 VDD VbD VDD AL8 Vss Vss Vss AJ3 Vpb VpD VbD B1 Vss Vss Vss AK2 VDD VDD VpD B29 Vss Vss Vss AK30 VDD VpD VDD B3 Vss Vss Vss AL1 Vbpb VpD Vpb B31 Vss Vss Vss AL31 Vop Vpp VpD C1 Vss Vss Vss B2 VDD Vpb VpD C2 Vss Vss Vss B30 VbbD VppD Vpb C30 Vss Vss Vss C29 VpD Vpb VDD C31 Vss Vss Vss C3 VDD VDD Vpo Hi Vss Vss Vss D11 VoD VDD Vpb H31 Vss Vss Vss D15 Vob Vop Vppb M1 Vss Vss Vss D17 Vpb Vppb Vpp M31 Vss Vss Vss D21 VDD Vpp VDD T1 Vss Vss Vss D25 VDD VpD VoD T31 Vss Vss Vss D28 VpD Vpp VDD Y1 Vss Vss vss D4 VDD Vop Vop Y31 Vss Vss Vss D7 VDD VoD Vopb Al VoD Vob VDD G28 VDD Vop Vbb A31 VDD VDD VbD G4 Vop Vop Vob AA28 VpD VDD VDD L28 Vop VpD VDD AA4 Vpb Voppb Vop L4 VDD VDD VDD AE28 VDD Vpp VDD R28 VDD Vopp Vpp AE4 Vpb Vpb Vpb R4 VDD VpD VDD AH11 VDD Vpb VDD U28 Vopb VDD VbD AH15 VoD VoD VDD U4 Vop Vpp VDD 186 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout Pin ons 25 Function Pin maine 25 Function E4 PRD_CFGN RD_CFG R2 PR12C vO E3 PR1D vO Ri PR12B VO E2 PR1C V/O T4 PR12A VO F5 PR1B VO T3 PR13D 1/0 F4 PRIA Oo T2 PR13C /O F3 PR2D /O U2 PR13B VO F2 PR2C VO U4 PR13A Oo G5 PR2B 1/0 U5 PR14D VO G4 PR2A /O U3 PR14C (0 G3 PR3D VO U1 PR14B /O G2 PR3C vO V2 PECKR I-ECKR H5 PR3B /O V4 PR15D VO H4 PR3A V/O-wWR V5 PR15C VO H3 PR4D VO V3 PR15B 1/0 H2 PR4C /O We2 PR15A /O J5 PR4B (8) W3 PRi6D /O J4 PR4A /O W4 PR16C VO J3 PR5D VO W5 PR16B /O J2 PR5C VO Y2 PR16A VO J1 PR5B vO Y3 PR17D vO K5 PR5A 1/0 Y4 PR17C VO K4 PR6D 1/0 AA1 PR17B /O K3 PR6C VO AA2 PR1I7A 1/0O-M3 K2 PR6B VO AAS PR18D VO K1 PR6A VO AA4 PRi8C VO L4 PR7D /O AA5 PR18B 1/0 L3 PR7C 1/0 AB1 PR18A /O L2 PR7B /O AB2 PRi9D VO L1 PR7A /O-RD/MPI_STRB AB3 PR19C vO M5 PR8D vO AB4 PR19B /O M4 PR8C 0 AB5 PR19A /0-M2 M3 PR8B 1/0 AC2 PR20D VO M2 PR8A 1/0 AC3 PR20C VO M1 PR9D /O AC4 PR20B VO N5 PROC vO AC5 PR20A VO N4 PROB 1/0 AD1 PR21D VO N3 PR9A /O-CSO AD2 PR21C vO N2 PR10D VO AD3 PR21B VO P4 PR10C VO AD4 PR21A VO P5 PR10B 1/0 AD5 PR22D /O-M1 P3 PR10A 1/0 AE1 PR22C VO P2 PR11D VO AE2 PR22B V/O P14 PR11C vO AE3 PR22A vO R4 PR11B VO AE4 PR23D vO R5 PR11A /0-CS1 AF4 PR23C VO R3 PR12D VO AF2 PR23B VO Lucent Technologies Inc. 187Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout (continued) Pin OR 25 Function Pin one 25 Function AF3 PR23A vO AP10 PB23C 0 AF4 PR24D /O AR10 PB23B VO AF5 PR24C /O AM11 PB23A V/O AG1 PR24B Oo AN11 PB22D VO AG2 PR24A VO AP11 PB22C VO AG3 PR25D /O AR11 PB22B VO AG4 PR25C V/O AL12 PB22A VO AG5 PR25B VO AM12 PB21D VO AH2 PR25A VO AN12 PB21C VO AH3 PR26D vO AP12 PB21B VO AH4 PR26C VO AR12 PB21A VO AH5 PR26B VO AL13 PB20D VO AJ2 PR26A VO AM13 PB20C VO AJ3 PR27D VO AN13 PB20B VO AJ4 PR27C VO AP13 PB20A 1/O-LDC AJ5 PR27B VO AM14 PBi9D VO AK2 PR27A VO AL14 PB19C VO AK3 PR28D VO AN14 PB19B VO AK4 PR28C VO AP14 PB19A VO AK5 PR28B VO AR14 PB18D VO AL2 PR28A 1/O-MO AM15 PB18C VO AL3 PPRGMN PRGM AL15 PB18B Vo AL4 PRESETN RESET AN15 PB18A 1//O-HDC AM5 PDONE DONE AP15 PB17D VO ANS5 PB28D VO AR15 PB17C VO AP5 PB28C /O AM16 PBi7B VO AL6 /O AN16 PB1i7A VO AM6 PB28B /O AP16 PB16D VO AN6 PB28A VO AP17 PB16C /O AP6 PB27D VO AM17 PB16B VO AL7 PB27C VO AL17 PB16A /O AM7 PB27B VO AN17 PB15D /O AN7 PB27A VO AR17 PB15C 1/0 AP7 PB26D VO AP18 PB15B /O AL8 PB26C VO AM18 PECKB |-ECKB AM8 PB26B VO AL18 PB14D VO AN8 PB26A 1/0 AN18 PB14C VO AP8 PB25D VO AP19 PB14B /O AL9 PB25C VO AN19 PB14A 1/0 AM9 PB25B VO AM19 PB13D //O AN9 PB25A VO AL19 PB13C Vo AP9 PB24D VO AP20 PB13B VO ARQ PB24C VO AN20 PB13A VO AL10 PB24B /O AM20 PB12D Oo AM10 PB24A VO-INIT AR21 PB1i2C VO AN10 PB23D /O AP21 PBi2B /O 188 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout (continued) Pin OR 25 Function Pin On 25 Function AN21 PB12A VO AL32 PCCLK CCLK AM21 PB11D VO AL33 PL28A VO-A15 AL21 PB11C VO AL34 PL28B /O AR22 PB11B VO AK31 PL28C VO AP22 PB11A VO AK32 PL28D 1/0 AN22 PB10D VO AK33 VO AM22 PB10C VO AK34 PL27A VO-SECKLL AL22 PB10B VO AJ31 PL27B VO AP23 PB10A 1/0 AJ32 PL27C VO AN23 PB9D /O AJ33 PL27D Vo AM23 PBSC /O AJ34 PL26A VO AL23 PB9SB VO AH31 PL26B VO AR24 PB9A VO AH32 PL26C VO AP24 PB8D 1/0 AH33 PL26D VO AN24 PB8C VO AH34 PL25A VO AM24 PB8B /O AG31 PL25B VO AL24 PB8A /O AG32 PL25C VO AR25 PB7D vO AG33 PL25D VO AP25 PB7C VO AG34 PL24A VO-A14 AN25 PB7B 2) AG35 PL24B vO AM25 PB7A VO AF31 PL24C VO AR26 PB6D /O AF32 PL24D VO AP26 PB6C /O AF33 PL23A VO AN26 PB6B VO AF34 PL23B vO AM26 PB6A VO AF35 PL23C VO AL26 PB5D /O AE32 PL23D VO AR27 PB5C /O- AE33 PL22A VO AP27 PB5B VO AE34 PL22B VO AN27 PB5A VO AE35 PL22C VO AM27 PB4D O-A17 AD31 PL22D /O AL27 PB4C /O AD32 PL21A /O AP28 PB4B /O AD33 PL21B /0-A13 AN28 PB4A VO AD34 PL21C /O AM28 PB3D VO AD35 PL21D VO AL28 PB3C 1/0 AC31 PL20A vO AP29 PB3B //O AC32 PL20B VO AN29 PB3A VO AC33 PL20C vO AM29 PB2D vO AC34 PL20D /0-A12 AL29 PB2C VO AB32 PLI9A 1/0-A11/MPI_IRQ AP3O PB2B VO AB31 PL19B 1/0 AN30 PB2A VO AB33 PL19C VO AM30 PB1D (/O AB34 PL19D VO AL30 PB1C vO AB35 PL1I8A VO AP31 VO AA32 PL18B VO AN31 PB1B 1/0 AA31 PL1i8C /O AM31 PBIA /O-A16 AA33 PL18D vO Lucent Technologies Inc. 189Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout (continued) Pin on Function Pin ons Function AA34 PLI7A 1/0-A10/MPI_BI K33 PL6C VO AA35 PL17B VO K32 PL6D /O Y32 PL17C VO K31 PL5A VO 33 PLi7D 0 J35 PL5B /O Y34 PLi6A /O J34 PL5C 1/0 W34 PLi6B /O J33 PL5D /O Ww32 PL16C /O J32 PL4A VO W311 PL1i6D (/O-A9/MPI_LACK J31 PL4B 1/0 W33 PL15A 1/O-A8/MPI_RW H34 PL4Cc VO W35 PL15B VO H33 PL4D VO V34 PL15C /O H32 PL3A VO V32 PL15D /O H31 PL3B VO V31 PL14A VO-A7/MPI_CLK G34 PL3C vO V33 PL14B 1/0 G33 PL3D vO U34 PL14C /O G32 PL2A VO U33 PECKL I-ECKL G31 PL2B VO U32 PL13A 1//O-A6 F34 PL2C vO U31 PL13B 1/0 F33 PL2D 1/O-A0/MPI_BEO T34 PL13C 1/0 F32 PLIA VO T33 PL13D 1/0 F31 PL1B ie) T32 PL12A 1/0 E34 PL1C VO R35 PL12B 1/0 E33 VO R34 PLi2C 1/0 E32 a) Vo R33 PL12D 1/0-A5 D31 PRD_DATA RD_DATA/TDO R32 PL11A /0-A4 C31 PT1A VO-TCK R31 PL11B 0 B31 VO P35 PL1iC VO E30 PT1B VO P34 PL11D VO D30 PT1C VO P33 PLI0A 1/0 C30 PT1D VO P32 PL10B /O B30 PT2A VO P31 PL10C VO E29 PT2B VO N34 PL10D VO D29 PT2C /O N33 PL9OA 1//0-A3 C29 PT2D /O N32 PL9B VO B29 PT3A 1/0 N31 PL9C VO E28 PT3B /O M35 PL9D VO D28 PT3C VO M34 PL8A /0-A2 C28 PT3D /O M33 PL8B VO B28 PT4A /O-TMS M32 PL8C VO E27 PT4B VO M31 PL8D VO D27 PT4C VO L35 PL7A VO C27 PT4D VO L34 PL7B VO B27 PT5A vO L33 PL7C VO A27 PT5B VO L32 PL7D V/O-A1/MPI_BE1 E26 PT5C VO K35 PL6A vO D26 PT5D Vo K34 PL6B vO C26 PT6A //O-TDI 190 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout (continued) Pin Ore 25 Function Pin Oe 25 Function B26 PT6B VO C15 PT17D VO A26 PT6C VO D15 PT18A //O-D5 D25 PT6D VO E15 PT18B VO C25 PT7A /O A14 PT18C VO B25 PT7B VO Bi4 PT18D VO A25 PT7C vO C14 PT19A VO E24 PT7D VO D14 PT19B VO D24 PT8A /O E14 PT19C VO C24 PT8B VO B13 PT19D VO B24 PT8C /O C13 PT20A vO A24 PT8D VO D13 PT20B Oo E23 PT9A VO E13 PT20C VO D23 PT9B VO A12 PT20D /0-D6 C23 PT9C VO B12 PT21A VO B23 PT9D VO C12 PT21B VO D22 PT10A /0-DOUT Di2 PT21C /O E22 PT10B VO E12 PT21D VO C22 PT10C /O Ali PT22A VO B22 PT10D /O B11 PT22B VO A22 PT11A VO C11 PT22C VO D21 PT11B vO D11 PT22D VO E21 PT11C VO A10 PT23A VO C21 PT11D VO Bio PT23B VO B21 PT12A /0-D0/DIN C10 PT23C VO A21 PT12B VO D10 PT23D 0 D20 PT12C VO E10 PT24A VO C20 PT12D VO AQ PT24B vO B20 PT13A 1/0 B9 PT24C VO B19 PT13B VO cg PT24D /O-D7 D19 PT13C VO D9 PT25A 0 E19 PT13D /O-D1 E9 PT25B VO C19 PT14A VO-D2 Bs PT25C VO A193 PT14B /O C8 PT25D /O B18 PT14C VO D8 PT26A /O D18 PT14D /O Es PT26B /O E18 PTI5A VO-D3 B7 PT26C VO C18 PT15B VO C7 PT26D 1/0 B17 PT15C VO D7 PT27A VO-RDY/RCLK/MPI_ALE C17 PECKT !-ECKT E7 PT27B /O D17 PTI6A /0-D4 B6 PT27C VO E17 PT16B //O C6 PT27D VO B16 PT16C VO D6 PT28A VO C16 PT16D /O E6 PT28B ie) Di6 PT17A VO B5 PT28C VO A15 PT17B VO C5 VO B15 PT17C VO D5 PT28D /O-SECKUR Lucent Technologies Inc. 191Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout (continued) Pin on 25 Function Pin One 25 Function A13 Vss Vss B3 Vss Vss A1i6 Vss Vss B32 Vss Vss A20 Vss Vss B33 Vss Vss A23 Vss Vss B4 Vss Vss A28 Vss Vss C1 Vss Vss A29 Vss Vss C2 Vss Vss A3 Vss Vss C32 Vss Vss A32 Vss Vss C34 Vss Vss A33 Vss Vss C35 Vss Vss A4 Vss vss C4 Vss Vss A7 Vss Vss D1 Vss Vss A8 Vss Vss D2 Vss Vss AC1 Vss Vss D3 Vss Vss AC35 Vss Vss D33 Vss Vss AH1 Vss Vss D34 Vss Vss AH35 Vss Vss D35 Vss Vss AJ1 Vss Vss G1 Vss Vss AJ35 Vss Vss G35 Vss Vss AM1 Vss Vss H1 Vss Vss AM2 Vss Vss H35 Vss Vss AM3 Vss Vss N1 Vss Vss AM33 Vss Vss N35 Vss Vss AM34 Vss Vss T1 Vss Vss AM35 Vss Vss T35 Vss Vss AN1 Vss Vss Y1 Vss Vss AN2 Vss Vss Y35 Vss Vss AN32 Vss Vss Al Vpb Vbb AN34 Vss Vss A17 Vpp VDD AN35 Vss Vss A18 VoD VbD AN4 Vss Vss A2 Vop VDD AP3 Vss Vss A30 VDD Vpb AP32 Vss Vss A31 Vpp Vpb AP33 Vss Vss A34 VDD Vpb AP4 Vss Vss A385 VbD VDD AR13 Vss Vss A5 Vpo VDD AR16 Vss Vss A6 VDD Vop AR20 Vss Vss AE31 Vob VbD AR23 Vss Vss AE5 VpD VDD AR28 Vss Vss AK1 VDD Vpb AR29 Vss Vss AK35 VDD VoD AR3 Vss Vss AL1 VbD VDD AR32 Vss Vss AL11 Vbb Vpb AR33 Vss Vss AL16 Vpp VpD AR4 Vss Vss AL20 VpD VDD AR7 Vss Vss AL25 Voo VbD AR8 Vss Vss AL31 Vopp VDD 192 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout (continued) Pin ORST125 Function Pin OR3T125 Function Pad Pad AL35 VoD Vop C3 Vop VppD AL5 VDD VpD C33 Vop Vpp AM32 VDD Vpb D32 Vob VDD AM4 VoD VoD D4 VDD VDD ANS Vpp Vopb E1 VbbD Voo AN33 VDD Vobp E11 VbD VDD AP1 VoD Vobd E16 Voo Vob AP2 VDD Vpb E20 Vpp VDD AP34 Vbpb VDD E25 Vopp VoD AP35 VoD VpD E31 VDD VDD AR1 Vob Vbb E35 Voo Voo AR18 VDD Vopo E5 VpD VDD AR19 VoD VDD Fi VoD VbD AR2 VpD VDD F35 Vop VDD AR30 VoD Vob L31 Vob Voo AR31 VDD VoD L5 VDD VbD AR34 VDD VoD T31 VoD VDD AR35 VpD Vpb T5 Vpp Vob AR5 VbD VoD U35 Vob VDD AR6 Vbb Voo vi Vpp VpD Bi VpD Voo V35 VDD VDD B2 VoD VpD W1 VDD VpD B34 Vpb VoD Y31 Vpb VDD B35 VpD Vbppb 5 VbDD VDD Lucent Technologies inc. 193ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Package Thermal Characteristics There are four thermal parameters that are in common use: QA, VIC, GUC, and euB. It should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. The data base containing the thermal values for all of Lucent Technologies IC packages is currently being updated to conform to modern JEDEC standards. Thus, Table 76 contains the currently available thermal specifications for Lucent Technologies FPGA pack- ages mounted on both JEDEC and non-JEDEC test boards. The thermal values for the newer package types correspond to those packages mounted on a JEDEC four-layer board. The values for the older pack- ages, however, correspond to those packages mounted on a non-JEDEC, single-layer, sparse copper board (see Note 2). It should also be noted that the values for the older packages are considered conservative. @JA This is the thermal resistance from junction to ambient (a.k.a. theta-JA, R-theta, etc.). TJ-TA QJA = a where Ty is the junction temperature, TA is the ambient air temperature, and Q is the chip power. Experimentally, QJA is determined when a special ther- mal test die is assembled into the package of interest, and the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The package/board is placed either ina JEDEC natural convection box or in the wind tunnel, the latter for forced convection measurements. A controlled amount of power (Q) is dissipated in the test chip's heater resistor, the chips temperature (Tu) is deter- mined by the forward drop on the diodes, and the ambi- ent temperature (TA) is noted. Note that QJA is expressed in units of C/watt. 194 wJC This JEDEC designated parameter correlates the junc- tion temperature to the case temperature. It is generally used to infer the junction temperature while the device is operating in the system. It is not considered a true thermal resistance, and it is defined by: TJ-TC WIC = > where Tc is the case temperature at top dead center, Ty is the junction temperature, and Q is the chip power. During the QJA measurements described above, besides the other parameters measured, an additional temperature reading, Tc, is made with a thermocouple attached at top-dead-center of the case. wc is also expressed in units of C/watt. eJC This is the thermal resistance from junction to case. It is most often used when attaching a heat sink to the top of the package. It is defined by: TJ-TC OJC = The parameters in this equation have been defined above. However, the measurements are performed with the case of the part pressed against a water-cooled heat sink so as to draw most of the heat generated by the chip out the top of the package. It is this difference in the measurement process that differentiates Quc from Wc. Ouc is a true thermal resistance and is expressed in units of C/watt. OJB This is the thermal resistance from junction to board (a.k.a. QUL). It is defined by: Ts-T! Q where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other param- eters on the right-hand side have been defined above. This is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board so as to draw most of the heat out of the leads. Note that Que is expressed in units of C/watt, and that this parameter and the way it is measured is still in JEDEC committee. QJB = Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Package Thermal Characteristics (continued) FPGA Maximum Junction Temperature Once the power dissipated by the FPGA has been determined (see the Estimating Power Dissipation section), the maximum junction temperature of the FPGA can be found. This is needed to determine if speed derating of the device from the 85 C junction temperature used in all of the delay tables is needed. Using the maximum ambient temperature, TAmax, and the power dissipated by the device, Q (expressed in C), the maximum junction tempera- ture is approximated by: TJmax = TAmax + (Q * Qua) Table 76 lists the plastic package thermal characteristics for the ORCA Series FPGAs. Table 76. Plastic Package Thermal Characteristics for the ORCA Series' Qua (('C/IW) TA = 70 C max Package 0 fpm 200 fpm 500 fpm "5 O tpn wy 208-Pin SQFP' 26.5 23.0 21.0 2.1 208-Pin SQFP2!' 12.8 10.3 9.1 4.3 240-Pin SQFP' 25.5 22.5 21.0 2.2 240-Pin SQFP2! 13.0 10.0 9.0 4.2 256-Pin PBGA' 2 22.5 19.0 17.5 2.4 256-Pin PBGA? 3 26.0 22.0 20.5 2.1 352-Pin PBGA! 4 19.0 16.0 15.0 2.9 352-Pin PBGA' 25.5 22.0 20.5 2.1 432-Pin EBGA' 11.0 8.5 7.5 5.0 600-Pin EBGA' 11.0 8.5 7.5 5.5 1. Mounted on 4-layer JEDEC standard test board with two power/ground planes. 2. With thermal balis connected to board ground plane. 3. Without thermal balls connected to board ground piane. Lucent Technologies Inc. 195ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Package Coplanarity The coplanarity limits of the ORCA Series 3 packages are as follows. Table 77. Package Coplanarity Coplanarity Limit Package Type P (mils) EBGA 8.0 PBGA 8.0 SQFP/SQFP2 4.0 3.15 Package Parasitics The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. Table 78 lists eight parasitics associated with the ORCA packages. These parasitics Table 78. Package Parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. Four inductances in nH are listed: Lsw and LsL, the self-inductance of the lead; and Law and LML, the mutual inductance to the nearest neighbor lead. These parameters are important in determining ground bounce noise and inductive crosstalk noise. Three capacitances in pF are listed: Cm, the mutual capaci- tance of the lead to the nearest neighbor lead; and C1 and C2, the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). These parameters are important in determining capaci- tive crosstalk and the capacitive loading effect of the lead. The lead resistance value, Rw, is in MQ. The parasitic values in Table 78 are for the circuit model of bond wire and package lead parasitics. If the mutual capacitance value is not used in the designer's model, then the value listed as mutual capacitance should be added to each of the C1 and C2 capacitors. Package Type Lsw Luw Rw C1 C2 Cm LSL LML 208-Pin SQFP 4 2 200 1 1 1 710 46 208-Pin SQFP2 4 2 200 1 1 1 69 46 240-Pin SQFP 4 2 200 1 1 4 812 58 240-Pin SQFP2 4 2 200 1 1 1 711 47 256-Pin PBGA 5 2 220 1 1 1 58 24 352-Pin PBGA 5 2 220 1.5 1.5 1.5 712 36 432-Pin EBGA 4 1.5 500 1 1 0.3 3--5.5 0.51 600-Pin EBGA 4 1.5 500 1 1 0.4 36 0.51 Lsw Rw Lst BOARD PAD PAD N PADN+1 5-3862(F).a Figure 104. Package Parasitics 196 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Package Outline Diagrams Terms and Definitions Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. Design Size: The design size of a dimension is the actual size of the design, including an allowance for fit and tolerance. Typical (TYP): When specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. Reference (REF): The reference dimension is an untoleranced dimension used for informational purposes only. It is a repeated dimension or one that can be derived from other values in the drawing. Minimum (MIN) or Maximum (MAX): Indicates the minimum or maximum allowable size of a dimension. Lucent Technologies Inc. 197Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Package Outline Diagrams (continued) 208-Pin SQFP Dimensions are in millimeters. 30.60 + 0.20, ______- 1.30 REF 28.00 + 0.20 _____ PIN #1 IDENTIFIER ZONE 208 157 AAA AAA A A 0.25 == f GAGE PLANE = SEATING PLANE = __ | = _.| J~ 0.50/0.75 = = DETAIL A = = 28.00 + 0.20 = = 30.60 = = + 0.20 = = 0.090/0.200 = = 0.17/0.27 | = | 52 = = 105 { UIUUUUZESUUSUUOUCHOOUERRIMUURUCOUUGERMUGWUUEHY _ DETAILB DETAILA DETAIL B J [ 3.40 + 0.20 4 C y Inn _ 0.50 TYP _.| LL ~ 0.25 MIN J Lit 4.10 MAX SEATING PLANE {O [0.08 | Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Lucent Technologies Sales Representative. 198 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Package Outline Diagrams (continued) 208-Pin SQFP2 Dimensions are in millimeters. 30.60 + 0.20 28.00 + 0.20 ______ 21.0 REF ______- bos | PIN #1 IDENTIFIER ZONE 157 1.30 REF ARIAT ARTA A = = 156 } = = ft 0.25 = = GAGE PLANE | = = SEATING PLANE f | = == 210 J 0.50/0.75 = = 28.00 = = 0.20 DETAILA = = 30.60 = = 0.20 = = 0.090/0.200 = = _t = = + 0.17102=| b | = 105 i eae aC x; 53 104 DETAIL B EXPOSED HEAT SINK APPEARS ON BOTTOM SURFACE: CHIP BONDED FACE UP. (SEE DETAIL C.) DETAILA DETAIL B J. [- 3.40 + 0.20 Ob a | 41d max SO ee CUNEIMM N+ 34 = | seatine PLANE ~~ oso tve+l | 0.25 MIN q La {o.08) eee / CHIP BONDED FACE UP fa es } \_ STE TZ COPPER HEAT SINK DETAIL C (SQFP2 CHIP-UP) 5-3828(F).a Lucent Technologies Inc. 199Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Package Outline Diagrams (continued) 240-Pin SQFP Dimensions are in millimeters. B4E 0 O20 mmm nt 32.00 + 0.20 ___-_} PIN #1 IDENTIFIER ZONE 1.30 REF 240 181 CATT A ; lo 5 180 = 0.25 = = GAGE PLANE } = SEATING PLANE = 0.50/0.75 = = DETAILA = = 32.00 + 0.20 = = 34.60 = + 0.20 = = ;oononat = = 0.1710.271 ~ = = $0108) = = DETAIL B o= = 121 aU i 61 120 DETAIL A DETAIL B Lo [ 3.40 + 0.20 N / 4 F NIN - eee pee SEATING PLANE 0.50 TYP _.| lo1o.08 | Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Lucent Technologies Sales Representative. 0.25 MIN 200 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Package Outline Diagrams (continued) 240-Pin SQFP2 Dimensions are in millimeters. 34.60 + 0.20 _____________ 32.00 + 0.20 -_-_______ [ewer wen 24.2 REF _ | 240 PIN #1 IDENTIFIER ZONE 181 a Oe eee eer ere a ae uO Ra aU EXPOSED HEAT SINK APPEARS ON BOTTOM SURFACE: CHIP BONDED FACE UP. (SEE DETAIL C.) DETAIL A DETAIL B J / 3.40 +0.20 4 4 ST TTT, t+ *"ysearine pane 0.50 TYP _.| | 0.25 MIN f let o.08 | / CHIP BONDED FACE UP ND fees COPPER HEAT SINK DETAIL C (SQFP2 CHIP-UP) -3825(F).a Lucent Technologies Inc. 201; Data Sheet ORCA Series 3C and 3T FPGAs June 1999 Package Outline Diagrams (continued) 256-Pin PBGA Dimensions are in millimeters. }~____-_-- 27.00 + 0.20 +0.70 24.00 _.00 Ai BALL IDENTIFIER ZONE All| +0.70 24.00 -0.00 27.00 + 0.20 moto _4 COMPOUND \ iw PWB ~] , Y 0.38 # 0.04 1.17 40.05 7 2.13 0.19 y 4 Sa hog errr RETO TET UT EST {SEATING PLANE f t XK IQLo207 0.60 +0.10 SOLDER BALL 19 SPACES @ 1.27 = 24.13 Y 00000000000000000000 7 Wloooo0c000D 0000000000 Vv 0000000000\0000000000 t uloon000 00 0000000000007 Tloaoo e000 R] 0990 | 0000] 975+0.15 Ploooo 2000 N] OC OO ' eo0o0o Mj) Oooo ooloo e000 L] 0000 colle 0900 19 SPACES K1TO9060 7 &#+4+; G06 ~ 7 o60007 @ 1.27 = 24.13 Jj o00o0 eoloo e000 Hj] oo0 eoo0o Glo ' 0000 F 000 ooo CENTER ARRAY l oo 0 0 | cooe EASE Dl eoo000000000000000000 (OPTIONAL) ClLocecoD OOOO OO OO0000000 (SEE NOTE BELOW) Blondc0 COCO OD Ol O00 000000 q eccoococacoooocOOONdND 72345678910 12 14 16 18 20 Qi BALL 7 113 415~17~19 5-4406(F) Note: Although the 16 thermal enhancement balls are stated as an option, they are standard on the 256 FPGA package. 202 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Package Outline Diagrams (continued) 352-Pin PBGA Dimensions are in millimeters. << 35.00 + 0.20 ___--__> +0.70 _ A1 BALL 30.00 9.00 IDENTIFIER ZONE : . yy | T \ [ ' | PLoins | | +0.70 JL ef 1 000 | 35.00 | + 0.20 d MOLD 7 ! COMPOUND NN | WA Un + , PWB ot 1172008 | 2.93 20.21 1 pont eet SEATING PLANE t XK 0.60 + 0.10 SOLDER BALL pe 25 SPACES @ 1.27 = 31.75 AF | 00000000000000000000000000 : AE| CO900000000000000000000000 ap} 00000000000000000000000000 t Ac] 0060000000000000000000000007 AB 9900 9900 AA} COCO 000 -y|o0000 | 02000 0.75 40.15 wl o0ooo 0000 vl} ooo0o | 2000 u{ 0000 0000 T 9990 000P00 0000 R| OOO 000600 0000 PLOQOO _ __ 909900 __ _ _9990} 25 SPACES NT O000 oOCp00 o000 @ 1.27 = 31.75 M{ OOOO 000000 0000 L}] 0000 ooopoo 0000 K| 0000 0000 J[ oo | 0000 CENTER ARRAY _#4+8289 - 3388 FOR THERMAL fj o900 J 0000 ENHANCEMENT Ee] 0000 0000 . _ (OPTIONAL) . D 9009000000000 999000000000 Cc] OO00000000000000 (SEE NOTE BELOW) = 5} 00000000000009000000000000 ' A] 00000000000000000000000000 Ai Batt _A 12345678 910,12 44 16, 18,20, 22,26, 26 5-4407(F) Note: Although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 FPGA package. Lucent Technologies Inc. 203ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Package Outline Diagrams (continued) 432-Pin EBGA Dimensions are in millimeters. A1 BALL 40.00 + 0.10 __-__} IDENTIFIER ZONE \ J--- +-=-- S88 wm ww | 1.54 + 0.13 ffenestr SEATING E PLANE SOLDER BALL 0.63 + 0.07 -e-30 SPACES @ 1.27 = 38.10 -_ 1 ALFoooo000CC ODD D0000000D00000000000 AK 900000000000009000000000000000 a AlPO0000000600000000000000000000000 AH 0000000000000009000000000000000 AG] OO00 1 0000 t AF e000 e000} AEL O000 e000 AD e000 I e000 ACL Oooo e000 0.75 +0.15 AB e000 | 9000 AA} O00 0000 Y 0000 a000 Wlooco | 9000 Vv 0000 e000 UL oo0eo e000 T speoso| +. |sesat 30 SPACES 000 9000 P 0000 e000 @ 1.27 = 38.10 Nl oooo 0000 M e000 e000 L|oooo | e000 K e000 e000 Jl ooo0o e000 H e000 | e000 Gloooo o000 F 0000 0000 Ef oooo e000 o ed00000c0CCOODDOND COCO OOCODNDCSo0N0000 Cloooo 00 OCC ODO OO Og OOO DOOD ND0000000 B 0000000000000000000000000000000 ' A] 0000000000000009000000000000000 A1 BALL 13 Ay BALL 7 z 4 204 5 7 9 11 13 15 17 19 21 23 25 27 29 31 6 8 10 12 14 16 16 20 22 24 26 28 30 5-4409(F) Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Package Outline Diagrams (continued) 600-Pin EBGA Dimensions are in millimeters. A1 BALL IDENTIFIER ZONE a 0 | ! 1 ; | Pos | 45.00 +---+---} +0.10 l | | , I 0.91 + 0.06 0.63 + 0.07 je 34 SPACES @ 1.27 = 43.18 _> |. AR 100000000000000000000000000000000000 AP 188992999099000000990900000000000000 AN 190000090000000000000000000000000000 AM 1000000000090000009600006000000000000 4 100000000006000000$660006000600000000 | AK [O0000 900007 ailoaooa 90900 AH | [00000 | 00000 aa looado 00000 AF 100000 00000 AE lOO900 oo00co AD. [00000 00000 ac [00000 00000 ag |o0000 90000 aa |00000 1 60000 vy [00000 00000 w|oo0000 00000 v seoecef[ - -_-_~ /] eceeo+ u }ooa00 00000 T _ jo0000 00000 R]00000 I 90000 Pp Jo0000 00000 n ]o0000 o0c00 mu [oo000 | eoc00 LJo0000 00000 k ~foooce 00000 J}oo0so | 90000 4 ~j00000 00900 a ]ooo000 00000 F _|o0000 00000 100000000000000000660000000000000000 D }90000000000000000000000000000000000 1006000000000000009000000000060000000 B |00000000000000000500000000000000000 4100000000000000000900000000600000000 3.5 7 8 11 13:15 17 19 21 23 25 27 29 31 33 35 A1BALL_4% 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 92 36 CORNER Lucent Technologies inc. 1.54+0.13 SEATING PLANE een BALL | rg 0.75 0.15 34 SPACES @ 1.27 = 43.18 5-4408(F) 205ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Ordering Information Example: SPEED GRADE OR3C80-4 PS 240 DEVICE TYPE _ Fits TEMPERATURE RANGE NUMBER OF PINS PACKAGE TYPE OR3C80, -4 Speed Grade, 240-pin Power Quad Shrink Flat Package (SQFP2), Commercial Temperature Table 79. Voltage Options Device Voltage OR3Cxx 5.0V OR3Txxx 3.3 V Table 80. Temperature Options Symbol Description Temperature (Blank) Commercial 0 C to 70C I Industrial 40 C to +85 C Table 81. Package Options Symbol Description BA Plastic Ball Grid Array (PBGA) BG Enhanced Ball Grid Array (EBGA) PS Power Quad Shrink Fiat Package (SQFP2) $s Shrink Quad Fiat Package (SQFP) Table 82. ORCA Series 3 Package Matrix 208-Pin 208-Pin 240-Pin 240-Pin 256-Pin | 352-Pin | 432-Pin 600-Pin Packages EIAJ SQFP | EIAJ/SQFP2! EIAJ SQFP!| EIAJ/SQFP2; PBGA PBGA EBGA EBGA $208 PS208 $240 PS240 BA256 BA352 BC432 BCc600 OR3T20 Cl _ Cl Cl Cl _ _ OR3T30 Cl Cl Cl Cl _ _ OR3C/T55 _ Cl Cl Cl Cl _ _ OR3C/T80 Cl Cl Cl Cl OR3T125 _ Cl Cl ~ Cl Cl Cl Key: C = commercial, | = industrial. Table 83. Speed Grade Options Device Speed Grade OR3Cxx -4, -5 OR3Txxx -5, -6, -7 206 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs index A Absolute Maximum Ratings, 96 AND-OR-INVERT (AO)), 6 AND-OR-INVERT (AOI),1 (see also Supplemental Logic Interconnect Cell (SLIC), 1 Architecture Overview, 69 ASWE, 9, 11, 1517, 23, 33, 48 B Bidirectional Buffers (BIDIs), 6, 19, 43, 83 (see also Routingand SLIC) Bit Stream (see FPGA Configuration) Bit Stream Error Checking, 88 (see also FPGA states of Operation) Boundary Scan, 55 (see Special Function Blocks) Cc Clock Control (CLKCNTRL), 50 (see also Clock Distribution Network and Special Function Blocks) Clock Distribution Network, 48-51 CLKCNTRL, 50 ExpressCLk, 48 inputs, 51 Fast Clock, 48, 51 Global Control Signals, 48 In the PICs ExpressCLK, 50 System Clock, 50 in the PLC Array Fast Clock, 49 System Clock, 49 PFU Clock Sources, 48 Selecting Clock Input Pins, 51 System Clock, 48 To the PLC Array Fast Clock, 50 System Clock, 50 Clock Enable (CE), 9, 11, 17, 23, 31, 48 Clock Multiplication (see PCM) Comparator (see LUT Operating Modes) Configuration (see FPGA States of Operation or FPGA Configuration) Control Inputs (see PICs, Inputs) D Demultiplexing (see PICs, Input Demultiplexing), 38 Duty-Cycle Adjustment (see PCM) Lucent Technologies Inc. E Electrical Characteristics, 97, 98 Error Checking (see FPGA Configuration) ExpressCLk, 1, 6, 31, 34, 37, 39, 41, 43, 4751, 7074, 7781 (see also Clock distribution Network and Programmable Clock Manager) F Fast Clock, 4651, 54 (see Clock Distribution Network) 5 V Tolerant /O 35 Flexible Input Structure (FINS) 1, 27, 32 (see also Routing) FPGA Configuration, 87--94 Configuration Frame Format, 87 Configuration Modes, 89 Asynchronous Peripheral Mode, 91 Daisy-Chaining, 95 Master Parallel Mode, 89 Master Serial Mode, 90 Microprocessor Interface (MPI) Mode, 91 Slave Parailel Mode, 94 Slave Serial Mode, 94 Data Format, 86 Data Frame, 86 Using ORCA Foundry to Generate RAM Data, 86 FPGA States of Operation Configuration, 83 Initialization, 82 Other Configuration Options, 85 Partial Reconfiguration, 85 Reconfiguration, 85 Start-Up, 84 J/EEE Standard, 1149.1 55, 59 Initialization (see FPGA States of Operation) Input/Output Buffers Measurement Conditions, 138 Output Buffer Characteristics OR3Cxx, 139 ORSTxxx, 141 J JTAG (see Boundry Scan) 207ORCA Series 3C and 3T FPGAs Data Sheet June 1999 index (continued) L Look-Up Table (LUT) Operating Modes, 1118 Adder-Subtractor Submode, 15 Counter Submode, 15 Equality Comparators, 16 Half-Logic Mode, 14 Logic Mode, 12 Memory Mode, 17 Multiplier Submode, 16 Ripple Mode, 14 LSR, 11, 17, 2824, 31, 48 Maximum Ratings (see Absolute Maximum Ratings) Microprocessor Interface (MPI), 6269 i960 System, 64 Interface to FPGA, 65 PowerPC System, 63 Setup and Control Registers, 66 Multiplexing (see Output Multiplexing) Multiplier (see LUT Operating Modes) Oo ORCA Foundry Development System, 25 Overview, 7 Ordering Information Package Matrix, 207 Package Options, 207 Temperature Options, 207 Voltage Options, 207 Output (see PICs) Output Multiplexing, 39 P Package Information, 200206 Package Matrix, 204 Package Outline Diagrams, 200 208-Pin SQFP2, 199 240-Pin SQFP2, 202 256-Pin PBGA, 203 352-Pin PBGA, 204 432-Pin EBGA, 205 600-Pin EBGA, 206 Terms and Definitions, 200 PAL, 1 (see also Supplemental Logic and interconnect Cell (SLIC)) 1 PIC Routing (see Routing) Pin information 208-Pin SQFP2 Pinout, 151 240-Pin SQFP2 Pinout, 156 256-Pin PBGA Pinout, 162 352-Pin PBGA Pinout, 165 208 432-Pin EBGA Pinout, 177 600-Pin EBGA Pinout, 184 Package Compatibility, 152 Pin Descriptions 147, 151 Power Dissipation, 144 5 V Tolerant VO, 143 OR3Cxx, 144 OR3Txxx, 145 PowerPC (see Microprocessor Interface) Programmable Clock Manager (PCM), 6, 81 Clock Delay, 74 Clock Multiplication, 75 DLL Mode, 73 PCM Cautions, 81 PCM Detailed Programming, 77 PCM Operation, 76 PCM/FPGA Internal Interface, 76 PLL Mode, 74 Registers, 71 Programmable Function Unit (PFU), 9 Cintrol Inputs, 11 Operating Modes, 11 Softwired LUTs (SWL), 12 Twin-quad Architecture, 1, 8, 14, 19 Programmable input/Output Cells (PICs), 3444 5 V Tolerant I/O, 35 Architecture, 43 Control Inputs, 17, 23 ASWE, 11 CE, 11 CLK, 11 GSRN, 11, 24 LSR, 11 SEL, 11 Input Demultiplexing, 38 Inputs, 36 Output Multiplexing, 39 Outputs, 39 Open-Drain Output Option, 39 Propagation Delays, 39 Overview, 32 PIO, 34 PIO Logic, 41 PIO Options, 35 PiO Register Control Signals, 41 Zero-Hold Input, 37 Programmable Logic Cells (PLCs), 933 Architecture, 32 Latches/Flip-Flops, 23, 24 PFU, 9 Propagation Delays (see PICs, Outputs) Routing, 25 SLIC, 1922 Lucent Technologies Inc.Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Index (continued) R RAM (see also FPGA Configuration), 85 Dual-port, 3, 10, 17 Single-port, 3, 10, 17 Recommended Operating Conditions, 95 Reconfiguration (see FPGA States of Operation) Routing 3-Statable Bidirectional Buffers, 24 BIDI Routing, 24, 27 Clock (and Global CE and LSR) Routing, 30 Configurable Interconnect Points (CIPs), 24 Conirol Signal and Fast-Carry Routing, 27 Flexible Input Structure (FINS), 26 Inter-PLC Routing Resources, 28 Interquad Routing, 44 Intra-PLC Routing Resources, 2627 Minimizing Routing Delay, 30 Overview, 5 PFU Output Switching, 26 PIC Routing, 4i43 PIC Interquad (MID) Routing, 46 PLC Routing, 2632 Programmable Comer Cell Routing, 45 SLIC Connectivity, 27 Switching Routing Segments (xSW), 26 S SEL, 8, 10, 22 Softwired LUTs (SWLs),1, 6, 11, 12 (see also Look-Up Table Operating Modes) Special Function Blocks Boundary Scan, 60 Boundary-Scan Cells, 59 Boundary-Scan Timing, 60 Microprocessor Interface (MPI), 6168 Programmable Clock Manager (PCM), 6980 Single Function Blocks, 51 Clock Control (CLKCNTRL), 53 Global 3-State Control (TS_ALL), 52 Global Set/Reset (GSRN), 52 Internal Oscillator, 52 Readback Logic, 51 Start-Up Logic, 53 Start-Up (see FPGA States of Operation) StopCLK, 1, 5, 53 (see also Special Function Blocks) Subtractor (see LUT Operating Modes) Supplemental Logic and Interconnect Cell (SLIC), 1, 1821 System Clock (see Clock Distribution Network), 47 3-state, 34, 1718, 34, 38, 4546, 52, 56, 59, 82, 84 Lucent Technologies Inc. T Timing Characteristics Asynchronous Peripheral Configuration Mode, 132 Boundry-Scan Timing, 119 Clock Timing, 119 Derating, 98 Description, 98 General Configuration Mode Timing, 129, 130 Master Parallel Configuration Mode, 131 Master Serial Configuration Mode, 130 Microprocessor Interface Configuration Timing, 137 PFU Timing, 100 PIO Timing, 108, 109, 110 PLC Timing, 107 Programmable Clock Manager Timing, 115 Readback Timing, 139 Slave Parallel Configuration Mode, 134 Slave Serial Configuration Mode, 133 SLIC Timing, 107 Tolerant I/O (see 5 V Tolerant I/O), 34 TS_ALL, 52 Twin-quad Architecture (see PFU), 1 UZ Zero-hold Inputs, 3436 209For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: _http:/Avww.lucent.com/micro, or for FPGA information, http:/Avww.lucent.comv/orca E-MAIL: docmaster@ micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech Ill, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 . CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road Shanghai 200233 PR. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical inquiries: GERMANY: (48} 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 906 (Ascot), FRANCE:(33)140836800(Paris), SWEDEN: (46)859460700(Stockholm), FINLAND:(358)943542800(Helsinki), ITALY:(39)02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid) LucentTechnotogiesinc.reservestherighttomakechangestotheproduct(s)orinformationcontainedhereinwithoutnotice.Noliabilityisassumedasaresultoftheiruseorapplication.Norightsunderanypatent accompany the sale of any such product(s) or information. ORCA is a registered trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc. Copyright 1999 Lucent Technologies Inc. microelectronics group All Rights Reserved Printed in U.S.A. June 1999 . DS99-087FPGA (Replaces DS98-163F PGA-01) Lucent Technologies