MAX17009GTL+T - Hytronics

General Description

The MAX17009 is a 2-phase, step-down interleaved,

fixed-frequency controller for AMD’s®serial VID inter-

face (SVI) CPU core supplies. Power-on detection of

the CPU configures the MAX17009 as two independent

single-phase regulators for a dual CPU core applica-

tion, or one high-current, dual-phase, combined-output

regulator for a unified core application. A reference

buffer output (NBV_BUF) sets the voltage-regulation

level for a North Bridge (NB) regulator, completing the

total CPU cores and NB power requirements.

The MAX17009 is fully AMD SVI compliant. Output volt-

ages are dynamically changed through a 2-wire serial

interface, allowing the switching regulator and the refe-

rence buffer to be individually programmed to different

voltages. A programmable slew-rate controller enables

controlled transitions between VID codes, soft-start limits

the inrush current, and soft-shutdown brings the output

voltage back down to zero without any negative ring.

Transient phase repeat improves the response of the

fixed-frequency architecture. Independently program-

mable AC and DC droop and selectable offset improve

stability and reduce the total output-capacitance

requirement. A thermistor-based temperature sensor

allows for a programmable thermal-fault output

(VRHOT). The MAX17009 includes thermal-fault protec-

tion, undervoltage protection (UVP), and selectable out-

put overvoltage protection (OVP). When any of these

protection features detect a fault, the controller shuts

down. True differential current sensing improves cur-

rent limit, load-line accuracy, and current balance when

operating in combined mode. The MAX17009 has an

adjustable switching frequency, allowing 100kHz to

1.2MHz per-phase operation.

Applications

Mobile AMD SVI Core Supply

Multiphase CPU Core Supply

Voltage-Positioned, Step-Down Converters

Notebook/Desktop Computers

Features

oDual-Output, Fixed-Frequency, Core Supply

Controller

oSeparate or Combinable Outputs Detected at

Power-Up

oReference Buffer Output for NB Controller

o±0.4% VOUT Accuracy Over Line, Load, and

Temperature

oAMD SVI-Compliant Serial Interface

o7-Bit On-Board DAC: 0 to +1.550V Output Adjust

Range

oDynamic Phase Selection Optimizes Active/Sleep

Efficiency

oTransient Phase Repeat Reduces Output

Capacitance

oTrue Out-of-Phase Operation Reduces Input

Capacitance

oIntegrated Boost Switches

oProgrammable AC and DC Droop

oProgrammable 100kHz to 1.2MHz Switching

Frequency

oAccurate Current Balance and Current Limit

oAdjustable Slew-Rate Control

oPower-Good (PWRGD) and Thermal-Fault

(VRHOT) Outputs

oSystem Power-OK (PGD_IN) Input

oDrives Large Synchronous-Rectifier MOSFETs

o4V to 26V Battery Input-Voltage Range

oOvervoltage, Undervoltage, and Thermal-Fault

Protection

oPower Sequencing and Timing

oSoft-Startup and Soft-Shutdown

o< 1µA Typical Shutdown Current

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-0814; Rev 0; 5/07

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Denotes a lead-free package.

EP = Exposed pad.

EVALUATION KIT

AVAILABLE

PART

TEMP RANGE

PIN-

PACKAGE

PKG

CODE

MAX17009GTL+

-40°C to +105°C 40 TQFN-EP*,

5mm x 5mm

T4055-1

Pin Configuration appears at end of data sheet.

AMD is a registered trademark of Advanced Micro Devices, Inc.

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ =

GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= 0°C to +85°C, unless otherwise noted.

Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD1, VDD2, VCC, VDDIO to GND_............................-0.3V to +6V

PWRGD to GND_......................................................-0.3V to +6V

FBDC_, FBAC_, PRO to GND_...................-0.3V to (VCC + 0.3V)

GNDS2, THRM, VRHOT to GND_.............................-0.3V to +6V

CSP_, CSN_, ILIM to GND_......................................-0.3V to +6V

SVC, SVD, PGD_IN to GND_....................................-0.3V to +6V

NBV_BUF, NBSKP to GND_ .......................-0.3V to (VCC + 0.3V)

REF, OSC, TIME, OPTION to GND_ ..........-0.3V to (VCC + 0.3V)

BST1, BST2 to GND_..............................................-0.3V to +36V

BST1 to VDD1..........................................................-0.3V to +30V

BST2 to VDD2..........................................................-0.3V to +30V

LX1 to BST1..............................................................-6V to +0.3V

LX2 to BST2..............................................................-6V to +0.3V

DH1 to LX1 .............................................-0.3V to (VBST1 + 0.3V)

DH2 to LX2 .............................................-0.3V to (VBST2 + 0.3V)

DL1 to GND_.............................................-0.3V to (VDD1 + 0.3V)

DL2 to GND_.............................................-0.3V to (VDD2 + 0.3V)

GNDS1, GNDS_NB to GND_.................................-0.3V to +0.3V

Continuous Power Dissipation (TA= +70°C)

Multilayer PCB (derate 35.7mW/°C above +70°C) .....2857mW

Single-Layer PCB (derate 22.2mW/°C above +70°C)..1778mW

Operating Temperature Range .........................-40°C to +105°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

INPUT SUPPLIES

VIN Drain of external high-side MOSFET 4 26

VBIAS VCC, VDD1, VDD2 4.5 5.5Input Voltage Range

VDDIO 1.0 2.7

VCC Undervoltage-Lockout

Threshold VUVLO VCC rising 50mV typical hysteresis

4.10 4.25 4.45

VCC Power-On Reset

Threshold VCC

Falling edge, typical hysteresis = 1.1V,

faults cleared and DL_ forced high when

VCC falls below this level

1.8 V

VDDIO Undervoltage-Lockout

Threshold VDDIO rising 100mV typical hysteresis 0.7 0.8 0.9 V

Quiescent Supply Current (VCC)I

CC Skip mode, FBDC_ forced above their

regulation points 510mA

Quiescent Supply Currents

(VDD1, VDD2)

IDD1, IDD2

Skip mode, FBDC_ forced above their

regulation points

0.01

1µA

Q ui escent S up p l y C ur r ent ( V

D D I O)

IDDIO 10 25 µA

Shutdown Supply Current (VCC)SHDN = GND

0.01

1µA

Shutdown Supply Currents

(VDD1, VDD2)SHDN = GND

0.01

1µA

Shutdown Supply Current (VDDIO)

SHDN = GND

0.01

1µA

Reference Voltage VREF VCC = 4.5V to 5.5V, no REF load

1.986 2.000 2.014

Sourcing: IREF = 0 to 500µA -2

-0.2

Reference Load Regulation Sinking: IREF = 0 to -100µA

0.21

6.2 mV

REF Fault Lockout Voltage Typical hysteresis = 85mV

1.84

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

_______________________________________________________________________________________ 3

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MAIN SMPS CONTROLLERS

DAC codes from 0.8375V to 1.5500V -0.4 +0.4 %

DAC codes from 0.5000V to 0.8250V -4 +4

DC Output-Voltage Accuracy

(Note 1) VOUT

DAC codes below 0.4875V -10 +10 mV

DC Load Regulation Either SMPS, PWM mode, droop disabled,

zero to full load -0.1 %

Line-Regulation Error Either SMPS, 4V < VIN < 26V 0.03 %/V

GNDS_ Input Range VGNDS_ Separate mode -200 +200 mV

GNDS_ Gain AGNDS_

Separate: ΔVOUT_/ΔVGNDS_,

-200mV ≤ VGNDS_ ≤ +200mV;

combined: ΔVOUT/ΔVGNDS1,

-200mV ≤ VGNDS1 ≤ +200mV

0.95 1.00 1.05 V/V

GNDS_ Input Bias Current IGNDS_-2+2µA

Combined-Mode Detection

Threshold

GNDS2, detection after REFOK, latched,

cleared by cycling SHDN 0.7 0.8 0.9 V

FBDC_ Input Bias Current IFBDC0_ CSP_ = CSN_ -3 +3 µA

ROSC = 143kΩ (fOSC = 300kHz nominal) -5 +5

Switching-Frequency Accuracy fOSC ROSC = 35.7kΩ (fOSC = 1.2MHz nominal) to

432kΩ (fOSC = 99kHz nominal) -7.5 +7.5 %

Maximum Duty Factor DMAX 90 92 %

Minimum On-Time tONMIN 175 ns

50 %

SMPS1-to-SMPS2 Phase Shift SMPS2 starts after SMPS1 180 D eg r ees

RTIME = 143kΩ, SR = 6.25mV/µs -10 +10

During

transition RTIME = 35.7kΩ to 357kΩ,

SR = 25mV/µs to 2.5mV/µs -15 +15 %

TIME Slew-Rate Accuracy

Startup and shutdown 1 mV/µS

CURRENT LIMIT

Current-Limit Threshold Tolerance VLIMIT VCSP_ - VCSN_ = 0.05 x (VREF - VILIM),

(VREF - VILM) = 0.2V to 1.0V -3 +3 mV

Zero-Crossing Threshold VZX VGND_ - VLX_, SKIP mode 3 mV

Idle Mode™ Threshold Tolerance VIDLE VCSP_ - VCSN_, SKIP mode, 0.15 x VLIMIT -1.5 +1.5 mV

CS_ Input-Leakage Current CSP_ and CSN_ -0.2 +0.2 µA

CS_ Common-Mode Input Range CSP_ and CSN_ 0 2 V

Phase-Disable Threshold CSP2 3 VCC

- 1

VCC

-0.4 V

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ =

GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= 0°C to +85°C, unless otherwise noted.

Typical values are at TA= +25°C.)

Idle Mode is a trademark of Maxim Integrated Products, Inc.

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ =

GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= 0°C to +85°C, unless otherwise noted.

Typical values are at TA= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DROOP AND CURRENT BALANCE

DC Droop Amplifier

Transconductance

(

FBDC_

)

ΔIFBDC_/(ΔVCS_),

VFBDC_ = VCSN_ = 1.2V,

VCSP_ - VCSN_ = -60mV to +60mV

0.97 1.00 1.03 mS

DC Droop and Current-Balance

Amplifier Offset IFBDC_/Gm(FBDC_)-1.5 +1.5 mV

AC Droop and Current-Balance

Amplifier Transconductance Gm

(

FBAC_

)

ΔIFBAC_/(ΔVCS_),

VFBAC_ = VCSN_ = 1.2V,

VCSP_ - VCSN_ = -60mV to +60mV

0.97 1.00 1.03 mS

AC Droop and Current-Balance

Amplifier Offset IFBAC_/Gm(FBAC_)-1.5 +1.5 mV

No-Load Positive Offset with

Offset Enabled Offset enabled, OPTION = REF or GND 12.5 mV

Transient Detection Threshold

Measured at FBDC_ with respect to steady-

state FBDC_ regulation voltage, 5mV

hysteresis (typ), transient phase-repeat

enabled, OPTION = OPEN or GND

-32 -18 mV

NB BUFFER

DAC codes from 0.8375V to 1.5500V -0.4 +0.4 %

DAC codes from 0.5000V to 0.8250V -4 +4

NBV_BUF Output Voltage

Accuracy VNBV_BUF

DAC codes below 0.4875V to 0.0125V -10 +10 mV

RTIME = 143kΩ,

INBV_BUF = 7.0µA -10 +10

NBV_BUF Short-Circuit Current

(Sets Slew Rate Together with

External Capacitor CNBV_BUF)

DAC code set to

1.2V, VNBV_BUF

= 0.4V and 2V RTIM E

= 35.7kΩ to 357kΩ ,

IN BV

_BU F

= 28µA to 2.8µA -15 +15

GNDS_NB Input Range VGNDS_NB -200 +200 mV

GNDS_NB Gain AGNDS_NB

ΔVNBV_BUF/ΔVGNDS_NB,

-200mV ≤ VGNDS_NB ≤ +200mV 0.95 1.00 1.05 V/V

GNDS_NB Input Bias Current IGNDS_NB -2 +2 µA

FAULT DETECTION

Normal operation 250 300 350 mV

Output not in regulation

after a downward VID

transition

1.80 1.85 1.90

Output Overvoltage Trip

Threshold VOVP_

Measured at

FBDC_,

rising edge

Minimum OVP threshold 0.8

Output Overvoltage Fault-

Propagation Delay tOVP FBDC_ forced 25mV above trip threshold 10 µs

Output Undervoltage-Protection

Trip Threshold VUVP Measured at FBDC_ with respect to

unloaded output voltage -450 -400 -350 mV

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ =

GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= 0°C to +85°C, unless otherwise noted.

Typical values are at TA= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Undervoltage Fault-

Propagation Delay tUVP FBDC_ forced 25mV below trip threshold 10 µs

Measured at

FBDC_ with

respect to

unloaded output

voltage

Lower threshold, falling

edge (undervoltage) -350 -300 -250

PWRGD Threshold

15mV hysteresis

(typ)

Upper threshold, rising

edge (overvoltage) +150 +200 +250

PWRGD Propagation Delay tPWRGD_FBDC_ forced 25mV outside the PWRGD

trip thresholds 10 µs

PWRGD Output Low Voltage ISINK = 4mA 0.4 V

PWRGD Leakage Current IPWRGD_ High state, PWRGD forced to 5.5V 1 µA

PWRGD Startup Delay and

Transition Blanking Time tBLANK

Measured from the time when FBDC_

reaches the target voltage based on the

slew rate set by RTIME

20 µs

VRHOT Trip Threshold Measured at THRM, with respect to VCC,

falling edge, 115mV hysteresis (typ) 29.5 30 30.5 %

VRHOT Delay tVRHOT THRM forced 25mV below the VRHOT trip

threshold, falling edge 10 µS

VRHOT Output Low Voltage ISINK = 4mA 0.4 V

VRHOT Leakage Current High state, VRHOT forced to 5V 1 µA

THRM Input Leakage -100 +100 nA

Thermal-Shutdown Threshold TSHDN Hysteresis = 15°C 160 °C

GATE DRIVERS

High state (pullup) 0.9 2.0

DH_ Gate-Driver On-Resistance RON

(

DH_

)

BST_ - LX_ forced

to 5V Low state (pulldown) 0.7 2.0

DL_, high state 0.7 2.0

DL_ Gate-Driver On-Resistance RON

(

DL_

)

DL_, low state 0.25 0.6

DH_ Gate-Driver Source/Sink

Current IDH_ DH_ forced to 2.5V, BST_ - LX_ forced to 5V 2.2 A

DL_ Gate-Driver Source Current IDL_

(

SOURCE

)

DL_ forced to 2.5V 2.7 A

DL_ Gate-Driver Sink Current IDL_

(

SINK

)

DL_ forced to 2.5V 8 A

tDH_DL DH_ low to DL_ high 15 25 40

Dead Time tDL_DH DL_ low to DH_ high 9 20 35 ns

Internal Boost Diode Switch RON BST1 to VDD1, BST2 to VDD2; measure with

10mA of current 10 20 Ω

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ =

GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= 0°C to +85°C, unless otherwise noted.

Typical values are at TA= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

2-WIRE SVI BUS LOGIC INTERFACE

SVI Logic Input Current SVC, SVD -1 +1 µA

SVI Logic Input Threshold SVC, SVD, rising edge,

hysteresis = 0.15VDDIO

0.3 x

VDDIO

0.7 x

VDDIO V

SVC Clock Frequency fSVC 3.4 MHz

START Condition Hold Time tHD

STA 160 ns

Repeated START Condition

Setup Time tSU

STA 160 ns

STOP Condition Setup Time tSU

STO 160 ns

Data Hold tHD

DAT

A master device must internally provide a

hold time of at least 300ns for the SDA

signal (referred to the VIL of SCK signal) to

bridge the undefined region of SCL’s falling

edge

70 ns

Data Setup Time tSU

DAT 10 ns

SVC Low Period tLOW 160 ns

SVC High Period tHIGH 60 ns

SVC/SVD Rise and Fall Time tR, tFMeasured from 10% to 90% of VDDIO 40 ns

Pulse Width of Spike Suppression Input filters on SVD and SVC suppress

noise spikes less than 50ns 20 ns

INPUTS AND OUTPUTS

SHDN, PGD_IN -1 +1

Logic Input Current PRO, OPTION -3 +3 µA

Logic Input Threshold SHDN, rising edge, hysteresis = 225mV 0.8 2.0 V

High VCC -

0.4

Open 3.15 3.85

REF 1.65 2.35

Four-Level Input-Logic Levels OPTION

Low 0.4

High VCC -

0.4

Open 3.15 3.85

Tri-Level Input-Logic Levels PRO

Low 0.4

PGD_IN Logic Input Threshold PGD_IN 0.3 x

VDDIO

0.7 x

VDDIO V

Low state, ISINK = 3mA 0.4

NBSKP Logic Output Voltage High state, ISOURCE = 3mA VCC -

0.4

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ =

GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= -40°C to +105°C, unless otherwise noted.)

(Note 2)

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

INPUT SUPPLIES

VIN Drain of external high-side MOSFET 4 26

VBIAS VCC, VDD1, VDD2 4.5 5.5Input Voltage Range

VDDIO 1.0 2.7

VCC Undervoltage-Lockout

Threshold VUVLO VCC rising 50mV typical hysteresis 4.10 4.45 V

VDDIO Undervoltage-Lockout

Threshold VDDIO rising 100mV typical hysteresis 0.8 0.9 V

Quiescent Supply Current (VCC)I

CC Skip mode, FBDC_ forced above their

regulation points 10 mA

Quiescent Supply Currents

(VDD1, VDD2)IDD1, IDD2 Skip mode, FBDC_ forced above their

regulation points, TA = -40°C to +85°C 1µA

Q ui escent S up p l y C ur r ent ( V

D D I O) IDDIO 25 µA

Shutdown Supply Current (VCC)SHDN = GND, TA = -40°C to +85°C 1 µA

Shutdown Supply Currents

(VDD1, VDD2)SHDN = GND, TA = -40°C to +85°C 1 µA

Shutdown Supply Current (VDDIO)T

A = -40°C to +85°C 1 µA

Reference Voltage VREF VCC = 4.5V to 5.5V, no REF load 1.98 2.02 V

Sourcing: IREF = 0 to 500µA -2

Reference Load Regulation Sinking: IREF = 0 to -100µA 6.2 mV

MAIN SMPS CONTROLLERS

DAC codes from 0.8375V to 1.5500V -0.6 +0.6 %

DAC codes from 0.5000V to 0.8250V -6 +6

DC Output-Voltage Accuracy

(Note 1) VOUT

DAC codes from 0.4875V to 0.0125V -15 +15 mV

GNDS_ Input Range VGNDS_ Separate mode -200 +200 mV

GNDS_ Gain AGNDS_

Separate: ΔVOUT_ /ΔVGNDS_,

-200mV ≤ VGNDS_ ≤ +200mV,

Combined: ΔVOUT/ΔVGNDS1,

-200mV ≤ VGNDS1 ≤ +200mV

0.95 1.05 V/V

Combined-Mode Detection

Threshold

GNDS2, detection after REFOK, latched,

cleared by cycling SHDN 0.7 0.9 V

ROSC = 143kΩ (fOSC = 300kHz nominal) -7.5 +7.5

Switching-Frequency Accuracy fOSC ROSC = 35.7kΩ (fOSC = 1.2MHz nominal) to

432kΩ (fOSC = 99kHz nominal) -10 +10 %

Maximum Duty Factor DMAX 90 %

Minimum On-Time tONMIN 185 ns

RTIME = 143kΩ

SR = 6.25mV/

s -10 +10

TIME Slew-Rate Accuracy During

transition RTIME = 35.7kΩ to 357kΩ,

SR = 25mV/µs to 2.5mV/µs -15 +15 %

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

8 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ =

GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= -40°C to +105°C, unless otherwise noted.)

(Note 2)

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

CURRENT LIMIT

Current-Limit Threshold Tolerance VLIMIT VCSP_ - VCSN_ = 0.05 x (VREF - VILIM),

(VREF - VILM) = 0.2V to 1.0V -3 +3 mV

Idle Mode Threshold Tolerance VIDLE VCSP_ - VCSN_, SKIP mode, 0.15 x VLIMIT -1.5 +1.5 mV

CS_ Common-Mode Input Range CSP_ and CSN_ 0 2 V

Phase Disable Threshold CSP2 3 VCC -

0.4 V

DROOP AND CURRENT BALANCE

DC Droop Amplifier

Transconductance Gm

(

FBDC_

)

ΔIFBDC_ /(ΔVCS_),

VFBDC_ = VCSN_ = 1.2V,

VCSP_ - VCSN_ = -60mV to +60mV

0.97 1.03 mS

DC Droop Amplifier Offset IFBDC_ /Gm(FBDC_)-1.5 +1.5 mV

AC Droop and Current-Balance

Amplifier Transconductance Gm

(

FBAC_

)

ΔIFBAC_ /(ΔVCS_),

VFBAC_ = VCSN_ = 1.2V,

VCSP_ - VCSN_ = -60mV to +60mV

0.97 1.03 mS

AC Droop and Current-Balance

Amplifier Offset IFBAC_/Gm(FBAC_)-1.5 +1.5 mV

Transient-Detection Threshold

Measured at FBDC_ with respect to

steady-state

FBDC_ regulation voltage,

5mV hysteresis (typ),

transient phase repeat enabled,

OPTION = OPEN or GND

-32 -18 mV

NB BUFFER

DAC codes from 0.8375V to 1.5500V -0.6 +0.6 %

DAC codes from 0.5000V to 0.8250V -6 +6

NBV_BUF Output-Voltage

Accuracy VNBV_BUF

DAC codes from 0.4875V to 0.0125V -15 +15 mV

RTIME = 143kΩ,

INBV_BUF = 7.0µA -10 +10

NBV_BUF Short-Circuit Current

(Sets Slew Rate Together with

External Capacitor CNBV_BUF)

DAC code set to

1.2V, VNBV_BUF

= 0.4V and 2V RTI M E

= 35.7kΩ to 357kΩ ,

IN B V

_BU F = 28µA to 2.8µA -15 +15

GNDS_NB Input Range VGNDS_NB -200 +200 mV

GNDS_NB Gain AGNDS_NB

ΔVNBV_BUF/ΔVGNDS_NB,

-200mV ≤ VGNDS_NB ≤ +200mV 0.95 1.05 V/V

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

_______________________________________________________________________________________ 9

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ =

GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= -40°C to +105°C, unless otherwise noted.)

(Note 2)

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

FAULT DETECTION

Output Overvoltage Trip

Threshold VOVP_ Measured at FBDC_,

rising edge Normal operation 250 350 mV

Output Undervoltage-Protection

Trip Threshold VUVP Measured at FBDC_ with respect to

unloaded output voltage -450 -350 mV

Measured at FBDC_

with respect to

unloaded output

voltage

Lower threshold,

falling edge

(undervoltage)

-350 -250

PWRGD Threshold

15mV hysteresis

(typ)

Upper threshold,

rising edge

(overvoltage)

+150 +250

PWRGD Output Low Voltage ISINK = 4mA 0.4 V

VRHOT Trip Threshold Measured at THRM, with respect to VCC,

falling edge, 115mV hysteresis (typ) 29.5 30.5 %

VRHOT Output Low Voltage ISINK = 4mA 0.4 V

GATE DRIVERS

High state (pullup) 2.0

DH_ Gate-Driver On-Resistance RON

(

DH_

)

BST_ - LX_ forced

to 5V Low state (pulldown) 2.0

DL_, high state 2.0

DL_ Gate-Driver On-Resistance RON

(

DL_

)

DL_, low state 0.6

tDH_DL DH_ low to DL_ high 15 40

Dead Time tDL_DH DL_ low to DH_ high 9 40 ns

Internal Boost Diode Switch RON BST1 to VDD1, BST2 to VDD2, measured

with 10mA of current 20 Ω

2-WIRE SVI BUS LOGIC INTERFACE

SVI Logic Input Threshold SVC, SVD, rising edge,

hysteresis = 0.15 x VDDIO

0.3 x

VDDIO

0.7 x

VDDIO V

SVC Clock Frequency fSVC 3.4 MHz

START Condition Hold Time tHD

STA 160 ns

Repeated START Condition

Setup Time tSU

STA 160 ns

STOP Condition Setup Time tSU

STO 160 ns

Data Hold tHD

DAT

A m aster device must i nternal ly p rovid e a hold

tim e of at l east 300ns for the SD A sig nal (r efer r ed

to the VIL of S CK sig nal ) to b ri dg e the und efi ned

r eg ion of S CL’s fal li ng ed ge

70 ns

Data Setup Time tSU

DAT 10 ns

SVC Low Period tLOW 160 ns

SVC High Period tHIGH 60 ns

SVC/SVD Rise and Fall Time tR, tFMeasured from 10% to 90% of VDDIO 40 ns

Note 1: When the inductor is in continuous conduction, the output voltage has a DC regulation level lower than the error comparator

threshold by 50% of the ripple. In discontinuous conduction, the output voltage will have a DC regulation level higher than

the error comparator threshold by 50% of the ripple.

Note 2: Specifications to TA= -40°C to +105°C are guaranteed by design, not production tested.

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

10 ______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ =

GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= -40°C to +105°C, unless otherwise noted.)

(Note 2)

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

INPUTS AND OUTPUTS

Logic Input Threshold SHDN, rising edge, hysteresis = 225mV 0.8 2.0 V

High VCC -

0.4 V

Open 3.15 3.85

REF 1.65 2.35

Four-Level Input Logic Levels OPTION

Low 0.4

High VCC -

0.4

Open 3.15 3.85

Tri-Level Input Logic Levels PRO

Low 0.4

PGD_IN Logic Input Threshold PGD_IN 0.3 x

VDDIO

0.7 x

VDDIO V

SVD

SVC

tSUSTP

tSUDAT

tHDDAT

tCLH

tHDSTT

VIH

VIL

tCLL

tBF

Figure 1. Timing Definitions Used in the Electrical Characteristics

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________

1-PHASE EFFICIENCY vs. LOAD CURRENT

(VOUT = 1.2125V)

MAX17009 toc01

LOAD CURRENT (A)

EFFICIENCY (%)

101

100

0.1 100

VIN = 7V

VIN = 12V

VIN = 20V

2-PHASE EFFICIENCY vs. LOAD CURRENT

(VOUT = 1.2125V)

MAX17009 toc02

LOAD CURRENT (A)

EFFICIENCY (%)

100

0.1 100

VIN = 7V

VIN = 12V

VIN = 20V

1-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT

(VOUT = 1.2125V, -1.2mV/A DROOP)

MAX17009 toc03

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

10 155

1.17

1.19

1.21

1.23

1.25

1.15

020

VIN = 12V

1-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT

(VOUT = 1.2000V, NO DROOP)

MAX17009 toc04

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

10 155

1.17

1.19

1.21

1.23

1.25

1.15

020

VIN = 12V

1-PHASE EFFICIENCY vs. LOAD CURRENT

(VOUT = 0.8000V)

MAX17009 toc05

LOAD CURRENT (A)

EFFICIENCY (%)

101

100

0.1 100

VIN = 7V

VIN = 12V

VIN = 20V

2-PHASE EFFICIENCY vs. LOAD CURRENT

(VOUT = 0.8000V)

MAX17009 toc06

LOAD CURRENT (A)

EFFICIENCY (%)

100

0.1 100

VIN = 7V

VIN = 12V

VIN = 20V

1-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT

(VOUT = 0.8000V, -1.2mV/A DROOP)

MAX17009 toc07

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

10 155

0.75

0.76

0.77

0.78

0.79

0.80

0.81

0.82

0.83

0.84

0.74

020

VIN = 12V

1-PHASE SWITCHING FREQUENCY

vs. LOAD CURRENT

MAX17009 toc08

LOAD CURRENT (A)

SWITCHING FREQUENCY (kHz)

101

150

200

250

300

350

100

0.1 100

VIN = 7V

VIN = 12V

VIN = 20V

MAXIMUM INDUCTOR CURRENT

vs. INPUT VOLTAGE

MAX17009 toc09

INPUT VOLTAGE (V)

INDUCTOR CURRENT (A)

15 2010

525

PEAK CURRENT

DC CURRENT

VOUT = 1.2V

Typical Operating Characteristics

(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25°C, unless otherwise noted.)

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

12 ______________________________________________________________________________________

MAXIMUM INDUCTOR CURRENT

vs. TEMPERATURE

MAX17009 toc10

TEMPERATURE (%)

INDUCTOR CURRENT (A)

20 40 60 80-20 0

-40

PEAK CURRENT

DC CURRENT

VIN = 12V

VOUT = 1.2V

CURRENT BALANCE vs. LOAD CURRENT

MAX17009 toc11

TOTAL LOAD CURRENT (A)

PER-PHASE CURRENT (A)

20 30 4010

IOUT1

IOUT2

VOUT = 1.2V

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE

MAX17009 toc12

INPUT VOLTAGE (V)

SUPPLY CURRENT (mA)

15 20 2510

0.1

0.01

IIN

IDD1 + IDD2

ICC

VOUT = 1.2V

REFERENCE VOLTAGE DISTRIBUTION

MAX17009 toc13

REFERENCE VOLTAGE (mV)

SAMPLE PERCENTAGE (%)

2.000 2.003 2.0051.998

1.995

SAMPLE SIZE = 150

SMPS OUTPUT OFFSET

VOLTAGE DISTRIBUTION

MAX17009 toc14

OUTPUT OFFSET VOLTAGE (mV)

SAMPLE PERCENTAGE (%)

-1 1 3 5-3

-5

SAMPLE SIZE = 150

VOUT1

VOUT2 VDAC1 = VDAC2 = 1.200V

NBV_BUF OFFSET

VOLTAGE DISTRIBUTION

MAX17009 toc15

OFFSET VOLTAGE (mV)

SAMPLE PERCENTAGE (%)

-1 1 3 5-3

-5

SAMPLE SIZE = 150

VDAC_NB = 1.200V

FBDC TRANSCONDUCTANCE

DISTRIBUTION

MAX17009 toc16

TRANSCONDUCTANCE (mS)

SAMPLE PERCENTAGE (%)

50 SAMPLE SIZE = 150

FBDC1

FBDC2

1.000 1.005 1.0100.9950.990

REFERENCE VOLTAGE vs. LOAD CURRENT

MAX17009 toc17

REF LOAD CURRENT (μA)

REFERENCE VOLTAGE (V)

40 60 80 10020

1.999

1.998

2.000

2.001

2.002

Typical Operating Characteristics (continued)

(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25°C, unless otherwise noted.)

STARTUP WAVEFORMS (HEAVY LOAD)

MAX17009 toc18

200μs/div

A. SHDN, 5V/div

B. ILX1, 10A/div

C. VOUT1, 0.5V/div

D. ILX2, 10A/div

VIN = 12V, VBOOT = 0.8V, ILOAD1 = ILOAD2 = 12A

E. VOUT2, 0.5V/div

F. PWRGD, 5V/div

G. VNBV_BUF, 0.5V/div

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________

STARTUP SEQUENCE WAVEFORMS

MAX17009 toc19

400μs/div

A. SHDN, 5V/div

B. VNBV_BUF, 0.5V/div

C. VOUT1, 0.5V/div

D. VOUT2, 0.5V/div

VIN = 12V, VBOOT = 1.0V, ILOAD1 = ILOAD2 = 3A

E. PWRGD, 3.3V/div

F. PGD_IN, 3.3V/div

G. SVC, 2V/div

H. SVD, 2V/div

SHUTDOWN WAVEFORMS

MAX17009 toc20

200μs/div

A. SHDN, 5V/div

B. DL1, 10V/div

C. VOUT1, 0.5V/div

D. DL2, 10V/div

VIN = 12V, ILOAD1 = ILOAD2 = 3A

3.3V

1.2V

3.3V

E. VOUT2, 0.5V/div

F. VNBV_BUF, 2V/div

G. PWRGD, 5V/div

1-PHASE LOAD TRANSIENT (-1.2mV/A DROOP)

MAX17009 toc21

20μs/div

A. VOUT1, 50mV/div

B. ILX1, 10A/div

C. LX1, 10V/div

VIN = 12V

ILOAD1 = 3A TO 15A TO 3A

1.2V

15A

12V

1-PHASE TRANSIENT PHASE REPEAT

(-1.2mV/A DROOP)

MAX17009 toc22

2μs/div

A. VOUT1, 50mV/div

B. ILX1, 10A/div

C. LX1, 10V/div

VIN = 12V

ILOAD1 = 3A TO 15A TO 3A

1.2V

15A

12V

1-PHASE LOAD TRANSIENT

(NO DROOP)

MAX17009 toc23

20μs/div

A. VOUT1, 50mV/div

B. ILX1, 10A/div

C. LX1, 10V/div

VIN = 12V

ILOAD1 = 3A TO 15A TO 3A

1.2V

15A

12V

1-PHASE TRANSIENT PHASE REPEAT

(NO DROOP)

MAX17009 toc24

2μs/div

A. VOUT1, 50mV/div

B. ILX1, 10A/div

C. LX1, 10V/div

VIN = 12V

ILOAD1 = 3A TO 15A TO 3A

1.2V

15A

12V

Typical Operating Characteristics (continued)

(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25°C, unless otherwise noted.)

______________________________________________________________________________________

2-PHASE LOAD TRANSIENT

(-1.2mV/A DROOP)

MAX17009 toc25

20μs/div

A. VOUT1, 50mV/div

B. ILX1, 10A/div

C. ILX2, 10A/div

VIN = 12V

ILOAD = 6A TO 30A TO 6A

1.2V

15A

2-PHASE TRANSIENT PHASE REPEAT

(-1.2mV/A DROOP)

MAX17009 toc26

2μs/div

A. VOUT1, 50mV/div

B. ILX1, 10A/div

C. ILX2, 10A/div

VIN = 12V

ILOAD = 6A TO 30A TO 6A

1.2V

15A

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

14 ______________________________________________________________________________________

1-PHASE OUTPUT OVERLOAD

MAX17009 toc27

200μs/div

A. PWRGD, 5V/div

B. VOUT1, 1V/div

C. DL1, 10V/div

D. VOUT2, 1V/div

E. DL2, 10V/div

F. VNBV_BUF, 1V/div

VIN = 12V, ILOAD1 = 3A TO 30A, ILOAD2 = 3A

3.3V

1.2A

1.2V

1-PHASE OUTPUT OVERVOLTAGE

MAX17009 toc28

200μs/div

A. PWRGD, 5V/div

B. VOUT1, 1V/div

C. DL1, 10V/div

D. VOUT2, 1V/div

E. DL2, 10V/div

F. VNBV_BUF, 1V/div

VIN = 12V, ILOAD1 = 50mA, ILOAD2 = 3A

3.3V

1.2A

1.2V

DYNAMIC OUTPUT-VOLTAGE

TRANSITIONS (LIGHT LOAD)

MAX17009 toc29

100μs/div

A. VNBV_BUF, 1V/div

B. LX1, 20V/div

C. VOUT1, 0.5V/div

D. LX2, 20V/div

E. VOUT2, 0.5V/div

F. SVC, 5V/div

G. SVD, 5V/div

VIN = 12V, VDACS = 1.3V TO 0.6V TO 1.3V,

ILOAD1 = ILOAD2 = 3A

1.3V

12V

2.5V

1.3V

0.6V

2.5V

DYNAMIC OUTPUT-VOLTAGE

TRANSITIONS (HEAVY LOAD)

MAX17009 toc30

100μs/div

A. VNBV_BUF, 1V/div

B. LX1, 20V/div

C. VOUT1, 0.5V/div

D. LX2, 20V/div

E. VOUT2, 0.5V/div

F. SVC, 5V/div

G. SVD, 5V/div

VIN = 12V, VDACS = 1.3V TO 0.6V TO 1.3V,

ILOAD1 = ILOAD2 = 10A

1.3V

12V

2.5V

1.3V

0.6V

2.5V

PGD_IN FALLING TRANSITIONS

MAX17009 toc31

10μs/div

A. VNBV_BUF, 200mV/div

B. VOUT1, 200mV/div

C. VOUT2, 200V/div

D. LX1, 20V/div

E. LX2, 20V/div

F. PGD_IN, 5V/div

G. PWRGD, 5V/div

VIN = 12V, VBOOT = 1.1V, VDAC1 = 0.8V, VDAC2 = 1.3V,

VNBV_BUF = 0.8V, ILOAD1 = ILOAD2 = 3A

1.1V

12V

2.5V

0.8V

1.3V

2.5V

14 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25°C, unless otherwise noted.)

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 15______________________________________________________________________________________ 15

Pin Description

PIN NAME FUNCTION

1PWRGD

Open-Drain, Power-Good Output. PWRGD indicates when both SMPSs are in regulation.

PWRGD is forced high impedance whenever the slew-rate controller is active (output-voltage

transitions). After output-voltage transitions, except during power-up and power-down, if FBDC_ is in

regulation, then PWRGD is high impedance.

During startup, PWRGD is held low an additional 20μs after the MAX17009 reaches the startup boot

voltage set by the SVC, SVD pins. The MAX17009 stores the boot VID when PWRGD first goes high.

The stored boot VID is cleared by rising SHDN.

PWRGD is forced low in shutdown.

When in pulse-skipping mode, the upper PWRGD threshold comparator is blanked during a lower VID

transition. The upper PWRGD threshold comparator is reenabled once the output is in regulation (Figure 4).

2NBV_BUF

North Bridge Buffered Reference Voltage. This output is connected to the REFIN input of the NB

controller (switcher or LDO) to set the NB regulator voltage. The NBV_BUF output current is set by the

TIME resistor. The NBV_BUF current and the total output capacitance set the NBV_BUF slew rate:

INBV_BUF = (7μA) x (143k / RTIME)

NBV_BUF Slew rate = INBV_BUF / CNBV_BUF

INBV_BUF is the same during startup, shutdown, and any VID transition.

Bypass to GND with a 100pF minimum low-ESR (ceramic) capacitor at the NBV_BUF pin.

3SHDN

Shutdown Control Input. Connect high (2V to VCC) for normal operation. Connect to ground to put the IC

into its 1μA max shutdown state.

During startup, the SMPS output voltages and the NBV_BUF voltage are ramped up to the voltage set

by the SVC, SVD inputs. The SMPSs start up and shut down at a fixed slew rate of 1mV/μs.

SVC SVD BOOT VOLTAGE (VBOOT)

(PRO = VCC OR GND)

BOOT VOLTAGE (VBOOT)

(PRO = OPEN)

0 0 1.1 1.1

0 1 1.0 1.2

1 0 0.9 1.0

1 1 0.8 0.8

The MAX17009 stores the boot VID when PWRGD first goes high. The stored boot VID is cleared by

rising SHDN.

4REF

2.0V Reference Output. Bypass to GND with a 1μF maximum low-ESR (ceramic) capacitor. REF

sources up to 500μA for external loads. Loading REF degrades output accuracy, according to the REF

load-regulation error.

5ILIM

Current-Limit Adjust Input. The positive current-limit threshold voltage is precisely 1/20 of the voltage

between REF and ILIM over a 0.2V to 1.0V range of V(REF, ILIM). The IMIN minimum current-limit threshold

voltage in skip mode is precisely 15% of the corresponding positive current-limit threshold voltage.

6OSC

Oscillator Adjustment Input. Connect a resistor (ROSC) between OSC and GND to set the switching

frequency (per phase):

fOSC = 300kHz x 143k / ROSC

A 35.7k to 432k corresponds to switching frequencies of 1.2MHz to 100kHz, respectively.

Switching-frequency selection is limited by the minimum on-time. See the Switching frequency bullet

in the SMPS Design Procedure section.

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

16 ______________________________________________________________________________________

PIN NAME FUNCTION

7 TIME

Slew-Rate Adjustment Pin. Connect a resistor RTIME from TIME to GND to set the internal slew rate:

PWM Slew rate = (6.25mV/µs) x (143kΩ / RTIME)

NBV_BUF Slew rate = (7µA) x (143kΩ / RTIME) / CNBV_BUF

where RTIME is between 35.7kΩ and 357kΩ for corresponding slew rates between 25mV/µs to 2.5mV/µs,

respectively, for the SMPSs, and NBV_BUF currents between 28µA and 2.8µA, respectively, for the

NBV_BUF.

This slew rate applies to both upward and downward VID transitions, and to the transition from boot mode

to VID mode. Downward VID transition slew rate can appear slower because the output transition is not

forced by the SMPS.

The SMPS slew rate for startup and shutdown is fixed at 1mV/µs.

The NBV_BUF slew rate is the same during startup, shutdown, and normal VID transitions.

8 SVC S er i al V ID C l ock. D ur i ng the p ow er - up seq uence and i n d eb ug m od e, S V C i s the M S B of the 2- b i t V ID D AC .

9 SVD S er i al V ID D ata. D ur i ng the p ow er - up seq uence and i n d eb ug m od e, S V D i s the LS B of the 2- b i t V ID D AC .

10 THRM

Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC and

GND) to THRM. Select the components so the voltage at THRM falls below 1.5V (30% of VCC) at the

desired high temperature.

11 GNDS2

SMPS2 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS2 internally

connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage

drops from the regulator ground to the load ground.

Connect GNDS2 above 0.9V combined-mode operation (unified core). When operating in combined

mode, GNDS1 is used as the remote ground-sense input.

12 FBDC2

Output of the DC Voltage-Positioning Transconductance Amplifier for SMPS2. Connect a resistor RFBDC2

between FBDC2 and the positive side of the feedback remote sense to set the DC steady-state droop

based on the voltage-positioning gain requirement:

RFBDC2 = RDROOPDC / (RSENSE2 x Gm(FBDC2))

where RDROOPDC is the desired voltage positioning slope and Gm(FBDC2) = 1mS typ. RSENSE2 is the

value of the current-sense resistor that is used to provide the (CSP2, CSN2) current-sense voltage.

To disable the load-line, short FBDC2 to the positive remote-sense point.

FBDC2 is high impedance in shutdown.

13 FBAC2

Output of the AC Voltage-Positioning Transconductance Amplifier for SMPS2. The resistance between

this pin and the positive side of the remote-sensed output voltage sets the transient AC droop:

RFBAC2 = RDROOPAC / (RSENSE2 x Gm(FBAC2))

where RDROOPAC is the transient (AC) voltage-positioning slope that provides an acceptable tradeoff

between stability and load transient response, Gm(FBAC2) and RSENSE2 is the value of the current-sense

resistor that is used to provide the (CSP2, CSN2) current-sense voltage.

The maximum difference between transient (AC) droop and DC droop should not exceed ±80mV at the

maximum allowed load current (DC droop is set at the FBDC2 pin).

Internally, V(FBDC2 - GNDS2) goes to the internal voltage integrator (slow DC loop), whereas V(FBAC2 -

GNDS2) goes to the error comparator (fast transient loop).

FBAC2 is high impedance in shutdown.

Note: The AC and DC droop cannot be different by more than ±3mV/A.

14 VDDIO CPU I/O Voltage (1.8V or 1.5V). Logic thresholds for SVD and SVC are relative to the voltage at VDDIO.

15 GNDS_NB

North Bridge Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the

load. GNDS_NB internally connects to a transconductance amplifier that fine tunes the NBV_BUF output

voltage compensating for voltage drops from the regulator ground to the load ground.

Pin Description (continued)

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 17

PIN NAME FUNCTION

16 CSN2 Negative Current-Sense Input for SMPS2. Connect to the negative side of the output current-sensing

resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.

17 CSP2

Positive Current-Sense Input for SMPS2. Connect to the positive side of the output current-sensing

resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.

Connect CSP2 to VCC to disable SMPS2. This allows the MAX17009 to operate as a 1-phase regulator.

18 VCC

Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1µF minimum. A VCC

UVLO event that occurs while the IC is functioning is latched, and can only be cleared by cycling VCC

power or by toggling SHDN.

19 NBSKP

North Bridge Skip Push-Pull Control Output. When NBSKP is high, the NB switching regulator is set to

forced-PWM mode. When NBSKP is low, the NB switching regulator is set to pulse-skipping mode. The

NBSKP level is set through the serial interface during normal operation.

NBSKP is high in shutdown and during soft-shutdown.

NBSKP is high in startup until commanded otherwise.

20 DH2 SMPS2 High-Side, Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.

21 LX2 SMPS2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also

used as an input to phase 2’s zero-crossing comparator.

22 BST2 Boost Flying-Capacitor Connection for the DH2 High-Side Gate Driver. An internal switch between VDD2

and BST2 charges the flying capacitor during the time the low-side FET is on.

23 VDD2

Supply Voltage Input for the DL2 Driver. VDD2 is also the supply voltage used to internally recharge the

BST2 flying capacitor during the off-time of phase 2. Connect VDD2 to the 4.5V to 5.5V system supply

voltage. Bypass VDD2 to GND with a 1µF or greater ceramic capacitor.

24 DL2

SMPS2 Low-Side Gate-Driver Output. DL2 swings from GND2 to VDD2. DL2 is forced low in shutdown.

DL2 is also forced high when an output overvoltage fault is detected. DL2 is forced low in skip mode after

an inductor current zero crossing (GND2 - LX2) is detected.

25 GND2 Power Ground for SMPS2. Ground connection for the DL2 driver. Also used as an input to SMPS2’s zero-

crossing comparator. GND1 and GND2 are internally connected.

26 GND1 Power Ground for SMPS1. Ground connection for the DL1 driver. Also used as an input to SMPS1’s zero-

crossing comparator. GND1 and GND2 are internally connected.

27 DL1

SMPS1 Low-Side, Gate-Driver Output. DL1 swings from GND1 to VDD1. DL1 is forced low in shutdown.

DL1 is also forced high when an output overvoltage fault is detected. DL1 is forced low in skip mode after

an inductor current zero crossing (GND1 - LX1) is detected.

28 VDD1

Supply Voltage Input for the DL1 Driver. VDD1 is also the supply voltage used to internally recharge the

BST1 flying capacitor during the off-time of phase 1. Connect VDD1 to the 4.5V to 5.5V system supply

voltage. Bypass VDD1 to GND with a 1µF or greater ceramic capacitor.

29 BST1 Boost Flying-Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between VDD1

and BST1 charges the flying capacitor during the time the low-side FET is on.

30 LX1 SMPS1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also

used as an input to phase 1’s zero-crossing comparator.

31 DH1 SMPS1 High-Side, Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.

32 VRHOT Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below

1.5V (30% of VCC). VRHOT is high impedance in shutdown.

Pin Description (continued)

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

18 ______________________________________________________________________________________

PIN NAME FUNCTION

33 PRO

Protection Disable. PRO also sets the MAX17009 in debug mode.

Connect PRO high to disable OVP protection.

Connect PRO to GND to enable OVP protection.

When PRO is floated, the MAX17009 disables the OVP protection and also enters debug mode (see the

SHDN pin description). When PGD_IN is low in debug mode, the MAX17009 DAC voltages are set by

the 2-bit boot VID. When PGD_IN is high, the MAX17009 changes to serial VID mode.

34 CSP1 Positive Current-Sense Input for SMPS1. Connect to the positive side of the output current-sensing resistor

or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.

35 CSN1 Negative Current-Sense Input for SMPS1. Connect to the negative side of the output current-sensing resistor

or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.

36 PGD_IN

System Power-Good Input. Indicates to the MAX17009 that the system is ready to enter serial VID mode.

PGD_IN is low when SHDN first goes high, the MAX17009 decodes the boot VID to determine the boot

voltage. The boot VID can be changed dynamically while PGD_IN remains low and PWRGD. The boot

VID is stored after PWRGD goes high.

PGD_IN goes high after the MAX17009 reaches the boot voltage. This indicates that the SVI block is

active, and the MAX17009 starts to respond to the serial-interface commands.

After PGD_IN has gone high, if at anytime PGD_IN should go low, the MAX17009 regulates to the

previously stored boot VID.

37 OPTION

Four-Level Input to Enable Offset and Transient-Phase Repeat

OPTION OFFSET ENABLED TRANSIENT-PHASE REPEAT ENABLED

VCC 0 0

OPEN 0 1

REF 1 0

GND 1 1

When OFFSET is enabled, the MAX17009 enables a fixed +12.5mV offset on each of the SMPS VID

codes after PGD_IN goes high. This configuration is intended for applications that implement a load-

line. An external resistor at FBDC_ sets the load-line. The offset can be disabled by setting the PSI_L

bit to zero through the serial interface.

When OFFSET is disabled, the intended application has no load-line, and the FBDC_ pins are directly

connected to the remote-sense points.

Transient phase repeat allows the MAX17009 to reenable the current phase in response to a load

transient, even after that phase has finished its on-pulse.

38 FBAC1

Output of the AC Voltage-Positioning Transconductance Amplifier for SMPS1. The resistance between

this pin and the positive side of the remote-sensed output voltage sets the transient AC droop:

RFBAC1 = RDROOPAC / (RSENSE1 x Gm(FBAC1))

where RDROOPAC is the transient (AC) voltage-positioning slope that PROvides an acceptable tradeoff

between stability and load-transient response, Gm(FBAC1) and RSENSE1 is the value of the current-sense

resistor that is used to PROvide the (CSP1, CSN1) current-sense voltage.

The maximum difference between transient (AC) droop and DC droop should not exceed ±80mV at the

maximum allowed load current (DC droop is set at the FBDC2 pin).

Internally, V(FBDC1 - GNDS1) goes to the internal voltage integrator (slow DC loop), whereas V(FBAC1

- GNDS1) goes to the error comparator (fast-transient loop).

FBAC1 is high impedance in shutdown.

Note: The AC and DC droop cannot be different by more than ±3mV/A.

Pin Description (continued)

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 19

PIN NAME FUNCTION

39 FBDC1

Output of the DC Voltage-Positioning Transconductance Amplifier for SMPS1. Connect a resistor

RFBDC1 between FBDC1 and the positive side of the feedback remote sense to set the DC steady-

state droop based on the voltage-positioning gain requirement:

RFBDC1 = RDROOPDC / (RSENSE1 x Gm(FBDC1))

where RDROOPDC is the desired voltage-positioning slope and Gm(FBDC1) = 1mS typ. RSENSE1 is the

value of the current-sense resistor that is used to PROvide the (CSP1, CSN1) current-sense voltage.

To disable the load-line, short FBDC2 to the positive remote-sense point.

FBDC1 is high impedance in shutdown.

40 GNDS1

SMPS1 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS1 internally

connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage

drops from the regulator ground to the load ground.

GNDS1 is the remote ground-sense input in combined-mode operation.

EP EP Exposed Pad. Connect the exposed backside pad to GND1 and GND2.

Pin Description (continued)

COMPONENT VIN = 7V TO 20V

VOUT = 1.0V - 1.3V / 18A PER PHASE

VIN = 4.5V TO 14V

VOUT_ = 1.0V - 1.3V / 18A PER PHASE

MODE Separate, 2-phase mobile

(GNDS2 not high)

Separate, 2-phase mobile

(GNDS2 not high)

Switching Frequency 280kHz

(ROSC = 154k)

600kHz

(ROSC = 71.5k)

CIN_, Input Capacitor (per Phase) (2) 10μF, 25V

Taiyo Yuden TMK432BJ106KM

(2) 10μF, 16V

Taiyo Yuden TMK432BJ106KM

COUT_, Output Capacitor

(per Phase)

(2) 470μF, 2V, 6m,

low-ESR capacitor

NEC/Tokin PSGD0E477M6 or

Panasonic EEFUD0D471L6

(2) 330μF, 2.5V, 6m,

low-ESR capacitor

Panasonic EEFSD0D331XR

NH_ High-Side MOSFET (1) Fairchildsemi

FDMS8690

(1) International Rectifier

IRF7811W

NL_ Low-Side MOSFET (2) Vishay

Si7336ADP

(2) Fairchildsemi

FDMS8660S

DL_ Schottky Rectifier

3A, 40V Schottky diode

Central Semiconductor

CMSH3-40

None

L_ Inductor

0.45μH, 30A, 1.1m power inductor

TOKO FDUE1040D-R45M or

NEC/Tokin MPC1040LR45

0.22μH, 25A, 1m power inductor

NEC/Tokin MPC0730LR20

Table 1. Component Selection for Standard Applications

Table 1 shows the component selection for standard applications and Table 2 lists component suppliers.

Note: Mobile applications should be designed for separate mode operation. Component selection dependent on AMD CPU AC and

DC specifications.

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

20 ______________________________________________________________________________________

Standard Application Circuits

The MAX17009 standard application circuit (Figure 2)

generates two independent 18A outputs for AMD

mobile CPU applications. See Table 1 for component

selections. Table 2 lists the component manufacturers.

Detailed Description

The MAX17009 consists of a dual-fixed-frequency PWM

controller that generates the supply voltage for two inde-

pendent CPU cores. A reference buffer output

(NBV_BUF) sets the regulation voltage for a separate

NB regulator. The CPU cores can be configured as

independent outputs, or as a combined output based

on the GNDS2 pin strap (GNDS2 pulled to 1.5V - 1.8V,

which are the respective voltages for DDR3 and DDR2).

Both SMPS outputs and the NB buffer can be pro-

grammed to any voltage in the VID table (see Table 4)

using the SVI. The CPU is the SVI bus master, while the

MAX17009 is the SVI slave. Voltage transitions are

commanded by the CPU as a single-step command

from one VID code to another. The MAX17009 slews

the SMPS outputs at the slew rate programmed by the

external RTIME resistor. For the NB buffer, the slew rate

is set by the combination of RTIME and the total capaci-

tance on the output of the buffer.

By default, the MAX17009 SMPSs are always in pulse-

skip mode. In separate mode, the PSI_L bit does not

change the mode of operation, but removes the

+12.5mV offset, if enabled by the OPTION pin. In com-

bined mode, the PSI_L bit removes the +12.5mV offset

and switches from 2-phase to 1-phase operation. The

NB_SKP output always follows the state of PSI_L for the

NB regulator.

+5V Bias Supply (VCC, VDD)

The MAX17009 requires an external 5V bias supply in

addition to the battery. Typically, this 5V bias supply is

the notebook’s main 95%-efficient 5V system supply.

Keeping the bias supply external to the IC improves

efficiency and eliminates the cost associated with the

5V linear regulator that would otherwise be needed to

supply the PWM circuit and gate drivers.

The 5V bias supply powers both the PWM controller

and internal gate-drive power, so the maximum current

drawn is:

IBIAS = ICC + fSWQG= 10mA to 60mA (typ)

where ICC is provided in the

Electrical Characteristics

table, and fSWQG(per phase) is the driver’s supply cur-

rent, as defined in the MOSFET’s data sheet. If the +5V

bias supply is powered up prior to the battery supply,

the enable signal (SHDN going from low to high) must

be delayed until the battery voltage is present to ensure

startup.

Switching Frequency (OSC)

Connect a resistor (ROSC) between OSC and GND to

set the switching frequency (per phase):

fSW = 300kHz x 143kΩ/ ROSC

A 35.7kΩto 432kΩcorresponds to switching frequencies

of 1.2MHz to 100kHz, respectively. High-frequency

(1.2MHz) operation optimizes the application for the

smallest component size, trading off efficiency due to

higher switching losses. This may be acceptable in

ultra-portable devices where the load currents are lower

and the controller is powered from a lower voltage sup-

ply. Low-frequency (100kHz) operation offers the best

overall efficiency at the expense of component size and

board space. Minimum on-time (tON(MIN)) must also be

taken into consideration. See the Switching frequency

bullet in the

SMPS Design Procedure

section.

MANUFACTURER WEBSITE

AVX www.avxcorp.com

BI Technologies www.bitechnologies.com

Central Semiconductor www.centralsemi.com

Fairchild Semiconductor www.fairchildsemi.com

International Rectifier www.irf.com

KEMET www.kemet.com

NEC Tokin www.nec-tokin.com

Panasonic www.panasonic.com

MANUFACTURER WEBSITE

Pulse www.pulseeng.com

Renesas www.renesas.com

SANYO www.secc.co.jp

Siliconix (Vishay) www.vishay.com

Sumida www.sumida.com

Taiyo Yuden www.t-yuden.com

TDK www.component.tdk.com

TOKO www.tokoam.com

Table 2. Component Suppliers

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 21

REFIN

SKIP

VCORE_NB

AGND

FROM

MAX17009

NB CONTROL

POWER GROUND

ANALOG GROUND

PWRGD

+3.3V

+5V

LX1

DH1

BST1

DL1

VDD1

GND1

RVCC

10Ω

CVCC

2.2μF

CREF

0.22μF

ROSC

RTIME

VCC

VDDIO

ILIM

VIN

4.5V TO 28V

RSENSE1

1mΩ

COUT1

2 x 470μF

6mΩ

VCORE0/18A

0.45μH

CSP1

100kΩ

VR_HOT

LX2

DH2

BST2

DL2

GND2

SERIAL

INPUT

SVC

SVD

PGD_IN

SHDN

OPTION

TO NB

REGULATOR

OSC

TIME

REF

CNBV_BUF

CONNECT TO SYSTEM

1.8V VDDIO SUPPLY

CONNECT TO SYSTEM

PWROK SIGNAL

VDD2

1000pF

CSN1

CSP1

CSN2

CSP2

PRO 3-LEVEL OPTION:

VCC = DISABLE OVP

OPEN = DEBUG MODE

GND = ENABLE OVP

OPTION

VCC

OPEN

REF

GND

OFFSET PH-RPT

PWR

AGND

{

VCC

FBDC1 CORE0 SENSE_H

FBAC1

AGND

ENABLE

FBDC2

FBAC2

GNDS1 40

GNDS2 11

100kΩ

MAX17009

RILIM2

RTHRM

RNTC

RILIM1

PRO

AGND

CSN1

NB_SKP

NBV_BUF

THRM

10Ω

GNDS_NB

AGND

CVDD1

1μF

CBST1

0.22μF

NH1

NL1 DL1

PWR

CVDD2

1μF

PWR

CIN1

PWR

VIN

4.5V TO 28V

RSENSE2

1mΩ

COUT2

2 x 470μF

6mΩ

VCORE1/18A

0.45μH

CSP2

PWR

RFBAC1

1.5kΩ

RFBDC1

1.1Ω

100Ω

4700pF

1000pF

CSN2

CBST2

0.22μF

NH2

NL2 DL2

CIN2

PWR

RCSP1

75Ω

CCSP1

2.2nF

CSP1

RCSN1

10Ω

CCSN1

1nF

CSN1

AGND

RCSP2

75Ω

CCSP2

2.2nF

CSP2

RCSN2

10Ω

CCSN2

1nF

CSN2

CORE1 SENSE_H

AGND

RFBAC2

1.5kΩ

RFBDC2

1.1Ω

100Ω

4700pF

1000pF

CORE0 SENSE_L

AGND

100Ω

4700pF

CORE1 SENSE_L

AGND

100Ω

4700pF

NB REGULATOR

Figure 2. Standard Application Circuit

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

22 ______________________________________________________________________________________

Interleaved Multiphase Operation

The MAX17009 interleaves both phases—resulting in

180° out-of-phase operation that minimizes the input and

output filtering requirements, reduces electromagnetic

interference (EMI), and improves efficiency. The high-

side MOSFETs do not turn on simultaneously during nor-

mal operation. The instantaneous input current is

effectively reduced by the number of active phases,

resulting in reduced input-voltage ripple, ESR power loss,

and RMS ripple current (see the

Input-Capacitor

Selection

section). Therefore, the controller achieves high

performance while minimizing the component count,

which reduces cost, saves board space, and lowers

component power requirements, making the MAX17009

ideal for high-power, cost-sensitive applications.

Transient-Phase Repeat

When a transient occurs, the output-voltage deviation

depends on the controller’s ability to quickly detect the

transient and slew the inductor current. A fixed-fre-

quency controller typically responds only when a clock

edge occurs, resulting in a delayed transient response.

To minimize this delay time, the MAX17009 includes

enhanced transient detection and transient- phase-

repeat capabilities. If the controller detects that the out-

put voltage has dropped by 25mV, the transient-

detection comparator immediately retriggers the phase

that completed its on-time last. The controller triggers

the subsequent phases as normal on the appropriate

oscillator edges. This effectively triggers a phase a full

cycle early, increasing the total inductor-current slew

rate and providing an immediate transient response.

The OPTION pin setting enables or disables the tran-

sient phase-repeat feature. Keep OPTION OPEN or

connected to GND to enable transient-phase repeat.

Connect OPTION to VCC or REF to disable transient-

phase repeat. See the

Offset and Transient-Phase

Repeat (OPTION)

section.

Feedback Adjustment Amplifiers

Steady-State Voltage-Positioning

Amplifier (DC Droop)

Each of the MAX17009 SMPS controllers includes two

transconductance amplifiers—one for steady-state DC

droop, and another for AC droop. The amplifiers’ inputs

are generated by summing their respective current-sense

inputs, which differentially sense the voltage across either

current-sense resistors or the inductor’s DCR.

The DC droop amplifier’s output (FBDC) connects to

the remote-sense point of the output through a resistor

that sets each phase’s DC voltage-positioning gain:

where the target voltage (VTARGET) is defined in the

Nominal Output-Voltage Selection

section, and the

FBDC amplifier’s output current (IFBDC) is determined

by each phase’s current-sense voltage:

where VCS = VCSP - VCSN is the differential current-

sense voltage, and GM(FBDC) is typically 1mS as

defined in the

Electrical Characteristics

table.

DC droop is typically used together with the +12.5mV

offset feature to keep within the DC tolerance window of

the application. See the

Offset and Transient-Phase

Repeat

(

OPTION)

section. The ripple voltage on FBDC

must be less than the 18mV (min) transient phase

repeat threshold:

where ΔILis the inductor ripple current, RESR is the

effective output ESR at the remote sense point, RSENSE is

the current-sense element, and Gm(FBDC) is 1.03mS

(max) as defined in the

Electrical Characteristics

table.

The worst-case inductor ripple occurs at the maximum

input voltage and the minimum output-voltage conditions:

To disable voltage positioning, set RFBDC to zero.

Transient Voltage-Positioning Amplifier (AC Droop)

The AC droop amplifier’s output (FBAC) connects to

the remote-sense point of the output through a resistor

that sets each phase’s AC voltage-positioning gain:

where the target voltage (VTARGET) is defined in the

Nominal Output-Voltage Selection

section, and the

FBAC amplifier’s output current (IFBAC) is determined

by each phase’s current-sense voltage:

where VCS = VCSP - VCSN is the differential current-

sense voltage, and GM(FBAC) is 1.03mS (max), as

defined in the

Electrical Characteristics

table.

AC droop is required for stable operation of the

MAX17009. A minimum of 1mV/A is recommended. AC

droop must not be disabled.

IG V

FBAC m FBAC CS

=()

VV RI

OUT TARGET FBAC FBAC

=−

ΔIVVV

VfL

L MAX OUT MIN IN MAX OUT MIN

IN MAX OSC

() () ( ) ()

()

=−

()

RmV

IRRG

FBDC LESR SENSE m FBDC

≤−

⎛

⎝

⎜⎞

⎠

⎟−

Δ()

ΔΔIR G R IR mV

L SENSE m FBDC FBDC L ESR() +≤18

IG V

FBDC m FBDC CS

=()

VV RI

OUT TARGET FBDC FBDC

=−

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 23

The maximum allowable AC droop is limited by the rec-

ommended integrator correction range of ±100mV and

on the DC droop:

Differential Remote Sense

The MAX17009 controller includes independent differ-

ential, remote-sense inputs for each CPU core to elimi-

nate the effects of voltage drops along the PC board

(PCB) traces and through the processor’s power pins.

The feedback-sense (FBDC_) input connects to the

voltage-positioning resistor (RFBDC_). The ground-

sense (GNDS_) input connects to an amplifier that

adds an offset directly to the target voltage, effectively

adjusting the output voltage to counteract the voltage

drop in the ground path. Connect the feedback-sense

(FBDC_) voltage-positioning resistor (RFBDC_), and

ground-sense (GNDS_) input directly to the respective

CPU core’s remote-sense outputs as shown in Figure 2.

GNDS2 has a dual function. At power-on, the voltage

level on GNDS2 configures the MAX17009 as two inde-

pendent switching regulators, or one higher current

two-phase regulator. Keep GNDS2 low during power-

up to configure the MAX17009 in separate mode.

Connect GNDS2 to a voltage above 0.8V (typ) for com-

bined-mode operation. In the AMD mobile system, this

is automatically done by the CPU that is plugged into

the socket that pulls GNDS2 to the VDDIO voltage level.

The MAX17009 checks the GNDS2 level at the time

when the internal REFOK signal goes high, and latches

the operating mode information (separate or combined

mode). This latch is cleared by cycling the SHDN pin.

Integrator Amplifier

An internal integrator amplifier forces the DC average

of the FBDC_ voltage to equal the target voltage. This

transconductance amplifier integrates the feedback

voltage and provides a fine adjustment to the regulation

voltage (Figure 3), allowing accurate DC output-voltage

regulation regardless of the output-ripple voltage. The

integrator amplifier has the ability to shift the output

voltage by ±100mV (min).

The MAX17009 disables the integrator by connecting

the amplifier inputs together at the beginning of all VID

transitions done in pulse-skipping mode. The integrator

remains disabled until 20µs after the transition is com-

pleted (the internal target settles), and the output is in

regulation (edge detected on the error comparator).

When voltage positioning is disabled (RFBDC_ = 0Ω),

the AC droop setting must be less than the ±100mV

minimum adjustment range of the integrator amplifier to

guarantee proper DC output-voltage accuracy. See the

Steady State Voltage-Positioning Amplifiers (DC Droop)

and the

Transient Voltage-Positioning Amplifiers (AC

Droop)

sections.

2-Wire Serial Interface (SVC, SVD)

The MAX17009 supports the 2-wire, write only, serial-

interface bus as defined by the AMD Serial VID

Interface Specification. The serial interface is similar to

the high-speed 3.4MHz I2C bus, but without the master

mode sequence. The bus consists of a clock line (SVC)

and a data line (SVD). The CPU is the bus master, and

the MAX17009 is the slave. The MAX17009 serial inter-

face works from 100kHz to 3.4MHz. In the AMD mobile

application, the bus runs at 3.4MHz.

The serial interface is active only after PGD_IN goes

high in the startup sequence. The CPU sets the VID

voltage of the three internal DACs and the PSI_L bit

through the serial interface.

During the startup sequence, the SVC and SVD inputs

serve an alternate function to set the 2-bit boot VID for

all three DACs while PWRGD is low. In debug mode,

the SVC and SVD inputs function in the 2-bit VID mode

when PGD_IN is low, and in the serial-interface mode

when PGD_IN is high.

Nominal Output-Voltage Selection

SMPS Output Voltage

The nominal no-load output voltage (VTARGET_) for

each SMPS is defined by the selected voltage refer-

ence (VID DAC) plus the remote ground-sense adjust-

ment (VGNDS) and the offset voltage (VOFFSET) as

defined in the following equation:

where VDAC is the selected VID voltage of the SMPS

DAC, VGNDS is the ground-sense correction voltage,

and VOFFSET is the +12.5mV offset enabled by the

OPTION pin, when the PSI_L is set high.

NBV_BUF Output Voltage

The nominal output voltage (VTARGET) for the NBV_BUF

is defined by the selected voltage reference (VID DAC)

plus the remote ground-sense adjustment (VGNDS), as

defined in the following equation:

where VDAC_ is the selected VID voltage of the

NBV_BUF DAC, and VGNDS_NB_ is the ground-sense

correction voltage. The offset voltage (VOFFSET) is not

applied to NBV_BUF.

VV VV

TARGET NBV BUF DAC GNDS NB

==+

VVVVV

TARGET FBDC DAC GNDS OFFSET

==++

RR mV

mSI R

FBAC FBDC LOAD MAX SENSE

−≤ 100

103.()

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

24 ______________________________________________________________________________________

DAC1

PWRGD

UVLO

REFOK

RUN

REF

NBSKP

VCC

REF (2.0V)

DEBUG

MODE

NBV_BUF

SVC

SVD

SVI

INTERFACE

PGD_IN

SHDN

VDDIO

7-BIT VID

SKIP1

DAC2

7-BIT VID

SKIP2

DAC3

7-BIT VID

OSC

OSCILLATOR

PWM_

GNDS1

RUN

FAULT2

FAULT1

TIME

PRO

DACOUT1

TIME

BLANK1

TARGET1

BLANK2

TARGET2

DACOUT2

VDDIO

DACOUT3

CLOCK2

GNDS2

BST_

DH_

LX_

GND_

DL_

VDD

PHASE 1

TARGET AND

SLEW-RATE

BLOCK

COMBINE

SKIP3

GNDS1

OFS_EN

0.8V

CLOCK1

ISLOPE1

ISLOPE2

A/B

OUT

GNDS_NB

VRHOT

THRM

DRIVER

BLOCK

CSP_

CSN_

FBDC_

PWM

BLOCK

FBAC_

PWM_

CLOCK_

TARGET_

IMIN_

IMAX_

SKIP_

TPR_EN

ISLOPE_

DRP_EN

CSA_

OPTION 4-LEVEL

DECODE TPR_EN

OFS_EN

ILIM CURRENT

LIMIT

IMAX_

INEG_

IMIN_

CSA_

REF

SKIP_

CCV1S

CCV1 CCV2

CCV2S

CCV_S

CCV_

PHASE 2

FAULT

BLOCK

PHASE 1

FAULT

BLOCK

FAULT2

FBDC2

TARGET2

PGD1

FAULT1

FBDC1

TARGET1

PGD2

BLANK2

BLANK1

3-LEVEL

DECODE DEBUG

MODE

MAX17009

0.3 x VCC

PHASE 2

TARGET AND

SLEW-RATE

BLOCK

Figure 3. Functional Diagram

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 25

7-Bit DAC

Inside the MAX17009 are three 7-bit digital-to-analog

converters (DACs). Each DAC can be individually pro-

grammed to different voltage levels through the serial-

interface bus. The DAC sets the target for the output

voltage for the SMPSs and the NB buffer output

(NBV_BUF). The available DAC codes and resulting

output voltages are compatible with the AMD SVI

(Table 4) specifications

Boot Voltage

On startup, the MAX17009 slews the target for all three

DACs from ground to the boot voltage set by the SVC

and SVD pin voltage levels. While the output is still below

regulation, the SVC and SVD levels can be changed,

and the MAX17009 sets the DACs to the new boot volt-

age. Once the programmed boot voltage is reached and

PWRGD goes high, the MAX17009 stores the boot VID.

Changes in the SVC and SVD settings do not change the

output voltage once the boot VID is stored. When

PGD_IN goes high, the MAX17009 exits boot mode, and

the three DACs can be independently set to any voltage

in the VID table through the serial interface.

If PGD_IN goes from high to low anytime after the boot

VID is stored, the MAX17009 sets all three DACs back

to the voltage of the stored boot VID.

When in debug mode (PRO = OPEN), the MAX17009

uses a different boot-voltage code set. Keeping

PGD_IN low allows the SVC and SVD inputs to set the

three DACs to different voltages in the boot-voltage

code table. When PGD_IN is subsequently set high, the

three DACs can be independently set to any voltage in

the VID table serial interface. Table 3 shows the boot-

voltage code table.

Offset

A +12.5mV offset can be added to both SMPS DAC

voltages for applications that include DC droop. The

offset is applied only after the MAX17009 exits boot

mode (PGD_IN going from low to high), and the

MAX17009 enters the serial-interface mode. The offset

is disabled when the PSI_L bit is set, saving more

power when the load is light.

The OPTION pin setting enables or disables the

+12.5mV offset. Connect OPTION to REF or GND to

enable the offset. Keep OPTION open or connected to

VCC to disable the offset. See the

Offset and Transient-

Phase Repeat

(

OPTION)

section.

Output-Voltage Transition Timing

SMPS Output-Voltage Transition

The MAX17009 performs positive voltage transitions in a

controlled manner, automatically minimizing input surge

currents. This feature allows the circuit designer to

achieve nearly ideal transitions, guaranteeing just-in-time

arrival at the new output voltage level with the lowest

possible peak currents for a given output capacitance.

The slew rate (set by resistor RTIME) must be set fast

enough to ensure that 35.7kΩand 357kΩfor corre-

sponding slew rates between 25mV/µs to 2.5mV/µs,

respectively, for the SMPSs.

At the beginning of an output-voltage transition, the

MAX17009 blanks both PWRGD comparator thresh-

olds, preventing the PWRGD open-drain output from

changing states during the transition. At the end of an

upward VID transition, the controller enables both

PWRGD thresholds approximately 20µs after the slew-

rate controller reaches the target output voltage. At the

end of a downward VID transition, the upper PWRGD

threshold is enabled only after the output reaches the

lower VID code setting.

The MAX17009 automatically controls the current to the

minimum level required to complete the transition in the

calculated time. The slew-rate controller uses an internal

capacitor and current source programmed by RTIME to

transition the output voltage. The total transition time

depends on RTIME, the voltage difference, and the

accuracy of the slew-rate controller (CSLEW accuracy).

The slew rate is not dependent on the total output

capacitance, as long as the surge current is less than

the current limit set by ILIM. For all dynamic positive VID

transitions, the transition time (tTRAN) is given by:

where dVTARGET/dt = 6.25mV/µs x 143kΩ/ RTIME is the

slew rate, VOLD is the original output voltage, and VNEW

is the new target voltage. See the TIME Slew-Rate

Accuracy row in the

Electrical Characteristics

table for

slew-rate limits.

The output voltage tracks the slewed target voltage,

making the transitions relatively smooth. The average

inductor current per phase required to make an output-

voltage transition is:

tVV

dV dt

TRAN NEW OLD

TARGET

=−

()

SVC SVD

BOOT VOLTAGE

(VBOOT)

(PRO = VC C

O R G N D )

BOOT VOLTAGE

(VBOOT)

(PRO = OPEN)

0 0 1.1 1.4

0 1 1.0 1.2

1 0 0.9 1.0

1 1 0.8 0.8

Table 3. Boot-Voltage Code Table

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

26 ______________________________________________________________________________________

where dVTARGET/dt is the required slew rate, COUT is

the total output capacitance.

The MAX17009 SMPSs remain in a pulse-skipping

mode even during upward and downward VID transi-

tions. As such, downward VID transitions are not

forced, and the output voltage may take a longer time

to settle to the lower VID code. The discharge rate of

the output voltage during downward transitions is

dependent on the load current and total output capaci-

tance for loads less than a minimum current, and

dependent on the RTIME programmed slew rate for

heavier loads. The critical load current (ILOAD(CRIT))

where the transition time is dependent on the load is:

For load currents less than ILOAD(CRIT), the transition

time is:

For soft-start and shutdown, the controller uses a fixed

slew rate of 1mV/µs. Figure 4 is the VID transition timing

diagram. Table 4 shows the output-voltage VID DAC

codes.

tCdV

TRANS OUT TARGET

LOAD

≅×

I C dV dt

LOAD CRIT OUT TARGET() /≅×

()

I C dV dt

L OUT TARGET

≅×

()

CORE VOLTAGE

(CORE TARGET)

PWRGD

CORE LOAD LIGHT LOAD

HEAVY LOAD

SVC/SVD BUS IDLE BUS IDLEBUS IDLE

PWRGD UPPER

THRESHOLD

PWRGD LOWER

THRESHOLD

20μs20μs

CORE TARGET

UPPER THRESHOLD BLANKED

20μs

BLANK

HIGH IMPEDANCE

BLANK

HIGH IMPEDANCE

BLANK

HIGH IMPEDANCE

Figure 4. VID Transition Timing Figure

SVID[6:0]

OUTPUT

VOLTAGE (V)

SVID[6:0]

OUTPUT

VOLTAGE (V)

SVID[6:0]

OUTPUT

VOLTAGE (V)

SVID[6:0]

OUTPUT

VOLTAGE (V)

000_0000

1.5500

010_0000

1.1500

100_0000

0.7500

110_0000

0.3500

000_0001

1.5375

010_0001

1.1375

100_0001

0.7375

110_0001

0.3375

000_0010

1.5250

010_0010

1.1250

100_0010

0.7250

110_0010

0.3250

000_0011

1.5125

010_0011

1.1125

100_0011

0.7125

110_0011

0.3125

000_0100

1.5000

010_0100

1.1000

100_0100

0.7000

110_0100

0.3000

000_0101

1.4875

010_0101

1.0875

100_0101

0.6875

110_0101

0.2875

000_0110

1.4750

010_0110

1.0750

100_0110

0.6750

110_0110

0.2750

000_0111

1.4625

010_0111

1.0625

100_0111

0.6625

110_0111

0.2625

000_1000

1.4500

010_1000

1.0500

100_1000

0.6500

110_1000

0.2500

000_1001

1.4375

010_1001

1.0375

100_1001

0.6375

110_1001

0.2375

Table 4. Output Voltage VID DAC Codes

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 27

NBV_BUF Output-Voltage Transition

The MAX17009 includes a buffered output voltage that

sets the target for the NB regulator. When a voltage

transition on the NB DAC occurs, the NBV_BUF

sources or sinks a programmed current on its output.

The programmed current (INBV_BUF) is set by RTIME.

RTIME is between 35.7kΩand 357kΩfor corresponding

INBV_BUF between 28µA and 2.8µA, respectively:

INBV_BUF = (7µA) x (143kΩ/ RTIME)

INBV_BUF and the external capacitor (CNBV_BUF) set

the voltage slew rate of the NBV_BUF:

dVNBV_BUF/dt = INBV_BUF / CNBV_BUF

Program the NB regulator with a slew rate faster than

that set by NBV_BUF to allow the NBV_BUF to control

the NB regulator’s output slew rate.

Alternatively, the NB regulator can be programmed with

the desired slew rate, and the NBV_BUF voltage can

approach a step function by keeping CNBV_BUF small.

A minimum of 100pF capacitor is required.

Pulse-Skipping Operation

The SMPS of the MAX17009 always operates in pulse-

skipping mode. Pulse-skipping mode enables the driver’s

zero-crossing comparator, so the driver pulls its DL low

when “zero” inductor current is detected (VGND - VLX

= 0). This keeps the inductor from discharging the output

capacitors and forces the controller to skip pulses under

light-load conditions to avoid overcharging the output.

In the pulse-skipping operation, the controller termi-

nates the on-time when the output voltage exceeds the

feedback threshold and when the current-sense voltage

exceeds the Idle Mode current-sense threshold (VIDLE

= 0.15 x VLIMIT). Under heavy-load conditions, the con-

tinuous inductor current remains above the Idle Mode

current-sense threshold, so the on-time depends only

on the feedback-voltage threshold. Under light-load

conditions, the controller remains above the feedback

voltage threshold, so the on-time duration depends

solely on the Idle Mode current-sense threshold, which

is approximately 15% of the full-load peak current-limit

threshold set by ILIM.

SVID[6:0]

OUTPUT

VOLTAGE (V)

SVID[6:0]

OUTPUT

VOLTAGE (V)

SVID[6:0]

OUTPUT

VOLTAGE (V)

SVID[6:0]

OUTPUT

VOLTAGE (V)

000_1010

1.4250

010_1010

1.0250

100_1010

0.6250

110_1010

0.2250

000_1011

1.4125

010_1011

1.0125

100_1011

0.6125

110_1011

0.2125

000_1100

1.4000

010_1100

1.0000

100_1100

0.6000

110_1100

0.2000

000_1101

1.3875

010_1101

0.9875

100_1101

0.5875

110_1101

0.1875

000_1110

1.3750

010_1110

0.9750

100_1110

0.5750

110_1110

0.1750

000_1111

1.3625

010_1111

0.9625

100_1111

0.5625

110_1111

0.1625

001_0000

1.3500

011_0000

0.9500

101_0000

0.5500

111_0000

0.1500

001_0001

1.3375

011_0001

0.9375

101_0001

0.5375

111_0001

0.1375

001_0010

1.3250

011_0010

0.9250

101_0010

0.5250

111_0010

0.1250

001_0011

1.3125

011_0011

0.9125

101_0011

0.5125

111_0011

0.1125

001_0100

1.3000

011_0100

0.9000

101_0100

0.5000

111_0100

0.1000

001_0101

1.2875

011_0101

0.8875

101_0101

0.4875

111_0101

0.0875

001_0110

1.2750

011_0110

0.8750

101_0110

0.4750

111_0110

0.0750

001_0111

1.2625

011_0111

0.8625

101_0111

0.4625

111_0111

0.0625

001_1000

1.2500

011_1000

0.8500

101_1000

0.4500

111_1000

0.0500

001_1001

1.2375

011_1001

0.8375

101_1001

0.4375

111_1001

0.0375

001_1010

1.2250

011_1010

0.8250

101_1010

0.4250

111_1010

0.0250

001_1011

1.2125

011_1011

0.8125

101_1011

0.4125

111_1011

0.0125

001_1100

1.2000

011_1100

0.8000

101_1100

0.4000

111_1100

001_1101

1.1875

011_1101

0.7875

101_1101

0.3875

111_1101

001_1110

1.1750

011_1110

0.7750

101_1110

0.3750

111_1110

001_1111

1.1625

011_1111

0.7625

101_1111

0.3625

111_1111

Table 4. Output Voltage VID DAC Codes (continued)

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

28 ______________________________________________________________________________________

During downward VID transitions, the controller tem-

porarily sets the OVP threshold to 1.85V (typ), preventing

false OVP faults. Once the error amplifier detects that the

output voltage is in regulation, the OVP threshold tracks

the selected VID DAC code. The MAX17009 automati-

cally uses forced-PWM operation during soft-shutdown.

When configured for separate-mode operation, both

SMPSs remain in pulse-skipping mode, regardless of

the PSI_L bit state.

When configured for combined-mode operation, the

PSI_L bit sets the MAX17009 in 1-phase pulse-skipping

mode or 2-phase pulse-skipping mode.

Idle Mode Current-Sense Threshold

The Idle Mode current-sense threshold forces a lightly

loaded regulator to source a minimum amount of power

with each on-time since the controller cannot terminate

the on-time until the current-sense voltage exceeds the

Idle Mode current-sense threshold (VIDLE = 0.15 x

VLIMIT). Since the zero-crossing comparator prevents

the switching regulator from sinking current, the con-

troller must skip pulses to avoid overcharging the out-

put. When the clock edge occurs, if the output voltage

still exceeds the feedback threshold, the controller

does not initiate another on-time. This forces the con-

troller to actually regulate the valley of the output volt-

age ripple under light-load conditions.

Automatic Pulse-Skipping Crossover

In skip mode, the MAX17009 zero-crossing compara-

tors are active. Therefore, an inherent automatic

switchover to PFM takes place at light loads, resulting

in a highly efficient operating mode. This switchover is

affected by a comparator that truncates the low-side

switch on-time at the inductor current’s zero crossing.

The driver’s zero-crossing comparator senses the

inductor current across the low-side MOSFET. Once

VGND - VLX drops below the zero-crossing threshold,

the driver forces DL low. This mechanism causes the

threshold between pulse-skipping PFM and nonskip-

ping PWM operation to coincide with the boundary

between continuous and discontinuous inductor-cur-

rent operation (also known as the “critical-conduction”

point). The load-current level at which the PFM/PWM

crossover occurs, ILOAD(SKIP), is given by:

The switching waveforms may appear noisy and asyn-

chronous when light loading causes pulse-skipping

operation, but this is a normal operating condition that

results in high light-load efficiency. Trade-offs in PFM

noise vs. light-load efficiency are made by varying the

inductor value. Generally, low inductor values produce

a broader efficiency vs. load curve, while higher values

result in higher full-load efficiency (assuming that the

coil resistance remains fixed) and less output-voltage

ripple. Penalties for using higher inductor values

include larger physical size and degraded load-tran-

sient response (especially at low input-voltage levels).

Current Sense

The output current of each phase is sensed differentially.

A low offset voltage and high gain (10V/V) differential

current amplifier at each phase allows low-resistance

current-sense resistors to be used to minimize power

dissipation. Sensing the current at the output of each

phase offers advantages, including less noise sensitivi-

ty, more accurate current sharing between phases, and

the flexibility of using either a current-sense resistor or

the DC resistance of the output inductor.

Using the DC resistance (RDCR) of the output inductor

allows higher efficiency. In this configuration, the initial

tolerance and temperature coefficient of the inductor’s

DCR must be accounted for in the output-voltage

droop-error budget and power monitor. This current-

sense method uses an RC filtering network to extract

the current information from the output inductor (see

Figure 5). The time constant of the RC network should

match the inductor’s time constant (L/RDCR):

where CSENSE and REQ are the time-constant matching

components. To minimize the current-sense error due

to the current-sense inputs’ bias current (ICSP and

ICSN), choose REQ less than 2kΩand use the above

equation to determine the sense capacitance

(CSENSE). Choose capacitors with 5% tolerance and

resistors with 1% tolerance specifications. Temperature

compensation is recommended for this current-sense

method. See the

Voltage-Positioning and Loop

Compensation

section for detailed information.

When using a current-sense resistor for accurate output-

voltage positioning, the circuit requires a differential RC

filter to eliminate the AC voltage step caused by the

equivalent series inductance (LESL) of the current-sense

resistor (see Figure 5). The ESL-induced voltage step

does not affect the average current-sense voltage, but

results in a significant peak current-sense voltage error

that results in unwanted offsets in the regulation voltage

and results in early current-limit detection. Similar to the

inductor DCR sensing method above, the RC filter’s time

constant should match the L/R time constant formed by

the current-sense resistor’s parasitic inductance:

RRC

DCR EQ SENSE

IVVV

Vf L

LOAD SKIP OUT IN OUT

IN SW

()

=−

()

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 29

where LESL is the equivalent series inductance of the

current-sense resistor, RSENSE is current-sense resis-

tance value, and CSENSE and REQ are the time-con-

stant matching components.

Combined-Mode Current Balance

When configured in combined mode, the MAX17009

current-mode architecture automatically forces the

individual phases to remain current balanced. SMPS1 is

the main voltage-control loop, and SMPS2 maintains the

current balance between the phases. This control

scheme regulates the peak inductor current of each

phase, forcing them to remain properly balanced.

Therefore, the average inductor current variation

depends mainly on the variation in the current-sense ele-

ment and inductance value.

Peak Current Limit

The MAX17009 current-limit circuit employs a fast peak

inductor current-sensing algorithm. Once the current-

sense signal (CSP to CSN) of the active phase exceeds

the peak current-limit threshold, the PWM controller ter-

minates the on-time. See the

Peak-Inductor Current

Limit

section in the

SMPS Design Procedure

section.

RRC

ESL

SENSE EQ SENSE

A) SERIES SENSE-RESISTOR SENSING

DH_

INPUT (VIN)

DL_

LX_

GND

CIN

CSP_

CSN_

B) OUTPUT INDUCTOR DCR SENSING

DH_

INPUT (VIN)

DL_

LX_

GND

CIN

CSP_

CSN_

COUT

INDUCTOR

CSENSE

LESL RDCR

SENSE RESISTOR

ESL RSENSE

COUT

REQ CSENSE

( )RDCR

R1 + R2

REQ =

R1 R2CSENSE

RDCR =[ + ]

FOR THERMAL COMPENSATION:

R2 SHOULD CONSIST OF AN NTC RESISTOR IN

SERIES WITH A STANDARD THIN-FILM RESISTOR.

MAX17009

Figure 5. Current-Sense Configurations

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

30 ______________________________________________________________________________________

Power-Up Sequence (POR, UVLO, PGD_IN)

Power-on reset (POR) occurs when VCC rises above

approximately 2V, resetting the fault latch and prepar-

ing the controller for operation. The VCC undervoltage

lockout (UVLO) circuitry inhibits switching until VCC

rises above 4.25V. The controller powers up the refer-

ence once the system enables the controller—VCC

above 4.25V and SHDN driven high. With the reference

in regulation, the controller ramps the SMPS and

NBV_BUF voltages to the boot voltage set by the SVC

and SVD inputs:

The soft-start circuitry does not use a variable current

limit, so full output current is available immediately.

PWRGD becomes high impedance approximately 20µs

after the SMPS outputs reach regulation. The boot VID is

stored the first time PWRGD goes high. The MAX17009

is in pulse-skipping mode during soft-start, and in

forced-PWM mode soft-shutdown.

The NB regulator soft-start time is set by the NB regula-

tor soft-start timer, or by t(NBV_BUF-START), whichever is

longer.

For automatic startup, the battery voltage should be

present before VCC. If the controller attempts to bring

the output into regulation without the battery voltage

present, the fault latch trips. The controller remains shut

down until the fault latch is cleared by toggling SHDN

or cycling the VCC power supply below 0.5V.

If the VCC voltage drops below 4.25V, the controller

assumes that there is not enough supply voltage to

make valid decisions and could also result in the stored

boot VIDs being corrupted. As such, the MAX17009

immediately stops switching (DH_ and DL_ pulled low),

latches off, and discharges the outputs using the inter-

nal 10Ωswitches from CSL_ to GND. See Figure 6.

tVRC

NBV BUF START BOOT TIME NBV BUF

(_ ) _

−=×

()

7 143μΩ

mV s

SMPS START BOOT

()

−=

()

1μ

12 34 56

DC_IN

VDDIO

VCORE_

VNBV_BUF

SVC/SVD

GNDS2

(VDD_PLANE_STRAP)

PWRGD

PGD_IN

RESET_L

SHDN

20μs

10μs

BUS IDLE

SERIAL MODE2-BIT BOOT VID

BLANK

HIGH IMPEDANCE

Figure 6. Startup Sequence

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 31

Notes:

1) The relationship between DC_IN and VDDIO is not

guaranteed. It is possible to have VDDIO powered

when DC_IN is not powered, and it is possible to

have DC_IN power-up before VDDIO powers up.

2) As the VDDIO power rail comes within specification,

VDD_Plane_Strap becomes valid and SVC and SVD

are driven to the boot VID value by the processor.

The system guarantees that VDDIO is in specification

and SVC and SVD are driven to the boot VID value

for at least 10µs prior to SHDN being asserted to the

MAX17009.

3) After SHDN is asserted, the MAX17009 samples

and latches the VDD_Plane_Strap level at its

GNDS2 pin when REF reaches the REFOK thresh-

old, and ramps up the voltage-plane outputs to the

level indicated by the 2-bit boot VID. The boot VID

is stored in the MAX17009 for use when PGD_IN

deasserts. The MAX17009 soft-starts the output

rails to limit inrush current from the DC_IN rail.

4) The MAX17009 asserts PWRGD. After PWRGD is

asserted and all system-wide voltage planes and

free-running clocks are within specification, then

the system asserts PGD_IN.

5) The processor holds the 2-bit boot VID for at least

10µs after PGD_IN is asserted.

6) The processor issues the set VID command through

SVI.

7) The MAX17009 transitions the voltage planes to the

set VID. The set VID may be greater than, or less

than the boot VID voltage.

8) The chipset enforces a 1ms delay between PGD_IN

assertion and RESET_L deassertion.

PWRGD

The MAX17009 features internal power-good fault com-

parators for each phase. The outputs of these individ-

ual power-good fault comparators are logically ORed to

drive the gate of the open-drain PWRGD output transis-

tor. Each phase’s power-good fault comparator has an

upper threshold of +200mV (typ) and a lower threshold

of -300mV (typ). PWRGD goes low if the output of either

phase exceeds its respective thresholds.

PWRGD is forced low during the startup sequence up to

20µs after both SMPS internal DACs reach the boot VID.

The 2-bit boot VID is stored when PWRGD goes high

during the startup sequence. PWRGD is immediately

forced low when SHDN goes low.

PWRGD is blanked high impedance while either of the

internal SMPS DACs are slewing during a VID transition,

plus an additional 20µs after the DAC transition is com-

pleted. For downward VID transitions, the upper thresh-

old of the power-good fault comparators remains

blanked until the output reaches regulation again.

PWRGD goes low for a minimum of 20µs when PGD_IN

goes low, and stays low until 20µs after both SMPS

internal DACs reach the boot VID.

PGD_IN

After the SMPS outputs reach the boot voltage, the

MAX17009 switches over to the serial-interface mode

when PGD_IN goes high. Anytime during normal opera-

tion, a high-to-low transition on PGD_IN causes the

MAX17009 to slew all three internal DACs back to the

stored boot VIDs. PWRGD goes low for a minimum of

20µs when PGD_IN goes low, and stays low until 20µs

after the SMPS outputs are within the PWRGD thresh-

olds. The SVC and SVD inputs are disabled during the

time that PGD_IN is low. The serial interface is reen-

abled when PGD_IN goes high again.

In debug mode (PRO = OPEN), the function of the SVC

and SVD inputs depend on the PGD_IN level. If

PGD_IN is low, the SVC and SVD inputs are used as 2-

bit inputs to set the three internal DAC voltages. See

Table 3. If PGD_IN is high, the MAX17009 switches

over to serial-interface mode. A high-to-low transition

on PGD_IN causes the MAX17009 to slew all three

internal DACs back to the stored boot VIDs and revert

to the 2-bit VID mode. See Figure 7.

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

32 ______________________________________________________________________________________

Shutdown

When SHDN goes low, the MAX17009 enters the low-

power shutdown mode. PWRGD is pulled low immedi-

ately, and the SMPS output voltages ramp down at

1mV/µs, while the NBV_BUF output slews at a rate set

by RTIME. At the end of the soft-shutdown sequence,

DL_ is kept low, and the 10Ωswitches from CSL_ to

GND are enabled, holding the outputs low:

Slowly discharging the output capacitors by slewing the

output over a long period of time keeps the average

negative inductor current low (damped response), there-

by eliminating the negative output-voltage excursion that

occurs when the controller discharges the output quick-

ly by permanently turning on the low-side MOSFET

(underdamped response). This eliminates the need for

the Schottky diode normally connected between the out-

put and ground to clamp the negative output-voltage

excursion. The MAX17009 shuts down completely—the

drivers are disabled, the reference turns off, and the

supply currents drop to about 1µA (max)—20µs after

the controller reaches the 0V target. When a fault condi-

tion—overvoltage or undervoltage—occurs on one

SMPS, the other SMPS and the NBV_BUF immediately

go through the soft-shutdown sequence. To clear the

fault latch and reactivate the controller, toggle SHDN or

cycle VCC power below 0.5V.

Soft-shutdown for the NB regulator is determined by the

particular NB regulator’s shutdown behavior. In the typ-

ical application, the NB regulator’s SHDN pin or enable

pin is toggled at the same time as the MAX17009’s

SHDN pin.

tVRC

NBV BUF SHDN NBV BUF TIME NBV BUF

(_ ) __

−=×

()

7 143μΩ

mV s

SMPS SHDN OUT

()

−=

()

1μ

SVC/SVD INPUTS DISABLED

SVC/SVD

(NBV_BUF TARGET)

VNBV_BUF

PGD_IN

PWRGD

VCORE0

(CORE0 TARGET)

(CORE1 TARGET)

VCORE1

2-BIT BOOT VID

NOTE: MAX17009 IS IN SKIP MODE.

CORE0 IS LIGHTLY LOADED.

CORE1 IS HEAVILY LOADED.

BUS IDLE

SVC/SVD

(PRO = OPEN)

20μs

BLANK

HIGH IMPEDANCE

Figure 7. PGD_IN Timing Figure

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 33

VRHOT

Temperature Comparator

The MAX17009 features an independent comparator

with an accurate threshold (VHOT) that tracks the ana-

log supply voltage (VHOT = 0.3 x VCC). Use a resistor-

and thermistor-divider between VCC and GND to gene-

rate a voltage-regulator overtemperature monitor. Place

the thermistor as close to the MOSFETs and inductors

as possible.

For combined-mode operations, the current-balance

circuit balances the currents between phases. As such,

the power loss and heat in each phase should be iden-

tical, apart from the effects of placement and airflow

over each phase. A single thermistor can be placed

near either of the phases and still be effective.

For separate mode operation, the load currents between

phases may be very different. Using two “logic-level”

thermistors (e.g., Murata PRF series POSITORS) allows

the same VRHOT comparator to monitor the tempera-

ture of both phases. Figure 8 is the THRM configuration.

Fault Protection (Latched)

PPRROO

Selectable Overvoltage

Protection and Debug Mode

The MAX17009 features a tri-level PRO pin that enables

the overvoltage protection feature, or puts the MAX17009

in debug mode. Table 5 shows the PRO-selectable

options. Debug mode is intended for applications where

the serial interface is not properly functioning, and the

output voltage needs to be adjusted to different levels.

The DAC voltage settings in debug mode further depend

on the PGD_IN level to switch between the 2-bit VID

setting or the serial interface operation.

Output Overvoltage Protection

The overvoltage-protection (OVP) circuit is designed to

protect the CPU against a shorted high-side MOSFET

by drawing high current and blowing the battery fuse.

The MAX17009 continuously monitors the output for an

overvoltage fault. The controller detects an OVP fault if

the output voltage exceeds the set VID DAC voltage by

more than 300mV. The OVP threshold tracks the VID

DAC voltage except during a downward VID transition.

During a downward VID transition, the OVP threshold is

set at 1.80V (min), until the output reaches regulation,

when the OVP threshold is reset back to 300mV above

the VID setting.

When the OVP circuit detects an overvoltage fault, it

immediately forces the external low-side driver high on

the faulted side and initiates the soft-shutdown for the

other SMPS and the NBV_BUF. The synchronous-recti-

fier MOSFETs of the faulted side are turned on with

100% duty, which rapidly discharges the output filter

capacitor and forces the output low. If the condition

that caused the overvoltage (such as a shorted high-

side MOSFET) persists, the battery fuse blows. Toggle

SHDN or cycle the VCC power supply below 0.5V to

clear the fault latch and reactivate the controller.

When in combined mode, the synchronous-rectifier

MOSFETs of both phases are turned on with 100% duty

in response to an overvoltage fault.

Overvoltage protection can be disabled by setting PRO

to high or open.

Output Undervoltage Protection

The output UVP function is similar to foldback current

limiting, but employs a timer rather than a variable cur-

rent limit. If the MAX17009 output voltage is 400mV

below the target voltage, the controller activates the

shutdown sequence for both SMPS and NBV_BUF, and

sets the fault latch. Toggle SHDN or cycle the VCC

power supply below 0.5V to clear the fault latch and

reactivate the controller.

THRM

RTHRM RTHRM

THRM

PLACE RNTC NEXT TO THE

HOTTEST POWER COMPONENT. PLACE RPTC1 AND RPTC2

NEXT TO THE RESPECTIVE

PHASE'S POWER COMPONENT.

RPTC1

VCC VCC

GND

MAX17009 MAX17009

RNTC

RPTC2

Figure 8. THRM Configuration

PRO DESCRIPTION

VCC OVP disabled

OPEN Debug mode, OVP disabled

GND OVP enabled

Table 5. PRO Settings

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

34 ______________________________________________________________________________________

Thermal-Fault Protection

The MAX17009 features a thermal-fault protection cir-

cuit. When the junction temperature rises above

+160°C, a thermal sensor sets the fault latch and shuts

down, immediately forcing DH and DL low, without

going through the soft-shutdown sequence. Toggle

SHDN or cycle the VCC power supply below 0.5V to

clear the fault latch and reactivate the controller after

the junction temperature cools by 15°C.

MOSFET Gate Drivers

The DH and DL drivers are optimized for driving mode-

rate-sized high-side and larger low-side power

MOSFETs. This is consistent with the low duty factor

seen in notebook applications where a large VIN - VOUT

differential exists. The high-side gate drivers (DH)

source and sink 2.2A, and the low-side gate drivers

(DL) source 2.7A and sink 8A. This ensures robust gate

drive for high-current applications. The DH floating

high-side MOSFET drivers are powered by internal

boost switch charge pumps at BST, while the DL syn-

chronous-rectifier drivers are powered directly by the

5V bias supply (VDD).

Adaptive dead-time circuits monitor the DL and DH dri-

vers and prevent either FET from turning on until the

other is fully off. The adaptive driver dead time allows

operation without shoot-through with a wide range of

MOSFETs, minimizing delays and maintaining efficiency.

There must be a low-resistance, low-inductance path

from the DL and DH drivers to the MOSFET gates for

the adaptive dead-time circuits to work properly; other-

wise, the sense circuitry in the MAX17009 interprets the

MOSFET gates as “off” while charge actually remains.

Use very short, wide traces (50 mils to 100 mils wide if

the MOSFET is 1in from the driver).

The internal pulldown transistor that drives DL low is

robust, with a 0.25Ω(typ) on-resistance. This helps pre-

vent DL from being pulled up due to capacitive cou-

pling from the drain to the gate of the low-side

MOSFETs when the inductor node (LX) quickly switch-

es from ground to VIN. Applications with high input volt-

ages and long inductive driver traces may require

rising LX edges that do not pull up the low-side

MOSFETs’ gate, causing shoot-through currents. The

capacitive coupling between LX and DL created by the

MOSFET’s gate-to-drain capacitance (CRSS), gate-to-

source capacitance (CISS - CRSS), and additional

board parasitics should not exceed the following mini-

mum threshold:

Typically, adding a 4700pF between DL and power

ground (CNL in Figure 9), close to the low-side

MOSFETs, greatly reduces coupling. Do not exceed

22nF of total gate capacitance to prevent excessive

turn-off delays.

Alternatively, shoot-through currents can be caused by

a combination of fast high-side MOSFETs and slow low-

side MOSFETs. If the turn-off delay time of the low-side

MOSFET is too long, the high-side MOSFETs can turn

on before the low-side MOSFETs have actually turned

off. Adding a resistor less than 5Ωin series with BST

slows down the high-side MOSFET turn-on time, elimi-

nating the shoot-through currents without degrading

the turn-off time (RBST in Figure 9). Slowing down the

high-side MOSFET also reduces the LX node rise time,

thereby reducing EMI and high-frequency coupling

responsible for switching noise.

GS TH IN RSS

ISS

()

>⎛

⎝

⎜⎞

⎠

⎟

BST

(RBST)*

INPUT (VIN)

CBST

CBYP

(RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE

SWITCHING NODE RISE TIME.

(CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE

COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.

PGND

(CNL)*

VDD

Figure 9. Gate Drive Circuit

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 35

Offset and Transient-Phase

Repeat (OPTION)

The +12.5mV offset and the transient-phase repeat fea-

tures of the MAX17009 can be selectively enabled and

disabled by the OPTION pin setting. Table 6 shows the

OPTION pin voltage levels and the features that are

enabled. See the

Transient Phase Repeat

section for a

detailed description of the respective features. When

the offset is enabled, setting the PSI_L bit low disables

the offset reducing power consumption in the low-

power state.

SMPS Design Procedure

Firmly establish the input voltage range and maximum

load current before choosing a switching frequency

and inductor operating point (ripple-current ratio). The

primary design trade-off lies in choosing a good switch-

ing frequency and inductor operating point, and the fol-

lowing four factors dictate the rest of the design:

•Input voltage range: The maximum value (VIN(MAX))

must accommodate the worst-case high AC

adapter voltage. The minimum value (VIN(MIN))

must account for the lowest input voltage after

drops due to connectors, fuses, and battery selec-

tor switches. If there is a choice at all, lower input

voltages result in better efficiency.

•Maximum load current: There are two values to

consider. The peak load current (ILOAD(MAX)) deter-

mines the instantaneous component stresses and fil-

tering requirements, and thus drives output capacitor

selection, inductor saturation rating, and the design

of the current-limit circuit. The continuous load cur-

rent (ILOAD) determines the thermal stresses and

thus drives the selection of input capacitors,

MOSFETs, and other critical heat-contributing com-

ponents. Modern notebook CPUs generally exhibit

ILOAD = ILOAD(MAX) x 80%.

For multiphase systems, each phase supports a

fraction of the load, depending on the current bal-

ancing. When properly balanced, the load current

is evenly distributed among each phase:

where ηPH is the total number of active phases.

• Switching frequency: This choice determines the

basic trade-off between size and efficiency. The

optimal frequency is largely a function of maximum

input voltage, due to MOSFET switching losses that

are proportional to frequency and VIN2. The opti-

mum frequency is also a moving target, due to

rapid improvements in MOSFET technology that are

making higher frequencies more practical.

When selecting a switching frequency, the mini-

mum on-time at the highest input voltage and low-

est output voltage must be greater than the 185ns

(max) minimum on-time specification in the

Electrical Characteristics

table:

VOUT(MIN) / VIN(MAX) x TSW > tONMIN

A good rule is to choose a minimum on-time of at

least 200ns.

When in pulse-skipping operation SKIP_ = GND,

the minimum on-time must take into consideration

the time needed for proper skip-mode operation.

The on-time for a skip pulse must be greater than

the 185ns (max) minimum on-time specification in

the

Electrical Characteristics

table:

•Inductor operating point: This choice provides

trade-offs between size vs. efficiency and transient

response vs. output noise. Low inductor values pro-

vide better transient response and smaller physical

size, but also result in lower efficiency and higher

output noise due to increased ripple current. The

minimum practical inductor value is one that causes

the circuit to operate at the edge of critical conduc-

tion (where the inductor current just touches zero

with every cycle at maximum load). Inductor values

lower than this grant no further size-reduction bene-

fit. The optimum operating point is usually found

between 20% and 50% ripple current.

Inductor Selection

By design, the AMD Mobile Serial VID application

should regard each of the MAX17009 SMPSs as inde-

pendent, single-phase regulators. The switching fre-

quency and operating point (% ripple current or LIR)

determine the inductor value as follows:

tLV

RV V

ONMIN IDLE

SENSE IN MAX OUT MIN

≤−

()

() ()

LOAD PHASE LOAD

()

=η

OPTION

OFFSET ENABLED

TRANSIENT-PHASE

REPEAT ENABLED

VCC 0 0

OPEN 0 1

REF 1 0

GND 1 1

Table 6. OPTION Pin Settings

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

36 ______________________________________________________________________________________

where ILOAD(MAX) is the maximum current per phase,

and fSW is the switching frequency per phase.

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. If using a

swinging inductor (where the inductance decreases lin-

early with increasing current), evaluate the LIR with

properly scaled inductance values. For the selected

inductance value, the actual peak-to-peak inductor rip-

ple current (ΔIINDUCTOR) is defined by:

Ferrite cores are often the best choice, although pow-

dered iron is inexpensive and can work well at 200kHz.

The core must be large enough not to saturate at the

peak inductor current (IPEAK):

Peak-Inductor Current Limit (ILIM)

The MAX17009 overcurrent protection employs a peak

current-sensing algorithm that uses either current-

sense resistors or the inductor’s DCR as the current-

sense element (see the

Current Sense

section). Since

the controller limits the peak inductor current, the maxi-

mum average load current is less than the peak cur-

rent-limit threshold by an amount equal to half the

inductor ripple current. Therefore, the maximum load

capability is a function of the current-sense resistance,

inductor value, switching frequency, and input-to-out-

put voltage difference. When combined with the output

undervoltage-protection circuit, the system is effectively

protected against excessive overload conditions.

The peak current-limit threshold is set by voltage differ-

ence between ILIM and REF using an external resistor-

divider:

VCS(PK) = VCSP_ - VCSN_ = 0.05 x (VREF - VILIM)

ILIMIT(PK) = VCS(PK) / RSENSE

where RSENSE is the resistance value of the current-

sense element (inductors’ DCR or current-sense resis-

tor), and ILIMIT(PK) is the desired peak current limit (per

phase). The peak current-limit threshold voltage-adjust-

ment range is from 10mV to 50mV.

Output-Capacitor Selection

The output filter capacitor must have low-enough ESR

to meet output ripple and load-transient requirements.

In CPU VCORE converters and other applications where

the output is subject to large-load transients, the output

capacitor’s size typically depends on how much ESR is

needed to prevent the output from dipping too low

under a load transient. Ignoring the sag due to finite

capacitance:

In non-CPU applications, the output capacitor’s size

often depends on how much ESR is needed to maintain

an acceptable level of output ripple voltage. The output

ripple voltage of a step-down controller equals the total

inductor ripple current multiplied by the output capaci-

tor’s ESR. When operating multiphase systems out-of-

phase, the peak inductor currents of each phase are

staggered, resulting in lower output-ripple voltage

(VRIPPLE) by reducing the total inductor ripple current.

For nonoverlapping, multiphase operation (VIN ≥VOUT),

the maximum ESR to meet the output-ripple-voltage

requirement is:

where fSW is the switching frequency per phase. The

actual capacitance value required relates to the physi-

cal size needed to achieve low ESR, as well as to the

chemistry of the capacitor technology. Thus, the

capacitor selection is usually limited by ESR and volt-

age rating rather than by capacitance value (this is true

of polymer types).

The capacitance value required is determined primarily

by the output transient-response requirements. Low

inductor values allow the inductor current to slew faster,

replenishing charge removed from or added to the out-

put filter capacitors by a sudden load step. Therefore,

the amount of output soar when the load is removed is

a function of the output voltage and inductor value. The

minimum output capacitance required to prevent over-

shoot (VSOAR) due to stored inductor energy can be

calculated as:

CIL

OUT LOAD MAX

OUT SOAR

≥

()

Δ()

RVf L

VV V V

ESR IN SW

IN OUT OUT RIPPLE

≤−

()

⎡

⎣

⎢

⎤

⎦

⎥

RR V

ESR PCB STEP

LOAD MAX

()

≤Δ()

III

PEAK LOAD MAX

INDUCTOR

=⎛

⎝

⎜⎞

⎠

⎟+⎛

⎝

⎜⎞

⎠

⎟

()

ΔIVVV

Vf L

INDUCTOR OUT IN OUT

IN SW

=−

()

LVV

f I LIR

IN OUT

SW LOAD MAX

OUT

=−

⎛

⎝

⎜⎞

⎠

⎟⎛

⎝

⎜⎞

⎠

⎟

()

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 37

When using low-capacity ceramic-filter capacitors,

capacitor size is usually determined by the capacity

needed to prevent VSOAR from causing problems during

load transients. Generally, once enough capacitance is

added to meet the overshoot requirement, undershoot at

the rising load edge is no longer a problem.

Input-Capacitor Selection

The input capacitor must meet the ripple-current

requirement (IRMS) imposed by the switching currents.

For a dual, 180° interleaved controller, the out-of-phase

operation reduces the RMS input ripple current, effec-

tively lowering the input capacitance requirements.

When both outputs operate with a duty cycle less than

50% (VIN > 2 x VOUT), the RMS input-ripple current is

defined by the following equation:

where IIN is the average input current:

In combined mode (GNDS2 = VDDIO) with both phases

active, the input RMS current simplifies to:

For most applications, nontantalum chemistries (ceramic,

aluminum, or OS-CON) are preferred due to their resis-

tance to inrush surge currents typical of systems with a

mechanical switch or connector in series with the input.

If the MAX17009 is operated as the second stage of a

two-stage power-conversion system, tantalum input

capacitors are acceptable. In either configuration,

choose an input capacitor that exhibits less than 10°C

temperature rise at the RMS input current for optimal

circuit longevity.

Voltage Positioning and

Loop Compensation

Voltage positioning dynamically lowers the output volt-

age in response to the load current, reducing the out-

put capacitance and processor’s power-dissipation

requirements. The controller uses two transconduc-

tance amplifiers to set the transient and DC output-volt-

age droop (Figure 3). The transient-compensation

(TRC) amplifier determines how quickly the MAX17009

responds to the load transient. The FBDC_ amplifier

adjusts the steady-state regulation voltage as a func-

tion of the load. This adjustability allows flexibility in the

selected current-sense resistor value or inductor DCR,

and allows smaller current-sense resistance to be

used, reducing the overall power dissipated.

Steady-State Voltage Positioning

Connect a resistor (RFBDC_) between FBDC_ and the

remote-sense point to set the steady-state DC droop

(load line) based on the required voltage-positioning

slope (RDROOPDC):

RFBDC_ = RDROOPDC / (RSENSE_ x Gm(FBDC_))

where RDROOPDC is the desired steady-state droop,

Gm(FBDC_) is typically 1ms as defined in the

Electrical

Characteristics

table, and RSENSE_ is the value of the

current-sense resistor that is used to provide the

(CSP_, CSN_) current-sense voltage.

When the inductors’ DCR is used as the current-sense

element (RSENSE = RDCR), the inductor DCR circuit

should include an NTC thermistor to cancel the temper-

ature dependence of the inductor DCR, maintaining a

constant voltage-positioning slope.

Transient Droop

Connect a resistor (RFBAC_) between FBAC_ and the

remote-sense point to set the DC transient AC droop

(load-line) based on the required voltage-positioning

slope (RDROOPAC):

RFBAC_ = RDROOPAC / (RSENSE_ x Gm(FBAC_))

where RDROOPAC is the desired steady-state droop,

Gm(FBAC_) is typically 1mS as defined in the

Electrical

Characteristics

table, and RSENSE_ is the value of the

current-sense resistor that is used to provide the

(CSP_, CSN_) current-sense voltage.

When the inductors’ DCR is used as the current-sense

element (RSENSE = RDCR), the inductor DCR circuit

should include an NTC thermistor to cancel the temper-

ature dependence of the inductor DCR, maintaining a

constant voltage-positioning slope.

Power-MOSFET Selection

Most of the following MOSFET guidelines focus on the

challenge of obtaining high load-current capability

when using high-voltage (> 20V) AC adapters. Low-

current applications usually require less attention.

The high-side MOSFET (NH) must be able to dissipate

the resistive losses plus the switching losses at both

VIN(MIN) and VIN(MAX). Calculate both these sums.

Ideally, the losses at VIN(MIN) should be roughly equal to

losses at VIN(MAX), with lower losses in between. If the

losses at VIN(MIN) are significantly higher than the losses

at VIN(MAX), consider increasing the size of NH(reducing

RDS(ON) but with higher CGATE). Conversely, if the losses

at VIN(MAX) are significantly higher than the losses at

II V

RMS OUT OUT

OUT

=⎛

⎝

⎜⎞

⎠

⎟−

⎛

⎝

⎜⎞

⎠

⎟

VIV

IN OUT

IN OUT OUT

IN OUT

=⎛

⎝

⎜⎞

⎠

⎟+⎛

⎝

⎜⎞

⎠

⎟

1122

VII I V

VII I

RMS OUT

IN OUT OUT IN OUT

IN OUT OUT IN

=⎛

⎝

⎜⎞

⎠

⎟−

()

+⎛

⎝

⎜⎞

⎠

⎟−

()

111 222

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

38 ______________________________________________________________________________________

VIN(MIN), consider reducing the size of NH(increasing

RDS(ON) to lower CGATE). If VIN does not vary over a

wide range, the minimum power dissipation occurs

where the resistive losses equal the switching losses.

Choose a low-side MOSFET that has the lowest possible

on-resistance (RDS(ON)), comes in a moderate-sized

package (i.e., one or two 8-pin SOs, DPAK, or D2PAK),

and is reasonably priced. Make sure that the DL gate

driver can supply sufficient current to support the gate

charge and the current injected into the parasitic gate-

to-drain capacitor caused by the high-side MOSFET

turning on; otherwise, cross-conduction problems may

occur (see the

MOSFET Gate Drivers

section).

MOSFET Power Dissipation

Worst-case conduction losses occur at the duty-factor

extremes. For the high-side MOSFET (NH), the worst-

case power dissipation due to resistance occurs at the

minimum input voltage:

where ILOAD is the per-phase current.

Generally, a small high-side MOSFET is desired to

reduce switching losses at high input voltages.

However, the RDS(ON) required to stay within package

power dissipation often limits how small the MOSFET

can be. Again, the optimum occurs when the switching

losses equal the conduction (RDS(ON)) losses. High-

side switching losses do not usually become an issue

until the input is greater than approximately 15V.

Calculating the power dissipation in high-side MOSFET

(NH) due to switching losses is difficult since it must

allow for difficult quantifying factors that influence the

turn-on and turn-off times. These factors include the

internal gate resistance, gate charge, threshold volt-

age, source inductance, and PCB layout characteris-

tics. The following switching-loss calculation provides

only a very rough estimate and is no substitute for

breadboard evaluation, preferably including verification

using a thermocouple mounted on NH:

where CRSS is the reverse transfer capacitance of NH

and IGATE is the peak gate-drive source/sink current

(1A typ), and ILOAD is the per-phase current.

Switching losses in the high-side MOSFET can become

an insidious heat problem when maximum AC adapter

voltages are applied, due to the squared term in the C

x VIN2x fSW switching-loss equation. If the high-side

MOSFET chosen for adequate RDS(ON) at low-battery

voltages becomes extraordinarily hot when biased from

VIN(MAX), consider choosing another MOSFET with

lower parasitic capacitance.

For the low-side MOSFET (NL), the worst-case power

dissipation always occurs at maximum input voltage:

The worst case for MOSFET power dissipation occurs

under heavy overloads that are greater than

ILOAD(MAX) but are not quite high enough to exceed

the current limit and cause the fault latch to trip. To pro-

tect against this possibility, you can “overdesign” the

circuit to tolerate:

where IPEAK(MAX) is the maximum valley current

allowed by the current-limit circuit, including threshold

tolerance and on-resistance variation. The MOSFETs

must have a good-size heatsink to handle the overload

power dissipation.

Choose a Schottky diode (DL) with a forward voltage

low enough to prevent the low-side MOSFET body

diode from turning on during the dead time. As a gen-

eral rule, select a diode with a DC current rating equal

to 1/3 the load current per phase. This diode is optional

and can be removed if efficiency is not critical.

Boost Capacitors

The boost capacitors (CBST) must be selected large

enough to handle the gate-charging requirements of

the high-side MOSFETs. Typically, 0.1µF ceramic

capacitors work well for low-power applications driving

medium-sized MOSFETs. However, high-current appli-

cations driving large, high-side MOSFETs require boost

capacitors larger than 0.1µF. For these applications,

select the boost capacitors to avoid discharging the

capacitor more than 200mV while charging the high-

side MOSFETs’ gates:

CNQ

BST GATE

=×

200

II I

II LIR

LOAD MAX PEAK MAX INDUCTOR

PEAK MAX LOAD MAX

() ()

=−

⎛

⎝

⎜⎞

⎠

⎟

PD NL sistive V

OUT

IN MAX

LOAD

TOTAL DS ON

(Re )

() ()

=−

⎛

⎝

⎜⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

⎛

⎝

⎜⎞

⎠

⎟

PD NHSwitching V Cf

IN MAX RSS SW

GATE LOAD

()

⎛

⎝

⎜⎞

⎠

⎟

PD NH sistive V

VIR

OUT

IN LOAD DS ON

(Re ) ()

=⎛

⎝

⎜⎞

⎠

⎟2

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 39

where N is the number of high-side MOSFETs used for

one regulator, and QGATE is the gate charge specified

in the MOSFET’s data sheet. For example, assume (2)

IRF7811W n-channel MOSFETs are used on the high

side. According to the manufacturer’s data sheet, a sin-

gle IRF7811W has a maximum gate charge of 24nC

(VGS = 5V). Using the above equation, the required

boost capacitance would be:

Selecting the closest standard value, this example

requires a 0.22µF ceramic capacitor.

SVI Applications Information

I2C-Bus-Compatible Interface

The MAX17009 is a receive-only device. The 2-wire ser-

ial bus (pins SVC and SVD) is designed to attach on a

low-voltage, I2C-like bus. In the AMD mobile applica-

tion, the CPU directly drives the bus at a speed of

3.4MHz. The CPU has a push-pull output driving to the

VDDIO voltage level. External pullup resistors may be

required during the initial power-up sequence before

the CPU’s push-pull drivers are active. Refer to AMD for

specific implementation.

When not used in the specific AMD application, the ser-

ial interface can be driven to as high as 2.5V, and oper-

ate at the lower speeds (100kHz, 400kHz, or 1.7MHz).

At lower clock speeds, external pullup resistors can be

used for open-drain outputs. Connect both SVC and

SVD lines to VDDIO through individual pullup resistors.

Calculate the required value of the pullup resistors

using:

where tRis the rise time, and should be less than 10%

of the clock period. CBUS is the total capacitance on

the bus.

The MAX17009 is compatible with the standard SVI inter-

face protocol as defined in the following subsections.

Bus Not Busy

The SVI bus is not busy when both data and clock lines

remain HIGH. Data transfers can be initiated only when

the bus is not busy.

Start Data Transfer (S)

Starting from an idle bus state (both SVC and SVD are

high), a HIGH to LOW transition of the data (SVD) line

while the clock (SVC) is HIGH determines a START

condition. All commands must be preceded by a

START condition.

Stop Data Transfer (P)

A LOW to HIGH transition of the SDA line while the

clock (SVC) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

Figure 10 shows the SVI bus START, STOP, and data

change conditions

Slave Address

After generating a START condition, the bus master

transmits the slave address consisting of a 7-bit device

code (110xxxx) for the MAX17009. Since the

MAX17009 is a write-only device, the eighth bit of the

slave address is zero. The MAX17009 monitors the bus

for its corresponding slave address continuously. It

generates an acknowledge bit if the slave address was

true and it is not in a programming mode.

SVD Data Valid

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal. The

data on the line must be changed during the LOW peri-

od of the clock signal. There is one clock pulse per bit

of data.

PULLUP R

≤CBUS

CnC

mV F

BST =×=

224

200 024.μ

SVC

SVD

START

CONDITION

STOP

CONDITION

DATA LINE

STABLE

DATA VALID

CHANGE

OF DATA

ALLOWED

Figure 10. SVI Bus START, STOP, and Data Change Conditions

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

40 ______________________________________________________________________________________

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse that is associated with this acknowledge bit. The

device that acknowledges has to pull down the SVD

line during the acknowledge clock pulse so the SVD

line is stable LOW during the HIGH period of the

acknowledge-related clock pulse. Setup and hold times

must be taken into account. See Figure 11. Figure 12

shows the SVI bus data transfer summary.

Command Byte

A complete command consists of a START condition

(S) followed by the MAX17009’s slave address and a

data phase, followed by a STOP condition (P).

SMPS Applications Information

Duty-Cycle Limits

Minimum Input Voltage

The minimum input operating voltage (dropout voltage)

is restricted by stability requirements, not the minimum

off-time (tOFF(MIN)). The MAX17009 does not include

slope compensation, so the controller becomes unsta-

ble with duty cycles greater than 50% per phase:

VIN(MIN) ≥2 x VOUT(MAX)

However, the controller can briefly operate with duty

cycles over 50% during heavy load transients.

SVC FROM

MASTER

DATA OUTPUT

BY MAX17009

DATA OUTPUT

BY MASTER

CLK1

START

CONDITION

CLK2

CLK8

CLK9

ACKNOWLEDGE

CLOCK PULSE

ACKNOWLEDGE

NOT ACKNOWLEDGE

D7 D6 D0

Figure 11. SVI Bus Acknowledge

SET DAC AND PSI_LSLAVE ADDRESSS P

Figure 12. SVI Bus Data Transfer Summary

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 41

Maximum Input Voltage

The MAX17009 controller has a minimum on-time,

which determines the maximum input operating voltage

that maintains the selected switching frequency. With

higher input voltages, each pulse delivers more energy

than the output is sourcing to the load. At the beginning

of each cycle, if the output voltage is still above the

feedback threshold voltage, the controller does not trig-

ger an on-time pulse, resulting in pulse-skipping opera-

tion. This allows the controller to maintain regulation

above the maximum input voltage, but forces the con-

troller to effectively operate with a lower switching fre-

quency. This results in an input threshold voltage at

which the controller begins to skip pulses (VIN(SKIP)):

where fSW is the per-phase switching frequency set by

the OSC resistor, and tONMIN is 185ns (max) minus the

driver’s turn-on delay (DL low to DH high). For the best

high-voltage performance, use the slowest switching

frequency setting (100kHz per phase, ROSC = 432kΩ).

PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching

losses and clean, stable operation. The switching

power stage requires particular attention (Figure 13). If

possible, mount all the power components on the top

side of the board with their ground terminals flush

against one another, and mount the controller and ana-

log components on the bottom layer so the internal

ground layers shield the analog components from any

noise generated by the power components. Follow

these guidelines for good PCB layout:

• Keep the high-current paths short, especially at the

ground terminals. This is essential for stable, jitter-

free operation.

• Connect all analog grounds to a separate solid cop-

per plane, then connect the analog ground to the

GND pins of the controller. The following sensitive

components connect to analog ground: VCC, VDDIO,

and REF bypass capacitors, remote-sense and

GNDS bypass capacitors, and the resistive connec-

tions (ILIM, OSC, TIME).

• Keep the power traces and load connections short.

This is essential for high efficiency. The use of thick

copper PCBs (2oz vs. 1oz) can enhance full-load

efficiency by 1% or more. Correctly routing PCB

traces is a difficult task that must be approached in

terms of fractions of centimeters, where a single mΩ

of excess trace resistance causes a measurable

efficiency penalty.

• Connections for current limiting (CSP_, CSN_) and

voltage positioning (FBS, GNDS) must be made

using Kelvin-sense connections to guarantee the

current-sense accuracy. Place current-sense filter

capacitors and voltage-positioning filter capacitors

as close to the IC as possible.

• Route high-speed switching nodes and driver

traces away from sensitive analog areas (REF, VCC,

FBAC, FBDC, etc.). Make all pin-strap control input

connections (SHDN, PGD_IN, OPTION) to analog

ground or VCC rather than power ground or VDD.

• Route the high-speed serial-interface signals (SVC,

SVD) in parallel, keeping the trace lengths identical.

Keep the SVC and SVD away from the high-current

switching paths.

IN SKIP OUT SW ONMIN

()

=⎛

⎝

⎜⎞

⎠

⎟

BITS DESCRIPTION

6:4 Always 110b

3 X = don’t care

VDAC2, if set, then the following data byte contains

the VID for VDAC2; bit 2 is ignored in combined

mode (GNDS2 = VDDIO)

VDAC1, if set, then the following data byte contains

the VID for VDAC1 in separate mode, and the

unified VDD in combined mode

0VDAC_NB, if set then the following data byte

contains the VID for VDAC_NB

Table 7. SVI Send Byte Address Description

BITS DESCRIPTION

PSI_L: Power-Save Indicator:

• 0 means the processor is at an optimal load

and the regulator(s) can enter power-saving

mode. Offset is disabled if previously enabled

through the OPTION pin. The MAX17009 enters

1-phase operation if in combined mode

(GNDS2 = H).

• 1 means the processor is at a high current-

consumption state. Offset is enabled if

previously enabled through the OPTION pin.

The MAX17009 returns to 2-phase operation if

in combined mode (GNDS2 = H).

6:0 SVID[6:0] as defined in Table 7.

Table 8. Serial VID 8-Bit Data Field Encoding

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

42 ______________________________________________________________________________________

• Keep the drivers close to the MOSFET, with the

gate-drive traces (DL, DH, LX, and BST) short and

wide to minimize trace resistance and inductance.

This is essential for high-power MOSFETs that

require low-impedance gate drivers to avoid shoot-

through currents.

• When trade-offs in trace lengths must be made, it is

preferable to allow the inductor charging path to be

made longer than the discharge path. For example,

it is better to allow some extra distance between the

input capacitors and the high-side MOSFET than to

allow distance between the inductor and the low-

side MOSFET or between the inductor and the out-

put filter capacitor.

Layout Procedure

1) Place the power components first, with ground ter-

minals adjacent (low-side MOSFET source, CIN,

COUT, and DL anode). If possible, make all these

connections on the top layer with wide, copper-

filled areas.

2) Mount the driver IC adjacent to the low-side

MOSFETs. The DL gate traces must be short and

wide (50 mils to 100 mils wide if the MOSFET is 1in

from the driver IC).

3) Group the gate-drive components (BST capacitors,

VDD bypass capacitor) together near the driver IC.

4) Make the DC-DC controller ground connections as

shown in the standard application circuit in Figure

2. This diagram can be viewed as having three sep-

arate ground planes: input/output ground, where all

the high-power components go; the power ground

plane, where the PGND pin, VDD bypass capacitor,

and driver IC ground connection go; and the con-

troller’s analog ground plane where sensitive ana-

log components, the master’s GND pin, and VCC

bypass capacitor go. The controller’s analog

ground plane (GND) must meet the power ground

plane (PGND) only at a single point directly

beneath the IC. The power ground plane should

connect to the high-power output ground with a

short, thick metal trace from PGND to the source of

the low-side MOSFETs (the middle of the star

ground).

5) Connect the output power planes (VCORE and sys-

tem ground planes) directly to the output-filter

capacitor positive and negative terminals with multi-

ple vias. Place the entire DC-DC converter circuit

as close to the CPU as is practical. Figure 13 is a

PCB layout example.

SPLIT CORE

CPU SOCKET

KELVIN SENSE

VIAS UNDER

THE INDUCTORS

FOR DCR SENSING

CONNECT THE

EXPOSED PAD TO

ANALOG GND

ANALOG

GROUND

(INNER

LAYER)

INDUCTOR

POWER

GROUND

INDUCTOR

INPUT

VDDNB

VCORE0

COUT

CIN

CVDD1

CREF

CVDD2

CVCC

CIN

COUT

VCORE1

Figure 13. PCB Layout Example

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

______________________________________________________________________________________ 43

Chip Information

TRANSISTOR COUNT: 14,497

PROCESS: BiCMOS

MAX17009

THIN QFN

5mm x 5mm

TOP VIEW

NBV_BUF

REF

ILIM

OSC

TIME

PWRGD

DL1

GND2

DL2

VDD1

BST1

LX1

VDD2

BST2

CSP1

4567

27282930 26 24 23 22

CSN1

PGD_IN

VCC

CSP2

CSN2

GNDS_NB

SHDN

GND1

OPTION VDDIO

FBAC1

FBDC1

GNDS1

FBAC2

FBDC2

GNDS2

PRO

VRHOT

20 DH2

SVC

SVD

THRM LX2

8910

DH1

NBSKP

Pin Configuration

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

44 ______________________________________________________________________________________

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)

QFN THIN.EPS

MAX17009

AMD Mobile Serial VID Dual-Phase

Fixed-Frequency Controller

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)