1. General description
The 74HC4094; 74HCT4094 are high-speed Si-gate CMOS devices and are pin
compatible with the 4094 of the 4000B series. It is specified in compliance with JEDEC
standard no. 7A.
The 74HC4094; 74HCT4094 is an 8-stage serial shift register. It has a storage latch
associated with each stage for strobing data from the serial input to parallel buffered
3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common
bus lines. Data is shif ted on positive-goin g clock transitions. The da ta in each shif t register
stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in
the storage register appears at the outputs whenever the output enable (OE) signal is
HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a number of 74HC4094;
74HCT4094 devices. Serial data is available at QS1 on positive -going clock edges to
allow high-speed operation in cascaded systems with a fast clock rise time. The same
serial data is available at QS2 on the next negative going clock edge. This is used for
cascading 74HC4094; 74HCT4094 devices when the clock has a slow rise time.
2. Features and benefits
Low-power dissipation
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD2 2 -A115-A exce eds 20 0 V
Specified from −40 °Cto+85°C and from −40 °Cto+125°C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
74HC4094; 74HCT4094
8-stage shift-and-store bus register
Rev. 5 — 28 June 2012 Product data sheet
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 2 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC4094N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT4094N
74HC4094D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width
3.9 mm SOT109-1
74HCT4094D
74HC4094DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HCT4094DB
74HC4094PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outlin e package; 16 leads;
body width 4.4 mm SOT403-1
Fig 1. Functional di agram Fig 2. Logic symbol
15
2
OE
D
CP STR
31
QP0
QP1
QP2
QP3
QP4
QP5
QP6
QP7
QS1
QS2
9
10
4
5
6
7
14
13
12
11
001aaf111
001aaf112
24
C1/
1D
EN3
SRG8
C2
5
6
7
14
13
12
11
9
10
32D
3
15
1
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 3 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
Fig 3. Logic diag ram
001aaf119
8-STAGE SHIFT
REGISTER
8-BIT STORAGE
REGISTER
3-STATE OUTPUTS
D
2QS2 10
QS1
QP0
4 5 6 7 14 13 12 11
QP1 QP2 QP3 QP4 QP5 QP6 QP7
9
CP
3
STR
1
OE
15
Fig 4. Logic diag ram
001aag799
DD
CP
CP
Q
FF 0
D
LE
Q
LATCH 0
D
CP
Q
FF 7
D
LE
Q
LATCH 7
D
CP
Q
STAGES 1 TO 6STAGE 0 STAGE 7
QP2
QP0
D QS2
QS1
LE
Q
LATCH
QP1 QP4
QP3 QP6
QP5 QP7
STR
OE
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 4 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 5. Pin configuration DIP16 and SO16 Fig 6. Pin configuration SSOP16 and TSSOP16
74HC4094
74HCT4094
STR V
CC
DOE
CP QP4
QP0 QP5
QP1 QP6
QP2 QP7
QP3 QS2
GND QS1
001aan577
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC4094
74HCT4094
STR VCC
DOE
CP QP4
QP0 QP5
QP1 QP6
QP2 QP7
QP3 QS2
GND QS1
001aan578
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
STR 1 strobe input
D 2 data input
CP 3 clock input
QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output
VSS 8 ground supply voltage
QS1, QS2 9, 10 serial output
OE 15 output enable input
VDD 16 supply voltage
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 5 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
7. Functional description
[1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
↑ = positive-going transition; ↓ = negative-going transition;
Z = HIGH-impedance OFF-state; NC = no change;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
Table 3. Function table[1]
Inputs Parallel outputs Serial outputs
CP OE STR DQP0 QPn QS1 QS2
↑LXXZZQ6SNC
↓LXXZZNCQ7S
↑H L X NCNCQ6SNC
↑HHLLQPn −1Q6S NC
↑HHHHQPn −1Q6S NC
↓HHHNCNCNCQ7S
Fig 7. Timing diagram
001aaf117
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
OUTPUT QP0
INTERNAL Q6S (FF 6)
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
Z-state
Z-state
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 6 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO16: Ptot derates linearly with 8 mW/K above 70 °C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or VI>V
CC +0.5 V - ±20 mA
IOK output clamping current VO<−0.5 V or VO>V
CC +0.5V - ±20 mA
IOoutput current VO = −0.5 V to (VCC +0.5V) - ±25 mA
ICC supply current - +50 mA
IGND ground current - −50 mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation DIP16 package [1] - 750 mW
SO16, SSOP16 and TSSOP16 packages [2] - 500 mW
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC4094 74HCT4094 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0- V
CC V
VOoutput voltage 0 - VCC 0- V
CC V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 7 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ Max Min Max Min Max
74HC4094
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=−20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=−20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=−20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO=−4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO=−5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=20μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO=20μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO=20μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO= 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =6.0V --±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current VI=V
IH or VIL;
VO=V
CC or GND;
VCC =6.0V
--±0.5 - ±5.0 - ±10.0 μA
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80 - 160 μA
CIinput
capacitance -3.5- pF
74HCT4094
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=−20 μA 4.4 4.5 - 4.4 - 4.4 - V
IO=−4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20μA - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 8 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
IIinput leakage
current VI=V
CC or GND;
VCC =5.5V --±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current VI=V
IH or VIL; VCC =5.5V;
VO=V
CC or GND per input
pin; other inputs at VCC or
GND; IO=0A
--±0.5 - ±5.0 - ±10 μA
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 8.0 - 80 - 160 μA
ΔICC additional
supply current VI=V
CC −2.1 V;
other inp uts at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO=0A
per input pin; STR input - 100 360 - 450 - 490 μA
per input pin; OE input - 150 540 - 675 - 735 μA
per input pin; CP input - 150 540 - 675 - 735 μA
per input pin; D input - 40 144 - 180 - 196 μA
CIinput
capacitance -3.5- pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ Max Min Max Min Max
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 9 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ Max Min Max Min Max
74HC4094
tpd propagation
delay CP to QS1; see Figure 8 [1]
VCC = 2.0 V - 50 150 - 190 - 225 ns
VCC = 4.5 V - 18 30 - 38 - 45 ns
VCC =5V; C
L=15pF - 15 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
CP to QS2; see Figure 8 [1]
VCC = 2.0 V - 44 135 - 170 - 205 ns
VCC = 4.5 V - 16 27 - 34 - 41 ns
VCC =5V; C
L=15pF - 13 - - - - - ns
VCC = 6.0 V - 13 23 - 29 - 35 ns
CP to QPn; see Figure 8 [1]
VCC = 2.0 V - 63 195 - 245 - 295 ns
VCC = 4.5 V - 23 39 - 49 - 59 ns
VCC =5V; C
L=15pF - 20 - - - - - ns
VCC = 6.0 V - 18 33 - 42 - 50 ns
STR to QPn; see Figure 9 [1]
VCC = 2.0 V - 58 180 - 225 - 270 ns
VCC = 4.5 V - 21 36 - 45 - 54 ns
VCC =5V; C
L=15pF - 18 - - - - - ns
VCC = 6.0 V - 17 31 - 38 - 46 ns
ten enable time OE to QPn; see Figure 11 [2]
VCC = 2.0 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC = 6.0 V - 16 30 - 37 - 45 ns
tdis disable time OE to QPn; see Figure 11 [3]
VCC = 2.0 V - 41 125 - 155 - 190 ns
VCC = 4.5 V - 15 25 - 31 - 38 ns
VCC = 6.0 V - 12 21 - 26 - 32 ns
tttransition
time QPn and QSn; see
Figure 8 [4]
VCC = 2.0 V - 19 75 - 95 - 110 n s
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 10 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
tWpulse width CP HIGH or LOW;
see Figure 8
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
STR HIGH; see Figure 9
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
tsu set-up time D to CP; see Figure 10
VCC = 2.0 V 50 14 - 65 - 75 - ns
VCC = 4.5 V 10 5 - 13 - 15 - ns
VCC = 6.0 V 9 4 - 11 - 13 - ns
CP to STR; see Figure 9
VCC = 2.0 V 100 28 - 125 - 150 - ns
VCC = 4.5 V 20 10 - 25 - 30 - ns
VCC = 6.0 V 17 8 - 21 - 26 - ns
thhold time D to CP; see Figure 10
VCC = 2.0 V 3 -6 - 3 - 3 - ns
VCC = 4.5 V 3 -2 - 3 - 3 - n s
VCC = 6.0 V 3 -2 - 3 - 3 - n s
CP to STR; see Figure 9
VCC = 2.0 V 0 -14 - 0 - 0 - ns
VCC = 4.5 V 0 -5 - 0 - 0 - ns
VCC = 6.0 V 0 -4 - 0 - 0 - n s
fmax maximum
frequency CP; see Figure 8
VCC = 2.0 V 6.0 28 - 4.8 - 4.0 - MHz
VCC = 4.5 V 30 87 - 24 - 20 - MHz
VCC =5V; C
L=15pF - 95 - - - - - MHz
VCC = 6.0 V 35 103 - 28 - 24 - MHz
CPD power
dissipation
capacitance
CL= 50 pF; f = 1 MHz;
VI=GNDtoV
CC
[5] -83- - - - -pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ Max Min Max Min Max
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 11 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
[1] tpd is the same as tPLH and tPHL.
74HCT4094
tpd propagation
delay CP to QS1; see Figure 8 [1]
VCC = 4.5 V - 23 39 - 49 - 59 ns
VCC =5V; C
L=15pF - 19 - - - - - ns
CP to QS2; see Figure 8 [1]
VCC = 4.5 V - 21 36 - 45 - 54 ns
VCC =5V; C
L=15pF - 18 - - - - - ns
CP to QPn; see Figure 8 [1]
VCC = 4.5 V - 25 43 - 54 - 65 ns
VCC =5V; C
L=15pF - 21 - - - - - ns
STR to QPn; see Figure 9 [1]
VCC = 4.5 V - 22 39 - 49 - 59 ns
VCC =5V; C
L=15pF - 19 - - - - - ns
ten enable time OE to QPn; see Figure 11 [2]
VCC = 4.5 V - 20 35 - 44 - 53 ns
tdis disable time OE to QPn; see Figure 11 [3]
VCC = 4.5 V - 21 35 - 44 - 53 ns
tttransition
time QPn and QSn; see
Figure 8 [4]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tWpulse width CP HIGH or LOW;
see Figure 8
VCC = 4.5 V 16 7 - 20 - 24 - ns
STR HIGH; see Figure 9
VCC = 4.5 V 16 5 - 20 - 24 - ns
tsu set-up time Dn to CP; see Figure 10
VCC = 4.5 V 10 4 - 13 - 15 - ns
CP to STR; see Figure 9
VCC = 4.5 V 20 9 - 25 - 30 - ns
thhold time Dn to CP; see Figure 10
VCC = 4.5 V 4 0 - 4 - 4 - ns
CP to STR; see Figure 9
VCC = 4.5 V 0 −4- 0 - 0 - ns
fmax maximum
frequency CP; see Figure 8
VCC = 4.5 V 30 80 - 24 - 20 - MHz
VCC =5V; C
L=15pF - 86 - - - - - MHz
CPD power
dissipation
capacitance
CL= 50 pF; f = 1 MHz;
VI=GNDtoV
CC
[5] -92- - - - -pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ Max Min Max Min Max
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 12 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPLZ and tPHZ.
[4] tt is the same as tTHL and tTLH.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD=C
PD ×VCC2×fi×N+(CL×VCC2×fo) where:
fi = input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL×VCC2×fo) = sum of outputs.
12. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Prop a ga tio n de la y in pu t (CP) to out pu t (QPn, QS1, QS2), output transition time, clock input (CP) pulse
width and the maximum frequency (CP)
1/fmax
tWtPHL
tPLH
VI
GND
VOH
VOL
QPn, QS1 output
CP input VM
VM90 %
10 %
aaa-003132
tPHL
tPLH
tTLH tTHL
VOH
VOL
QS2 output VM
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 13 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Propagation delay strobe input (STR) to output (QPn), strobe input (STR) pulse width and the clock
set-up and hold times for strobe input
tWtPHL
tPLH
th
VI
GND
VOH
VOL
QPn output
STR input VM
VM
001aaf114
tsu
VI
GND
CP input VM
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 14 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 11. Enable and disabl e times
001aaf116
tPLZ
tPHZ
outputs
disabled outputs
enabled
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input VM
VI
VOL
VOH
GND
VY
VX
tPZL
tPZH
VM
VM
VCC
GND
Table 8. Measurement points
Type Input Output
VMVMVXVY
74HC4094 0.5VCC 0.5VCC 0.1VOH 0.9VOH
74HCT4094 1.3 V 1.3 V 0.1VOH 0.9VOH
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 15 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 12. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
VIVO
RT
RLS1
CL
open
G
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC4094 VCC 6ns 15pF, 50 pF 1kΩopen GND VCC
74HCT4094 3 V 6 ns 15 pF, 50 pF 1 kΩopen GND VCC
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 16 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
13. Package outline
Fig 13. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051 0.021
0.015 0.014
0.009
1.25
0.85
0.049
0.033 0.77
0.73 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 17 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
Fig 14. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 18 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
Fig 15. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25
7.9
7.6 1.03
0.63 0.9
0.7 1.00
0.55 8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 19 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
Fig 16. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 20 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
14. Abbreviations
15. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM M ac hine Model
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT4094 v.5 20120628 Product data sheet - 74HC_HCT4094 v.4
Modifications: •VX and VY measurement points added to Table 8.
74HC_HCT4094 v.4 20111219 Product data sheet - 74HC_HCT4094 v.3
Modifications: •Legal pages updated.
74HC_HCT4094 v.3 20110214 Product data sheet - 74HC_HCT4094_CNV v.2
74HC_HCT4094_CNV v.2 19970901 Product specification - -
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 21 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyri ghts, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 22 of 23
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specificatio ns, and (b)
whenever cust omer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specificat ions.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC4094; 74HCT4094
8-stage shift-and-store bus register
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 June 2012
Document identifier: 74HC_HCT4094
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Recommended operating conditions. . . . . . . . 6
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
17 Contact information. . . . . . . . . . . . . . . . . . . . . 22
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23