DFPDIV - Lattice Semiconductor

All trademarks mentioned in this document http://www.DigitalCoreDesign.com

are trademarks of their respective owners. http://www.dcd.pl

Floating Point Pipelined Divider Unit

ver 2.07

OVERVIEW

The DFPDIV uses the pipelined mathemat-

ics algorithm to divide two arguments. The

input numbers format is according to IEEE-

754 standard. DFPDIV supports single preci-

sion real number. Divide operation was pipe-

lined up to 15 levels. Input data are fed every

clock cycle. The first result appears after 15

clock periods latency and next results are

available each clock cycle. Full IEEE-754

precision and accuracy are included.

APPLICATION

● Math coprocessors

● DSP algorithms

● Embedded arithmetic coprocessor

● Data processing & control

KEY FEATURES

● Full IEEE-754 compliance

● Single precision real format support

● Simple interface

● No programming required

● 15 levels pipeline

● Full accuracy and precision

● Results available at every clock

● Overflow, underflow and invalid operation

flags

● Fully configurable

● Fully synthesizable, static synchronous

design with no internal tri-states

DELIVERABLES

♦ Source code:

◊ VHDL Source Code or/and

◊ VERILOG Source Code or/and

◊ Encrypted, or plain text EDIF netlist

♦ VHDL & VERILOG test bench environ-

ment

◊ Active-HDL automatic simulation mac-

ros

◊ ModelSim automatic simulation macros

◊ Tests with reference responses

♦ Technical documentation

◊ Installation notes

◊ HDL core specification

◊ Datasheet

♦ Synthesis scripts

♦ Example application

♦ Technical support

◊ IP Core implementation support

◊ 3 months maintenance

● Delivery the IP Core updates, minor

and major versions changes

● Delivery the documentation updates

● Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

Single Design license allows use IP Core in

single FPGA bitstream and ASIC implemen-

tation.

All trademarks mentioned in this document http://www.DigitalCoreDesign.com

are trademarks of their respective owners. http://www.dcd.pl

Unlimited Designs, One Year licenses allow

use IP Core in unlimited number of FPGA

bitstreams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

● Single Design license for

○ VHDL, Verilog source code called HDL

Source

○ Encrypted, or plain text EDIF called Netlist

● One Year license for

○ Encry pted Netlist only

● Unlimited Designs license for

○ HDL Source

○ Netlist

● Upgrade from

○ HDL Source to Netlist

○ Single Design to Unlimited Designs

SYMBOL

adatai(31:0)

bdatai(31:0)

datao(31:0)

rst

clk

ofo

ufo

ifo

PINS DESCRIPTION

PIN TYPE DESCRIPTION

clk Input Global system clock

rst Input Global system reset

en Input Enable computing

adatai[31:0] Input A data bus input

bdatai[31:0] Input B data bus input

datao[31:0] Output Data bus output

ofo Output Overflow flag

ufo Output Underflow flag

ifo Output Invalid flag

BLOCK DIAGRAM

bdatai(31:0)

datao(31:0)

rst

clk

ofo

ufo

ifo

rguments

Checker Main FP

Pipelined Unit

Result

Composer

adatai(31:0)

Arguments Checker - performs input data

analyze against IEEE-754 number standard

compliance. The appropriate numbers and

information about the input data classes are

given as the results to Main FP Pipelined

Unit.

Main FP Pipelined Unit - performs floating

point divide function. Gives the complex in-

formation about the results and makes final

flags settings.

Result Composer - performs result rounding

function, data alignment to IEEE-754 stan-

dard, and the final flags setting.

PERFORMANCE

The following table gives a survey about the

Core area and performance in the LATTICE®

devices after Place & Route (all key features

have been included):

Device Speed

grade LUTs/PFUs Fmax

ORCA 4 -3 2996/479 27 MHz

ispXPGA -4 3132/1063 41 MHz

Core performance in LATTICE® devices

All trademarks mentioned in this document http://www.DigitalCoreDesign.com

are trademarks of their respective owners. http://www.dcd.pl

CONTACTS

For any modification or special request

please contact to Digital Core Design or local

distributors.

Headquarters:

Wroclawska 94

41-902 Bytom, POLAND

e-mail: i

tel. : +48 32 282 82 66

fax : +48 32 282 74 37

Field Office:

Texas Research Park

14815 Omicron Dr. suite 100

San Antonio, TX 78245,USA

e-mail: i

tel. : +1 210 422 8268

fax : +1 210 679 7511

Distributors:

MTC - Micro Tech Components GmbH

AM Reitweg 15

89407 Dillingen, GERMANY

e-mail : M

tel. : +49 9071 7945-0

fax : +49 9071 7945-20

Territory: Germany, Austria, Switzerland