AD-FMCOMMS4-EBZ - Analog Devices

RF Agile Transceiver

Data Sheet AD9364

Rev. C Document Feedback

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FEATURES

RF 1 × 1 transceiver with integrated 12-bit DACs and ADCs

Band: 70 MHz to 6.0 GHz

Supports time division duplex (TDD) and frequency division

duplex (FDD) operation

Tunable channel bandwidth (BW): <200 kHz to 56 MHz

3-band receiver: 3 differential or 6 single-ended inputs

Superior receiver sensitivity with a noise figure of <2.5 dB

Rx gain control

Real-time monitor and control signals for manual gain

Independent automatic gain control

2-band differential output transmitter

Highly linear broadband transmitter

Tx EVM: ≤−40 dB

Tx noise: ≤−157 dBm/Hz noise floor

Tx monitor: ≥66 dB dynamic range with 1 dB accuracy

Integrated fractional-N synthesizers

2.4 Hz maximum local oscillator (LO) step size

Multichip synchronization

CMOS/LVDS digital interface

APPLICATIONS

Point to point communication systems

Femtocell/picocell/microcell base stations

General-purpose radio systems

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD9364 is a high performance, highly integrated radio fre-

quency (RF) Agile Transceiver™ designed for use in 3G and 4G base

station applications. Its programmability and wideband capability

make it ideal for a broad range of transceiver applications.

The device combines an RF front end with a flexible mixed-signal

baseband section and integrated frequency synthesizers, simpli-

fying design-in by providing a configurable digital interface to a

processor. The AD9364 operates in the 70 MHz to 6.0 GHz range,

covering most licensed and unlicensed bands. Channel bandwidths

from less than 200 kHz to 56 MHz are supported.

The direct conversion receiver has state-of-the-art noise figure

and linearity. The receive (Rx) subsystem includes independent

automatic gain control (AGC), dc offset correction, quadrature

correction, and digital filtering, thereby eliminating the need for

these functions in the digital baseband. The AD9364 also has

flexible manual gain modes that can be externally controlled.

Two high dynamic range ADCs digitize the received I and Q

signals and pass them through configurable decimation filters

and 128-tap FIR filters to produce a 12-bit output signal at the

appropriate sample rate.

The transmitter uses a direct conversion architecture that achieves

high modulation accuracy with ultralow noise. This transmitter

design produces a Tx EVM of ≤−40 dB, allowing significant system

margin for the external power amplifier (PA) selection. The on-

board transmit (Tx) power monitor can be used as a power

detector, enabling highly accurate Tx power measurements.

The fully integrated phase-locked loops (PLLs) provide low

power fractional-N frequency synthesis for all Rx and Tx channels.

All VCO and loop filter components are integrated.

The core of the AD9364 can be powered directly from a 1.3 V

regulator. The IC is controlled via a standard 4-wire serial port and

four real-time input control pins. Comprehensive power-down

modes are included to minimize power consumption during

normal use. The AD9364 is packaged in a 10 mm × 10 mm,

144-ball chip scale package ball grid array (CSP_BGA).

AD9364

RXB_P,

RXB_N

P1_[D11:D0]/

RX_[D5:D0]

P0_[D11:D0]/

TX_[D5:D0]

RADIO

SWITCHING

RXA_P,

RXA_N

RXC_P,

RXC_N

X_MON

DATA INT E RFACE

Rx LO

Tx LO

TXA_P,

TXA_N

TXB_P,

TXB_N

CTRL

AUXDACx XTALNAUXADC

CTRL

SPI

DAC

GPO

PLLs

DAC

ADC

CLK_OUT

DAC

ADC

11846-001

NOTES

1. SPI, CTRL , P 0_ [ D1 1:D0]/T X _ [ D 5: D 0], P 1 _[D11:D 0]/RX_[D5: D 0],

AND RADIO S WITCHING CONT A IN MULTIPLE P INS.

AD9364 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Current Consumption—VDD_Interface .................................. 7

Current Consumption—VDDD1P3_DIG and VDDAx

(Combination of All 1.3 V Supplies) ......................................... 8

Absolute Maximum Ratings ..................................................... 10

Reflow Profile .............................................................................. 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 15

800 MHz Frequency Band ......................................................... 15

2.4 GHz Frequency Band .......................................................... 20

5.5 GHz Frequency Band .......................................................... 24

Theory of Operation ...................................................................... 28

General......................................................................................... 28

Receiver........................................................................................ 28

Transmitter .................................................................................. 28

Clock Input Options .................................................................. 28

Synthesizers ................................................................................. 29

Digital Data Interface................................................................. 29

Enable State Machine ..................................................................... 29

SPI Interface ................................................................................ 30

Control Pins ................................................................................ 30

GPO Pins (GPO_3 to GPO_0) ................................................. 30

Auxiliary Converters .................................................................. 30

Powering the AD9364 ................................................................ 30

Packaging and Ordering Information ......................................... 31

Outline Dimensions ................................................................... 31

Ordering Guide .......................................................................... 31

REVISION HISTORY

7/14—Rev. B to Rev. C

Changed CMOS VDD_INTERFACE from

1.2 V (min)/2.5 V (max) to 1.14 V (min)/2.625 V (max); and

Changed LVDS VDD_INTERFACE from 1.8 V (min)/2.5 V (max)

to 1.71 V (min)/2.625 V (max); Table 1......................................... 7

Added Powering the AD9364 Section ......................................... 30

2/14—Revision B: Initial Version

Rev. C | Page 2 of 32

Data Sheet AD9364

SPECIFICATIONS

Electrical characteristics at VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and all other VDDx pins = 1.3 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments

RECEIVER, GENERAL

Center Frequency 70 6000 MHz

Gain

Minimum

Maximum 74.5 dB At 800 MHz

73.0

At 2300 MHz, RXA

72.0 dB At 2300 MHz, RXB, RXC

65.5 dB At 5500 MHz, RXA

Gain Step 1 dB

Received Signal Strength

Indicator

RSSI

Range 100 dB

Accuracy ±2 dB

RECEIVER, 800 MHz

Noise Figure NF 2 dB Maximum Rx gain

Third-Order Input Intermod-

ulation Intercept Point

IIP3

−18

dBm

Maximum Rx gain

Second-Order Input Intermod-

ulation Intercept Point

IIP2 40 dBm Maximum Rx gain

Local Oscillator (LO) Leakage −122 dBm At Rx front-end input

Quadrature

Gain Error 0.2 %

Phase Error 0.2 Degrees

Modulation Accuracy (EVM) −42 dB 19.2 MHz reference clock

Input S11 −10 dB

RECEIVER, 2.4 GHz

Noise Figure NF 3 dB Maximum Rx gain

Third-Order Input Intermod-

ulation Intercept Point

IIP3 −14 dBm Maximum Rx gain

Second-Order Input Intermod-

ulation Intercept Point

IIP2 45 dBm Maximum Rx gain

Local Oscillator (LO) Leakage −110 dBm At Rx front-end input

Quadrature

Gain Error 0.2 %

Phase Error 0.2 Degrees

Modulation Accuracy (EVM) −42 dB 40 MHz reference clock

Input S11 −10 dB

RECEIVER, 5.5 GHz

Noise Figure NF 3.8 dB Maximum Rx gain

Third-Order Input Intermod-

ulation Intercept Point

IIP3 −17 dBm Maximum Rx gain

Second-Order Input Intermod-

ulation Intercept Point

IIP2 42 dBm Maximum Rx gain

Local Oscillator (LO) Leakage −95 dBm At Rx front-end input

Quadrature

Gain Error 0.2 %

Phase Error 0.2 Degrees

Modulation Accuracy (EVM) −37 dB 40 MHz reference clock

(doubled internally for RF

synthesizer)

Input S11 −10 dB

TRANSMITTER—GENERAL

Center Frequency 70 6000 MHz

Power Control Range 90 dB

Power Control Resolution 0.25 dB

Rev. C | Page 3 of 32

AD9364 Data Sheet

Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments

TRANSMITTER, 800 MHz

Output S22 −10 dB

Maximum Output Power 8 dBm 1 MHz tone into 50 Ω load

Modulation Accuracy (EVM) −40 dB 19.2 MHz reference clock

Third-Order Output Intermod-

ulation Intercept Point

OIP3 23 dBm

Carrier Leakage −50 dBc 0 dB attenuation

−32 dBc 40 dB attenuation

Noise Floor −157 dBm/Hz 90 MHz offset

TRANSMITTER, 2.4 GHz

Output S22 −10 dB

Maximum Output Power 7.5 dBm 1 MHz tone into 50 Ω load

Modulation Accuracy (EVM) −40 dB 40 MHz reference clock

Third-Order Output Intermod-

ulation Intercept Point

OIP3 19 dBm

Carrier Leakage −50 dBc 0 dB attenuation

−32 dBc 40 dB attenuation

Noise Floor −156 dBm/Hz 90 MHz offset

TRANSMITTER, 5.5 GHz

Output S22 −10 dB

Maximum Output Power 6.5 dBm 7 MHz tone into 50 Ω load

Modulation Accuracy (EVM) −36 dB

40 MHz reference clock

(doubled internally for RF

synthesizer)

Third-Order Output Intermod-

ulation Intercept Point

OIP3 17 dBm

Carrier Leakage −50 dBc 0 dB attenuation

−30 dBc 40 dB attenuation

Noise Floor −151.5 dBm/Hz 90 MHz offset

TX MONITOR INPUT (TX_MON)

Maximum Input Level 4 dBm

Dynamic Range 66 dB

Accuracy 1 dB

LO SYNTHESIZER

LO Frequency Step 2.4 Hz 2.4 GHz, 40 MHz reference

clock

Integrated Phase Noise

800 MHz 0.13 ° rms 100 Hz to 100 MHz, 30.72 MHz

reference clock (doubled

internally for RF synthesizer)

2.4 GHz

0.37

° rms

100 Hz to 100 MHz, 40 MHz

reference clock

5.5 GHz 0.59 ° rms

100 Hz to 100 MHz, 40 MHz

reference clock (doubled

internally for RF synthesizer)

REFERENCE CLOCK (REF_CLK) REF_CLK is either the input to

the XTALP/XTALN pins or a

line directly to the XTALN pin

Input

Frequency Range

MHz

Crystal input

MHz

External oscillator

Signal Level 1.3 V p-p AC-coupled external oscillator

AUXILIARY CONVERTERS

ADC

Resolution 12 Bits

Input Voltage

Minimum 0.05 V

Maximum VDDA1P3_BB − 0.05 V

DAC

Resolution

Bits

Rev. C | Page 4 of 32

Data Sheet AD9364

Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments

Output Voltage

Minimum 0.5 V

Maximum VDD_GPO − 0.3 V

Output Current 10 mA

DIGITAL SPECIFICATIONS (CMOS)

Logic Inputs

Input Voltage

High

VDD_INTERFACE × 0.8

VDD_INTERFACE

Low

VDD_INTERFACE × 0.2

Input Current

High −10 +10 μA

Low −10 +10 μA

Logic Outputs

Output Voltage

High VDD_INTERFACE × 0.8 V

Low VDD_INTERFACE × 0.2 V

DIGITAL SPECIFICATIONS (LVDS)

Logic Inputs

Input Voltage Range 825 1575 mV Each differential input in the

pair

Input Differential Voltage

Threshold

−100

+100

Receiver Differential Input

Impedance

100 Ω

Logic Outputs

Output Voltage

High 1375 mV

Low 1025 mV

Output Differential Voltage 150 mV Programmable in 75 mV

steps

Output Offset Voltage 1200 mV

GENERAL-PURPOSE OUTPUTS

Output Voltage

High VDD_GPO × 0.8 V

Low VDD_GPO × 0.2 V

Output Current 10 mA

SPI TIMING VDD_INTERFACE = 1.8 V

SPI_CLK

Period

Pulse Width tMP 9 ns

SPI_ENB Setup to First SPI_CLK

Rising Edge

Last SPI_CLK Falling Edge to

SPI_ENB Hold

tHC 0 ns

SPI_DI

Data Input Setup to

SPI_CLK

tS 2 ns

Data Input Hold to SPI_CLK tH 1 ns

SPI_CLK Rising Edge to Output

Data Delay

4-Wire Mode tCO 3 8 ns

3-Wire Mode tCO 3 8 ns

Bus Turnaround Time, Read tHZM tH tCO (max) ns After baseband processor

(BBP) drives the last address

bit

Bus Turnaround Time, Read tHZS 0 tCO (max) ns After the AD9364 drives the

last data bit

Rev. C | Page 5 of 32

AD9364 Data Sheet

Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments

DIGITAL DATA TIMING (CMOS),

VDD_INTERFACE = 1.8 V

DATA_CLK Clock Period tCP 16.276 ns 61.44 MHz

DATA_CLK and FB_CLK Pulse

Width

tMP 45% of tCP 55% of tCP ns

Tx Data TX_FRAME, P0_D, and P1_D

Setup to FB_CLK tSTX 1 ns

Hold to FB_CLK tHTX 0 ns

DATA_CLK to Data Bus Output

Delay

tDDRX 0 1.5 ns

DATA_CLK to RX_FRAME

Delay

tDDDV 0 1.0 ns

Pulse Width

ENABLE tENPW tCP ns

TXNRX tTXNRXPW tCP ns FDD independent ENSM

mode

TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode

Bus Turnaround Time

Before Rx

RPRE

2 × t

TDD mode

After Rx tRPST 2 × tCP ns TDD mode

Capacitive Load

Capacitive Input 3 pF

DIGITAL DATA TIMING (CMOS),

VDD_INTERFACE = 2.5 V

DATA_CLK Clock Period tCP 16.276 ns 61.44 MHz

DATA_CLK and FB_CLK Pulse

Width

tMP 45% of tCP 55% of tCP ns

Tx Data

TX_FRAME, P0_D, and P1_D

Setup to FB_CLK

STX

Hold to FB_CLK

HTX

DATA_CLK to Data Bus Output

Delay

tDDRX 0 1.2 ns

DATA_CLK to RX_FRAME

Delay

tDDDV 0 1.0 ns

Pulse Width

ENABLE tENPW tCP ns

TXNRX tTXNRXPW tCP ns FDD independent ENSM

mode

TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode

Bus Turnaround Time

Before Rx tRPRE 2 × tCP ns TDD mode

After Rx tRPST 2 × tCP ns TDD mode

Capacitive Load 3 pF

Capacitive Input 3 pF

DIGITAL DATA TIMING (LVDS)

DATA_CLK Clock Period tCP 4.069 ns 245.76 MHz

DATA_CLK and FB_CLK Pulse

Width

tMP 45% of tCP 55% of tCP ns

Tx Data TX_FRAME and TX_D

Setup to FB_CLK tSTX 1 ns

Hold to FB_CLK tHTX 0 ns

DATA_CLK to Data Bus Output

Delay

tDDRX 0.25 1.25 ns

DATA_CLK to RX_FRAME

Delay

tDDDV 0.25 1.25 ns

Pulse Width

ENABLE tENPW tCP ns

TXNRX tTXNRXPW tCP ns FDD independent ENSM

mode

TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode

Rev. C | Page 6 of 32

Data Sheet AD9364

Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments

Bus Turnaround Time

Before Rx tRPRE 2 × tCP ns

After Rx tRPST 2 × tCP ns

Capacitive Load 3 pF

Capacitive Input 3 pF

SUPPLY CHARACTERISTICS

1.3 V Main Supply Voltage 1.267 1.3 1.33 V

VDD_INTERFACE Supply

Nominal Settings

CMOS

1.14

2.625

LVDS 1.71 2.625 V

VDD_INTERFACE Tolerance −5 +5 % Tolerance is applicable to

any voltage setting

VDD_GPO Supply Nominal

Setting

1.3 3.3 V When unused, must be set

to 1.3 V

VDD_GPO Tolerance −5 +5 % Tolerance is applicable to

any voltage setting

Current Consumption

VDDx, Sleep Mode 180 μA Sum of all input currents

VDD_GPO 50 μA No load

1 When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin

names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.

CURRENT CONSUMPTION—VDD_INTERFACE

Table 2. VDD_INTERFACE = 1.2 V

Parameter Min Typ Max Unit Test Conditions/Comments

SLEEP MODE 45 μA Power applied, device disabled

RX AND TX, DOUBLE DATA RATE (DDR)

LTE 10 MHz

Single Port 2.9 mA 30.72 MHz data clock, CMOS

Dual Port 2.7 mA 15.36 MHz data clock, CMOS

LTE 20 MHz

Dual Port 5.2 mA 30.72 MHz data clock, CMOS

Table 3. VDD_INTERFACE = 1.8 V

Parameter Min Typ Max Unit Test Conditions/Comments

SLEEP MODE 84 μA Power applied, device disabled

RX AND TX, DDR

LTE 10 MHz

Single Port 4.5 mA 30.72 MHz data clock, CMOS

Dual Port 4.1 mA 15.36 MHz data clock, CMOS

LTE 20 MHz

Dual Port

8.0

30.72 MHz data clock, CMOS

Table 4. VDD_INTERFACE = 2.5 V

Parameter Min Typ Max Unit Test Conditions/Comments

SLEEP MODE 150 μA Power applied, device disabled

RX AND TX, DDR

LTE 10 MHz

Single Port 6.5 mA 30.72 MHz data clock, CMOS

Dual Port 6.0 mA 15.36 MHz data clock, CMOS

LTE 20 MHz

Dual Port 11.5 mA 30.72 MHz data clock, CMOS

Rev. C | Page 7 of 32

AD9364 Data Sheet

CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES)

Table 5. 800 MHz, TDD Mode

Parameter Min Typ Max Unit Test Conditions/Comments

5 MHz Bandwidth 180 mA Continuous Rx

10 MHz Bandwidth 210 mA Continuous Rx

20 MHz Bandwidth 260 mA Continuous Rx

5 MHz Bandwidth

7 dBm 340 mA Continuous Tx

−27 dBm 190 mA Continuous Tx

10 MHz Bandwidth

7 dBm 360 mA Continuous Tx

−27 dBm 220 mA Continuous Tx

20 MHz Bandwidth

7 dBm 400 mA Continuous Tx

−27 dBm 250 mA Continuous Tx

Table 6. TDD Mode, 2.4 GHz

Parameter Min Typ Max Unit Test Conditions/Comments

5 MHz Bandwidth 175 mA Continuous Rx

10 MHz Bandwidth 200 mA Continuous Rx

20 MHz Bandwidth 240 mA Continuous Rx

5 MHz Bandwidth

7 dBm 350 mA Continuous Tx

−27 dBm

160

Continuous Tx

10 MHz Bandwidth

7 dBm 380 mA Continuous Tx

−27 dBm 220 mA Continuous Tx

20 MHz Bandwidth

7 dBm 410 mA Continuous Tx

−27 dBm 260 mA Continuous Tx

Table 7. TDD Mode, 5.5 GHz

Parameter Min Typ Max Unit Test Conditions/Comments

5 MHz Bandwidth 175 mA Continuous Rx

40 MHz Bandwidth 275 mA Continuous Rx

5 MHz Bandwidth

7 dBm 400 mA Continuous Tx

−27 dBm 240 mA Continuous Tx

40 MHz Bandwidth

7 dBm 490 mA Continuous Tx

−27 dBm 385 mA Continuous Tx

Rev. C | Page 8 of 32

Data Sheet AD9364

Table 8. FDD Mode, 800 MHz

Parameter Min Typ Max Unit Test Conditions/Comments

RX AND TX

5 MHz Bandwidth

7 dBm 490 mA

−27 dBm 345 mA

10 MHz Bandwidth

7 dBm 540 mA

−27 dBm 395 mA

20 MHz Bandwidth

7 dBm 615 mA

−27 dBm 470 mA

Table 9. FDD Mode, 2.4 GHz

Parameter Min Typ Max Unit Test Conditions/Comments

RX AND TX

5 MHz Bandwidth

7 dBm 500 mA

−27 dBm 350 mA

10 MHz Bandwidth

7 dBm 540 mA

−27 dBm 390 mA

20 MHz Bandwidth

7 dBm 620 mA

−27 dBm 475 mA

Table 10. FDD Mode, 5.5 GHz

Parameter Min Typ Max Unit Test Conditions/Comments

RX AND TX

5 MHz Bandwidth

7 dBm 550 mA

−27 dBm 385 mA

Rev. C | Page 9 of 32

AD9364 Data Sheet

Rev. C | Page 10 of 32

ABSOLUTE MAXIMUM RATINGS

Table 11.

Parameter Rating

VDDx to VSSx −0.3 V to +1.4 V

VDD_INTERFACE to VSSx −0.3 V to +3.0 V

VDD_GPO to VSSx −0.3 V to +3.9 V

Logic Inputs and Outputs to

VSSx

−0.3 V to VDD_INTERFACE + 0.3 V

Input Current to Any Pin

Except Supplies

±10 mA

RF Inputs (Peak Power) 2.5 dBm

Tx Monitor Input Power (Peak

Power)

9 dBm

Package Power Dissipation (TJMAX − TA)/θJA

Maximum Junction

Temperature (TJMAX)

110°C

Operating Temperature Range −40°C to +85°C

Storage Temperature Range −65°C to +150°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

REFLOW PROFILE

The AD9364 reflow profile is in accordance with the JEDEC

JESD20 criteria for Pb-free devices. The maximum reflow

temperature is 260°C.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 12. Thermal Resistance

Package

Type

Airflow

Velocity

(m/sec) θJA1, 2 θ

JC1, 3 θ

JB1, 4 JT1, 2 Unit

144-Ball

CSP_BGA

0 32.3 9.6 20.2 0.27 °C/W

1.0 29.6 0.43 °C/W

2.5 27.8 0.57 °C/W

1 Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board.

2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3 Per MIL-STD 883, Method 1012.1.

4 Per JEDEC JESD51-8 (still air).

ESD CAUTION

Data Sheet AD9364

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration, Top View

Table 13. Pin Function Descriptions

Pin No.

Type

Mnemonic

Description

A1, A2, A4 to

A6, B1, B2,

B12, C1, C2,

C7 to C12, D1,

E1, F1, F3, H2,

H3, H6, J2, K2,

L2, L3, L7 to

L12, M4, M6

I VSSA Analog Ground. Tie these pins directly to the VSSD digital ground on the printed

circuit board (one ground plane).

A3, M3 NC NC No Connect. Do not connect to these pins.

A7 to A10, D3 I VDDA1P3_RX_TX 1.3 V Supply Input.

A11 I VDDA1P1_TX_VCO Transmit VCO Supply Input. Connect to B11.

A12 I TX_EXT_LO_IN External Transmit Local Oscillator (LO) Input. When this pin is unused, tie it to

ground.

B3 O AUXDAC1 Auxiliary DAC 1 Output.

B4 to B7 O GPO_3 to GPO_0 3.3 V Capable General-Purpose Outputs.

B8 I VDD_GPO 2.5 V to 3.3 V Supply for the Auxiliary DAC and General-Purpose Output Pins.

When the VDD_GPO supply is not used, this supply must be set to 1.3 V.

B9 I VDDA1P3_TX_LO Transmit LO 1.3 V Supply Input.

B10

VDDA1P3_TX_VCO_LDO

Transmit VCO LDO 1.3 V Supply Input. Connect to B9.

B11 O TX_VCO_LDO_OUT Transmit VCO LDO Output. Connect B11 to A11 and a 1 μF bypass capacitor in

series with a 1 Ω resistor to ground.

C3 O AUXDAC2 Auxiliary DAC 2 Output.

C4 I TEST/ENABLE Test Input. Ground this pin for normal operation.

ANALOG I/O DC P OW E R

DIGITAL I/O GROUND

NO CO NNE CT

12345678910 11 12

VSSA VSSA NC VSSA VSSA VSSA VDDA1P3_

RX_TX VDDA1P3_

RX_TX VDDA1P1_

TX_VCO TX_EXT_

LO_IN

VSSA VSSA AUXDAC1 GPO_3 GPO_2 GPO_1 GPO_0 VDD_GPO VDDA1P3_

TX_LO

VDDA1P3_

TX_VCO_

LDO

TX_VCO_

LDO_OUT VSSA

VSSA VSSA AUXDAC2 TEST/

ENABLE CTRL_IN0 CTRL_IN1 VSSA VSSA VSSA VSSA VSSA VSSA

VSSA VDDA1P3_

RX_RF VDDA1P3_

RX_TX CTRL_OUT0 CTRL_IN3 CTRL_IN2 P0_D9/

TX_D4_P P0_D7/

TX_D3_P P0_D5/

TX_D2_P P0_D3/

TX_D1_P P0_D1/

TX_D0_P VSSD

VSSA VDDA1P3_

RX_LO

VDDA1P3_

TX_LO_

BUFFER CTRL_OUT1 CTRL_OUT2 CTRL_OUT3 P0_D11/

TX_D5_P P0_D8/

TX_D4_N P0_D6/

TX_D3_N P0_D4/

TX_D2_N P0_D2/

TX_D1_N P0_D0/

TX_D0_N

VSSA VDDA1P3_

RX_VCO_

LDO VSSA CTRL_OUT6 CTRL_OUT5 CTRL_OUT4 VSSD P0_D10/

TX_D5_N VSSD FB_CLK_P VSSD VDDD1P3_

DIG

RX_EXT_

LO_IN RX_VCO_

LDO_OUT VDDA1P1_

RX_VCO CTRL_OUT7 EN_AGC ENABLE RX_

FRAME_N RX_

FRAME_P TX_

FRAME_P FB_CLK_N DATA_

CLK_P VSSD

RXB_P VSSA VSSA TXNRX SYNC_IN VSSA VSSD P1_D11/

RX_D5_P TX_

FRAME_N VSSD DATA_

CLK_N VDD_

INTERFACE

RXB_N VSSA VDDA1P3_

RX_SYNTH SPI_DI SPI_CLK CLK_OUT P1_D10/

RX_D5_N P1_D9/

RX_D4_P P1_D7/

RX_D3_P P1_D5/

RX_D2_P P1_D3/

RX_D1_P P1_D1/

RX_D0_P

RXC_P VSSA VDDA1P3_

TX_SYNTH VDDA1P3_

BB RESETB SPI_ENB P1_D8/

RX_D4_N P1_D6/

RX_D3_N P1_D4/

RX_D2_N P1_D2/

RX_D1_N P1_D0/

RX_D0_N VSSD

RXC_N VSSA VSSA RBIAS AUXADC SPI_DO VSSA VSSA VSSA VSSA VSSA VSSA

RXA_P RXA_N NC VSSA TX_MON VSSA TXA_P TXA_N TXB_P TXB_N XTALP XTALN

11846-002

Rev. C | Page 11 of 32

AD9364 Data Sheet

Pin No. Type1 Mnemonic Description

C5, C6, D6, D5 I CTRL_IN0 to CTRL_IN3 Control Inputs. Use C5, C6, D5, and D6 for manual Rx gain and Tx attenuation

control.

D2 I VDDA1P3_RX_RF Receiver 1.3 V Supply Input. Connect to D3.

D4, E4 to E6,

F4 to F6, G4

O CTRL_OUT0, CTRL_OUT1 to

CTRL_OUT3, CTRL_OUT6 to

CTRL_OUT4, CTRL_OUT7

Control Outputs. These pins are multipurpose outputs that have programmable

functionality.

D7 I/O P0_D9/TX_D4_P Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D9, it functions as part of the 12-bit, bidirectional, parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D4_P) can function as part of the LVDS 6-

bit Tx differential input bus with internal LVDS termination.

D8 I/O P0_D7/TX_D3_P Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D7, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D3_P) can function as part of the LVDS 6-bit Tx

differential input bus with internal LVDS termination.

D9 I/O P0_D5/TX_D2_P Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D5, it functions as part of the 12-bit, bidirectional, parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D2_P) can function as part of the LVDS

6-bit Tx differential input bus with internal LVDS termination.

D10 I/O P0_D3/TX_D1_P Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D3, it functions as part of the 12-bit, bidirectional, parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D1_P) can function as part of the LVDS

6-bit Tx differential input bus with internal LVDS termination.

D11 I/O P0_D1/TX_D0_P Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D0_P) can function as part of the LVDS 6-bit Tx

differential input bus with internal LVDS termination.

D12, F7, F9,

F11, G12, H7,

H10, K12

I VSSD Digital Ground. Tie these pins directly to the VSSA analog ground on the printed

circuit board (one ground plane).

E2 I VDDA1P3_RX_LO Receive LO 1.3 V Supply Input.

E3 I VDDA1P3_TX_LO_BUFFER 1.3 V Supply Input.

E7 I/O P0_D11/TX_D5_P Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D11, it functions as part of the 12-bit, bidirectional, parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D5_P) can function as part of the LVDS

6-bit Tx differential input bus with internal LVDS termination.

E8 I/O P0_D8/TX_D4_N Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D8, it functions as part of the 12-bit, bidirectional, parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D4_N) can function as part of the LVDS

6-bit Tx differential input bus with internal LVDS termination.

E9 I/O P0_D6/TX_D3_N Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D6, it functions as part of the 12-bit, bidirectional, parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D3_N) can function as part of the LVDS

6-bit Tx differential input bus with internal LVDS termination.

E10

I/O

P0_D4/TX_D2_N

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D4, it functions as part of the 12-bit, bidirectional, parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D2_N) can function as part of the LVDS

6-bit Tx differential input bus with internal LVDS termination.

E11 I/O P0_D2/TX_D1_N Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D2, it functions as part of the 12-bit, bidirectional, parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D1_N) can function as part of the LVDS

6-bit Tx differential input bus with internal LVDS termination.

E12 I/O P0_D0/TX_D0_N Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D0, it functions as part of the 12-bit, bidirectional, parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D0_N) can function as part of the LVDS

6-bit Tx differential input bus with internal LVDS termination.

F2 I VDDA1P3_RX_VCO_LDO Receive VCO LDO 1.3 V Supply Input. Connect F2 to E2.

Rev. C | Page 12 of 32

Data Sheet AD9364

Pin No. Type1 Mnemonic Description

F8 I/O P0_D10/TX_D5_N Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D10, it functions as part of the 12-bit, bidirectional, parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D5_N) can function as part of the LVDS

6-bit Tx differential input bus with internal LVDS termination.

F10, G10

FB_CLK_P, FB_CLK_N

Feedback Clock. These pins receive the FB_CLK signal that clocks in Tx data. In

CMOS mode, use FB_CLK_P as the input and tie FB_CLK_N to ground.

F12 I VDDD1P3_DIG 1.3 V Digital Supply Input.

G1 I RX_EXT_LO_IN External Receive LO Input. When this pin is unused, tie it to ground.

G2 O RX_VCO_LDO_OUT Receive VCO LDO Output. Connect this pin directly to G3 and a 1 μF bypass

capacitor in series with a 1 Ω resistor to ground.

G3 I VDDA1P1_RX_VCO Receive VCO Supply Input. Connect this pin directly to G2 only.

G5 I EN_AGC Manual Control Input for Automatic Gain Control (AGC).

G6 I ENABLE Control Input. This pin moves the device through various operational states.

G7, G8 O RX_FRAME_N, RX_FRAME_P Receive Digital Data Framing Output Signal. These pins transmit the RX_FRAME

signal that indicates whether the Rx output data is valid. In CMOS mode, use

RX_FRAME_P as the output and leave RX_FRAME_N unconnected.

G9, H9 I TX_FRAME_P, TX_FRAME_N Transmit Digital Data Framing Input Signal. These pins receive the TX_FRAME

signal that indicates when Tx data is valid. In CMOS mode, use TX_FRAME_P as

the input and tie TX_FRAME_N to ground.

G11, H11 O DATA_CLK_P, DATA_CLK_N Receive Data Clock Output. These pins transmit the DATA_CLK signal that is used

by the BBP to clock Rx data. In CMOS mode, use DATA_CLK_P as the output and

leave DATA_CLK_N unconnected.

H1, J1 I RXB_ P, RXB_N Receive Channel Differential Input B. Alternatively, each pin can be used as a

single-ended input. These inputs experience degraded performance above

3 GHz. Unused pins must be tied to ground.

H4 I TXNRX Enable State Machine Control Signal. This pin controls the data port bus direction.

Logic low selects the Rx direction; logic high selects the Tx direction.

H5 I SYNC_IN Input to Synchronize Digital Clocks Between Multiple AD9364 Devices. If this pin

is unused, it must be tied to ground.

H8 I/O P1_D11/RX_D5_P Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D11, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D5_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

H12 I VDD_INTERFACE 1.2 V to 2.5 V Supply for Digital I/O Pins (1.8 V to 2.5 V in LVDS Mode).

J3 I VDDA1P3_RX_SYNTH 1.3 V Supply Input.

J4 I SPI_DI SPI Serial Data Input.

J5 I SPI_CLK SPI Clock Input.

J6 O CLK_OUT Output Clock. This pin can be configured to output either a buffered version of the

external input clock, the DCXO, or a divided-down version of the internal ADC_CLK.

J7 I/O P1_D10/RX_D5_N Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D10, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D5_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

J8 I/O P1_D9/RX_D4_P Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D9, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D4_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

J9 I/O P1_D7/RX_D3_P Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D7, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D3_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

J10 I/O P1_D5/RX_D2_P Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D5, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D2_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

J11 I/O P1_D3/RX_D1_P Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D3, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D1_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

Rev. C | Page 13 of 32

AD9364 Data Sheet

Pin No. Type1 Mnemonic Description

J12 I/O P1_D1/RX_D0_P Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D1, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D0_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

K1, L1

RXC_P, RXC_N

Receive Channel Differential Input C. Alternatively, each pin can be used as a

single-ended input. These inputs experience degraded performance above

3 GHz. Unused pins must be tied to ground.

K3 I VDDA1P3_TX_SYNTH 1.3 V Supply Input.

K4 I VDDA1P3_BB 1.3 V Supply Input.

K5 I RESETB Asynchronous Reset. Logic low resets the device.

K6 I SPI_ENB SPI Enable Input. Set this pin to logic low to enable the SPI bus.

K7 I/O P1_D8/RX_D4_N Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D8, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D4_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

K8 I/O P1_D6/RX_D3_N Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D6, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D3_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

K9 I/O P1_D4/RX_D2_N Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D4, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D2_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

K10 I/O P1_D2/RX_D1_N Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D2, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D1_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

K11 I/O P1_D0/RX_D0_N Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 1. Alternatively, this pin (RX_D0_N) can function as part of the LVDS 6-bit Rx

differential output bus with internal LVDS termination.

L4 I RBIAS Bias Input Reference. Connect this pin through a 14.3 kΩ (1% tolerance) resistor

to ground.

L5 I AUXADC Auxiliary ADC Input. If this pin is unused, tie it to ground.

L6 O SPI_DO SPI Serial Data Output in 4-Wire Mode, High-Z in 3-Wire Mode.

M1, M2 I RXA_ P, RXA_N Receive Channel Differential Input A. Alternatively, each pin can be used as a

single-ended input. Unused pins must be tied to ground.

M5 I TX_MON Transmit Channel Power Monitor Input. If this pin is unused, tie it to ground.

M7, M8 O TXA_P, TXA_N Transmit Channel Differential Output A. Unused pins must be tied to 1.3 V.

M9, M10 O T X B _ P, T XB_N Transmit Channel Differential Output B. Unused pins must be tied to 1.3 V.

M11, M12 I XTALP, X TALN Reference Frequency Crystal Connections. When a crystal is used, connect it

between these two pins. When an external clock source is used, connect it to

XTALN and leave XTALP unconnected.

1 I is input, O is output, I/O is input/output, NC is not connected.

Rev. C | Page 14 of 32

Data Sheet AD9364

TYPICAL PERFORMANCE CHARACTERISTICS

800 MHZ FREQUENCY BAND

Figure 3. Rx Noise Figure vs. Frequency

Figure 4. RSSI Error vs. Input Power, LTE 10 MHz Modulation

(Referenced to −50 dBm Input Power at 800 MHz)

Figure 5. RSSI Error vs. Input Power, EDGE Modulation

(Referenced to −50 dBm Input Power at 800 MHz)

Figure 6. Rx EVM vs. Input Power, 64 QAM LTE 10 MHz Mode,

19.2 MHz REF_CLK

Figure 7. Rx EVM vs. Input Power, GSM Mode, 30.72 MHz REF_CLK (Doubled

Internally for RF Synthesizer)

Figure 8. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with

PIN = −82 dBm, 5 MHz OFDM Blocker at 7.5 MHz Offset

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

700 750 800 850 900

Rx NOI S E FI GURE ( dB)

FREQUENCY (MHz)

–40°C

+25°C

+85°C

11846-003

–3

–2

–1

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

RSSI E RROR (dB)

INPUT POW E R ( dBm)

–40°C

+25°C

+85°C

11846-004

–3

–2

–1

–

110

–

100

–

RSSI E RROR (dB)

INPUT POW E R ( dBm)

–40°C

+25°C

+85°C

11846-005

–45

–40

–35

–30

–25

–20

–15

–10

–5

–75 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25

Rx EVM (dB)

INPUT POW E R ( dBm)

–40°C

+25°C

+85°C

11846-006

–45

–40

–35

–30

–25

–20

–15

–10

–5

–90 –80 –70 –60 –50 –40 –30 –20 –10

Rx EVM (dB)

INPUT POW E R ( dBm)

–40°C

+25°C

+85°C

11846-007

–30

–25

–20

–15

–10

–5

–

Rx EVM (dB)

INTERFERER POWER LEVEL (dBm)

–40°C

+25°C

+85°C

11846-008

Rev. C | Page 15 of 32

AD9364 Data Sheet

Figure 9. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with

PIN = −90 dBm, 5 MHz OFDM Blocker at 17.5 MHz Offset

Figure 10. Rx Noise Figure vs. Interferer Power Level, EDGE Signal of Interest

with PIN = −90 dBm, CW Blocker at 3 MHz Offset, Gain Index = 64

Figure 11. Rx Gain vs. Frequency, Gain Index = 76 (Maximum Setting)

Figure 12. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index,

f1 = 1.45 MHz, f2 = 2.89 MHz, GSM Mode

Figure 13. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index,

f1 = 2.00 MHz, f2 = 2.01 MHz, GSM Mode

Figure 14. Rx Local Oscillator (LO) Leakage vs. Frequency

–16

–12

–8

–4

–56 –54 –52 –50 –48 –46 –44 –42 –40 –38 –36

Rx EVM (dB)

INTERFERER POWER LEVEL (d Bm)

–40°C

+25°C

+85°C

11846-009

–47 –43 –39 –35 –31 –27 –23

Rx NOI S E FI GURE ( dB)

INTERFERER POWER LEVEL (d Bm)

–40°C

+25°C

+85°C

11846-010

700 750 800 850 900

Rx GAI N (dB)

FREQUENCY (MHz)

–40°C

+25°C

+85°C

11846-011

–25

–20

–15

–10

–5

20 28 36 44 52 60 68 76

II P 3 ( dBm)

–40°C

+25°C

+85°C

Rx GAI N INDEX

11846-012

100

20 28 36 44 52 60 68 76

II P 2 ( dBm)

Rx GAI N INDEX

–40°C

+25°C

+85°C

11846-013

–130

–125

–120

–115

–110

–105

–100

700 750 800 850 900

Rx LO LE AKAGE ( dBm)

FREQUENCY (MHz)

–40°C

+25°C

+85°C

11846-014

Rev. C | Page 16 of 32

Data Sheet AD9364

Figure 15. Rx Emission at LNA Input, DC to 12 GHz, fLO_RX = 800 MHz,

LTE 10 MHz, fLO_TX = 860 MHz

Figure 16. Tx Output Power vs. Frequency, Attenuation Setting = 0 dB,

Single Tone Output

Figure 17. Tx Power Control Linearity Error vs. Attenuation Setting

Figure 18. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX =

800 MHz, LTE 10 MHz Downlink (Digital Attenuation Variations Shown)

Figure 19. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX =

800 MHz, GSM Downlink (Digital Attenuation Variations Shown), 3 MHz Range

Figure 20. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX =

800 MHz, GSM Downlink (Digital Attenuation Variations Shown), 12 MHz Range

–120

–100

–80

–60

–40

–20

02000 4000 6000 8000 10000 12000

POWER AT LNA INPUT ( dBm/ 750kHz )

FREQUENCY (MHz)

11846-015

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

700 750 800 850 900

Tx OUTP UT POWE R ( dBm)

FREQUENCY (MHz)

–40°C

+25°C

+85°C

11846-016

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

010 20 30 40 50

STEP LINE ARITY ERRO R ( dB)

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-017

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

–15 –10 –5 0510 15

Tx OUTP UT POWE R ( dBm/ 100kHz )

FREQUENCY OFFSET (MHz)

ATT 0dB

ATT 3dB

ATT 6dB

11846-018

–100

–80

–60

–40

–20

Tx OUTP UT POWE R ( dBm/ 30kHz )

FREQUENCY OFFSET (MHz)

ATT 0dB

ATT 3dB

ATT 6dB

–1.6

–1.4

–1.2

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

11846-019

–120

–100

–80

–60

–40

–20

–6 –4 –2 0246

Tx OUTP UT POWE R ( dBm/ 30kHz )

FREQUENCY OFFSET (MHz)

ATT 0dB

ATT 3dB

ATT 6dB

11846-020

Rev. C | Page 17 of 32

AD9364 Data Sheet

Figure 21. Tx EVM vs. Transmitter Attenuation Setting, fLO_TX =

800 MHz, LTE 10 MHz, 64 QAM Modulation, 19.2 MHz REF_CLK

Figure 22. Tx EVM vs. Transmitter Attenuation Setting, fLO_TX = 800 MHz, GSM

Modulation, 30.72 MHz REF_CLK (Doubled Internally for RF Synthesizer)

Figure 23. Integrated Tx LO Phase Noise vs. Frequency, 19.2 MHz REF_CLK

Figure 24. Integrated Tx LO Phase Noise vs. Frequency, 30.72 MHz REF_CLK

(Doubled Internally for RF Synthesizer)

Figure 25. Tx Carrier Rejection vs. Frequency

Figure 26. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency

–50

–45

–40

–35

–30

–25

–20

0 5 10 15 20 25 30 35 40

Tx EVM (dB)

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-021

–50

–45

–40

–35

–30

–25

–20

010 20 30 40 50

Tx EVM (dB)

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-022

0.1

0.2

0.3

0.4

0.5

700 750 800 850 900

INTEGRATED PHASE NOISE (°RMS)

FREQUENCY (MHz)

–40°C

+25°C

+85°C

11846-023

0.05

0.10

0.15

0.20

0.25

0.30

700 750 800 850 900

INTEGRATE D P HAS E NOI S E ( °rms)

FREQUENCY (MHz)

–40°C

+25°C

+85°C

11846-024

–70

–65

–60

–55

–50

–45

–40

–35

–30

700 750 800 850 900

Tx CARRIER AMPLITUDE ( dBc)

FREQUENCY (MHz)

ATT 0, –40°C

ATT 25, –40°C

ATT 50, –40°C

ATT 0, + 25°C

ATT 25, + 25°C

ATT 50, + 25°C

ATT 0, + 85°C

ATT 25, + 85°C

ATT 50, + 85°C

11846-025

–80

–75

–70

–65

–60

–55

–50

700 750 800 850 900

Tx S ECOND- ORDER HARM ONIC DISTORTI ON (dBc)

FREQUENCY (MHz)

ATT 0, –40°C

ATT 25, –40°C

ATT 50, –40°C

ATT 0, + 25°C

ATT 25, + 25°C

ATT 50, + 25°C

ATT 0, + 85°C

ATT 25, + 85°C

ATT 50, + 85°C

11846-026

Rev. C | Page 18 of 32

Data Sheet AD9364

Figure 27. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency

Figure 28. Tx Third-Order Output Intercept Point (OIP3) vs.

Attenuation Setting

Figure 29. Tx Signal-to-Noise Ratio (SNR) vs. Transmitter Attenuation Setting,

LTE 10 MHz Signal of Interest with Noise Measured at 90 MHz Offset

Figure 30. Tx Signal-to-Noise Ratio (SNR) vs. Transmitter Attenuation Setting,

GSM Signal of Interest with Noise Measured at 20 MHz Offset

Figure 31. Tx Single Sideband (SSB) Rejection vs. Frequency,

1.5375 MHz Offset

–60

–55

–50

–45

–40

–35

–30

–25

–20

700 750 800 850 900

Tx THIRD- ORDER HARM ONIC DISTORTI ON (dBc)

FREQUENCY (MHz)

ATT 0, –40°C

ATT 25, –40°C

ATT 50, –40°C

ATT 0, + 25°C

ATT 25, + 25°C

ATT 50, + 25°C

ATT 0, + 85°C

ATT 25, + 85°C

ATT 50, + 85°C

11846-027

04812 16 20

Tx OIP 3 ( dBm)

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-028

140

145

150

155

160

165

170

0 3 6912 15

Tx S NR ( dB/Hz )

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-029

140

145

150

155

160

165

170

0 4 812 16 20

Tx S NR ( dB/Hz )

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-030

–70

–65

–60

–55

–50

–45

–40

–35

–30

700 750 800 850 900

Tx S I NGL E S IDEBAND AM P LITUDE ( dBc)

FREQUENCY (MHz)

ATT 0, –40°C

ATT 25, –40°C

ATT 50, –40°C

ATT 0, + 25°C

ATT 25, + 25°C

ATT 50, + 25°C

ATT 0, + 85°C

ATT 25, + 85°C

ATT 50, + 85°C

11846-031

Rev. C | Page 19 of 32

AD9364 Data Sheet

2.4 GHZ FREQUENCY BAND

Figure 32. Rx Noise Figure vs. Frequency

Figure 33. RSSI Error vs. Input Power, Referenced to −50 dBm Input Power

at 2.4 GHz

Figure 34. Rx EVM vs. Input Power, 64 QAM LTE 20 MHz Mode,

40 MHz REF_CLK

Figure 35. Rx EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest

with PIN = −75 dBm, LTE 20 MHz Blocker at 20 MHz Offset

Figure 36. Rx EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest

with PIN = −75 dBm, LTE 20 MHz Blocker at 40 MHz Offset

Figure 37. Rx Gain vs. Frequency, Gain Index = 76 (Maximum Setting)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1800 1900 2000 2100 2200 2300 2400 2500 2600 2700

Rx NOI S E FI GURE ( dB)

FREQUENCY (MHz)

–40°C

+25°C

+85°C

11846-032

–3

–2

–1

–

100

–

RSSI E RROR (dB)

INPUT POW E R ( dBm)

–40°C

+25°C

+85°C

11846-033

–45

–40

–35

–30

–25

–20

–15

–10

–5

–75 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25

Rx EVM (dB)

INPUT POW E R ( dBm)

–40°C

+25°C

+85°C

11846-034

–30

–25

–20

–15

–10

–5

–72 –68 –64 –60 –56 –52 –48 –44 –40 –36 –32 –28

Rx EVM (dB)

INTERFERER POWER LEVEL (dBm)

–40°C

+25°C

+85°C

11846-035

–30

–25

–20

–15

–10

–5

–60 –55 –50 –45 –40 –35 –30 –25 –20

Rx EVM (dB)

INTERFERER POWER LEVEL (dBm)

–40°C

+25°C

+85°C

11846-036

1800 1900 2000 2100 2200 2300 2400 2500 2600 2700

Rx GAI N (dB)

FREQUENCY (MHz)

–40°C

+25°C

+85°C

11846-037

Rev. C | Page 20 of 32

Data Sheet AD9364

Figure 38. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index,

f1 = 30 MHz, f2 = 61 MHz

Figure 39. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index,

f1 = 60 MHz, f2 = 61 MHz

Figure 40. Rx Local Oscillator (LO) Leakage vs. Frequency

Figure 41. Rx Emission at LNA Input, DC to 12 GHz, fLO_RX = 2.4 GHz,

LTE 20 MHz, fLO_TX = 2.46 GHz

Figure 42. Tx Output Power vs. Frequency, Attenuation Setting = 0 dB,

Single Tone Output

Figure 43. Tx Power Control Linearity Error vs. Attenuation Setting

–25

–20

–15

–10

–5

20 28 36 44 52 60 68 76

II P 3 ( dBm)

Rx GAI N INDEX

–40°C

+25°C

+85°C

11846-038

20 28 36 44 52 60 68 76

II P 2 ( dBm)

Rx GAI N INDEX

–40°C

+25°C

+85°C

11846-039

–130

–125

–120

–115

–110

–105

–100

1800 1900 2000 2100 2200 2300 2400 2500 2600 2700

Rx LO LE AKAGE ( dBm)

FREQUENCY (MHz)

–40°C

+25°C

+85°C

11846-040

–120

–100

–80

–60

–40

–20

02000 4000 6000 8000 10000 12000

POWER AT LNA INPUT ( dBm/ 750kHz )

FREQUENCY (MHz)

11846-041

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

1800 1900 2000 2100 2200 2300 2400 2500 2600 2700

Tx OUTP UT POWE R ( dBm)

FREQUENCY (MHz)

–40°C

+25°C

+85°C

11846-042

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

010 20 30 40 50

STEP LINE ARITY ERROR (dB)

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-043

Rev. C | Page 21 of 32

AD9364 Data Sheet

Figure 44. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX =

2.3 GHz, LTE 20 MHz Downlink (Digital Attenuation Variations Shown)

Figure 45. Tx EVM vs. Transmitter Attenuation Setting, 40 MHz REF_CLK,

LTE 20 MHz, 64 QAM Modulation

Figure 46. Integrated Tx LO Phase Noise vs. Frequency, 40 MHz REF_CLK

Figure 47. Tx Carrier Rejection vs. Frequency

Figure 48. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency

Figure 49. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency

–120

–100

–80

–60

–40

–20

–25 –20 –15 –10 –5

0510 15 20 25

Tx OUTP UT POWE R ( dBm/ 100kHz )

FREQUENCY OFFSET (MHz)

ATT 0dB

ATT 3dB

ATT 6dB

11846-044

–50

–45

–40

–35

–30

–25

–20

0 5 10 15 20 25 30 35 40

Tx EVM (dB)

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-045

0.1

0.2

0.3

0.4

0.5

1800 1900 2000 2100 2200 2300 2400 2500 2600 2700

INTEGRATE D P HAS E NOI S E ( °rms)

FREQUENCY (MHz)

–40°C

+25°C

+85°C

11846-046

–70

–65

–60

–55

–50

–45

–40

–35

–30

1800 1900 2000 2100 2200 2300 2400 2500 2600 2700

Tx CARRIER AMPLITUDE ( dBc)

FREQUENCY (MHz)

ATT 0, –40°C

ATT 25, –40°C

ATT 50, –40°C

ATT 0, + 25°C

ATT 25, + 25°C

ATT 50, + 25°C

ATT 0, + 85°C

ATT 25, + 85°C

ATT 50, + 85°C

11846-047

–80

–75

–70

–65

–60

–55

–50

1800 1900 2000 2100 2200 2300 2400 2500 2600 2700

Tx S ECOND-ORDER HARM ONIC DISTORTI ON (dBc)

FREQUENCY (MHz)

ATT 0, –40°C

ATT 25, –40°C

ATT 50, –40°C

ATT 0, + 25°C

ATT 25, + 25°C

ATT 50, + 25°C

ATT 0, + 85°C

ATT 25, + 85°C

ATT 50, + 85°C

11846-048

–60

–55

–50

–45

–40

–35

–30

–25

–20

1800 1900 2000 2100 2200 2300 2400 2500 2600 2700

Tx THIRD- ORDER HARM ONIC DISTO RTION (dBc)

FREQUENCY (MHz)

ATT 0, –40°C

ATT 25, –40°C

ATT 50, –40°C

ATT 0, + 25°C

ATT 25, + 25°C

ATT 50, + 25°C

ATT 0, + 85°C

ATT 25, + 85°C

ATT 50, + 85°C

11846-049

Rev. C | Page 22 of 32

Data Sheet AD9364

Figure 50. Tx Third-Order Output Intercept Point (OIP3) vs.

Attenuation Setting

Figure 51. Tx Signal-to-Noise Ratio (SNR) vs. Transmitter Attenuation Setting,

LTE 20 MHz Signal of Interest with Noise Measured at 90 MHz Offset

Figure 52. Tx Single Sideband (SSB) Rejection vs. Frequency,

3.075 MHz Offset

04812 16 20

Tx OIP 3 ( dBm)

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-050

140

142

144

146

148

150

152

154

156

158

160

0 3 6 9 12 15

Tx S NR ( dB/Hz )

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-051

–70

–65

–60

–55

–50

–45

–40

–35

–30

1800 1900 2000 2100 2200 2300 2400 2500 2600 2700

Tx S I NGL E S IDEBAND AM P LITUDE ( dBc)

FREQUENCY (MHz)

ATT 0, –40°C

ATT 25, –40°C

ATT 50, –40°C

ATT 0, + 25°C

ATT 25, + 25°C

ATT 50, + 25°C

ATT 0, + 85°C

ATT 25, + 85°C

ATT 50, + 85°C

11846-052

Rev. C | Page 23 of 32

AD9364 Data Sheet

5.5 GHZ FREQUENCY BAND

Figure 53. Rx Noise Figure vs. Frequency

Figure 54. RSSI Error vs. Input Power, Referenced to −50 dBm Input Power

at 5.8 GHz

Figure 55. Rx EVM vs. Input Power, 64 QAM WiMAX 40 MHz Mode,

40 MHz REF_CLK (Doubled Internally for RF Synthesizer)

Figure 56. Rx EVM vs. Interferer Power Level, WiMAX 40 MHz Signal of Interest

with PIN = −74 dBm, WiMAX 40 MHz Blocker at 40 MHz Offset

Figure 57. Rx EVM vs. Interferer Power Level, WiMAX 40 MHz Signal of Interest

with PIN = −74 dBm, WiMAX 40 MHz Blocker at 80 MHz Offset

Figure 58. Rx Gain vs. Frequency, Gain Index = 76 (Maximum Setting)

5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0

Rx NOI S E FI GURE ( dB)

FRE Q UE NCY ( GHz)

–40°C

+25°C

+85°C

11846-053

–3

–2

–1

–90 –80 –70 –60 –50 –40 –30 –20 –10

RSSI E RROR (dB)

INPUT POW E R ( dBm)

–40°C

+25°C

+85°C

11846-054

–40

–35

–30

–25

–20

–15

–10

–5

–74 –68 –62 –56 –50 –44 –38 –32 –26 –20

Rx EVM (dB)

INPUT POW E R ( dBm)

–40°C

+25°C

+85°C

11846-055

–25

–20

–15

–10

–5

–72 –67 –62 –57 –52 –47 –42 –37 –32

Rx EVM (dB)

INTERFERER POWER LEVEL (dBm)

–40°C

+25°C

+85°C

11846-056

–25

–20

–15

–10

–5

–60 –55 –50 –45 –40 –35 –30 –25

Rx EVM (dB)

INTERFERER POWER LEVEL (dBm)

–40°C

+25°C

+85°C

11846-057

Rx GAI N (dB)

–40°C

+25°C

+85°C

5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0

FREQUENCY (GHz)

11846-058

Rev. C | Page 24 of 32

Data Sheet AD9364

Figure 59. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index,

f1 = 50 MHz, f2 = 101 MHz

Figure 60. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index,

f1 = 70 MHz, f2 = 71 MHz

Figure 61. Rx Local Oscillator (LO) Leakage vs. Frequency

Figure 62. Rx Emission at LNA Input, DC to 26 GHz, fLO_RX = 5.8 GHz,

WiMAX 40 MHz

Figure 63. Tx Output Power vs. Frequency, Attenuation Setting = 0 dB,

Single Tone

Figure 64. Tx Power Control Linearity Error vs. Attenuation Setting

–20

–15

–10

–5

616 26 36 46 56 66 76

II P 3 ( dBm)

Rx GAI N INDEX

–40°C

+25°C

+85°C

11846-059

20 28 36 44 52 60 68 76

II P 2 ( dBm)

Rx GAI N INDEX

–40°C

+25°C

+85°C

11846-060

–110

–108

–106

–104

–102

–100

–98

–96

–94

–92

–90

Rx LO LE AKAGE ( dBm)

5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0

FRE Q UE NCY ( GHz)

–40°C

+25°C

+85°C

11846-061

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25 30

POWER AT LNA INPUT ( dBm/ 150kHz )

FREQUENCY (GHz)

11846-062

5.0 5.1 5.2 5.3 5.4 5.5. 5.6 5.7 5.8 5.9 6.0

Tx OUTP UT POWE R ( dBm)

FREQUENCY (GHz)

–40°C

+25°C

+85°C

11846-063

–0.5

–0.4

–0.3

–0.2

–0.1

0.0

0.1

0.2

0.3

0.4

0.5

010 20 30 40 50 60 70 80 90

STEP LINE ARITY ERRO R ( dB)

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-064

Rev. C | Page 25 of 32

AD9364 Data Sheet

Figure 65. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX =

5.8 GHz, WiMAX 40 MHz Downlink (Digital Attenuation Variations Shown)

Figure 66. Tx EVM vs. Transmitter Attenuation Setting,

WiMAX 40 MHz, 64 QAM Modulation, fLO_TX = 5.495 GHz, 40 MHz REF_CLK

(Doubled Internally for RF Synthesizer)

Figure 67. Integrated Tx LO Phase Noise vs. Frequency, 40 MHz REF_CLK

(Doubled Internally for RF Synthesizer)

Figure 68. Tx Carrier Rejection vs. Frequency

Figure 69. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency

Figure 70. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency

–90

–80

–70

–60

–50

–40

–30

–20

–10

–50 –40 –30 –20 –10 010 20 30 40 50

Tx OUTP UT POWE R ( dBm/ 1M Hz )

FREQUENCY OFFSET (MHz)

ATT 0dB

ATT 3dB

ATT 6dB

11846-065

–40

–38

–36

–34

–32

–30

0246810

Tx EVM (dB)

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-066

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

INTEGRATED PHASE NOISE (°RMS)

5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0

FREQUENCY (GHz)

–40°C

+25°C

+85°C

11846-067

–70

–60

–50

–40

–30

–20

–10

Tx CARRIER AMPLITUDE ( dBc)

5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0

FREQUENCY (GHz)

ATT 0, –40°C

ATT 25, –40°C

ATT 50, –40°C

ATT 0, + 25°C

ATT 25, + 25°C

ATT 50, + 25°C

ATT 0, + 85°C

ATT 25, + 85°C

ATT 50, + 85°C

11846-068

–80

–75

–70

–65

–60

–55

–50

Tx S ECOND-ORDER HARM ONIC DISTORTI ON (dBc)

5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0

FRE Q UE NCY ( GHz)

ATT 0, –40°C

ATT 25, –40°C

ATT 50, –40°C

ATT 0, + 25°C

ATT 25, + 25°C

ATT 50, + 25°C

ATT 0, + 85°C

ATT 25, + 85°C

ATT 50, + 85°C

11846-069

–50

–45

–40

–35

–30

–25

–20

–15

–10

Tx THIRD- ORDER HARM ONIC DISTORTI ON (dBc)

5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0

FRE Q UE NCY ( GHz)

ATT 0, –40°C

ATT 25, –40°C

ATT 50, –40°C

ATT 0, + 25°C

ATT 25, + 25°C

ATT 50, + 25°C

ATT 0, + 85°C

ATT 25, + 85°C

ATT 50, + 85°C

11846-070

Rev. C | Page 26 of 32

Data Sheet AD9364

Figure 71. Tx Third-Order Output Intercept Point (OIP3) vs.

Attenuation Setting, fLO_TX = 5.8 GHz

Figure 72. Tx Signal-to-Noise Ratio (SNR) vs. Transmitter Attenuation Setting,

WiMAX 40 MHz Signal of Interest with Noise Measured at 90 MHz Offset,

fLO_TX = 5.745 GHz

Figure 73. Tx Single Sideband (SSB) Rejection vs. Frequency, 7 MHz Offset

–4

0 4 8 12 16 20

Tx OIP 3 ( dBm)

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-071

142

143

144

145

146

147

148

149

150

0 3 6 912 15

Tx S NR ( dB/Hz )

ATTENUATION SETTING (dB)

–40°C

+25°C

+85°C

11846-072

–70

–65

–60

–55

–50

–45

–40

–35

–30

Tx S I NGL E S IDEBAND AM P LITUDE ( dBc)

5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0

FRE Q UE NCY ( GHz)

ATT 0, –40°C

ATT 25, –40°C

ATT 50, –40°C

ATT 0, + 25°C

ATT 25, + 25°C

ATT 50, + 25°C

ATT 0, + 85°C

ATT 25, + 85°C

ATT 50, + 85°C

11846-073

Rev. C | Page 27 of 32

AD9364 Data Sheet

THEORY OF OPERATION

GENERAL

The AD9364 is a highly integrated radio frequency (RF)

transceiver capable of being configured for a wide range of

applications. The device integrates all RF, mixed signal, and

digital blocks necessary to provide all transceiver functions in a

single device. Programmability allows this broadband transceiver

to be adapted for use with multiple communication standards,

including frequency division duplex (FDD) and time division

duplex (TDD) systems. This programmability also allows the

device to be interfaced to various baseband processors (BBPs) using

a single 12-bit parallel data port, dual 12-bit parallel data ports,

or a 12-bit low voltage differential signaling (LVDS) interface.

The AD9364 also provides self calibration and automatic gain

control (AGC) systems to maintain a high performance level

under varying temperatures and input signal conditions. In addi-

tion, the device includes several test modes that allow system

designers to insert test tones and create internal loopback modes

that can be used by designers to debug their designs during

prototyping and optimize their radio configuration for a

specific application.

RECEIVER

The receiver section contains all blocks necessary to receive RF

signals and convert them to digital data that is usable by a BBP.

It has three inputs that can be multiplexed to the signal chain,

making the AD9364 suitable for use in multiband systems with

multiple antenna inputs. The receiver is a direct conversion

system that contains a low noise amplifier (LNA), followed by

matched in-phase (I) and quadrature (Q) amplifiers, mixers,

and band shaping filters that downconvert received signals to

baseband for digitization. External LNAs can also be interfaced

to the device, allowing designers the flexibility to customize the

receiver front end for their specific application.

Gain control is achieved by following a preprogrammed gain

index map that distributes gain among the blocks for optimal

performance at each level. This can be achieved by enabling the

internal AGC in either fast or slow mode or by using manual

gain control, allowing the BBP to make the gain adjustments as

needed. Additionally, each channel contains independent RSSI

measurement capability, dc offset tracking, and all circuitry

necessary for self calibration.

The receiver includes 12-bit, Σ-Δ ADCs and adjustable sample

rates that produce data streams from the received signals. The

digitized signals can be conditioned further by a series of

decimation filters and a fully programmable 128-tap FIR filter

with additional decimation settings. The sample rate of each

digital filter block is adjustable by changing decimation factors

to produce the desired output data rate.

TRANSMITTER

The transmitter section consists of two differential output stages

that can be multiplexed to the transmit channel. The transmit

channel provides all digital processing, mixed signal, and RF

blocks necessary to implement a direct conversion system. The

digital data received from the BBP passes through a fully

programmable 128-tap FIR filter with interpolation options. The

FIR output is sent to a series of interpolation filters that provide

additional filtering and data rate interpolation prior to reaching the

DAC. Each 12-bit DAC has an adjustable sampling rate. Both

the I and Q channels are fed to the RF block for upconversion.

When converted to baseband analog signals, the I and Q signals

are filtered to remove sampling artifacts and fed to the upcon-

version mixers. At this point, the I and Q signals are recombined

and modulated on the carrier frequency for transmission to the

output stage. The combined signal also passes through analog

filters that provide additional band shaping, and then the signal

is transmitted to the output amplifier. The transmit channel

provides a wide attenuation adjustment range with fine granularity

to help designers optimize signal-to-noise ratio (SNR).

Self calibration circuitry is built into each transmit channel to

provide automatic real-time adjustment. The transmitter block

also provides a Tx monitor block. This block monitors the

transmitter output and routes it back through the receiver

channel to the BBP for signal monitoring. The Tx monitor

block is available only in TDD mode operation while the

receiver is idle.

CLOCK INPUT OPTIONS

The AD9364 operates using a reference clock that can be provided

by two different sources. The first option is to use a dedicated

crystal with a frequency between 19 MHz and 50 MHz connected

between the XTALP and XTALN pins. The second option is to

connect an external oscillator or clock distribution device (such as

the AD9548) to the XTALN pin (with the XTALP pin remaining

unconnected). If an external oscillator is used, the frequency

can vary between 10 MHz and 80 MHz. This reference clock is

used to supply the synthesizer blocks that generate all data

clocks, sample clocks, and local oscillators inside the device.

Errors in the crystal frequency can be removed by using the

digitally programmable digitally controlled crystal oscillator

(DCXO) function to adjust an on-chip variable capacitor. This

capacitor can tune the crystal frequency variance out of the

system, resulting in a more accurate reference clock from which

all other frequency signals are generated. This function can also

be used with on-chip temperature sensing to provide oscillator

frequency temperature compensation during normal operation.

Rev. C | Page 28 of 32

Data Sheet AD9364

SYNTHESIZERS

RF PLLs

The AD9364 contains two identical synthesizers to generate the

required LO signals for the RF signal paths—one for the receiver

and one for the transmitter. Phase-locked loop (PLL) synthesizers

are fractional-N designs incorporating completely integrated

voltage controlled oscillators (VCOs) and loop filters. In TDD

mode, the synthesizers turn on and off as appropriate for the Rx

and Tx frames. In FDD mode, the Tx PLL and the Rx PLL can

be activated at the same time. These PLLs require no external

components.

BB PLL

The AD9364 also contains a baseband PLL (BB PLL)

synthesizer that is used to generate all baseband related clock

signals. These include the ADC and DAC sampling clocks, the

DATA_CLK signal (see the Digital Data Interface section), and

all data framing signals. This PLL is programmed from 700 MHz

to 1400 MHz based on the data rate and sample rate requirements

of the system.

DIGITAL DATA INTERFACE

The AD9364 data interface uses parallel data ports (P0 and P1)

to transfer data between the device and the BBP. The data ports can

be configured in either single-ended CMOS format or differential

LVDS format. Both formats can be configured in multiple arrange-

ments to match system requirements for data ordering and data

port connections. These arrangements include single port data

bus, dual port data bus, single data rate, and double data rate.

Bus transfers are controlled using simple hardware handshake

signaling. The two ports can be operated in either bidirectional

(half-duplex) mode or in full duplex mode where half the bits

are used for transmitting data and half are used for receiving data.

The interface can also be configured to use only one of the data

ports for applications that do not require high data rates and

prefer to use fewer interface pins.

DATA_CLK Signal

The AD9364 supplies the DATA_CLK signal that the BBP uses

when receiving the data. The DATA_CLK signal can be set to a

rate that provides single data rate (SDR) timing where data is

sampled on each rising clock edge, or it can be set to provide

double data rate (DDR) timing where data is captured on both

rising and falling edges. SDR or DDR timing applies to

operation using either a single port or both ports.

FB_CLK Signal

For transmit data, the interface uses the FB_CLK signal as the

timing reference. FB_CLK allows source synchronous timing

with rising edge capture for burst control signals and either

rising edge (SDR mode) or both edge capture (DDR mode) for

transmit signal bursts. The FB_CLK signal must have the same

frequency and duty cycle as DATA_CLK.

RX_FRAME Signal

The device generates an RX_FRAME output signal whenever the

receiver outputs valid data. This signal has two modes: level

mode (RX_FRAME stays high as long as the data is valid) and

pulse mode (RX_FRAME pulses with a 50% duty cycle). Similarly,

the BBP must provide a TX_FRAME signal that indicates the

beginning of a valid data transmission with a rising edge. Similar

to the RX_FRAME signal, the TX_FRAME signal can remain

high throughout the burst or it can be pulsed with a 50% duty

cycle.

ENABLE STATE MACHINE

The AD9364 transceiver includes an enable state machine (ENSM)

that allows real-time control over the current state of the device.

The device can be placed in several different states during normal

operation, including

• Wait—power save, synthesizers disabled

• Sleep—wait with all clocks/BB PLL disabled

• Tx—Tx signal chain enabled

• Rx—Rx signal chain enabled

• FDD—Tx and Rx signal chains enabled

• Alert—synthesizers enabled

The ENSM has two possible control methods: SPI control and

pin control.

SPI Control Mode

In SPI control mode, the ENSM is controlled asynchronously by

writing SPI registers to advance the current state to the next

state. SPI control is considered asynchronous to the DATA_CLK

because the SPI_CLK can be derived from a different clock

reference and can still function properly. The SPI control ENSM

method is recommended when real-time control of the

synthesizers is not necessary. SPI control can be used for real-

time control as long as the BBP has the ability to perform timed

SPI writes accurately.

Pin Control Mode

In pin control mode, the enable function of the ENABLE pin and

the TXNRX pin allow real-time control of the current state. The

ENSM allows TDD or FDD operation depending on the

configuration of the corresponding SPI register. The ENABLE

and TXNRX pin control method is recommended if the BBP

has extra control outputs that can be controlled in real time,

allowing a simple 2-wire interface to control the state of the

device. To advance the current state of the ENSM to the next

state, the enable function of the ENABLE pin can be driven by

either a pulse (edge detected internally) or a level.

When a pulse is used, it must have a minimum pulse width of

one FB_CLK cycle. In level mode, the ENABLE and TXNRX

pins are also edge detected by the AD9364 and must meet the

same minimum pulse width requirement of one FB_CLK cycle.

In FDD mode, the ENABLE and TXNRX pins can be remapped to

serve as real-time Rx and Tx data transfer control signals. In this

mode, the enable function of the ENABLE pin assumes the RXON

Rev. C | Page 29 of 32

AD9364 Data Sheet

function (controlling when the Rx path is enabled and disabled),

and the TXNRX pin assumes the TXON function (controlling

when the Tx path is enabled and disabled). In this mode, the

ENSM is removed from the system for control of all data flow

by these pins.

SPI INTERFACE

The AD9364 uses a serial peripheral interface (SPI) to communi-

cate with the BBP. The SPI can be configured as a 4-wire

interface with dedicated receive and transmit ports, or it can

be configured as a 3-wire interface with a bidirectional data

communication port. This bus allows the BBP to set all device

control parameters using a simple address data serial bus

protocol.

Write commands follow a 24-bit format. The first six bits are

used to set the bus direction and number of bytes to transfer.

The next 10 bits set the address where data is to be written.

The final eight bits are the data to be transferred to the specified

LSB-first format that allows the commands to be written in LSB

to MSB format. In this mode, the register addresses are incre-

mented for multibyte writes.

Read commands follow a similar format with the exception that

the first 16 bits are transferred on the SPI_DI pin and the final

eight bits are read from the AD9364, either on the SPI_DO pin

in 4-wire mode or on the SPI_DI pin in 3-wire mode.

CONTROL PINS

Control Outputs (CTRL_OUT7 to CTRL_OUT0)

The AD9364 provides eight simultaneous real-time output signals

for use as interrupts to the BBP. These outputs can be configured to

output a number of internal settings and measurements that the

BBP can use when monitoring transceiver performance in different

situations. The control output pointer register selects what

information is output to these pins, and the control output enable

the BBP. Signals used for manual gain mode, calibration flags,

state machine states, and the ADC output are among the outputs

that can be monitored on these pins.

Control Inputs (CTRL_IN3 to CTRL_IN0)

The AD9364 provides four edge detected control input pins. In

manual gain mode, the BBP can use these pins to change the gain

table index in real time. In transmit mode, the BBP can use two

of the pins to change the transmit gain in real time.

GPO PINS (GPO_3 TO GPO_0)

The AD9364 provides four, 3.3 V capable general-purpose logic

output pins: GPO_3, GPO_2, GPO_1, and GPO_0. These pins

can be used to control other peripheral devices such as regulators

and switches via the AD9364 SPI bus, or they can function as

slaves for the internal AD9364 state machine.

AUXILIARY CONVERTERS

AUXADC

The AD9364 contains an auxiliary ADC that can be used to mon-

itor system functions such as temperature or power output. The

converter is 12 bits wide and has an input range of 0.05 V to

VDDA1P3_BB − 0.05 V. When enabled, the ADC is free running.

SPI reads provide the last value latched at the ADC output. A

multiplexer in front of the ADC allows the user to select between

the AUXADC input pin and a built-in temperature sensor.

AUXDAC1 and AUXDAC2

The AD9364 contains two identical auxiliary DACs that can

provide power amplifier (PA) bias or other system functionality.

The auxiliary DACs are 10 bits wide, have an output voltage range

of 0.5 V to VDD_GPO − 0.3 V, a current drive of 10 mA, and

can be directly controlled by the internal enable state machine.

POWERING THE AD9364

The AD9364 must be powered by the following three supplies:

the analog supply (VDDD1P3_DIG/VDDAx = 1.3 V), the

interface supply (VDD_INTERFACE = 1.8 V), and the GPO

supply (VDD_GPO = 3.3 V).

For applications requiring optimal noise performance, it is

recommended that the 1.3 V analog supply be split and sourced

from low noise, low dropout (LDO) regulators. Figure 74 shows

the recommended method.

Figure 74. Low Noise Power Solution for the AD9364

For applications where board space is at a premium, and

optimal noise performance is not an absolute requirement, the

1.3 V analog rail can be provided directly from a switcher, and a

more integrated power management unit (PMU) approach can

be adopted. Figure 75 shows this approach.

Figure 75. Space-Optimized Power Solution for the AD9364

11846-074

3.3V

1.8V

1.3V_A

1.3V_B

ADP2164

ADP1755

11846-075

ADP1755

LDO

ADP5040

1.2A

BUCK

300mA

LDO

300mA

LDO

AD9364

1.3V VDDD1P3_DIG/VDDAx

1.8V VDD_INTERFACE

3.3V VDD_GPO

Rev. C | Page 30 of 32

Data Sheet AD9364

PACKAGING AND ORDERING INFORMATION

OUTLINE DIMENSIONS

Figure 76. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-144-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD9364BBCZ −40°C to +85°C 144-Ball CSP_BGA BC-144-7

AD9364BBCZREEL −40°C to +85°C 144-Ball CSP_BGA BC-144-7

1 Z = RoHS Compliant Part.

COM P LIANT T O JEDEC S TANDARDS M O-275- E EAB-1.

11-18-2011-A

0.80

0.60

REF

910 81112 7 56 4 23 1

BOTTOM VIEW

8.80 SQ

DETAI L A

TOP VIEW

DETAIL A

COPLANARITY

0.12

0.50

0.45

0.40

1.70 M AX

BALL DIAM E TER

SEATING

PLANE

10.10

10.00 SQ

9.90

A1 BALL

CORNER

A1 BALL

CORNER

0.32 M IN

1.00 M IN

Rev. C | Page 31 of 32

AD9364 Data Sheet

Rev. C | Page 32 of 32

NOTES

registered trademarks are the property of their respective owners.

D11846-0-7/14(C)

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

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