A416316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Document Title 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue March 06, 1998 Preliminary 0.1 Modify 40/44L TSOP type II package outline drawing and June 17, 1998 dimensions notes 0.2 Remove timing waveform of CAS -before- RAS refresh counter test cycle August 21, 1998 0.3 Final spec release September 8, 1998 0.4 Erase tCPT parameter October 23, 1998 Final Modify SOJ 40L outline dimensions Modify TSOP 40/44L (type II) outline dimensions (October, 1998, Version 0.4) AMIC Technology, Inc. A416316 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Features n Organization: 65,536 words X 16 bits n High speed - 40/50/60 ns RAS access time - 20/25/30 ns column address access time - 12/13/15 ns CAS access time n Low power consumption - Operating: 160mA (-40 max) - Standby: 3 mA (TTL) n 256 refresh cycles, 4 ms refresh interval n Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 400mil, 40-pin SOJ - 400mil, 40/44 TSOP type II package n Single 5V power supply/built-in VBB generator Pin Configuration Pin Descriptions n SOJ n TSOP Symbol 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE NC A7 A6 A5 A4 VSS (October, 1998, Version 0.4) VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 NC NC WE RAS NC A0 A1 A2 13 14 15 16 17 18 19 20 21 22 A3 VCC A416316V A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A416316S VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 44 43 42 41 40 39 38 37 36 35 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 32 31 30 29 28 27 26 25 NC LCAS UCAS OE NC A7 A6 A5 24 23 A4 VSS 1 Description A0 - A7 Address Inputs I/O0 - I/O15 Data Input/Output RAS Row Address Strobe UCAS Column Address Strobe/Upper Byte Control LCAS Column Address Strobe/Lower Byte Control WE Write Enable OE Output Enable VCC +5V Power Supply VSS Ground NC No Connection AMIC Technology, Inc. A416316 Selection Guide Symbol Description -40 -50 -60 Unit tRAC Maximum RAS Access Time 40 50 60 ns tAA Maximum Column Address Access Time 20 25 35 ns tCAC Maximum CAS Access Time 12 13 15 ns tOEA Maximum Output Enable ( OE ) Access Time 12 13 15 ns tRC Minimum Read or Write Cycle Time 75 90 110 ns tPC Minimum Fast Page Mode Cycle Time 22 31 40 ns ICC1 Maximum Operating Current 160 140 120 mA ICC6 Maximum CMOS Standby Current 2.0 2.0 2.0 mA Functional Description The A416316 is a high performance CMOS Dynamic Random Access Memory organized as 65,536 words X 16 bits. The A416316 is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. address strobe ( UCAS and LCAS ) which acts as an output enable independent of RAS . Very fast UCAS and LCAS to output access time eases system design. All inputs are TTL compatibel. Fast Page Mode operation allows random access up to 256 X 16 bits within a page, with cycle time as short as 22/31/40 ns. The A416316 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Output is tri-stated by a column (October, 1998, Version 0.4) The A416316 is best suited for graphics, digital signal processing and high performance peripherals. The A416316 is available in JEDEC standard 40-pin plastic SOJ package and 40/44 TSOP type II package. 2 AMIC Technology, Inc. A416316 REFRESH CONTROLLER Block Diagram VCC VSS Y0 - Y7 COLUMN DECODER UPPER BYTE DATA I/O BUFFER I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 LOWER BYTE DATA I/O BUFFER I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 SENSE AMP 256 X 16 A1 RAS CLOCK GENERATOR A2 A3 A4 A5 UCAS UCAS CLOCK GENERATOR LCAS LCAS CLOCK GENERATOR A6 A7 X0 - X7 ROW DECODER RAS ADDRESS BUFFERS A0 256 256 X 256 X 16 ARRAY WE CLOCK GENERATOR WE OE CLOCK GENERATOR OE SUBSTRATE BIAS GENERATOR Recommended Operating Conditions (Ta = 0C to +70C) Symbol VCC Description Supply Voltage VSS VIH Input Voltage VIL (October, 1998, Version 0.4) Min. Typ. Max. Unit 4.5 5.0 5.5 V 0.0 0.0 0.0 V 2.4 - VCC + 1 V -1.0 - 0.8 V 3 AMIC Technology, Inc. A416316 Absolute Maximum Ratings* *Comments Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . -1.0V to +7.0V Output Voltage (Vout) . . . . . . . . . . . . . . . . -1.0V to +7.0V Power Supply Voltage (VCC) . . . . . . . . . . -1.0V to +7.0V Operating Temperature (TOPR) . . . . . . . . . . 0C to +70C Storage Temperature (TSTG) . . . . . . . . . -55C to +150C Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C X 10sec Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W Short Circuit Output Current (Iout) . . . . . . . . . . . . . 50mA Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) Symbol Parameter -40 -50 -60 Unit Min. Max. Min. Max. Min. Max. Test Conditions IIL Input Leakage Current -10 +10 -10 +10 -10 +10 A 0V Vin +5.5V Pins not under Test = 0V IOL Output Leakage Current -10 +10 -10 +10 -10 +10 A DOUT disabled, 0V Vout +5.5V ICC1 Operating Power Supply Current - 160 - 140 - 120 mA RAS , UCAS , LCAS Address cycling; tRC = min. ICC2 TTL Standby Power Supply Current - 3.0 - 3.0 - 3.0 mA RAS = UCAS = LCAS =VIH ICC3 Average Power Supply Current, RAS Refresh Mode - 160 - 140 - 120 mA RAS cycling, UCAS = LCAS = VIH, tRC = min. ICC4 Fast Page Mode Average Power Supply Current - 160 - 140 - 120 mA RAS = VIL, UCAS , LCAS Address cycling; tPC = min. ICC5 CAS -before- RAS Refresh Power Supply Current - 160 - 140 - 120 mA RAS , UCAS , LCAS cycling; tRC = min. ICC6 CMOS Standby Power Supply Current - 2.0 - 2.0 - 2.0 mA RAS = UCAS = LCAS = VCC - 0.2V VOH Output Voltage 2.4 - 2.4 - 2.4 - V IOUT = -5.0mA - 0.4 - 0.4 - 0.4 V IOUT = 4.2mA VOL (October, 1998, Version 0.4) 4 Notes 1, 2 1 1, 2 1 AMIC Technology, Inc. A416316 AC Characteristics (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol -40 -50 -60 Parameter Unit Min. Max. Min. Max. Min. Max. Notes 1 tRL2RL2 tRC Random Read or Write Cycle Time 75 - 90 - 110 - ns 2 tRH2RL2 tRP RAS Precharge Time 25 - 25 - 25 - ns 3 tRL1RH1 tRAS RAS Pulse Width 40 75K 50 75K 60 75K ns 4 tCL1CH1 tCAS CAS Pulse Width 12 - 12 - 12 - ns 5 tRL1CL1 tRCD RAS to CAS Delay Time 16 30 18 37 20 45 ns 6 6 tRL1AV tRAD RAS to Column Address Delay Time 11 22 13 25 15 30 ns 7 7 tCL1RH1 tRSH(R) CAS to RAS Hold Time (Read) 12 - 12 - 12 - ns 8 tRL1CH1 tCSH RAS to CAS Hold Time 40 - 50 - 60 - ns 9 tCH2RL2 tCRP CAS to RAS Precharge Time 5 - 5 - 5 - ns 10 tAVRL2 tASR Row Address Setup Time 0 - 0 - 0 - ns 11 tRL1AX tRAH Row Address Hold Time 6 - 8 - 10 - ns tT tT Transition Time (Rise and Fall) 3 50 3 50 3 50 ns 4, 5 tRVRV tREF Refresh Period - 4 - 4 - 4 ms 3 tCL1QX tCLZ CAS to Output in Low Z 0 - 0 - 0 - ns 8 12 (October, 1998, Version 0.4) 5 AMIC Technology, Inc. A416316 Read Cycle (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol Parameter -40 -50 -60 Min. Max. Min. Max. Min. Max. Unit Notes 13 tRL1QV tRAC Access Time from RAS - 40 - 50 - 60 ns 6 14 tCL1QV tCAC Access Time from CAS - 12 - 13 - 15 ns 6, 13 15 tAVQV tAA Access Time from Address - 20 - 25 - 30 ns 7, 13 16 tRL1AZ tAR(R) Column Add Hold from RAS 30 - 40 - 45 - ns 17 tWH2CL2 tRCS Read Command Setup Time 0 - 0 - 0 - ns 18 tCH2WX tRCH Read Command Hold Time to CAS 0 - 0 - 0 - ns 9 19 tRH2WX tRRH Read Command Hold Time to RAS 0 - 0 - 0 - ns 9 20 tAVRH1 tRAL Column Address to RAS Lead Time 20 - 25 - 30 - ns 21 tCH2CL2 tCRP CAS Precharge Time 5 - 5 - 5 - ns 22 tRH2OL1 tODS Output Disable Setup Time 0 - 0 - 0 - ns 23 tCH2QZ tOFF Output Buffer Turn-Off Time 0 8 0 10 0 12 ns (October, 1998, Version 0.4) 6 8, 10 AMIC Technology, Inc. A416316 Write Cycle (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol -40 -50 -60 Parameter Unit Min. Max. Min. Max. Min. Max. Notes 24 tAVWL2 tASC Column Address Setup Time 0 - 0 - 0 - ns 25 t1CL1AX tCAH Column Address Hold Time 6 - 8 - 10 - ns 26 tRL1AX tAWR Column Address Hold Time to RAS 30 - 40 - 45 - ns 27 tWL1CL2 tWCS Write Command Setup Time 0 - 0 - 0 - ns 11 28 tCH2WH1 tWCH Write Command Hold Time 6 - 7 - 10 - ns 11 29 tRL1WH1 tWCR Write Command Hold Time to RAS 30 - 40 - 45 - ns 30 tWL1WH1 tWP Write Command Pulse Width 6 - 7 - 10 - ns 31 tWL1RH1 tRWL Write Command to RAS Lead Time 12 - 13 - 15 - ns 32 tWL1CH1 tCWL Write Command to CAS Lead Time 12 - 13 - 15 - ns 33 tDVWL2 tDS Data-in setup Time 0 - 0 - 0 - ns 12 34 tWL1DX tCL1DX tDH Data-in Hold Time 6 - 7 - 10 - ns 12 35 tRL1DX tDHR Data-in Hold Time to RAS 33 - 40 - 45 - ns Read-Modify-Wirte Cycle (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol -40 -50 -60 Parameter Unit Min. Max. Min. Max. Min. Max. Notes 36 tRL2RL2 tRWC Read-Modify-Write Cycle Time 120 - 130 - 140 - ns 37 tRL1WL2 tRWD RAS to WE Delay Time 63 - 75 - 85 - ns 11 38 tCL1WL2 tCWD CAS to WE Delay Time 30 - 33 - 38 - ns 11 39 tAVWL2 tAWD Column Address to WE Delay Time 38 - 43 - 53 - ns 11 40 tCL1RH1 tRSH(W) CAS to RAS Hold Time (Write) 12 - 12 - 12 - ns 41 tCL1CH1 tCAS(W) CAS Pulse Width (Write) 12 - 12 - 12 - ns (October, 1998, Version 0.4) 7 AMIC Technology, Inc. A416316 Fast Page Mode Cycle (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol -40 -50 -60 Parameter Min. Max. Min. Max. Min. Max. Unit Notes 42 tAVAV tWL2WL2 tPC Read-Write Cycle Time (Fast Page) 22 - 31 - 40 - ns 14 43 tCH2CQV tCPA Access Time from CAS Precharge - 25 - 30 - 35 ns 13 44 tCH2CL2 tCP CAS Precharge Time (Fast Page) 7 - 8 - 10 - ns 45 tCL2CL2 tPCM FAST PAGE Mode RMW Cycle 55 - 63 - 85 - ns 46 tCL2CH2 tCRW Page Mode CAS Pulse Width (RMW) 45 - 49 - 60 - ns 47 tRLRH1 tRASP RAS Pulse Width 40 125K 50 125K 60 125K ns Refresh Cycle (VCC = 5V 10%, VSS = 0V, Ta = 0C to +70C) # JEDEC Symbol Std Symbol -40 -50 -60 Parameter Min. Max. Min. Max. Min. Max. Unit Notes 48 tCL1RL2 tCSR CAS Setup Time ( CAS before- RAS ) 5 - 5 - 5 - ns 3 49 tRL1CH1 tCHR CAS Hold Time ( CAS before- RAS ) 10 - 10 - 10 - ns 3 50 tRH2CL2 tRPC RAS Precharge to CAS Hold Time 5 - 5 - 5 - ns 51 tOL1RH1 tROH RAS Hold Time Reference to OE 5 - 5 - 5 - ns 52 tOL1QV tOEA OE Access Time - 12 - 13 - 15 ns 53 tOH2QX tOED OE to Data Delay 8 - 10 - 13 - ns 54 tOH2QZ tOEZ Output Buffer Turn-off Delay from OE 0 8 0 10 0 13 ns 55 tWL1OL2 tOEH OE Command Hold Time 0 - 0 - 0 - ns (October, 1998, Version 0.4) 8 8 AMIC Technology, Inc. A416316 Notes: 1. ICC1, ICC3, ICC4, and ICC6 depend on cycle rate. 2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 3. An initial pause of 200s is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8ms). 4. AC Characteristics assume tT = 5ns. All AC parameters are measured with a load equivalent to two TTL loads and 100pF, VIL (min.) GND and VIH (max.) VCC. 5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC. 7. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA. 8. Assumes three state test load (5pF and a 380 Thevenin equivalent). 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output nvoltage levels. 11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (min.) and tWCH tWCH (min.), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD tRWD (min.) , tCWD tCWD (min.) and tAWD tAWD (min.), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. These parameters are referenced to UCAS and LCAS leading edge in early write cycles and to WE leading edge in read-write cycles. 13. Access time is determined by the longest of tAA or tCAC or tCAP. 14. tASC tCP to achieve tPC (min.) and tCAP (max.) values. 15. These parameters are sampled and not 100% tested. (October, 1998, Version 0.4) 9 AMIC Technology, Inc. A416316 Timing Waveform of Read Cycle tRC(1) tRAS(3) tRCD(5) tRSH(7) tRP(2) RAS tCSH(8) tCAH(25) tASC(24) tCRP(9) tRCS(17) tCAS(4) UCAS LCAS tAR(16) tRAD(6) tASR(10) Address tRAL(20) tRAH(11) Row Address Col Address tRRH(19) tRCH(18) WE tROH (51) OE tOEA(52) tOEZ(54) tRAC(13) tAA(15) tCAC(14) tCLZ(12) Data Out I/O (October, 1998, Version 0.4) tOFF(23) 10 AMIC Technology, Inc. A416316 Timing Waveform of Early Write Cycle tRC(1) tRAS(3) tRP(2) RAS tCSH(8) tRSH(40) tCRP(9) tRCD(5) tCAS(41) UCAS LCAS tAWR(26) tRAL(20) tRAD(6) tASR(10) Address tRAH(24) tCAH(25) tRAH(11) Row Address Col Address tWCR(29) tCWL(32) tRWL(31) tWP(30) tWCS(27) tWCH(28) WE OE tDHR(35) tDS(33) I/O (October, 1998, Version 0.4) tDH(34) Data In 11 AMIC Technology, Inc. A416316 Timing Waveform of Late Write Cycle tRC(1) tRAS(3) tRP(2) RAS tCSH(8) tRSH(40) tCRP(9) tRCD(5) tCAS(41) UCAS LCAS tAWR(26) tRAD(6) tASR(101) tRAH(11) tRAL(20) tASC(24) tCAH(25) Address Row Address Col Address tWCR(29) tCWL(32) tRWL(31) tWP(30) WE tOEH(55) OE tDHR(35) tEOD(53) tDS(33) tDH(34) I/O (October, 1998, Version 0.4) Data In 12 AMIC Technology, Inc. A416316 Timing Waveform of Read-Modify-Write Cycle tRWC(36) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRSH(7) tCAS(41) tRCD(5) UCAS LCAS tAR(16) tRAL(20) tRAD(6) tASR(10) Address tRAH(11) Row Address tASC(24) tASC(25) Col Address tRWD(37) tRWL(31) tAWD(39) tRCS(17) tCWD(38) tCWL(32) tWP(30) WE tOEZ(54) tOEA(52) tOED(53) OE tRAC(13) tDS(33) tAA(15) tCAC(14) tDH(34) tCLZ(12) I/O (October, 1998, Version 0.4) Data Out 13 Data In AMIC Technology, Inc. A416316 Timing Waveform of Fast Page Mode Read Cycle tRASP(47) tRP(2) RAS tCSH(8) tCRP(11) tRCD(3) tPC(42) tCAS(4) tRSH(7) tCP(44) UCAS LCAS tAR(16) tRAD(6) tASR(10) Address tRAH(11) Row Col Address Col Address tRCH(18) tRCS(17) Col Address tRCS(17) WE tOEA(52) tOEA(52) OE tRAC(13) tCAC(14) tOFF(23) tAA(15) I/O (October, 1998, Version 0.4) tCLZ(12) tCPA(43) tOEZ(54) Data Out 14 Data Out Data Out AMIC Technology, Inc. A416316 Timing Waveform of Fast Page Mode Early Write Cycle tRASP(47) tRAH(11) RAS tASC(24) tCSH(8) tPC(42) tRSH(7) tCRP(9) tRCD(5) tCAS(41) tWCS(27) tCP(44) tCAH(25) UCAS LCAS tRAL(20) tAR(16) tASR(10) Address tRAD(6) Row address Col Address Col Address Col Address tCWL(32) tWP(30) tWCH(28) tOEH(55) WE OE tDHR(35) tDS(33) I/O (October, 1998, Version 0.4) tDH(34) tOED(53) Data In Data In 15 Datat In AMIC Technology, Inc. A416316 Timing Waveform of Fast Page Mode Read-Modify-Write Cycle tRP(2) tRASP(47) RAS tPCM(45) tCSH (8) tRCD(5) tCAS UCAS (41) tRAD(6) LCAS tCAH(25) tASR(10) Address tCRP(9) tCP(44) tRAL(20) tRAH(11) tCAH(25) t CAH (25) tASC(24) Row Ad Col Ad Col Ad Col Address tRWL(31) t RWD (37) tCWD(38) tRCS (17) t CWD(38) tCWD(38) tCWL(32) tWP(30) t AWD (39) tAWD(39) WE tOEA(52) tOEZ(54) tOED(53) tOEA(52) OE tAA(15) tDH(34) tDS(33) tCLZ(12) ttRAC(13) tCLZ(12) tCAC(14) I/O tCLZ(12) tCAC(14) tDS(33) Data In Data In Data Out (October, 1998, Version 0.4) tCAP(43) Data Out 16 Data In Data Out AMIC Technology, Inc. A416316 Timing Waveform of RAS Only Refresh Cycle tRC(1) tRAS(3) tRP(2) RAS tCRP(9) UCAS LCAS tASR(10) Address tRAH(11) Row Address Timing Waveform of CAS -before- RAS Refresh Cycle tRC(1) tRP(2) tRAS(3) RAS tRPC(50) tCSR(48) tCHR(49) UCAS LCAS tOFF(23) I/O (October, 1998, Version 0.4) 17 AMIC Technology, Inc. A416316 Timing Waveform of Hidden Refresh Cycle (Read) tRC(1) tRC(1) tRAS(3) tRP(2) tRAS(3) tRP(2) RAS tCHR(49) tCPR(9) tRCD(5) tRSH(7) tCRP(9) UCAS LCAS tAR(16) tRAD(6) tRAH(11) tASR(10) Address tASC(24) Row Col Address tRCS(17) tRRH(19) WE OE tRAC(13) tOFF(23) tAA(15) tCAC(14) tOEZ(54) tCLZ(12) Data Out I/O (October, 1998, Version 0.4) 18 AMIC Technology, Inc. A416316 Timing Waveform of Hidden Refresh Cycle (Write) tRC(1) tRAS(3) tRP(2) RAS tCRP(9) tRCD(5) tRSH(40) UCAS LCAS tAR(16) tRAD(6) tRAH(11) tASC(24) tASR(10) Address tRAL(20) tCAH(25) Col Address Row Address tRWL(31) tWCR(29) tWP(30) tWCS(27) tWCH(28) WE tDS(33) tDH(34) tDHR(35) I/O Data In OE (October, 1998, Version 0.4) 19 AMIC Technology, Inc. A416316 Capacitance15 (f = 1MHz, Ta = Room Temperature, VCC = 5V 10%) Symbol Signals CIN1 A0 - A7 CIN2 RAS , UCAS , Parameter Max. Unit Test Conditions 5 pF Vin = 0V Input Capacitance 7 pF Vin = 0V I/O Capacitance 7 pF Vin = Vout = 0V LCAS , WE , OE CI/O I/O1 - I/O16 Ordering Codes Package\ RAS Access Time 40ns 50ns 60ns 40L SOJ (400 mil) A416316S-40 A416316S-50 A416316S-60 40/44L TSOP type II (400mil) A416316V-40 A416316V-50 A416316V-60 (October, 1998, Version 0.4) 20 AMIC Technology, Inc. A416316 Package Information SOJ 40L Outline Dimensions 21 1 20 E 40 HE unit: inches/mm L A A2 C D b b1 A1 e D S Seating Plane Symbol e1 y Dimensions in inches Min Nom Max Dimensions in mm Min Nom Max 3.66 A - - 0.144 - - A1 0.025 - - 0.64 - - A2 0.105 0.110 0.115 2.67 2.79 2.92 b1 0.026 0.028 0.032 0.66 0.71 0.81 b 0.016 0.018 0.022 0.41 0.46 0.56 C 0.008 0.010 0.014 0.20 0.25 0.36 D 1.020 1.025 1.030 25.91 26.04 26.16 E 0.395 0.400 0.405 10.03 10.16 10.29 e 0.044 0.050 0.056 1.12 1.27 1.42 e1 0.355 0.366 0.376 9.114 9.383 9.652 HE 0.430 0.440 0.450 10.92 11.18 11.43 L 0.081 0.093 0.105 2.083 2.39 2.70 S - - 0.050 - - 1.27 y - - 0.004 - - 0.10 0 - 10 0 - 10 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (October, 1998, Version 0.4) 21 AMIC Technology, Inc. A416316 Package Information TSOP 40/44L (Type II) Outline Dimensions unit: inches/mm HE E 44 L L1 1 B e D S A A1 A2 c D y L Dimensions in inches L1 Dimensions in mm Symbol Min Nom Max Min Nom Max A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 0.039 0.041 0.95 1.00 1.05 B 0.013 0.015 0.017 0.32 0.37 0.42 c 0.003 0.005 0.009 0.08 0.13 0.23 D 0.720 0.725 0.730 18.28 18.41 18.54 E 0.395 0.400 0.405 10.03 10.16 10.29 e 0.031 BSC 0.80 BSC HE 0.455 0.463 0.471 11.56 11.76 11.96 0.60 L 0.016 0.020 0.024 0.40 0.50 L1 - 0.031 - - 0.80 - S - - 0.035 - - 0.90 y - - 0.004 - - 0.10 1 3 5 1 3 5 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (October, 1998, Version 0.4) 22 AMIC Technology, Inc.