Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 LMV71x-N Low-Power, RRIO Operational Amplifiers With High Output Current Drive and Shutdown Option 1 Features 3 Description * * * * * * * The LMV710-N, LMV711-N, and LMV715-N are BiCMOS operational amplifiers with a CMOS input stage. These devices have greater than RR input common mode voltage range, rail-to-rail output and high output current drive. They offer a bandwidth of 5 MHz and a slew rate of 5 V/s. 1 * * * * Low Offset Voltage: 3 mV (Maximum) Gain-Bandwidth Product: 5 MHz (Typical) Slew Rate: 5 V/s (Typical) Space-Saving Packages: 5-Pin and 6-Pin SOT-23 Turnon Time From Shutdown: <10 s Industrial Temperature Range: -40C to 85C Supply Current in Shutdown Mode: 0.2 A (Typical) Ensured 2.7-V and 5-V Performance Unity Gain Stable Rail-to-Rail Input and Output Capable of Driving 600- Load On the LMV711 and LMV715, a separate shutdown pin can be used to disable the device and reduces the supply current to 0.2 A (typical). They also feature a turnon time of less than 10 s. It is an ideal solution for power-sensitive applications, such as cellular phone, pager, palm computer, and so forth. In addition, once the LMV715 is in shutdown the output is tri-stated. The LMV710 is offered in the space-saving, 5-pin SOT-23 package. The LMV711 and LMV715 are offered in the space saving 6-pin SOT-23 package. 2 Applications * * * * * * * Wireless Phones GSM, TDMA, and CDMA Power Amp Controls AGC and RF Power Detectors Temperature Compensation Wireless LAN Bluetooth HomeRF The LMV71x-N devices are designed to meet the demands of low power, low cost, and small size required by cellular phones and similar batterypowered portable electronics. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMV710-N SOT-23 (5) 2.92 mm x 1.50 mm LMV711-N LMV715-N SOT-23 (6) 2.92 mm x 1.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic - LMV711 V+ Ip VBIAS IN- IN+ Class AB Control IN VBIAS OUT (LMV711 ONLY) V- SD Bias Control Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 4 5 6 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information ................................................. Electrical Characteristics - 2.7 V .............................. Electrical Characteristics - 3.2 V .............................. Electrical Characteristics - 5 V ................................. Typical Characteristics .............................................. Detailed Description ............................................ 14 7.1 Overview ................................................................ 14 7.2 Functional Block Diagram ....................................... 14 7.3 Feature Description ................................................ 14 7.4 Device Functional Modes ....................................... 16 8 Application and Implementation ........................ 19 8.1 Application Information............................................ 19 8.2 Typical Applications ................................................ 19 9 Power Supply Recommendations...................... 22 10 Layout................................................................... 22 10.1 Layout Guidelines ................................................ 22 10.2 Layout Example ................................................... 22 11 Device and Documentation Support ................. 23 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Device Support .................................................... Documentation Support ....................................... Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 23 23 24 24 12 Mechanical, Packaging, and Orderable Information ........................................................... 24 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision J (March 2013) to Revision K * 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N LMV710-N, LMV711-N, LMV715-N www.ti.com SNOS519K - APRIL 2000 - REVISED AUGUST 2016 5 Pin Configuration and Functions LMV710 DBV Package 5-Pin SOT-23 Top View LMV711, LMV715 DBV Package 6-Pin SOT-23 Top View Pin Functions PIN NAME TYPE (1) DESCRIPTION DBV (5) DBV (6) +IN 3 3 I Noninverting input -IN 4 4 I Inverting input Output 1 1 O Output Shutdown -- 5 I Active low enable input V+ 5 6 P Positive supply input V- 2 2 P Supply negative input (1) I = Input, O = Output, P = Power Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N Submit Documentation Feedback 3 LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN Differential input voltage MAX UNIT Supply voltage (V-) - 0.4 (V+) + 0.4 V 5.5 V Current at input pin 10 mA Mounting temperature, infrared or convection (20 sec) 235 C 150 C 150 C Voltage at input or output pin + - Supply voltage (V - V ) Output short circuit to V+ See (3) Output short circuit to V- See (4) Junction temperature, TJ(MAX) (5) Storage temperature, Tstg (1) (2) (3) (4) (5) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Shorting circuit output to V+ will adversely affect reliability. Shorting circuit output to V- will adversely affect reliability. The maximum power dissipation is a function of TJ(MAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - T A) / RJA. All numbers apply for packages soldered directly into a PCB. 6.2 ESD Ratings VALUE V(ESD) (1) (2) (3) Electrostatic discharge Human-body model (HBM) (1) (2) 2000 Machine model (MM) (3) 100 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Human-body model, 1.5 k in series with 100 pF. Machine model, 0 in series with 100 pF. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX Supply voltage 2.7 5 UNIT V Temperature -40 85 C 6.4 Thermal Information THERMAL METRIC (1) LMV710-N LMV711-N LMV715-N DBV (SOT-23) DBV (SOT-23) DBV (SOT-23) 5 PINS 6 PINS 6 PINS 265 265 265 C/W UNIT RJA Junction-to-ambient thermal resistance RJC(top) Junction-to-case (top) thermal resistance 131.6 139 156.6 C/W RJB Junction-to-board thermal resistance 35.1 38.5 32.8 C/W JT Junction-to-top characterization parameter 22.2 28.6 34 C/W JB Junction-to-board characterization parameter 34.5 37.9 32.2 C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- -- -- C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N LMV710-N, LMV711-N, LMV715-N www.ti.com SNOS519K - APRIL 2000 - REVISED AUGUST 2016 6.5 Electrical Characteristics - 2.7 V TJ = 25C, V+ = 2.7 V, V- = 0 V, VCM = 1.35 V, and RL > 1 M (unless otherwise noted) PARAMETER VOS Input offset voltage IB Input bias current CMRR PSRR Common-mode rejection ratio Power supply rejection ratio Input common-mode voltage range VCM TEST CONDITIONS VCM = 0.85 V and VCM = 1.85 V TYP (2) 0.4 TJ = -40C to 85C MAX (1) 3 3.2 4 50 TJ = -40C to 85C 45 2.7 V V+ 5 V, VCM = 0.85 V TJ = 25C 70 TJ = -40C to 85C 68 2.7 V V+ 5 V, VCM = 1.85 V TJ = 25C 70 0 V VCM 2.7 V For CMRR 50 dB Output short-circuit current Sinking, VO = 2.7 V VO TJ = 25C TJ = 25C Sourcing, VO = 0 V ISC MIN (1) TJ = -40C to 85C V- 15 TJ = -40C to 85C 12 TJ = 25C 25 RL = 10 k to 1.35 V VID = 100 mV RL = 10 k to 1.35 V VID = -100 mV TJ = 25C RL = 600 to 1.35 V VID = 100 mV TJ = 25C RL = 600 to 1.35 V VID = -100 mV TJ = 25C Output swing TJ = -40C to 85C dB 110 dB 95 -0.3 2.9 V 28 mA 40 22 2.62 2.68 2.6 0.01 TJ = -40C to 85C TJ = -40C to 85C pA 75 3 TJ = 25C TJ = 25C mV 68 -0.2 V+ TJ = -40C to 85C UNIT 0.12 0.15 2.52 2.55 V 2.5 0.05 TJ = -40C to 85C 0.23 0.3 VO(SD) Output voltage level in shutdown mode LMV711 only 50 IO(SD) Output leakage current in shutdown mode LMV715 only 1 pA CO(SD) Output capacitance in shutdown mode LMV715 only 32 pF IS Supply current ON mode TJ = 25C 1.22 TJ = -40C to 85C SR Slew rate (3) GBWP Gain-bandwidth product m Phase margin TON Turnon time from shutdown (1) (2) (3) 0.002 Sourcing, RL = 10 k, VO = 1.35 V to 2.3 V TJ = 25C 80 TJ = -40C to 85C 76 Sinking, RL = 10 k, VO = 0.4 V to 1.35 V TJ = 25C 80 TJ = -40C to 85C 76 Sourcing, RL = 600 , VO = 1.35 V to 2.2 V TJ = 25C 80 TJ = -40C to 85C 76 Sinking, RL = 600 , VO = 0.5 V to 1.35 V TJ = 25C 80 TJ = -40C to 85C 76 Large signal voltage 1.7 1.9 Shutdown mode, VSD = 0 V AV 200 10 mV mA A 115 113 110 dB 100 5 V/s 5 MHz 60 <10 s All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Number specified is the slower of the positive and negative slew rates. Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N Submit Documentation Feedback 5 LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 www.ti.com Electrical Characteristics - 2.7 V (continued) TJ = 25C, V+ = 2.7 V, V- = 0 V, VCM = 1.35 V, and RL > 1 M (unless otherwise noted) PARAMETER TEST CONDITIONS VSD Shutdown pin voltage range en Input-referred voltage noise ON mode Shutdown mode MIN (1) TYP (2) MAX (1) 2.4 1.5 2.7 0 1 0.8 f = 1 kHz 20 UNIT V nV/Hz 6.6 Electrical Characteristics - 3.2 V TJ = 25C, V+ = 3.2 V, V- = 0 V, and VCM = 1.6 V (unless otherwise noted) PARAMETER IO = 6.5 mA VO MIN (1) TYP (2) TJ = 25C 2.95 3 TJ = -40C to 85C 2.92 TEST CONDITIONS Output Swing TJ = 25C 0.01 TJ = -40C to 85C (1) (2) MAX (1) 0.18 UNIT V 0.25 All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. 6.7 Electrical Characteristics - 5 V TJ = 25C, V+ = 5 V, V- = 0 V, VCM = 2.5 V, and RL > 1 M (unless otherwise noted) PARAMETER VOS Input offset voltage IB Input bias current CMRR PSRR Common-mode rejection ratio Power supply rejection ratio Input common-mode voltage range VCM TEST CONDITIONS VCM = 0.85 V and VCM = 1.85 V 0.4 3 TJ = 25C TJ = -40C to 85C 3.2 4 50 TJ = -40C to 85C 48 2.7 V V+ 5 V, VCM = 0.85 V TJ = 25C 70 TJ = -40C to 85C 68 2.7 V V+ 5 V, VCM = 1.85 V TJ = 25C 70 0 V VCM 5 V For CMRR 50 dB Output short-circuit current Sinking, VO = 5 V VO MAX (1) TJ = 25C Sourcing, VO = 0 V ISC MIN (1) TYP (2) TJ = -40C to 85C V- TJ = 25C 25 TJ = -40C to 85C 21 TJ = 25C 25 TJ = 25C RL = 10 k to 2.5 V VID = -100 mV TJ = 25C RL = 600 to 2.5 V VID = 100 mV TJ = 25C RL = 600 to 2.5 V VID = -100 mV TJ = 25C Output swing 110 -0.3 V mA 40 4.98 4.9 TJ = -40C to 85C 0.12 0.15 4.82 4.85 V 4.8 0.05 TJ = -40C to 85C 0.23 0.3 VO(SD) LMV711 only 50 IO(SD) Output leakage current in shutdown mode LMV715 only 1 6 5.2 35 Output voltage level in shutdown mode (1) (2) dB 95 0.01 TJ = -40C to 85C dB 21 4.92 TJ = -40C to 85C pA 70 5.3 TJ = -40C to 85C mV 68 -0.2 V+ RL = 10 k to 2.5 V VID = 100 mV UNIT 200 mV pA All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N LMV710-N, LMV711-N, LMV715-N www.ti.com SNOS519K - APRIL 2000 - REVISED AUGUST 2016 Electrical Characteristics - 5 V (continued) TJ = 25C, V+ = 5 V, V- = 0 V, VCM = 2.5 V, and RL > 1 M (unless otherwise noted) PARAMETER CO(SD) Output capacitance in shutdown mode IS Supply current TEST CONDITIONS MIN (1) TYP (2) LMV715 only ON mode TJ = 25C 1.17 TJ = -40C to 85C SR Slew rate (3) GBWP Gain-bandwidth product m Phase margin TON Turnon time from shutdown VSD Shutdown pin voltage range en Input-referred voltage noise (3) 0.2 Sourcing, RL = 10 k, VO = 2.5 V to 4.6 V 80 TJ = -40C to 85C 76 Sinking, RL = 10 k, VO = 0.4 V to 2.5 V TJ = 25C 80 TJ = -40C to 85C 76 Sourcing, RL = 600 , VO = 2.5 V to 4.5 V TJ = 25C 80 TJ = -40C to 85C 76 Sinking, RL = 600 , VO = 0.5 V to 2.5 V TJ = 25C 80 TJ = -40C to 85C 76 ON mode Shutdown mode f = 1 kHz pF 1.7 mA 1.9 TJ = 25C Large signal voltage gain UNIT 32 Shutdown mode AV MAX (1) 10 A 123 120 dB 110 118 5 V/s 5 MHz 60 <10 s 2.4 2 5 0 1.5 0.8 20 V nV/Hz Number specified is the slower of the positive and negative slew rates. Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N Submit Documentation Feedback 7 LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 www.ti.com 6.8 Typical Characteristics VS = 5 V, single supply, TA = 25C (unless otherwise noted) 8 Figure 1. Supply Current vs Supply Voltage (ON Mode) Figure 2. LMV711, LMV715 Supply Current vs Supply Voltage (Shutdown Mode) Figure 3. Output Positive Swing vs Supply Voltage Figure 4. Output Negative Swing vs Supply Voltage Figure 5. Output Positive Swing vs Supply Voltage Figure 6. Output Negative Swing vs Supply Voltage Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N LMV710-N, LMV711-N, LMV715-N www.ti.com SNOS519K - APRIL 2000 - REVISED AUGUST 2016 Typical Characteristics (continued) VS = 5 V, single supply, TA = 25C (unless otherwise noted) Figure 7. Output Positive Swing vs Supply Voltage Figure 8. Output Negative Swing vs Supply Voltage Figure 9. Input Voltage Noise vs Frequency Figure 10. PSRR vs Frequency Figure 11. CMRR vs Frequency Figure 12. LMV711 and LMV715 Turnon Characteristics Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N Submit Documentation Feedback 9 LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 www.ti.com Typical Characteristics (continued) VS = 5 V, single supply, TA = 25C (unless otherwise noted) 10 Figure 13. Sourcing Current vs Output Voltage Figure 14. Sinking Current vs Output Voltage Figure 15. Thd+N vs Frequency (VS = 5 V) Figure 16. Thd+N vs Frequency (VS = 2.7 V) Figure 17. Thd+N vs VOUT Figure 18. Thd+N vs VOUT Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N LMV710-N, LMV711-N, LMV715-N www.ti.com SNOS519K - APRIL 2000 - REVISED AUGUST 2016 Typical Characteristics (continued) VS = 5 V, single supply, TA = 25C (unless otherwise noted) Figure 19. CCM vs VCM Figure 20. CCM vs VCM Figure 21. CDIFF vs VCM (VS = 2.7 V) Figure 22. CDIFF vs VCM (VS = 5 V) Figure 23. Open-Loop Frequency Response Figure 24. Open-Loop Frequency Response Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N Submit Documentation Feedback 11 LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 www.ti.com Typical Characteristics (continued) VS = 5 V, single supply, TA = 25C (unless otherwise noted) 12 Figure 25. Open-Loop Frequency Response Figure 26. Open-Loop Frequency Response Figure 27. Open-Loop Frequency Response Figure 28. Open-Loop Frequency Response Figure 29. Noninverting Large Signal Pulse Response Figure 30. Noninverting Small Signal Pulse Response Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N LMV710-N, LMV711-N, LMV715-N www.ti.com SNOS519K - APRIL 2000 - REVISED AUGUST 2016 Typical Characteristics (continued) VS = 5 V, single supply, TA = 25C (unless otherwise noted) Figure 31. Inverting Large-Signal Pulse Response Figure 32. Inverting Small-Signal Pulse Response Figure 33. VOS vs VCM Figure 34. VOS vs VCM Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N Submit Documentation Feedback 13 LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 www.ti.com 7 Detailed Description 7.1 Overview The LMV710-N, LMV711-N, and LMV715-N operational amplifiers provide a CMOS input stage, high current drive rail-to-rail output, and a greater than RR input common mode voltage range. They also provide a slew rate of 5 V/s at a bandwidth of 5 MHz. 7.2 Functional Block Diagram V+ Ip VBIAS IN- IN+ Class AB Control IN OUT VBIAS (LMV711 ONLY) V- SD Bias Control Copyright (c) 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Supply Bypassing The application circuits in this datasheet do not show the power supply connections and the associated bypass capacitors for simplification. When the circuits are built, it is always required to have bypass capacitors. Ceramic disc capacitors (0.1 F) or solid tantalum (1 F) with short leads, and located close to the IC are usually necessary to prevent interstage coupling through the power supply internal impedance. Inadequate bypassing will manifest itself by a low frequency oscillation or by high frequency instabilities. Sometimes, a 10-F (or larger) capacitor is used to absorb low frequency variations and a smaller 0.1-F disc is paralleled across it to prevent any high frequency feedback through the power supply lines. 7.3.2 Shutdown Mode The LMV711 and LMV715 have a shutdown pin. To conserve battery life in portable applications, they can be disabled when the shutdown pin voltage is pulled low. For LMV711 during shutdown mode, the output stays at about 50 mV from the lower rail, and the current drawn from the power supply is 0.2 A (typical). This makes the LMV711 an ideal solution for power sensitive applications. For the LMV715 during shutdown mode, the output is tri-stated. The shutdown pin must never be left unconnected. In applications where shutdown operation is not required and the LMV711 or LMV715 is used, the shutdown pin must be connected to V+. Leaving the shutdown pin floating results in an undefined operation mode and the device may oscillate between shutdown and active modes. 14 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N LMV710-N, LMV711-N, LMV715-N www.ti.com SNOS519K - APRIL 2000 - REVISED AUGUST 2016 Feature Description (continued) 7.3.3 Rail-to-Rail Input The rail-to-rail input is achieved by using paralleled PMOS and NMOS differential input stages (see Functional Block Diagram). When the common mode input voltage changes from ground to the positive rail, the input stage goes through three modes. First, the NMOS pair is cutoff and the PMOS pair is active. At around 1.4 V, both PMOS and NMOS pairs operate, and finally the PMOS pair is cutoff and NMOS pair is active. Because both input stages have their own offset voltage (VOS), the offset of the amplifier becomes a function of the commonmode input voltage (see Figure 33 and Figure 34 in Typical Characteristics). As shown in the curve, the VOS has a crossover point at 1.4 V above V-. Proper design must be done in both DC- and AC-coupled applications to avoid problems. For large input signals that include the VOS crossover point in their dynamic range, it causes distortion in the output signal. One way to avoid such distortion is to keep the signal away from the crossover point. For example, in a unity-gain buffer configuration and with VS = 5 V, a 3-V peak-to-peak signal center at 2.5 V contains input-crossover distortion. To avoid this, the input signal must be centered at 3.5 V instead. Another way to avoid large signal distortion is to use a gain of -1 circuit which avoids any voltage excursions at the input terminals of the amplifier (see Figure 35). In this circuit, the common-mode DC voltage (VCM) can be set at a level away from the VOS crossover point. Figure 35. Inverting Configuration When the input is a small signal and this small signal falls inside the VOS transition range, the gain, CMRR and some other parameters is degraded. To resolve this problem, the small signal must be placed such that it avoids the VOS crossover point. To achieve maximum output swing, the output must be biased at mid-supply. This is normally done by biasing the input at mid-supply. But with supply voltage range from 2 V to 3.4 V, the input of the op amp must not be biased at mid-supply because of the transition of the VOS. Figure 36 shows an example of how to get away from the VOS crossover point and maintain a maximum swing with a 2.7-V supply. Figure 37 shows the waveforms of VIN and VOUT. Figure 36. Vout biasing Example Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N Submit Documentation Feedback 15 LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 www.ti.com Feature Description (continued) Figure 37. Vout biasing Output Results The inputs can be driven 300 mV beyond the supply rails without causing phase reversal at the output. However, the inputs must not be allowed to exceed the maximum ratings. 7.4 Device Functional Modes 7.4.1 Compensation of Input Capacitance In the application (Figure 38) where a large feedback resistor is used, the feedback resistor can react with the input capacitance of the op amp and introduce an additional pole to the close loop frequency response. Figure 38. Cancelling the Effect of Input Capacitance 16 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N LMV710-N, LMV711-N, LMV715-N www.ti.com SNOS519K - APRIL 2000 - REVISED AUGUST 2016 Device Functional Modes (continued) This pole occurs at frequency fp with Equation 1. fP = 1 2p(RIN P RF )CIN (1) Any stray capacitance due to external circuit board layout, any source capacitance from transducer or photodiode connected to the summing node is added to the input capacitance. If fp is less than or close to the unity-gain bandwidth (5 MHz) of the op amp, the phase margin of the loop is reduced and can cause the system to be unstable. To avoid this problem, make sure that fp occurs at least 2 octaves beyond the expected -3 dB frequency corner of the close loop frequency response. If not, a feedback capacitor CF can be placed in parallel with RF such that Equation 2. 1 1 = 2pRFCF 2p(RIN P RF ) (CF + CIN ) (2) The paralleled RF and CF introduce a zero, which cancels the effect from the pole. 7.4.2 Capacitive Load Tolerance The LMV71x-N can directly drive 200 pF in unity-gain without oscillation. The unity-gain follower is the most sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase margin of amplifiers. The combination of the amplifier's output impedance and the capacitive load induces phase lag. This results in either an underdamped pulse response or oscillation. To drive a heavier capacitive load, circuit in Figure 39 can be used. Figure 39. Indirectly Driving a Capacitive Load Using Resistive Isolation In Figure 39, the isolation resistor RISO and the load capacitor CL form a pole to increase stability by adding more phase margin to the overall system. The desired performance depends on the value of RISO. The bigger the RISO resistor value, the more stable VOUT is. But the DC accuracy is not great when the RISO gets bigger. If there were a load resistor in Figure 39, the output would be voltage divided by RISO and the load resistor. The circuit in Figure 40 is an improvement to the one in Figure 39 because it provides DC accuracy as well as AC stability. In this circuit, RF provides the DC accuracy by using feed-forward techniques to connect VIN to RL. CF and RISO serve to counteract the loss of phase margin by feeding the high-frequency component of the output signal back to the inverting input of the amplifier, thereby preserving phase margin in the overall feedback loop. Increased capacitive drive is possible by increasing the value of CF . This in turn slows down the pulse response. Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N Submit Documentation Feedback 17 LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 www.ti.com Device Functional Modes (continued) Figure 40. Indirectly Driving a Capacitive a Load With DC Accuracy 18 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N LMV710-N, LMV711-N, LMV715-N www.ti.com SNOS519K - APRIL 2000 - REVISED AUGUST 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMV71x family of amplifiers features low voltage, low power, and rail-to-rail output operational amplifiers designed for low-voltage portable applications. 8.2 Typical Applications 8.2.1 High-Side Current-Sensing V + + R1 2 kY RSENSE 0.2 Q1 2N3906 R2 + 2 kY VOUT Load R3 10 kY ICHARGE VOUT RSENSE x R3 x ICh arg e 1 : x ICh arg e R1 Copyright (c) 2016, Texas Instruments Incorporated Figure 41. High-Side, Current-Sensing Schematic 8.2.1.1 Design Requirements The high-side, current-sensing circuit (Figure 41) is commonly used in a battery charger to monitor charging current to prevent over charging. A sense resistor RSENSE is connected to the battery directly. This system requires an op amp with rail-to-rail input. The LMV71x are ideal for this application because its common-mode input range goes up to the rail. 8.2.1.2 Detailed Design Procedure As seen in (Figure 41), the ICHARGE current flowing through sense resistor RSENSE develops a voltage drop equal to VSENSE. The voltage at the negative sense point is now less than the positive sense point by an amount proportional to the VSENSE voltage. The low-bias currents of the LMV71x cause little voltage drop through R2, so the negative input of the LMV71x amplifier is at essentially the same potential as the negative sense input. The LMV71x detects this voltage error between its inputs and servo the transistor base to conduct more current through Q1, increasing the voltage drop across R1 until the LMV71x inverting input matches the noninverting input. At this point, the voltage drop across R1 now matches VSENSE. IG, a current proportional to ICHARGE, flows according to Equation 3. Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N Submit Documentation Feedback 19 LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 www.ti.com Typical Applications (continued) IG = VRSENSE / R1 = ( RSENSE x ICHARGE ) / R1 (3) IG also flows through the gain resistor R3 developing a voltage drop equal to Equation 4. V3 = IG x R3 = ( VRSENSE / R1 ) x R3 = ( ( RSENSE x ICHARGE ) / R2 ) x R3 VOUT = (RSENSE x ICHARGE ) x G (4) where * G = R3 / R1 (5) The other channel of the LMV71x may be used to buffer the voltage across R3 to drive the following stages. 8.2.1.3 Application Curve 5 VOUT (V) VOUT (V) 4 3 2 1 1 2 3 4 5 ILOAD (A) C003 Figure 42. High-Side Current-Sensing Results 8.2.2 Peak Detector R4 10 k R2 V+ 10 k V+ - R1 VIN D1 R3 LMV71x (A1) + LMV71x (A2) VO + 1N914A R5 C1 10 k 10 k Reset 2N2945 Copyright (c) 2016, Texas Instruments Incorporated Figure 43. Peak Detector 8.2.2.1 Design Requirements A peak detector outputs a DC voltage equal to the peak value of the applied AC signal. Peak detectors are used in many applications, such as test equipment, measurement instrumentation, ultrasonic alarm systems, and so forth. Figure 43 shows the schematic diagram of a peak detector using LMV71x-N. This peak detector basically consists of a clipper, a parallel RC network, and a voltage follower. 20 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N LMV710-N, LMV711-N, LMV715-N www.ti.com SNOS519K - APRIL 2000 - REVISED AUGUST 2016 Typical Applications (continued) 8.2.2.2 Detailed Design Procedure An AC voltage source applied to VIN charges capacitor C1 to the peak of the input. Diode D1 conducts positive half cycles, charging C1 to the waveform peak. Including D1 inside the feedback loop of the amplifier removes the voltage drop of D1 and allows an accurate peak detection of VIN on C1. When the input waveform falls below the DC peak stored on C1, D1 is reverse biased. The low input bias current of A1 and the reverse biasing of D1 limits current leakage from C1. As a result, C1 retains the peak value even as the waveform drops to zero. A2 further isolates the peak value on C1 while completing the peak detector circuit by operating as a voltage follower and reporting the peak voltage of C1 at its output. R5 and C1 are properly selected so that the capacitor is charged rapidly to VIN. During the holding period, the capacitor slowly discharge through C1, through leakage of the capacitor and the reverse-biased diode, or op amp bias currents. In any cases the discharging time constant is much larger than the charge time constant. And the capacitor can hold its voltage long enough to minimize the output ripple. Resistors R2 and R3 limit the current into the inverting input of A1 and the noninverting input of A2 when power is disconnected from the circuit. The discharging current from C1 during power off may damage the input circuitry of the op amps. The peak detector is reset by applying a positive pulse to the reset transistor. The charge on the capacitor is dumped into ground, and the detector is ready for another cycle. The maximum input voltage to this detector must be less than (V+ - VD), where VD is the forward voltage drop of the diode. Otherwise, the input voltage must be scaled down before applying to the circuit. 8.2.3 GSM Power Amplifier Control Loop GSM ANTENNA U1 U2 GSM PA C2 RF Signal Input Output Directional Coupler IN OUT C3 Coupled VPC VCC R2 R1 VCC R3 C4 Load R5 BIAS Schottky Diode Detector V+ OUT SD + V- U3 RLOAD C5 R4 Shut Down Ramp Up/Down Copyright (c) 2016, Texas Instruments Incorporated Figure 44. GSM P.A. Control Loop 8.2.3.1 Design Requirements The control loop in Figure 44 controls the output power level of a GSM mobile phones. The control loop is used to avoid intermodulation of Base Station receivers, to prevent intermodulation with other mobile phones, and to minimize power consumption depending on the distance between mobile and base station Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N Submit Documentation Feedback 21 LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 www.ti.com Typical Applications (continued) 8.2.3.2 Detailed Design Procedure There are four critical sections in the GSM Power Amplifier Control Loop. The class-C RF power amplifier provides amplification of the RF signal. A directional coupler couples small amount of RF energy from the output of the RF P. A. to an envelope detector diode. The detector diode senses the signal level and rectifies it to a DC level to indicate the signal strength at the antenna. An op amp is used as an error amplifier to process the diode voltage and ramping voltage. This loop control the power amplifier gain through the op amp and forces the detector diode voltage and ramping voltage to be equal. Power control is accomplished by changing the ramping voltage. The LMV71x-N are well suited as an error amplifier in this application. The LMV711 or LMV715 have an extra shutdown pin to switch the op amp to shutdown mode. In shutdown mode, the LMV711 or LMV715 consume very low current. The LMV711 provides a ground voltage to the power amplifier control pin VPC. Therefore, the power amplifier can be turned off to save battery life. The LMV715 output is tri-stated when in shutdown. 9 Power Supply Recommendations For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI recommends that 10-nF capacitors be placed as close as possible to the power supply pins of the operational amplifier. For single supply, place a capacitor between V+ and V- supply leads. For dual supplies, place one capacitor between V+ and ground, and one capacitor between V- and ground. 10 Layout 10.1 Layout Guidelines To properly bypass the power supply, several locations on a printed-circuit board must be considered. A 6.8-F or greater tantalum capacitor must be placed at the point where the power supply for the amplifier is introduced onto the board. Another 0.1-F ceramic capacitor must be placed as close as possible to the power supply pin of the amplifier. If the amplifier is operated in a single power supply, only the V+ pin requires a bypass with a 0.1-F capacitor. If the amplifier is operated in a dual power supply, both V+ and V- pins must be bypassed. It is good practice to use a ground plane on a printed-circuit board to provide all components with a low inductive ground connection. 10.2 Layout Example Rf Cf V+ Cbyp GND OUTPUT GND SHDN INPUT Rin Figure 45. LMV711 Layout Example 22 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N LMV710-N, LMV711-N, LMV715-N www.ti.com SNOS519K - APRIL 2000 - REVISED AUGUST 2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support For development support see the following: * LMV710 PSPICE Model (applicable for LMV711 and LMV715) * SPICE-based analog simulation program, TINA-TI * DIP adapter evaluation module, DIP Adapter EVM * TI universal operational amplifier evaluation module, Op Amp EVM * TI software, FilterPro 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: * Absolute Maximum Ratings for Soldering (SNOA549) * AN-29 IC Op Amp Beats FETs on Input Current (SNOA624) * AN-31 Op Amp Circuit Collection (SNLA140) * AN-71 Micropower Circuits Using the LM4250 Programmable Op Amp (SNOA652) * AN-127 LM143 Monolithic High Voltage Operational Amplifier Applications (SNVA516) 11.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMV710-N Click here Click here Click here Click here Click here LMV711-N Click here Click here Click here Click here Click here LMV715-N Click here Click here Click here Click here Click here 11.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.6 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N Submit Documentation Feedback 23 LMV710-N, LMV711-N, LMV715-N SNOS519K - APRIL 2000 - REVISED AUGUST 2016 www.ti.com 11.7 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.8 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 24 Submit Documentation Feedback Copyright (c) 2000-2016, Texas Instruments Incorporated Product Folder Links: LMV710-N LMV715-N PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMV710M5 NRND SOT-23 DBV 5 1000 Non-RoHS & Green Call TI Call TI -40 to 85 A48A LMV710M5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A48A LMV710M5X/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A48A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2021 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LMV710M5 SOT-23 DBV 5 1000 178.0 8.4 LMV710M5/NOPB SOT-23 DBV 5 1000 178.0 LMV710M5X/NOPB SOT-23 DBV 5 3000 178.0 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV710M5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV710M5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV710M5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 0.90 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. 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