Vishay Siliconix
Si2301BDS
Document Number: 72066
S11-2044-Rev. F, 17-Oct-11
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1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
P-Channel 2.5 V (G-S) MOSFET
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
•100 % R
g Te s ted
• Compliant to RoHS Directive 2002/95/EC
Notes:
a. Pulse width limited by maximum junction temperature.
b. Surface mounted on FR4 board, t 5 s.
c. Surface mounted on FR4 board.
* Pb containing terminations are not RoHS compliant, exemptions may apply.
PRODUCT SUMMARY
VDS (V) RDS(on) ()ID (A)b
- 20 0.100 at VGS = - 4.5 V - 2.4
0.150 at VGS = - 2.5 V - 2.0
Ordering Information: Si2301BDS-T1-E3 (Lead (Pb)-free)
Si2301BDS-T1-GE3 (Lead (Pb)-free and Halogen-free)
G
TO-236
(SOT-23)
S
D
Top View
2
3
1
Si2301 BDS (L1)*
* Marking Code
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter Symbol 5 s Steady State Unit
Drain-Source Voltage VDS - 20 V
Gate-Source Voltage VGS ± 8
Continuous Drain Current (TJ = 150 °C)bTA = 25 °C ID
- 2.4 - 2.2
A
TA = 70 °C - 1.9 - 1.8
Pulsed Drain CurrentaIDM - 10
Continuous Source Current (Diode Conduction)bIS- 0.72 - 0.6
Power DissipationbTA = 25 °C PD
0.9 0.7 W
TA = 70 °C 0.57 0.45
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambientb
RthJA
120 145 °C/W
Maximum Junction-to-Ambientc140 175
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Document Number: 72066
S11-2044-Rev. F, 17-Oct-11
Vishay Siliconix
Si2301BDS
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes:
a. Pulse test: pulse width 300 µs duty cycle 2 %.
b. For DESIGN AID ONLY, not subject to production testing.
c. Switching time is essentially independent of operating temperature.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter Symbol Test Conditions
Limits
Unit Min. Typ. Max.
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 µA - 20 V
Gate Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 0.45 - 0.95
Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 8 V ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = - 20 V, VGS = 0 V - 1 µA
VDS = - 20 V, VGS = 0 V, TJ = 55 °C - 10
On-State Drain CurrentaID(on) VDS - 5 V, VGS = - 4.5 V - 6 A
VDS - 5 V, VGS = - 2.5 V - 3
Drain-Source On-State ResistanceaRDS(on)
VGS - 4.5 V, ID = - 2.8 A 0.080 0.100
VGS = - 2.5 V, ID = - 2 A 0.110 0.150
Forward Transconductanceagfs VDS = - 5 V, ID = - 2.8 A 6.5 S
Diode Forward Voltage VSD IS = - 0.75 A, VGS = 0 V - 0.80 - 1.2 V
Dynamicb
Total Gate Charge QgVDS = - 6 V, VGS = - 4.5 V
ID - 2.8 A
4.5 10
nCGate-Source Charge Qgs 0.7
Gate-Drain Charge Qgd 1.1
Gate Resistance Rgf = 1 MHz 2 8 16
Input Capacitance Ciss
VDS = - 6 V, VGS = 0 V, f = 1 MHz
375
pFOutput Capacitance Coss 95
Reverse Transfer Capacitance Crss 65
Switchingc
Turn - O n T i m e td(on)
VDD = - 6 V, RL = 6
ID - 1 A, VGEN = - 4.5 V
Rg = 6
20 30
ns
tr40 60
Turn-Off Time td(off) 30 45
tf20 30
Document Number: 72066
S11-2044-Rev. F, 17-Oct-11
www.vishay.com
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Vishay Siliconix
Si2301BDS
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Output Characteristics
On-Resistance vs. Drain Current
Gate Charge
0
2
4
6
8
10
012345
VDS - Drain-to-Source Voltage (V)
- Drain Current (A)ID
VGS = 5 thru 2.5 V
1.5 V
2 V
1 V
0.0
0.1
0.2
0.3
0.4
0.5
0246810
-R
DS(on)
I
D
- Drain Current (A)
V
GS
= 2.5 V
V
GS
= 4.5 V
0
1
2
3
4
5
012345
- Gate-to-Source Voltage (V)
Qg - Total Gate Charge (nC)
VGS
VDS = 10 V
ID = 2.8 A
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
2
4
6
8
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0
V
GS
- Gate-to-Source Voltage (V)
- Drain Current (A)I
D
T
C
= - 55 °C
125 °C
25 °C
0
200
400
600
800
048121620
V
DS
- Drain-to-Source Voltage (V)
C - Capacitance (pF)
C
rss
C
oss
C
iss
R
DS(on)
- On-Resistance (Normalized)
0.6
0.8
1.0
1.2
1.4
1.6
- 50 - 25 0 25 50 75 100 125 150
V
GS
= 4.5 V
I
D
= 2.8 A
T
J
- Junction Temperature (°C)
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Document Number: 72066
S11-2044-Rev. F, 17-Oct-11
Vishay Siliconix
Si2301BDS
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Source-Drain Diode Forward Voltage
Threshold Voltage
- Source Current (A)I
S
T
J
= 150 °C
V
SD
- Source-to-Drain Voltage (V)
10
0.1
0 0.2 0.4 0.6 0.8 1.0 1.2
T
J
= 25 °C
1
Variance (V)VGS(th)
- 0.2
- 0.1
0.0
0.1
0.2
0.3
0.4
- 50 - 25 0 25 50 75 100 125 150
TJ - Temperature (°C)
ID = 250 µA
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power
Time (s)
Power (W)
T
A
= 25 °C
10
8
6
4
2
0
0.01 0.1 1 10 100 1000
Safe Operating Area
Square Wave Pulse Duration (s)
VDS
- Drain-to-Source Voltage (V)
100
1
0.1 1 10 100
0.01
10
- Drain Current (A)ID
0.1
10 µs
100 µs
1 ms
10 ms
100 ms
TA = 25 °C
Single Pulse
DC, 100 s, 10 s, 1 s
RDS(on)*
Limited by
* VGS minimum VGS at which RDS(on) is specified
Document Number: 72066
S11-2044-Rev. F, 17-Oct-11
www.vishay.com
5
Vishay Siliconix
Si2301BDS
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72066.
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Effective Transient
Thermal Impedance
2
1
0.1
0.01
10-4 -3 -2 -1
10 10 10 1 10 600
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 62.5 °C/W
3. TJM - TA = PDMZthJA(t)
t1
t2
t1
t2
Notes:
4. Surface Mounted
PDM
100
Square Wave Pulse Duration (s)
Vishay Siliconix
Package Information
Document Number: 71196
09-Jul-01
www.vishay.com
1
SOT-23 (TO-236): 3-LEAD
b
E
E1
1
3
2
Se
e1
D
A2
A
A1C
Seating Plane
0.10 mm
0.004"
CC
L1
L
q
Gauge Plane
Seating Plane
0.25 mm
Dim MILLIMETERS INCHES
Min Max Min Max
A0.89 1.12 0.035 0.044
A10.01 0.10 0.0004 0.004
A20.88 1.02 0.0346 0.040
b0.35 0.50 0.014 0.020
c0.085 0.18 0.0030.007
D2.80 3.04 0.110 0.120
E2.10 2.64 0.0830.104
E11.20 1.40 0.047 0.055
e0.95 BSC 0.0374 Ref
e11.90 BSC 0.0748 Ref
L0.40 0.60 0.016 0.024
L10.64 Ref 0.025 Ref
S0.50 Ref 0.020 Ref
q3°8°3°8°
ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479
AN807
Vishay Siliconix
Document Number: 70739
26-Nov-03
www.vishay.com
1
Mounting LITTLE FOOTR SOT-23 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.
Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the
ambient air. This pattern uses all the available area underneath the
body for this purpose.
FIGURE 1. Footprint With Copper Spreading
0.114
2.9
0.059
1.5
0.0394
1.0
0.037
0.95
0.150
3.8
0.081
2.05
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.
Application Note 826
Vishay Siliconix
Document Number: 72609 www.vishay.com
Revision: 21-Jan-08 25
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SOT-23
0.106
(2.692)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.022
(0.559)
0.049
(1.245)
0.029
(0.724)
0.037
(0.950)
0.053
(1.341)
0.097
(2.459)
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Revision: 12-Mar-12 1Document Number: 91000
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