MT41K128M16JT-125 AAT:KTR - MICRON TECHNOLOGY

DDR2 SDRAM FBDIMM

MT18HTF12872FD – 1GB

MT18HTF25672FD – 2GB

Features

•240-pin, DDR2 fully buffered dual in-line memory

module (FBDIMM)

•Fast data transfer rates: PC2-4200, PC2-5300, or

PC2-6400

•1GB (128 Meg x 72), 2GB (256 Meg x 72)

•3.2 Gb/s, 4 Gb/s, or 4.8 Gb/s link transfer rates

•High-speed, 1.5V differential, point-to-point link be-

tween the host controller and advanced memory

buffer (AMB)

•Fault-tolerant; can work around a bad bit lane in

each direction

•High-density scaling with up to eight FBDIMM devi-

cess per channel

•SMBus interface to AMB for configuration register

access

•In-band and out-of-band command access

•Deterministic protocol

–Enables memory controller to optimize DRAM ac-

cesses for maximum performance

–Delivers precise control and repeatable memory

behavior

•Automatic DDR2 SDRAM bus and channel calibra-

tion

•Transmitter de-emphasis to reduce ISI

•MBIST and IBIST test functions

•Transparent mode for DRAM test support

•VDD = VDDQ = 1.8V for DRAM

•VREF = 0.9V SDRAM command/address termination

•VCC = 1.5V for AMB

•VDDSPD = 3–3.6V for AMB and EEPROM

•Serial presence-detect (SPD) with EEPROM

•Gold edge contacts

•Dual rank

•Supports 95°C operation with 2X refresh

Figure 1: 240-Pin FBDIMM (MO-256 R/C B)

Module height: 30.35mm (1.19in)

Options Marking

•Package

–240-pin DIMM (Pb-free) Y

•Frequency/CAS latency

–2.5ns @ CL = 5 (DDR2-800) -80E

–3.0ns @ CL = 5 (DDR2-667) -667

–3.75ns @ CL = 4 (DDR2-533)1-53E

Note: 1. Not recommended for new designs.

1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

Features

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Products and specifications discussed herein are subject to change by Micron without notice.

Table 1: Key Timing Parameters

Speed

Grade Industry Nomenclature

Data Rate (MT/s)

tRCD (ns) tRP (ns) tRC (ns)CL = 5 CL = 4 CL = 3

-80E PC2-6400 800 533 –12.5 12.5 55

-667 PC2-5300 667 533 400 15 15 55

-53E PC2-4200 –533 400 15 15 55

Table 2: Addressing

Parameter 1GB 2GB

Refresh count 8K 8K

Device bank address 4 BA[1:0] 8 BA[2:0]

Device page size per bank 1KB 1KB

Device configuration 512Mb (64 Meg x 8) 1Gb (128 Meg x 8)

Row address 16K A[13:0] 16K A[13:0]

Column address 2K A[9:0] 2K A[9:0]

Module rank address 2 S#[1:0] 2 S#[1:0]

Table 3: Part Numbers and Timing Parameters – 1GB

Base device: MT47H64M8,1 512Mb DDR2 SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

Link Transfer

Rate

MT18HTF12872FDY-80E__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 4.8 GT/s

MT18HTF12872FDY-667__ 1GB 128 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 4.0 GT/s

MT18HTF12872FDY-53E__ 1GB 128 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4 3.2 GT/s

Table 4: Part Numbers and Timing Parameters – 2GB

Base device: MT47H128M8,1 1Gb DDR2 SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

Link Transfer

Rate

MT18HTF25672FDY-80E__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 4.8 GT/s

MT18HTF25672FDY-667__ 2GB 256 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 4.0 GT/s

MT18HTF25672FDY-53E__ 2GB 256 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4 3.2 GT/s

Notes: 1. Data sheets for the base devices can be found on Micron’s Web page.

2. All part numbers end with a four-place code (not shown) that designates component, PCB, and AMB revi-

sions. Consult factory for current revision codes. Example: MT18HTF25672FDY-667E1D4.

1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

Features

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Pin Assignments and Descriptions

Table 5: Pin Assignments

240-Pin FBDIMM Front 240-Pin FBDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin

Sym-

bol

1 VDD 31 PN3 61 PN9# 91 PS9#1121 VDD 151 SN3 181 SN9# 211 SS9#1

2 VDD 32 PN3# 62 VSS 92 VSS 122 VDD 152 SN3# 182 VSS 212 VSS

3 VDD 33 VSS 63 PN10 93 PS5 123 VDD 153 VSS 183 SN10 213 SS5

4 VSS 34 PN4 64 PN10# 94 PS5# 124 VSS 154 SN4 184 SN10# 214 SS5#

5 VDD 35 PN4# 65 VSS 95 VSS 125 VDD 155 SN4# 185 VSS 215 VSS

6 VDD 36 VSS 66 PN11 96 PS6 126 VDD 156 VSS 186 SN11 216 SS6

7 VDD 37 PN5 67 PN11# 97 PS6# 127 VDD 157 SN5 187 SN11# 217 SS6#

8 VSS 38 PN5# 68 VSS 98 VSS 128 VSS 158 SN5# 188 VSS 218 VSS

9 VCC 39 VSS 69 VSS 99 PS7 129 VCC 159 VSS 189 VSS 219 SS7

10 VCC 40 PN13170 PS0 100 PS7# 130 VCC 160 SN131190 SS0 220 SS7#

11 VSS 41 PN13#171 PS0# 101 VSS 131 VSS 161 SN13#1191 SS0# 221 VSS

12 VCC 42 VSS 72 VSS 102 PS8 132 VCC 162 VSS 192 VSS 222 SS8

13 VCC 43 VSS 73 PS1 103 PS8# 133 VCC 163 VSS 193 SS1 223 SS8#

14 VSS 44 DNU 74 PS1# 104 VSS 134 VSS 164 DNU 194 SS1# 224 VSS

15 VTT 45 DNU 75 VSS 105 DNU 135 VTT 165 DNU 195 VSS 225 DNU

16 DNU 46 VSS 76 PS2 106 DNU 136 DNU 166 VSS 196 SS2 226 DNU

17 RESET# 47 VSS 77 PS2# 107 VSS 137 M_Test

(DNU)

167 VSS 197 SS2# 227 VSS

18 VSS 48 PN12178 VSS 108 VDD 138 VSS 168 SN121198 VSS 228 SCK

19 DNU 49 PN12#179 PS3 109 VDD 139 DNU 169 SN12#1199 SS3 229 SCK#

20 DNU 50 VSS 80 PS3# 110 VSS 140 DNU 170 VSS 200 SS3# 230 VSS

21 VSS 51 PN6 81 VSS 111 VDD 141 VSS 171 SN6 201 VSS 231 VDD

22 PN0 52 PN6# 82 PS4 112 VDD 142 SN0 172 SN6# 202 SS4 232 VDD

23 PN0# 53 VSS 83 PS4# 113 VDD 143 SN0# 173 VSS 203 SS4# 233 VDD

24 VSS 54 PN7 84 VSS 114 VSS 144 VSS 174 SN7 204 VSS 234 VSS

25 PN1 55 PN7# 85 VSS 115 VDD 145 SN1 175 SN7# 205 VSS 235 VDD

26 PN1# 56 VSS 86 DNU 116 VDD 146 SN1# 176 VSS 206 DNU 236 VDD

27 VSS 57 PN8 87 DNU 117 VTT 147 VSS 177 SN8 207 DNU 237 VTT

28 PN2 58 PN8# 88 VSS 118 SA2 148 SN2 178 SN8# 208 VSS 238 VDDSPD

29 PN2# 59 VSS 89 VSS 119 SDA 149 SN2# 179 VSS 209 VSS 239 SA0

30 VSS 60 PN9 90 PS91120 SCL 150 VSS 180 SN9 210 SS91240 SA1

Note: 1. The following signals are cyclical redundancy code (CRC) bits and thus appear out of the

normal sequence: PN12/PN12#, SN12/SN12#, PN13/PN13#, SN13/SN13#, PS9/PS9#, SS9/SS9#.

1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

Pin Assignments and Descriptions

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htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 6: Pin Descriptions

Symbol Type Description

PS[9:0] Input Primary southbound data, positive lines.

PS#[9:0] Input Primary southbound data, negative lines.

SCK Input System clock input, positive line.

SCK# Input System clock Input, negative line.

SCL Input Serial presence-detect (SPD) clock input.

SS[9:0] Input Secondary southbound data, positive lines.

SS#[9:0] Input Secondary southbound data, negative lines.

PN[13:0] Output Primary northbound data, positive lines.

PN#[13:0] Output Primary northbound data, negative lines.

SN[13:0] Output Secondary northbound data, positive lines.

SN#[13:0] Output Secondary northbound data, negative lines.

SA[2:0] I/O SPD address inputs, also used to select the FBDIMM number in the AMB.

SDA I/O SPD data input/output.

RESET# Supply AMB reset signal.

VCC Supply AMB core power and AMB channel interface power (1.5V).

VDD Supply DRAM power and AMB DRAM I/O power (1.8V).

VDDSPD Supply SPD/AMB SMBUS power (3.3V).

VSS Supply Ground.

VTT Supply DRAM address/command/clock termination power (VDD/2).

M_Test –The M_Test pin provides an external connection for testing the margin of VREF, which is pro-

duced by a voltage divider on the module. It is not intended to be used in normal system

operation and must not be connected (DNU) in a system. This test pin may have other fea-

tures on future card designs and will be included in this specification at that time.

DNU –Do not use.

1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

Pin Assignments and Descriptions

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System Block Diagram

Figure 2: System Block Diagram

source

SMBus

Up to 8 modules

•••

Memory

controller

Commodity

DDR2 SDRAM

devices

DDR2 connector with unique key

Common clock source

SMBus access

to buffer registers

AMB

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

AMB

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

AMB

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

AMB

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

DDR2

component

1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

System Block Diagram

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Functional Block Diagram

Figure 3: Functional Block Diagram

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM/ CS# DQS DQS#

RDQS

DM/ CS# DQS DQS#

RDQS

U19

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM/ CS# DQS DQS#

RDQS

DM/ CS# DQS DQS#

RDQS

U13

DQS0

DQS0#

DM0

DQS4

DQS4#

DM4

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM/ CS# DQS DQS#

RDQS

U18

DM/ CS# DQS DQS#

RDQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM/ CS# DQS DQS#

RDQS

U12

DM/ CS# DQS DQS#

RDQS

DQS5

DQS5#

DM5

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM/ CS# DQS DQS#

RDQS

DM/ CS# DQS DQS#

RDQS

U17

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM/ CS# DQS DQS#

RDQS

DM/ CS# DQS DQS#

RDQS

U11

DQS2

DQS2#

DM2

DQS6

DQS6#

DM6

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM/ CS# DQS DQS#

RDQS

U16

DM/ CS# DQS DQS#

RDQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM/ CS# DQS DQS#

RDQS

U10

DM/ CS# DQS DQS#

RDQS

DQS7

DQS7#

DM7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DM/ CS# DQS DQS#

RDQS

U14

DM/ CS# DQS DQS#

RDQS

U15

DQS8

DQS8#

DM8

SPD EEPROM

A1 A2

SA0 SA1 SA2

SDASCL

SN[13:0]

SN#[13:0]

SS[9:0]

SS#[9:0]

A[15:0]

RAS#, CAS#

WE#, ODT0

CS0#, CS1#

CKE0, CKE1

CK0, CK0#

CK1, CK1#

PN[13:0]

PN#[13:0]

PS[9:0]

PS#[9:0]

DQ[63:0]

DQS[8:0]

DQS#[8:0]

CB[7:0]

DM[8:0]

SCL

SDA

SA0

SA[2:]

SCK, SCK#

RESET#

VREF

VSS

VDD DDR2 SDRAM

VDDSPD SPD EEPROM, AMB

U20

Command, address, and

clock signals to DDR2 channel

U1–U4, U6–U9, U10–U19

Data input/output

signals to DDR2 channel

U1–U4, U6–U9, U10–U19

VTT

VCC

Terminators

AMB

DDR2 SDRAM

SPD EEPROM, AMB

DDR2 SDRAM

CS1#

CS0#

DQS1

DQS1#

DM5

DQS3

DQS3#

DM5

Out to

controller

In from

adjacent FBDIMM

In from

controller

Out to

adjacent FBDIMM

VSS

VTT

CK0, CK0#, CK1, CK1#,

ODT0, CS0#, CKE0,

RAS#, CAS#, WE#,

A[15:0], BA[2:0]

Clock, command, and address line terminations:

1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

Functional Block Diagram

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General Description

Micron’s FBDIMM devices adhere to the currently proposed industry specifications for

FBDIMMs. The following specifications contain detailed information on FBDIMM de-

sign, interfaces, and theory of operation and are listed here for the system designers’

convenience. Refer to the JEDEC Web site for available specifications.

•FBDIMM Design Specification – pending JEDEC approval

•FBDIMM: Architecture and Protocol – JESD206

•FBDIMM: Advanced Memory Buffer (AMB) – JESD82-20

•Design for Test, Design for Validation (DFx) Specification

•Serial Presence-Detect (SPD) for Fully Buffered DIMM – JEDEC Standard No. 21-C,

page 4.1.2.7-1

This DDR2 SDRAM module is a high-bandwidth, large-capacity channel solution that

has a narrow host interface. FBDIMM devices use DDR2 SDRAM devices isolated from

the channel behind an AMB buffer on the FBDIMM. Memory device capacity remains

high, and total memory capacity scales with DDR2 SDRAM bit density.

As shown in the System Block Diagram, the FBDIMM channel provides a communica-

tion path from a host controller to an array of DDR2 SDRAM devices, with the DDR2

SDRAM devices buffered behind an AMB device. The physical isolation of the DDR2

SDRAM devices from the channel enhances the communication path and significantly

increases the reliability and availability of the memory subsystem.

Advanced Memory Buffer

The AMB isolates the DDR2 SDRAM devices from the channel. This single-chip AMB

component, located in the center of each FBDIMM, acts as a repeater and buffer for all

signals and commands exchanged between the host controller and DDR2 SDRAM devi-

ces, including data input and output. The AMB communicates with the host controller

and adjacent FBDIMMs on a system board using an industry-standard, high-speed, dif-

ferential, 1.5V, point-to-point interface. The AMB also enables buffering of memory

traffic to support large memory capacities. Refer to the JEDEC JESD82-20 specification

for further information.

IDD Conditions and Specifications

Table 7: IDD Conditions

Symbol Condition

IDD_IDLE_0 Idle current, single, or last DIMM: L0 state; Idle (0% bandwidth); Primary channel ena-

bled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2

SDRAM clock active

IDD_IDLE_1 Idle current, first DIMM: L0 state; Idle (0% bandwidth); Primary and secondary channels

enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active

IDD_ACTIVE_1 Active power: L0 state; 50% DRAM bandwidth; 67% READ; 33% WRITE; Primary and secon-

dary channels enabled; DDR2 SDRAM clock active; CKE HIGH

IDD_ACTIVE_2 Active power, data pass through: L0 state; 50% DRAM bandwidth to downstream

DIMM; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM

clock active; CKE HIGH; Command and address lines stable

1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

General Description

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Table 7: IDD Conditions (Continued)

Symbol Condition

IDD_TRAINING Training: Primary and secondary channels enabled; 100% toggle on all channel lanes;

DRAMs idle; 0% bandwidth; CKE HIGH; Command and address lines stable; DDR2 SDRAM

clock active

IDD_IBIST IBIST over all IBIST modes: DRAM idle (0% bandwidth); Primary channel enabled; Secon-

dary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active

IDD_EI Electrical idle: DRAM idle (0% bandwidth); Primary channel disabled; Secondary channel

disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active; ODT and

CKE driven LOW

Note: 1. Actual test conditions may vary from published JEDEC test conditions.

Table 8: IDD Specifications – 1GB DDR2-533

Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units

ICC 2200 3000 3400 3200 3500 3800 2000 A

IDD 1420 1420 2545 1420 1420 1420 326 A

Total power 6.2 7.4 10.2 7.7 8.2 8.7 3.8 W

Table 9: IDD Specifications – 1GB DDR2-667

Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units

ICC 2600 3400 3900 3700 4000 4500 2500 A

IDD 1510 1510 2777 1510 1510 1510 326 A

Total power 7.0 8.2 11.4 8.7 9.2 10.0 4.6 W

Table 10: IDD Specifications – 1GB DDR2-800

Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units

ICC TBD TBD TBD TBD TBD TBD TBD A

IDD TBD TBD TBD TBD TBD TBD TBD A

Total power TBD TBD TBD TBD TBD TBD TBD W

Table 11: IDD Specifications – 2GB DDR2-533

Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units

ICC 2200 3000 3400 3200 3500 3800 2000 A

IDD 1420 1420 2425 1420 1420 1420 326 A

Total power 6.2 7.4 10.0 7.7 8.2 8.7 3.8 W

1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

IDD Conditions and Specifications

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Table 12: IDD Specifications – 2GB DDR2-667

Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units

ICC 2600 3400 3900 3700 4000 4500 2500 A

IDD 1420 1420 2515 1420 1420 1420 326 A

Total power 6.8 8.1 11.0 8.5 9.0 9.8 4.6 W

Table 13: IDD Specifications – 12B DDR2-800

Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units

ICC TBD TBD TBD TBD TBD TBD TBD A

IDD TBD TBD TBD TBD TBD TBD TBD A

Total power TBD TBD TBD TBD TBD TBD TBD W

Note: 1. Total power is based on maximum voltage levels, ICC at 1.575V and IDD at 1.9V.

Serial Presence-Detect

Table 14: Serial Presence-Detect EEPROM DC Operating Conditions

Parameter/Condition Symbol Min Max Units

EEPROM and AMB supply voltage VDDSPD 3 3.6 V

Input high voltage: Logic 1; all inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V

Input low voltage: Logic 0; all inputs VIL –0.6 VDDSPD × 0.3 V

Output low voltage: IOUT = 3mA VOL –0.4 V

Input leakage current: VIN = GND to VDD ILI 0.10 3 µA

Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA

Standby current ISB 1.6 4 µA

Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA

Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA

Table 15: Serial Presence-Detect EEPROM AC Operating Conditions

Parameter/Condition Symbol Min Max Units Notes

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time the bus must be free before a new transition can start tBUF 1.3 –µs

Data-out hold time tDH 200 –ns

SDA and SCL fall time tF–300 ns 2

Data-in hold time tHD:DAT 0 –µs

Start condition hold time tHD:STA 0.6 –µs

Clock HIGH period tHIGH 0.6 –µs

Noise suppression time constant at SCL, SDA inputs tI–50 ns

Clock LOW period tLOW 1.3 –µs

1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

Serial Presence-Detect

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Table 15: Serial Presence-Detect EEPROM AC Operating Conditions (Continued)

Parameter/Condition Symbol Min Max Units Notes

SDA and SCL rise time tR–0.3 µs 2

SCL clock frequency fSCL –400 kHz

Data-in setup time tSU:DAT 100 –ns

Start condition setup time tSU:STA 0.6 –µs 3

Stop condition setup time tSU:STO 0.6 –µs

WRITE cycle time tWRC –10 ms 4

Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1

and the falling or rising edge of SDA.

2. This parameter is sampled.

3. For a restart condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a

write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the

WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-

up resistance, and the EEPROM does not respond to its slave address.

Serial Presence-Detect Data

For the latest serial presence-detect data, refer to Micron's SPD page: www.micron.com/

SPD.

1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

Serial Presence-Detect

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Module Dimensions

Figure 4: 240-Pin DDR2 FBDIMM

30.5 (1.201)

30.2 (1.189)

Pin 1

17.3 (0.681)

TYP

2.6 (0.102) D

(2X)

5.2 (0.205)

TYP

5.0 (0.197) TYP

123.0 (4.843)

TYP

1.0 (0.039)

TYP

0.8 (0.031)

TYP

1.5 (0.059) R

(4X)

0.75 (0.03) R

Pin 120

Front view

133.50 (5.256)

133.20 (5.244)

67.0 (2.638)

TYP

51.0 (2.01)

TYP

9.5 (0.374)

TYP

Back view

Pin 240 Pin 121

1.37 (0.054)

1.17 (0.046)

5.1 (0.201)

MAX

1.25 (0.0492)

TYP

66.68 (2.63) TYP 0.595 (0.0234) R

2.0 (0.079)

TYP

3.9 (0.153)

TYP

(x2)

120° (2X)

2.18 (0.086) TYP

74.68 (2.94)

TYP

3.05 (0.12) TYP

66.68 (2.63)

TYP

24.95 (0.982)

TYP

Detail A

1.19 (0.047)

1.06 (0.042)

45° x 0.18 (0.0071)

0.5 (0.02) R

(4X)

0.75 (0.03) R 8X

9.9 (0.39)

TYP

(x4)

Front view with heat spreader

Back view with heat spreader

7.68 (0.302)

MAX*

3.1 (0.122) TYP

5.48 (0.216)

TYP

U1 U2 U3 U4 U5

U6 U7 U8 U10 U11

U1 U2 U3 U4 U5

U6 U7 U8 U10 U11

1.37 (0.054)

1.17 (0.046)

*Including clip radius

7.92 (0.312)

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for

additional design dimensions.

1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

Module Dimensions

PDF: 09005aef81a2f237

htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.

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www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

1GB, 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM

Module Dimensions

PDF: 09005aef81a2f237

htf18c128_256x72fdy.pdf - Rev. D 12/09 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.