© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 10
1Publication Order Number:
MC74HC540A/D
MC74HC540A
Octal 3-State Inverting
Buffer/Line Driver/Line
Receiver
High−Performance Silicon−Gate CMOS
The MC74HC540A is identical in pinout to the LS540. The device
inputs are compatible with Standard CMOS outputs. External pull−up
resistors make them compatible with LSTTL outputs.
The HC540A is an octal inverting buffer/line driver/line receiver
designed to be used with 3−state memory address drivers, clock
drivers, and other bus−oriented systems. This device features inputs
and outputs on opposite sides of the package and two ANDed
active−low output enables.
The HC540A is similar in function to the HC541A, which has
noninverting outputs.
Features
•Output Drive Capability: 15 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2.0 to 6.0 V
•Low Input Current: 1 mA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance With the JEDEC Standard No. 7 A Requirements
•Chip Complexity: 124 FETs or 31 Equivalent Gates
•These Devices are Pb−Free and are RoHS Compliant
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20
1
1
20
MARKING
DIAGRAMS
SOIC−20
DW SUFFIX
CASE 751D
74HC540A
AWLYYWWG
HC
540A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
SOEIAJ−20
F SUFFIX
CASE 967
74HC540A
AWLYWWG
1
1
1
20
1
20
20
20
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
PDIP−20
N SUFFIX
CASE 738
1
20
MC74HC540AN
AWLYYWWG
1
20
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
MC74HC540A
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2
Figure 1. Pinout: 20−Lead Packages (Top View)
1920 18 17 16 15 14
21 34567
VCC
13
8
12
9
11
10
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
L
L
H
X
L
L
X
H
L
H
X
X
FUNCTION TABLE
Inputs Output Y
OE1 OE2 A
H
L
Z
Z
Z = High Impedance
X = Don’t Care
Figure 2. Logic Diagram
18 Y1
2
A1
17 Y2
3
A2
16 Y3
4
A3
15 Y4
5
A4
14 Y5
6
A5
13 Y6
7
A6
12 Y7
8
A7
11 Y8
9
A8
OE1
OE2
1
19
Output
Enables
Data
Inputs
Inverting
Outputs
PIN 20 = VCC
PIN 10 = GND
ORDERING INFORMATION
Device Package Shipping†
MC74HC540ANG PDIP−20
(Pb−Free)
18 Units / Rail
MC74HC540ADWG SOIC−20 WIDE
(Pb−Free)
38 Units / Rail
MC74HC540ADWR2G SOIC−20 WIDE
(Pb−Free)
1000 Tape & Reel
MC74HC540ADTR2G TSSOP−20* 2500 Tape & Reel
MC74HC540AFG SOEIAJ−20
(Pb−Free)
40 Units / Rail
MC74HC540AFELG SOEIAJ−20
(Pb−Free)
2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC74HC540A
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage *0.5 to )7.0 V
VIDC Input Voltage *0.5 to VCC )0.5 V
VODC Output Voltage (Note 1) *0.5 v VO v VCC )0.5 V
IIK DC Input Diode Current $20 mA
IOK DC Output Diode Current $35 mA
IODC Output Sink Current $35 mA
ICC DC Supply Current per Supply Pin $75 mA
IGND DC Ground Current per Ground Pin $75 mA
TSTG Storage Temperature Range *65 to )150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds 260 _C
TJJunction Temperature Under Bias )150 _C
qJA Thermal Resistance PDIP
SOIC
TSSOP
67
96
128
_C/W
PDPower Dissipation in Still Air at 85_C PDIP
SOIC
TSSOP
750
500
450
mW
MSL Moisture Sensitivity Level 1
FRFlammability Rating Oxygen Index: 30% − 35% UL 94 V0 @ 0.125 in
VESD ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
u1000
V
ILATCHUP Latchup Performance Above VCC and Below GND at 85_C (Note 5) $300 mA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Supply Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
2.0
ÎÎÎÎ
ÎÎÎÎ
6.0
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
Vin, Vout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
0
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
TA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Operating Temperature, All Package Types
ÎÎÎÎÎ
ÎÎÎÎÎ
*55
ÎÎÎÎ
ÎÎÎÎ
)125
ÎÎÎ
ÎÎÎ
_C
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Rise and Fall Time (Figure 3) VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
0
0
0
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
1000
500
400
ÎÎÎ
ÎÎÎ
ÎÎÎ
ns
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
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4
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol Parameter Condition −55 to
25°C
≤85°C≤125°C Unit
VIH Minimum High−Level Input Voltage Vout = 0.1 V
|Iout| ≤ 20 mA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL Maximum Low−Level Input Voltage Vout = VCC − 0.1 V
|Iout| ≤ 20 mA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH Minimum High−Level Output
Voltage
Vin = VIL
|Iout| ≤ 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIL |Iout| ≤ 3.6 mA
|Iout| ≤ 6.0 mA
|Iout| ≤ 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL Maximum Low−Level Output
Voltage
Vin = VIH
|Iout| ≤ 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH |Iout| ≤ 3.6 mA
|Iout| ≤ 6.0 mA
|Iout| ≤ 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
IOZ Maximum Three−State Leakage
Current
Output in High Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0 ±0.5 ±5.0 ±10.0 mA
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0 4 40 160 mA
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
VCC
V
Guaranteed Limit
Symbol Parameter −55 to
25°C
≤85°C≤125°C Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 3 and 5)
2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
20
120
55
28
25
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
Cin Maximum Input Capacitance 10 10 10 pF
Cout Maximum 3−State Output Capacitance (Output in High Impedance State) 15 15 15 pF
CPD Power Dissipation Capacitance (Per Buffer) (Note 7)
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
pF
35
7. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
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5
Figure 3. Switching Waveform
VCC
GND
INPUT A
OUTPUT Y
tPHL
OE1 or OE2 50%
VCC
GND
OUTPUT Y
tPZL
OUTPUT Y
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50%
tPLH
90%
50%
10%
tr
tTHL
tf
tTLH
Figure 4. Switching Waveform
90%
50%
10%
50%
CL*
*Includes all probe and jig capacitance
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 5. Test Circuit Figure 6. Test Circuit
CL*
*Includes all probe and jig capacitance
TEST POINT
DEVICE
UNDER
TEST
OUTPUT 1kWCONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
Figure 7. Logic Detail
One of Eight
Inverters
INPUT A
OE1
OE2
OUTPUT Y
VCC
To 7 Other Inverters
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9)
Data input pins. Data on these pins appear in inverted form
on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
OE1, OE2 (PINS 1, 19)
Output enables (active−low). When a low voltage is
applied to both of these pins, the outputs are enabled and the
device functions as an inverter. When a high voltage is
applied to either input, the outputs assume the high
impedance state.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11)
Device outputs. Depending upon the state of the output
enable pins, these outputs are either inverting outputs or
high−impedance outputs.
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6
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J20 PL
M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A25.66 27.171.010 1.070
B6.10 6.600.240 0.260
C3.81 4.570.150 0.180
D0.39 0.550.015 0.022
G2.54 BSC0.100 BSC
J0.21 0.380.008 0.015
K2.80 3.550.110 0.140
L7.62 BSC0.300 BSC
M0 15 0 15
N0.51 1.010.020 0.040
____
E
1.27 1.770.050 0.070
1
11
10
20
−A−
SEATING
PLANE
K
N
FG
D20 PL
−T−
M
A
M
0.25 (0.010) T
E
B
C
F
1.27 BSC0.050 BSC
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
20
1
11
10
B20X
H10X
C
L
18X A1
A
SEATING
PLANE
q
hX 45_
E
D
M
0.25 M
B
M
0.25 S
AS
B
T
eT
B
A
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D12.65 12.95
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
__
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7
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
DIM
A
MIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B4.30 4.50 0.169 0.177
C1.20 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.27 0.37 0.011 0.015
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
110
1120
PIN 1
IDENT
A
B
−T−
0.100 (0.004)
C
DGH
SECTION N−N
K
K1
JJ1
N
N
M
F
−W−
SEATING
PLANE
−V−
−U−
S
U
M
0.10 (0.004) V S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E 6.40 0.252
--- ---
S
U0.15 (0.006) T
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
MC74HC540A
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8
PACKAGE DIMENSIONS
SOEIAJ−20
F SUFFIX
CASE 967−01
ISSUE A
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.15 0.25 0.006 0.010
12.35 12.80 0.486 0.504
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.81 --- 0.032
A1
HE
Q1
LE
_10 _0
_10 _
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
HE
A1
LE
Q1
_
c
A
Z
D
E
20
110
11
b
M
0.13 (0.005)
e
0.10 (0.004)
VIEW P
DETAIL P
M
L
A
b
c
D
E
e
L
M
Z
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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MC74HC540A/D
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