2001 Microchip Technology Inc. Advance Information DS39582A
PIC16F87XA
Data Sheet
28/40-pin Enhanced FLASH
Microcontrollers
M
DS39582A - page ii Advance Information 2001 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
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to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
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veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART,
PRO MATE, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microID,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, MXDEV, PICC, PICDEM, PICDE M.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2001, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Note the following details of the code protection feature on PICmicro® MCUs.
•The PICmicro family meets the specifications contained in the Microchip Data Sheet.
•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter , please contact the local sales off ice nearest to you.
2001 Microchip Technology Inc. Advance Information DS39582A-page 1
MPIC16F87XA
Devices Included in thi s Data Sheet:
High Performance RISC CPU:
•Only 35 single word instructions to learn
•All single cycle instructions except for program
branches, which are two-cycle
•Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
•Up to 8K x 14 wor ds of FLASH Program M em ory,
Up to 368 x 8 bytes of Data Memory (RAM),
Up to 256 x 8 bytes of EEPROM Data Memory
•Pinout compatibl e to other 28-pin or 40/44-pin
PIC16CXXX and PIC16FXXX microcontrollers
Peripheral Feat ures:
•Timer0: 8-bit timer/counter with 8-bit prescaler
•Timer1: 16-bit timer/counter with prescaler,
can be increm en ted duri ng SLEEP via external
crystal/clock
•Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
•Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
•Synchronous Serial Port (SSP) with SPI™
(Master mode) and I2C™ (Master/Slave)
•Universal Synchronous Asynchronous Receiver
Trans m it ter (U SA RT/SCI ) with 9 -bi t addre ss detectio n
•Parallel Slave Port (PSP) 8-bits wide, with
external RD , WR a nd CS co ntro ls (40/44-p in o nl y)
•Brown-out detection circuitry for
Brown-out Reset (BOR)
Analog Features:
•10-bit, up to 8 channel Analog-to-Digital
Converter (A/D)
•Brown-out Reset (BOR)
•Analog Comparator module with:
- Two analog compara tors
- Programmable on-chip voltage reference
(VREF) module
- Program mable input multiplexi ng from devic e
inputs and internal voltage reference
- Comparator outputs are externally accessible
Special Microcontroller Features:
•100,000 eras e/w ri te cy cl e Enhan ced FLASH
program memory typical
•1,000,000 erase/write cycle Data EEPROM
memory typical
•Data EEPROM Retention > 40 years
•Self-reprogrammable under software control
•In-Circ uit Seria l Pro gramming ™ (I CSP™) vi a two pins
•Single supply 5V In-Circuit Serial Programming
•Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
•Programmable code protection
•Power saving SLEEP mode
•Select ab le os cil la t or options
•In-Circuit Debug (ICD) via two pins
CMOS Technology:
•Low power, high speed FLASH/EEPROM technolog y
•Fully static design
•Wide operating voltage range (2.0V to 5.5V)
•Commercial and Industrial temperature ranges
•Low power consumption
•PIC16F873A
•PIC16F874A •PIC16F876A
•PIC16F877A
Device
Program Memory Data
SRAM
(Bytes)
EEPROM
(Bytes) I/O 10-bit
A/D (ch) CCP
(PWM)
MSSP
USART Timers
8/16-bit Comparators
Bytes # Sing le Word
Instructions SPI Master
I2C
PIC16F873A 7.2K 4096 192 128 22 5 2 Yes Yes Yes 2/1 2
PIC16F874A 7.2K 4096 192 128 33 8 2 Yes Yes Yes 2/1 2
PIC16F876A 14.3K 8192 368 256 22 5 2 Yes Yes Yes 2/1 2
PIC16F877A 14.3K 8192 368 256 33 8 2 Yes Yes Yes 2/1 2
28/40-Pin Enhanced FLASH Microcontrollers
PIC16F87XA
DS39582A-page 2 Advance Information 2001 Microchip Technology Inc.
Pin Diagrams
PIC16F876A/873A
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
PDIP (28-pin), SOIC, SSOP
2
3
4
5
6
1
7
MCLR/VPP
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
VSS
OSC1/CLKIN 15
16
17
18
19
20
21 RB3/PGM
VDD
VSS
RB0/INT
RC7/RX/DT
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
23
24
25
2627
28 22
RA1/AN1
RA0/AN0
RB7/PGD
RB6/PGC
RB5
RB4
10 11
8912
1314
MLF
PIC16F873A
PIC16F876A
RB2
RB1
RC0/T1OSO/T1CKI
OSC2/CLKOUT
2001 Microchip Technology Inc. Advance Information DS39582A-page 3
PIC16F87XA
Pin Diagram
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16F87A7/874A
PDIP (40 pin)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
44
8
7
6
5
4
3
2
1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9PIC16F877A
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RE0/RD/AN5
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7/PGD
RB6/PGC
RB5
RB4
NC
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC16F877A
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7/PGD
RB6/PGC
RB5
RB4
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3/PGM
PLCC
QFP
PIC16F874A
PIC16F874A
RC7/RX/DT
PIC16F87XA
DS39582A-page 4 Advance Information 2001 Microchip Technology Inc.
Table of Contents
1.0 Device Overview......................................................................................................................................................................... 5
2.0 Memor y Or ganization................................................................................................................................................................ 13
3.0 Da ta EE PROM and FLA SH Pr ogram Mem ory ............................................................................................ .. ...... ...... ..... ...... .... 3 1
4.0 I/O Ports.................................................................................................................................................................................... 39
5.0 Timer0 Module................ .. .... .. .. .. ....... .. .. .... .. .. .. ....... .. .... .. .. .. .... ..... .. .... .. .. .. .... ..... .... .. .. .. .............................................................. 51
6.0 Timer1 Module................ .. .... .. .. .. ....... .. .. .... .. .. .. ....... .. .... .. .. .. .... ..... .. .... .. .. .. .... ..... .... .. .. .. .............................................................. 55
7.0 Timer2 Module................ .. .... .. .. .. ....... .. .. .... .. .. .. ....... .. .... .. .. .. .... ..... .. .... .. .. .. .... ..... .... .. .. .. .............................................................. 59
8.0 Ca pture/Com pare/PW M Modules... .......................................................................................................................................... 61
9.0 M aste r Sync hronous Ser ial Port (MS SP ) Module..................................................................................................................... 69
10.0 Addressable Universal Synchronous As ynchr onous Receiver T ransm itter (USA RT)............................................................ 109
11.0 Analog-to-Digital Converter (A/D) Module ................................................... ........... .... .... ......... ............................................... 125
12.0 Comparator Module................................................................................................................................................................ 133
13.0 Comparator Voltage Reference Module ..................... .... .... .. ......... .... .... .. .... ......... .... .... .. ......... .... .. ......................................... 139
14.0 Special Features of the CPU.................................................................................................................................................. 141
15.0 Instruction Se t Summary. ................. ................ ....... ................ ....... ................. ...... .................................................................. 157
16.0 Development Support............................ .... .. .... .. ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .... .. .... .. ...................................................... 165
17.0 Elec tr ical Characterist ic s........... ....... ...... ...... ...... ................. ....... ...... ...... ...... ....... ...... ...... ........................................................ 171
18.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 195
19.0 Packaging Information............................................................................................................................................................ 197
Appendix A: Revision History .............................................. .... .... ......... .... ...... .... ......... .... .... .... ...................................................... 207
Appendix B: Device Differences ......... ......... .. .... .... .. ......... .. .... .... .. ......... .... .. .... .. ......... .... .. .... .... ...................................................... 207
Appendix C: Conversion Considerations ......... .... .. .... ....... .. .... .. .... .. ....... .... .. .... .. ....... .... .. .... .. .... ....... .. ............................................. 208
Index ................................................................................................................................................................................................. 209
On-Line Support.................................. .... ....... .... .... .. .... ....... .... .... .. .... ......... .. .... .... .. ......... .. ................................................................ 217
Reader Response............................................................................................................................................................................. 218
PIC16F87XA Product Identification System........................................................... ........... .... ...... ...................................................... 219
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2001 Microchip Technology Inc. Advance Information DS39582A-page 5
PIC16F87XA
1.0 DEVICE OVERVIEW
This document contains device specific information
about the following devi ces:
•PIC16F873A
•PIC16F874A
•PIC16F876A
•PIC16F877A
PIC16F8 73A/876 A devic es are ava ilabl e only in 28-pi n
packages, while PIC16F874A/877A devices are avail-
able in 40-pin and 44-pin packages. All devices in the
PIC16F87XA family share common architecture, with
the following differences:
•the PIC16F873A and PIC16F876A have one-half
of the total on-chip memory of the PIC16F874A
and PIC16F877A
•the 28-pin devices have three I/O ports, while the
40/44-pin devices have five
•the 28-pin devices have 14 interrupts, while the
40/44-pin devices have 15
•the 28-pin devices have five A/D input channels,
while the 40/44-pin devices have eight
•the Paralle l Slave Port is implemented only on the
40/44-p in devices
The available features are summarized in Table 1-1.
Block diagrams of the PIC16F873A/876A and
PIC16F874A/877A devices are provided in Figure 1-1
and Figure 1-2, respectively. The pinouts for these
device families are listed in Table 1-2 and Table 1-3.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual shou ld be consi dered a complemen-
tary document to this data sheet, and is highly recom-
mended reading for a better underst anding of the device
architecture and operation of the peripheral modu les.
TABLE 1-1: PIC16F87XA DEVICE FEATURES
Key Features PIC16F873A PIC16F874A PIC16F876A PIC16F877A
Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz
RESETS (and Delays) POR, BOR
(PWR T, OST) POR, BOR
(PW RT, OS T) POR, BOR
(PWRT, OST) POR, BOR
(PWRT, OST)
FLASH Program Memory
(14-bit words) 4K 4K 8K 8K
Data Me mory (bytes) 192 192 368 368
EEPROM Data Memory (bytes) 128 128 256 256
Interrupts 14 15 14 15
I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E
Timers 3333
Captu re/C om p a re/PW M modules 2 2 2 2
Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART
Parallel Communications —PSP —PSP
10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels
Analog Comparators 2 2 2 2
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
Packages 28-pin PDIP
28-pin SOIC
28-p in SSOP
28-pin MLF
40-pin PDIP
44-pin PLCC
44-pin QFP
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin MLF
40-pin PDIP
44-pin PLCC
44-pin QF P
PIC16F87XA
DS39582A-page 6 Advance Information 2001 Microchip Technology Inc.
FIGURE 1-1: PIC16F873A/8 76A BLOCK DIAGRAM
FLASH
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RB0/INT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
USART
CCP1,2 Synchronous
10-bit A/ D
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
8
3
Data EEPROM
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
In-Circuit
Debugger
Low Voltage
Programming
Comparator Voltage
Reference
Device Program FLASH Data Memory Data EEPROM
PIC16F873A 4K words 192 Bytes 128 Bytes
PIC16F876A 8K words 368 Bytes 256 Bytes
2001 Microchip Technology Inc. Advance Information DS39582A-page 7
PIC16F87XA
FIGURE 1-2: PIC16F874A/8 77A BLOCK DIAGRAM
FLASH
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
PORTD
PORTE
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
8
8
Brown-out
Reset
Note 1: Higher ord er bits are from the STATUS regist er.
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
Parallel Slave Port
8
3
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
In-Circuit
Debugger
Low-Voltage
Programming
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
USART
CCP1,2 Synchronous
10-bit A/D
Timer0 Timer1 Timer2
Serial Port
Data EEPROM Comparator Voltage
Reference
Device Program FLASH Data Memory Data EEPROM
PIC16F874A 4K words 192 Bytes 128 Bytes
PIC16F877A 8K words 368 Bytes 256 Bytes
PIC16F87XA
DS39582A-page 8 Advance Information 2001 Microchip Technology Inc.
TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION
Pin Name Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKI
OSC1
CLKI
9I
I
ST/CMOS(3) Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input. ST
buffer when configured in RC mode. Otherwise CMOS.
External clock source input. Always associated with pin
function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).
OSC2/CLKO
OSC2
CLKO
10 O
O
—Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
MCLR/VPP
MCLR
VPP
1I
P
ST Master Clear (input) or programming voltage (output)
Master Clear (Reset) input. This pin is an active low RESET
to the device.
Programming voltage input.
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
AN0
2I/O
I
TTL Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3I/O
I
TTL Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
4I/O
I
I
O
TTL Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
Comparator VREF output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5I/O
I
I
TTL Digital I/O.
Analog input 3.
A/D reference voltage (High) input .
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
6I/O
I
O
ST Digital I/O – Open drain when configured as output.
Timer0 external clock input.
Comparator 1 output.
RA5/SS/AN4/C2OUT
RA5
SS
AN4
C2OUT
7I/O
I
I
O
TTL Digital I/O.
SPI slave select input.
Analog input 4.
Comparator 2 output.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt T rigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
2001 Microchip Technology Inc. Advance Information DS39582A-page 9
PIC16F87XA
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT
RB0
INT
21 I/O
I
TTL/ST(1)
Digital I/O.
External interrupt.
RB1 22 I/O TTL Digital I/O.
RB2 23 I/O TTL Digital I/O.
RB3/PGM
RB3
PGM
24 I/O
I/O
TTL Digital I/O.
Low voltage ICSP programming enable pin.
RB4 25 I/O TTL Digital I/O.
RB5 26 I/O TTL Digital I/O.
RB6/PGC
RB6
PGC
27 I/O
I/O
TTL/ST(2)
Digital I/O.
In-Circuit Debugger and ICSP programming clock.
RB7/PGD
RB7
PGD
28 I/O
I/O
TTL/ST(2)
Digital I/O.
In-Circuit Debugger and ICSP programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11 I/O
O
I
ST Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
12 I/O
I
I/O
ST Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
13 I/O
I/O
ST Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
14 I/O
I/O
I/O
ST Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RC4/SDI/SDA
RC4
SDI
SDA
15 I/O
I
I/O
ST Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO
RC5
SDO
16 I/O
O
ST Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
17 I/O
O
I/O
ST Digital I/O.
USART asynchronous transmit.
USART 1 synchronous clock.
RC7/RX/DT
RC7
RX
DT
18 I/O
I
I/O
ST Digital I/O.
USART asynchronous receive.
USART synchronous data.
VSS 8, 19 P —Ground reference for logic and I/O pins.
VDD 20 P —Positive supply for logic and I/O pins.
TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED)
Pin Name Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt T rigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
PIC16F87XA
DS39582A-page 10 Advance Information 2001 Microchip Technology Inc.
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION
Pin Nam e DIP
Pin# PLCC
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKI
OSC1
CLKI
13 14 30 I ST/CMOS(4) Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode. Otherwise
CMOS.
External clock source input. Always assoc iated with
pin function OSC1 (see OSC1/CLKI, OSC2/CLKO
pins).
OSC2/CLKOUT
OSC2
CLKO
14 15 31 O —Oscillator cryst al or clock output.
Oscillator crystal output.
Connects to crystal or resonator in Crystal Oscillator
mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
MCLR/VPP
MCLR
VPP
1 2 18 I/P ST Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an active low
RESET to the device.
Programming voltage input.
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
AN0
2319
I/O
I
TTL Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3420
I/O
I
TTL Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
4521
I/O
I
I
O
TTL Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
Comparator VREF output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5622
I/O
I
I
TTL Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
6723
I/O
I
O
ST Digital I/O – Open drain when configured as output.
Timer0 external clock input.
Comparator 1 output.
RA5/SS/AN4/C2OUT
RA5
SS
AN4
C2OUT
7824
I/O
I
I
O
TTL Digital I/O.
SPI slave select input.
Analog input 4.
Comparator 2 output.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1:This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
2001 Microchip Technology Inc. Advance Information DS39582A-page 11
PIC16F87XA
PORTB is a bi-directional I/O port. PORTB can be soft-
ware programmed for internal weak pull-up on all inputs.
RB0/INT
RB0
INT
33 36 8 I/O
I
TTL/ST(1)
Digital I/O.
External interrupt.
RB1 34 37 9 I/O TTL Digital I/O.
RB2 35 38 10 I/O TTL Digital I/O.
RB3/PGM
RB3
PGM
36 39 11 I/O
I/O
TTL Digital I/O.
Low voltage ICSP programming enable pin.
RB4 37 41 14 I/O TTL Digital I/O.
RB5 38 42 15 I/O TTL Digital I/O.
RB6/PGC
RB6
PGC
39 43 16 I/O
I/O
TTL/ST(2)
Digital I/O.
In-Circuit Debugger and ICSP programming clock.
RB7/PGD
RB7
PGD
40 44 17 I/O
I/O
TTL/ST(2)
Digital I/O.
In-Circuit Debugger and ICSP programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
15 16 32 I/O
O
I
ST Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
16 18 35 I/O
I
I/O
ST Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
17 19 36 I/O
I/O
ST Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
18 20 37 I/O
I/O
I/O
ST Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RC4/SDI/SDA
RC4
SDI
SDA
23 25 42 I/O
I
I/O
ST Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO
RC5
SDO
24 26 43 I/O
O
ST Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
25 27 44 I/O
O
I/O
ST Digital I/O.
USART asynchronous transmit.
USART 1 synchronous clock.
RC7/RX/DT
RC7
RX
DT
26 29 1 I/O
I
I/O
ST Digital I/O.
USART asynchronous receive.
USART synchronous data.
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
Pin Nam e DIP
Pin# PLCC
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1:This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
PIC16F87XA
DS39582A-page 12 Advance Information 2001 Microchip Technology Inc.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
RD0/PSP0
RD0
PSP0
19 21 38 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD1/PSP1
RD1
PSP1
20 22 39 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD2/PSP2
RD2
PSP2
21 23 40 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD3/PSP3
RD3
PSP3
22 24 41 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD4/PSP4
RD4
PSP4
27 30 2 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD5/PSP5
RD5
PSP5
28 31 3 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD6/PSP6
RD6
PSP6
29 32 4 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD7/PSP7
RD7
PSP7
30 33 5 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
PORTE is a bi-directional I/O port.
RE0/RD/AN5
RE0
RD
AN5
8925
I/O
I
I
ST/TTL(3)
Digital I/O.
Read control for parallel slave port.
Analog input 5.
RE1/WR/AN6
RE1
WR
AN6
91026
I/O
I
I
ST/TTL(3)
Digital I/O.
Write control for parallel slave port.
Analog input 6.
RE2/CS/AN7
RE2
CS
AN7
10 11 27 I/O
I
I
ST/TTL(3)
Digital I/O.
Chip select control for parallel slave port.
Analog input 7.
VSS 12,31 13,34 6,29 P —Ground reference for logic and I/O pins.
VDD 11,32 12,35 7,28 P —Positive supply for logic and I/O pins.
NC —1,17,
28,40 12,13,
33,34 —These pins are not internally connected. These pins
should be left unconnected.
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
Pin Nam e DIP
Pin# PLCC
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1:This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
2001 Microchip Technology Inc. Advance Information DS39582A-page 13
PIC16F87XA
2.0 MEMORY ORGANIZATION
There are three memory blocks in each of the
PIC16F8 7XA d evi ce s. The Progra m Mem or y an d D a t a
Memory have separate buses so that concurrent
access can occur and is detailed in this section. The
EEPROM data memory block is detailed in Section 3.0.
Addit ional informat ion on devi ce memory may be found
in the PICmicro Mid-Range Reference Manual
(DS33023).
FIGURE 2-1: PIC16F876A/877A
PROGRAM MEMORY MAP
AND STACK
2.1 Program Memory Organization
The PIC16F87XA devices have a 13-bit program
counter c ap able of addres sing a n 8K word x 14 bit p ro-
gram memory space. The PIC16F876A/877A devices
have 8K words x 14 bits of FLASH program memory,
while PIC16F873A/874A devices have 4K words x 14
bits. Accessing a location above the physically imple-
mented address will cause a wraparound.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-2: PIC16F873A/874A
PROGRAM MEMORY MAP
AND STACK
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-Chip
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 2
Program
Memory
Page 0
Page 1
Page 2
Page 3
07FFh
0800h
0FFFh
1000h
17FFh
1800h
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-Chip
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 2
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
1000h
PIC16F87XA
DS39582A-page 14 Advance Information 2001 Microchip Technology Inc.
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Functio n Register s. Above the Spe cial Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2. 1 GENERAL PURPOSE REGISTER
FILE
The registe r file can be accesse d either dire ctly , or ind i-
rectly through the File Select Register (FSR).
RP1:RP0 Bank
00 0
01 1
10 2
11 3
Note: EEPROM Dat a Memory desc ription can be
found in Section 4.0 of this data sheet.
2001 Microchip Technology Inc. Advance Information DS39582A-page 15
PIC16F87XA
FIGURE 2-3: PIC16F87 6A/8 77A REGIS T ER FILE MA P
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are not implemented on the PIC16F876A.
2: These registers are reserved, maintain these registers clear.
File
Address
Indirect addr.(*) Indirect addr.(*)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
120h 1A0h
17Fh 1FFh
Bank 2 Bank 3
Indirect addr.(*)
PORTD(1)
PORTE(1) TRISD(1)
ADRESL
TRISE(1)
TMR0 OPTION_REG
PIR2 PIE2
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
TXSTA
SPBRG
ADCON1
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
1EFh
1F0h
accesses
70h - 7Fh
EFh
F0h
accesses
70h-7Fh
16Fh
170h
accesses
70h-7Fh
General
Purpose
Register
General
Purpose
Register
TRISB
PORTB
96 Bytes 80 Bytes 80 Bytes 80 Bytes
16 Bytes 16 Bytes
SSPCON2
EEDATA
EEADR EECON1
EECON2
EEDATH
EEADRH Reserved(2)
Reserved(2)
File
Address File
Address File
Address
File
Address
CMCON
CVRCON
PIC16F87XA
DS39582A-page 16 Advance Information 2001 Microchip Technology Inc.
FIGURE 2-4: PIC16F87 3A/8 74A REGIS T ER FILE MA P
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Indirect addr.(*) Indirect add r.(*)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
17Fh 1FFh
Bank 2 Bank 3
Indirect addr.(*)
PORTD(1)
PORTE(1) TRISD(1)
ADRESL
TRISE(1)
TMR0 OPTION_REG
PIR2 PIE2
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
TXSTA
SPBRG
ADCON1
General
Purpose
Register
General
Purpose
Register
1EFh
1F0h
accesses
A0h - FFh
16Fh
170h
accesses
20h-7Fh
TRISB
PORTB
96 Bytes 96 Bytes
SSPCON2
10Ch
10Dh
10Eh
10Fh
110h
18Ch
18Dh
18Eh
18Fh
190h
EEDATA
EEADR EECON1
EECON2
EEDATH
EEADRH Reserved(2)
Reserved(2)
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are not implemented on the PIC16F873A.
2: These registers are reserved, mai ntain these registers clear.
120h 1A0h
File
Address
File
Address File
Address
File
Address
CMCON
CVRCON
2001 Microchip Technology Inc. Advance Information DS39582A-page 17
PIC16F87XA
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Ta ble 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Details
on
page:
Bank 0
00h
(3)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
29, 148
01h TMR0 Timer0 Module Regi ster
xxxx xxxx
53, 148
02h
(3)
PCL Program Counter (PC) Least Significant Byte
0000 0000
28, 148
03h
(3)
STATUS IRP RP1 RP0 TO PD ZDCC
0001 1xxx
20, 148
04h
(3)
FSR Indirect Data Memor y Addres s Pointer
xxxx xxxx
29, 148
05h PORTA — — PORTA Data Latch when written : PO RTA pins when read
--0x 0000
41, 148
06h PORT B PORTB Dat a Latch when wr itten: PORTB pins when read
xxxx xxxx
43, 148
07h PORTC P ORTC Data Latch wh en wr itte n: PORTC pins whe n r ead
xxxx xxxx
45, 148
08h
(4)
PORT D PORTD Data Latch when written: PORTD pins when read
xxxx xxxx
46, 148
09h
(4)
PORTE — — — — — RE2 RE1 RE0
---- -xxx
47, 148
0Ah
(1,3)
PCLATH — — — Write Bu ffer for the upp er 5 bi ts of th e Pr og r am Co un te r
---0 0000
28, 148
0Bh
(3)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
0000 000x
22, 148
0Ch PIR1 PSPIF
(3)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
0000 0000
24, 148
0Dh PIR2 —CMIF —EEIF BCLIF — — CCP2IF
-0-0 0--0
26, 148
0Eh TMR1L Holding reg ister for the Least Significant Byt e of the 16- bit TMR1 Register
xxxx xxxx
58, 148
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
58, 148
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
--00 0000
55, 148
11h TMR2 Timer2 Module Register
0000 0000
60, 148
12h T2CON —TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000
59, 148
13h SSPBUF Synchronous Serial Port Receive Buf fer/Transmit Reg ist er
xxxx xxxx
77, 148
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
0000 0000
71, 80,
148
15h CCPR1L Capture/Compare/PWM Regi ster1 (LSB )
xxxx xxxx
61, 148
16h CCPR1H Capture/Compare/PWM Register1 (MSB)
xxxx xxxx
61, 148
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
--00 0000
62, 148
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
0000 000x
110, 148
19h TXREG USART T r ansmit Dat a Register
0000 0000
116, 148
1Ah RCREG USAR T Re ceive Dat a Register
0000 0000
116, 148
1Bh CCPR2L Captur e/Comp ar e/PWM Register 2 (LSB)
xxxx xxxx
61, 148
1Ch CCPR2 H Capture/Compar e/PWM Register2 (MSB)
xxxx xxxx
61, 148
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0
--00 0000
62, 148
1Eh ADRESH A/D Result Register High Byte
xxxx xxxx
131, 148
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON
0000 00-0
125, 148
Legend:
x
= unknown,
u
= unchanged,
q
= value d epends on conditio n, - = unimplemented, read as '0', r = reserved .
Shaded locations are unimplem ented, read as ‘0’.
Note 1:
The upper byte of the program coun ter is not di r ectly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the progr am counter.
2:
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3:
These registers can be addressed from any bank.
4:
PORTD, PORTE, TRISD, and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5:
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
PIC16F87XA
DS39582A-page 18 Advance Information 2001 Microchip Technology Inc.
Bank 1
80h
(3)
INDF Addressing this location uses contents of FSR to address data memory
(not a physical regi ster)
0000 0000
29, 148
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
1111 1111
21, 148
82h
(3)
PCL Program Counter (PC) Least Significant Byte
0000 0000
28, 148
83h
(3)
STATUS IRP RP1 RP0 TO PD ZDCC
0001 1xxx
20, 148
84h
(3)
FSR Indirect Data Memor y Addres s Pointer
xxxx xxxx
29, 148
85h TRISA — — PORTA Dat a Direction Register
--11 1111
41, 148
86h TRISB POR TB Data Direction Register
1111 1111
43, 148
87h TRISC PORTC Data Direct ion Register
1111 1111
45, 148
88h
(4)
TRISD PORTD Dat a Directi on Register
1111 1111
46, 148
89h
(4)
TRISE IBF OBF IBOV PSPMODE —PORTE Dat a Dir ect ion Bits
0000 -111
48, 148
8Ah
(1,3)
PCLATH — — — Write Bu ffer for the upp er 5 bi ts of th e Pr og r am Co un te r
---0 0000
28, 148
8Bh
(3)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
0000 000x
22, 148
8Ch PIE1 PSPIE
(2)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
0000 0000
23, 149
8Dh PIE2 —CMIE —EEIE BCLIE — — CCP2IE
-0-0 0--0
25, 149
8Eh PCON — — — — — — POR BOR
---- --qq
27, 149
8Fh —Unimplemented — —
90h —Unimplemented — —
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
0000 0000
81, 149
92h PR2 Timer2 Per iod Register
1111 1111
60, 149
93h SSPADD Synchronou s Serial Port (I
2
C mode) Address Register
0000 0000
77, 149
94h SSPSTAT SMP CKE D/A PSR/WUA BF
0000 0000
77, 149
95h —Unimplemented — —
96h —Unimplemented — —
97h —Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D
0000 -010
109, 149
99h SPBRG Baud Rate Generator Register
0000 0000
111, 149
9Ah —Unimplemented — —
9Bh —Unimplemented — —
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
0000 0111
133, 149
9Dh CVRCON CVREN CVROE CVRR —CVR3 CVR2 CVR1 CVR0
000- 0000
139, 149
9Eh ADRESL A/D Result Register Low Byte
xxxx xxxx
131, 149
9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0
0--- 0000
126, 149
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Details
on
page:
Legend:
x
= unknown,
u
= unchanged,
q
= value d epends on condition, - = unimplemented, read a s '0', r = reserved.
Shaded locations are unimplem ented, read as ‘0’.
Note 1:
The upper byte of the program coun ter is not di r ectly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the progr am counter.
2:
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3:
These registers can be addressed from any bank.
4:
PORTD, PORTE, TRISD, and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5:
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
2001 Microchip Technology Inc. Advance Information DS39582A-page 19
PIC16F87XA
Bank 2
100h
(3)
INDF Addressing this location uses contents of FSR to address data memory
(not a physical regi ster)
0000 0000
29, 148
101h TMR0 Ti m er 0 Module Register
xxxx xxxx
53, 148
102h
(3)
PCL Prog ram Counte r ’s (PC) Least Significant Byte
0000 0000
28, 148
103h
(3)
STATUS IRP RP1 RP0 TO PD ZDCC
0001 1xxx
20, 148
104h
(3)
FSR Indirect Data Memor y Addres s Pointer
xxxx xxxx
29, 148
105h —Unimplemented — —
106h PORTB PORTB Data Latch when written: PORT B pins when read
xxxx xxxx
43, 148
107h —Unimplemented — —
108h —Unimplemented — —
109h —Unimplemented — —
10Ah
(1,3)
PCLATH — — — Write Bu ffer for the upp er 5 bi ts of th e Pr og r am Co un te r
---0 0000
28, 148
10Bh
(3)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
0000 000x
22, 148
10Ch EEDATA EEP ROM Data Register Low Byte
xxxx xxxx
37, 149
10Dh EEADR EEPROM Address Register Low Byte
xxxx xxxx
37, 149
10Eh EEDATH — — EEPROM Data Regi ster High Byte
--xx xxxx
37, 149
10Fh EEADRH — — — —
(5)
EEPROM Address Register High Byte
---- xxxx
37, 149
Bank 3
180h
(3)
INDF Addressing this location uses contents of FSR to address data memory
(not a physical regi ster)
0000 0000
29, 148
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
1111 1111
21, 148
182h
(3)
PCL Program Counter (PC) Least Significant Byte
0000 0000
28, 148
183h
(3)
STATUS IRP RP1 RP0 TO PD ZDCC
0001 1xxx
20, 148
184h
(3)
FSR Indirect Data Memor y Addres s Pointer
xxxx xxxx
29, 148
185h —Unimplemented — —
186h TRISB PORTB Dat a Direction Register
1111 1111
43, 148
187h —Unimplemented — —
188h —Unimplemented — —
189h —Unimplemented — —
18Ah
(1,3)
PCLATH — — — Write Bu ffer for the upp er 5 bi ts of th e Pr og r am Co un te r
---0 0000
28, 148
18Bh
(3)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
0000 000x
22, 148
18Ch EECON1 EEPGD — — — WRERR WREN WR RD
x--- x000
32, 149
18Dh EECON2 EEPROM Control Regis ter2 (not a physical register)
---- ----
37, 149
18Eh —Reserved ma intain clear
0000 0000
—
18Fh —Reserved maintain clear
0000 0000
—
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Details
on
page:
Legend:
x
= unknown,
u
= unchanged,
q
= value d epends on conditio n, - = unimplemented, read as '0', r = reserved .
Shaded locations are unimplem ented, read as ‘0’.
Note 1:
The upper byte of the program coun ter is not di r ectly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the progr am counter.
2:
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3:
These registers can be addressed from any bank.
4:
PORTD, PORTE, TRISD, and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5:
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
PIC16F87XA
DS39582A-page 20 Advance Information 2001 Microchip Technology Inc.
2.2.2.1 STATUS Register
The STATUS register contains the arithmetic status of
the ALU, th e RESET s tatu s and the b ank sele ct bit s for
data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set t he Z bit. T his leav es the STA T US regist er
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affe ct the Z, C or D C bits from th e ST ATUS register. For
other instructions not affecting any status bits, see the
“Instruction Set Summary.”
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
bit 7 IRP: Register Bank S elect bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP ins truction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high, or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. Advance Information DS39582A-page 21
PIC16F87XA
2.2.2.2 OPTION_RE G Regist er
The OP TI ON_R EG Regis ter is a readabl e and w rit able
register, which cont ains various control bit s to configure
the TMR0 prescaler/WDT postscaler (single assign-
able re gister known a lso as the pres caler), t he Ext ernal
INT Int errupt, T MR0 and the w eak pul l-up s on POR TB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
Note: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are
enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3
and ensure the proper operation of the device
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16F87XA
DS39582A-page 22 Advance Information 2001 Microchip Technology Inc.
2.2.2.3 INTCON Register
The INTCO N Register is a read able and writ able regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
Note: Interru pt fl ag bits are se t whe n an in terru pt
conditi on occ urs , re gardless of the st a te of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIETMR0IEINTE RBIETMR0IFINTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all inte rrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: TMR0 Overfl ow Interr upt Enab le bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 reg i ster did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external int errupt o c curred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At leas t o ne of the RB 7:RB4 pins changed s t ate ; a m is m atc h c ond iti on wi ll c on t in ue t o se t
the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared
(must be cleared in software).
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. Advance Information DS39582A-page 23
PIC16F87XA
2.2.2.4 PIE1 Register
The PIE1 regi ster cont ains the indivi dual enable b its for
the peripheral interrupts.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 PSPIE: Parallel Slav e Port Read/Wri te Interru pt Enab le bit(1)
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
Note 1: PSPIE is reserved on PIC16F873A/876A devices; always maintain this bit clear.
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interru pt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overfl ow Interr upt Enab le bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582A-page 24 Advance Information 2001 Microchip Technology Inc.
2.2.2.5 PIR1 Register
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate interrupt
bits a re c le ar pri or to en ab li ng an i nterrupt.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
Note 1: PSPIF is reserved on PIC16F873A/876A devices; always maintain this bit clear.
bit 6 ADIF: A/D Converter Interrupt Flag bi t
1 = An A/D conversion completed
0 = The A/D co nversion is not complete
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred, and must be cleared in software before returnin g
from the Interrupt Service Routine. The conditions that will set this bit are:
•SPI
- A transmission/reception has taken place.
• I2C Slave
- A transmission/reception has taken place.
•I2C Master
- A transmission/reception has taken place.
- The initiated START condition was completed by the SSP module.
- The initiated STOP condition was completed by the SSP module.
- The initiated Restart condition was completed by the SSP module.
- The initiated Acknowledge condition was completed by the SSP module.
- A START condition occurred while the SSP mod ule was idle (Mul ti-Master sy stem).
- A ST OP con di tion o cc urred w h ile th e SSP module was i dle (Multi-Master sy ste m).
0 = No SSP interrupt condition has occurred
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in softwar e)
0 = No TMR1 register compare match occurred
PWM mo de:
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. Advance Information DS39582A-page 25
PIC16F87XA
2.2.2.6 PIE2 Register
The PIE2 regi ster cont ains the indivi dual enable b its for
the CCP2 peripheral interrupt, the SSP bus collision
interrupt, EEPROM write operation interrupt, and the
comparator interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
—CMIE —EEIE BCLIE — — CCP2IE
bit 7 bit 0
bit 7 Unimplemented: Read as '0'
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disable the Comparator interrupt
bit 5 Unimplemented: Read as '0'
bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EEPROM write interrupt
0 = Disable EEPROM write interrupt
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt
0 = Disable bus collision interrupt
bit 2-1 Unimplemented: Read as '0 '
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582A-page 26 Advance Information 2001 Microchip Technology Inc.
2.2.2.7 PIR2 Register
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt, EEPROM
write operation interrupt, and the comparator interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
Note: Interru pt fl ag bits are se t whe n an in terru pt
conditi on occ urs , re gardless of the st a te of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
—CMIF —EEIF BCLIF — — CCP2IF
bit 7 bit 0
bit 7 Unimplemented: Read as '0'
bit 6 CMIF: Comparator Interrupt Flag bit
1 = The Comparator input has changed (must be cleared in software)
0 = The Comparator input has not changed
bit 5 Unimplemented: Read as '0'
bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP, when configured for I2C Master mode
0 = No bus collision has occurred
bit 2-1 Unimplemented: Read as '0 '
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR 1 register capture oc curred (must be cl eare d in software)
0 = No TMR1 re gister capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. Advance Information DS39582A-page 27
PIC16F87XA
2.2.2.8 PCON Register
The Power Control (PCON) Register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT), and an external MCLR Reset.
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
Note: BOR is unknown on Power-on Reset. It
must be set by the user and checked on
subsequent RESETS to see if BOR is
clear, indicati ng a brown-ou t has occurre d.
The BOR status bit is a “don’t care” and is
not predictable if the brown-out circuit is
dis abled (by cleari ng the BODEN bit in the
configu r ati on word).
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1
— — — — — — POR BOR
bit 7 bit 0
bit 7-2 Unimplemented: Read as '0 '
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582A-page 28 Advance Information 2001 Microchip Technology Inc.
2.3 PCL and PCLATH
The pr ogram count er (PC) is 13 bit s wide. The low by te
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will b e clea red. Fig ure 2-5 shows the two situat ion s
for the l oading of th e PC. The up per ex ample in the fi g-
ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower exampl e i n th e fi g-
ure shows how the PC is loaded during a CALL or GOTO
instruction (PCLAT H<4:3> → PCH).
FIGURE 2-5: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 COMPUTED GOTO
A comput ed GOTO is a ccom pli shed by a ddi ng a n offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be ex ercise d if th e t able loca tion c rosse s a PCL
memory boundary (each 256 byte block). Refer to the
application note, “Implementing a Table Read”
(AN556).
2.3.2 STACK
The PIC16F87XA family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either progra m or data space a nd the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not af fected by a PUSH or POP operation.
The st ack operates as a circular buf fer . This means that
after the st ack has been PUSHed ei ght times, th e ninth
push ov erwrit es the v alue tha t was stor ed from th e first
push. The tenth p us h ov erwrites the se co nd p us h (an d
so on).
2.4 Program Memory Paging
All PIC16F87XA devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper 2 bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruc-
tion, the us er must ensu re tha t the p age sele ct bit s are
programmed so that the desired program memory
page is addressed. If a return from a CALL instructi on
(or interrupt) is executed, the entire 13-bit PC is popped
off the stack. Therefore, manipulation of the
PCLATH<4:3> bits is not required fo r the return instruc-
tions (which POPs the address from the stack).
Example 2-1 shows the calling of a subroutine in
page 1 of the program mem ory . Thi s example as sumes
that PCLATH is saved and restored by the Interrupt
Service Routi ne (if interrupts are used).
EXAMPLE 2-1: CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU
GOTO,CALL
Opcode < 10:0 >
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interr upt add ress.
Note: The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH regis-
ter for any subsequent subroutine calls or
GOTO instructions.
ORG 0x500
BCF PCLATH,4
BSF PCLATH,3 ;Select page 1
;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 0x900 ;page 1 (800h-FFFh)
SUB1_P1
: ;called subroutine
;page 1 (800h-FFFh)
:
RETURN ;return to
;Call subroutine
;in page 0
;(000h-7FFh)
2001 Microchip Technology Inc. Advance Information DS39582A-page 29
PIC16F87XA
2.5 Indirect Addressing, INDF and
FSR Registers
The INDF register is no t a physica l register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
acces ses the register pointed to by the File Sele ct Reg-
ister, FSR. Reading the INDF register itself, indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirec tly resu lts in a no op era tion ( alth oug h status bits
may be affec ted). An ef fectiv e 9-bit add ress is o btaine d
by conc atenat ing the 8 -bit F SR regi ster and the IRP bit
(STATUS<7>), as shown in Figu re 2-6.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: INDIRECT ADDRESSING
FIGURE 2-6: DIRECT/INDIRECT ADDRESSING
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR,F ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
CONTINUE
: ;yes continue
Note 1: For register file map detail, see Figure 2-3.
Data
Memory(1)
Indirect AddressingDirect Addressing
Bank Select Location Select
RP1:RP0 6 0
From Opcode IRP FSR register
70
Bank Select Location Select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
PIC16F87XA
DS39582A-page 30 Advance Information 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. Advance Information DS39582A-page 31
PIC16F87XA
3.0 DATA EEPROM AND
FLASH PROGRAM MEMORY
The Data EEPROM and FLASH Program memory is
readable and writable during normal operation (over
the full VDD range). Thi s memory is not directly mapped
in the register file space. Instead, it is indirectly
addressed through the Special Function Registers.
There are six SFRs used to read and write this
memory:
• EECON1
• EECON2
• EEDATA
• EEDATH
• EEADR
• EEADRH
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write, and EEADR holds
the address of the EEPROM location being accessed.
These devices have 128 or 256 bytes of data EEPROM
(dependi ng on t he dev ice), w ith an address ra nge fro m
00h to FF h. On devic es with 128 by tes, addresses from
80h to FFh a re uni mple mented and wi ll wrap aro und to
the begin nin g of d at a EEPROM memory. When writin g
to unimplemented locations, the on-chip charge pump
will be turn ed off.
When interfacing the program memory block, the
EEDATA and EEDATH registers form a two-byte word
that holds the 14-bit data for read/write, and the
EEADR and EEADRH registers form a two-byte word
that holds the 13-bit address of the program memory
location being accessed. These devices have 4 or 8K
words of program FLASH with an address range from
0000h to 0FFFh for th e PI C16F8 73A/874A, an d 0 000 h
to 1FFFh for the PIC16F876A/877A. Addresses above
the range of the respective device will wrap around to
the beginning of program memory.
The EEPROM data memory allows single byte read
and write. The FLASH program memory allows single
word reads and four-word block writes. Program mem-
ory write operations automatically perform an erase-
before-write on blocks of four words. A byte write in
data EEPROM memory automatically erases the loca-
tion and writes the new data (erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on chip
charge pump, rated to operate over the voltage range
of the device for byte or word operations.
When the device is code protected, the CPU may
continu e to rea d an d write the data EEPROM memory.
Depending on the settings of the write protect bits, the
device may or may not be able to write certain blocks
of the program memory; however , reads of the program
memory are allowe d. When c ode prote cted, th e devic e
programmer can no longer access data or program
memory ; thi s does N OT inhibit in tern al read s o r writes .
3.1 EEADR and EEADRH
The EEADRH:EEADR register pair can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 8K words of program EEPROM. When
selecting a data address value, only the LSByte of the
address is writte n to the EEADR regi ster. When selec t-
ing a program address value, the MSByte of the
address is written to the EEADRH register and the
LSByte is written to the EEADR register.
If the device contains less memory than the full addres s
reach of the address register pair, the Most Significant
bits of the reg isters are not im plem ented. F or exam ple,
if the de vi ce has 128 bytes o f da t a EEPROM , th e Mos t
Signific ant bit of EEADR i s not impl ement ed on a cces s
to data EEPROM.
3.2 EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
Control bit EEPGD determines if the access will be a
program or data memory access. When clear, as it is
when reset, any sub seque nt operati ons will operate on
the data memory. When set, any subsequent opera-
tions will operate on the program memory.
Control bits RD and WR initiate read and write or erase,
resp ec ti v el y. These bi ts ca nn o t be cl ea re d, on l y s et , in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write or erase
operation. On power-up, the WREN bit is clear. The
WRERR bit is set when a write (or erase) operation is
interrupted by a MCLR or a WDT Time-out Reset dur-
ing normal operation. In these situations, following
RESET, the user can check the WRERR bit and rewri te
the location. The data and address will be unchanged
in the EEDATA and EEADR registers.
Interrupt flag bit EEIF in the PIR2 register is set when
write is complete. It must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the EEPROM write sequence.
Note: The self-programming mechanism for
FLASH program memory has been
changed. On previous PIC16F87X
device s, FLASH progra mming was do ne in
single word erase/write cycles. The newer
PIC16F87XA devices use a four-word
erase/write cycle. See Section 3.6 for
more information.
PIC16F87XA
DS39582A-page 32 Advance Information 2001 Microchip Technology Inc.
REGISTER 3-1: EECON1 REGISTER (ADDRESS 18Ch)
R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD ———WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
bit 6-4 Unimplemented: Read as '0 '
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prem at urel y term ina ted
(any MCLR or any WDT Reset during normal operation)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1 WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. Advance Information DS39582A-page 33
PIC16F87XA
3.3 Reading Data EEPROM Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>), and then set control bit RD
(EECON1<0>). The data is available in the very next
cycle, in the EEDATA register; therefo re, it can be rea d
in the next instruction (see Example 3-1). EEDATA will
hold this va lue unti l another read , or un til it is written to
by the user (during a write operation).
The steps to reading the EEPROM data memory are:
1. Write the address to EEADR. Make sure tha t the
address is not larger than the memory size of
the device.
2. Clear the EEPGD bit to point to EEPROM data
memory.
3. Set the RD bit to start the read operation.
4. Read the data from t he EEDATA regi ster.
EXAMPLE 3-1: DATA EEPROM READ
3.4 Writing to Data EEPROM Memory
To write an EEPROM data locati on, the user mu st first
write the address to the EEADR register and the data to
the EEDATA register. Then the use r must fol low a spe-
cific write sequence to initiate the write for each byte.
The write will not initiate if the write sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment (see Example 3-2).
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit wil l not af fect this wri te cycle. T he WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared b y softwar e.
The steps to write to EEPROM data memory are:
1. If step 10 is not implemented, check the WR bit
to see if a write is in progress.
2. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
3. Write the 8-bit data value to be programmed in
the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data
memory.
5. Set the WREN bit to enable program operations.
6. Disable interrupts (if enabled).
7. Execute the special five instruction sequence:
•Write 55h to EECON2 in two steps (first to W,
then to EECON2)
•Write AAh to EECON2 in two steps (first to W,
then to EECON2)
•Set the WR bit
8. Enable interrupts (if using interrupts).
9. Clear the WREN bit to disable program
operations.
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set.
(EEIF must be cleared by firmware.) If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to clear, to indi cate the
end of the program cycle.
EXAMPLE 3-2: DATA EEPROM WRITE
BSF STATUS,RP1 ;
BCF STATUS,RP0 ; Bank 2
MOVF DATA_EE_ADDR,W ; Data Memory
MOVWF EEADR ; Address to read
BSF STATUS,RP0 ; Bank 3
BCF EECON1,EEPGD ; Point to Data
; memory
BSF EECON1,RD ; EE Read
BCF STATUS,RP0 ; Bank 2
MOVF EEDATA,W ; W = EEDATA
BSF STATUS,RP1 ;
BSF STATUS,RP0
BTFSC EECON,WR1 ;Wait for write
GOTO $-1 ;to complete
BCF STATUS, RP0 ;Bank 2
MOVF DATA_EE_ADDR,W ;Data Memory
MOVWF EEADR ;Address to write
MOVF DATA_EE_DATA,W ;Data Memory Value
MOVWF EEDATA ;to write
BSF STATUS,RP0 ;Bank 3
BCF EECON1,EEPGD ;Point to DATA
;memory
BSF EECON1,WREN ;Enable writes
BCF INTCON,GIE ;Disable INTs.
MOVLW 55h ;
MOVWF EECON2 ;Write 55h
MOVLW AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1,WR ;Set WR bit to
;begin write
BSF INTCON,GIE ;Enable INTs.
BCF EECON1,WREN ;Disable writes
Required
Sequence
PIC16F87XA
DS39582A-page 34 Advance Information 2001 Microchip Technology Inc.
3.5 Reading FLASH Program Memory
To read a program memory location, the user must write
two bytes of the address to t he EEADR and EEADRH
registers, set the EEPGD control bit (EECON1<7>),
and then set control bit RD (EECON1<0>). Once the
read control bit is set, the program memory FLASH con-
troller will use the next two instruction cycles to read the
data. This causes these two instructions immediately
following the “BSF EECON1,RD” instruction to be
ignored. T he data is availa ble in the very next cycle, in
the EEDA T A and EEDA TH registers; therefore, it can be
read as two bytes in the following instructions. EEDAT A
and EEDAT H regi ste rs will hold t his value un til anot her
read or until it is written to by the user (during a write
operation).
EXAMPLE 3-3: FLASH PROGRAM READ
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Bank 2
MOVLW MS_PROG_EE_ADDR ;
MOVWF EEADRH ; MS Byte of Program Address to read
MOVLW LS_PROG_EE_ADDR ;
MOVWF EEADR ; LS Byte of Program Address to read
BSF STATUS, RP0 ; Bank 3
BSF EECON1, EEPGD ; Point to PROGRAM memory
BSF EECON1, RD ; EE Read
;
NOP
NOP ; Any instructions here are ignored as program
; memory is read in second cycle after BSF EECON1,RD
;
BCF STATUS, RP0 ;
MOVF EEDATA, W ; W = LS Byte of Program EEDATA
MOVWF DATAL ;
MOVF EEDATH, W ; W = MS Byte of Program EEDATA
MOVWF DATAH ;
Required
Sequence
2001 Microchip Technology Inc. Advance Information DS39582A-page 35
PIC16F87XA
3.6 Writing to FLASH Program
Memory
FLASH program memory may only be written to if the
desti nati on addr ess i s in a segment of me mory th at is
not w rite pr otecte d, as de fined in bits WRT 1:WRT0 of
the device configuration word (Register 14-1). FLASH
prog ram memor y must b e writte n in four -word bl ocks.
A block consists of four words with sequential
addresses, with a lower boundary defined by an
address, where EEADR<1:0> = ‘00’. At the same time,
all blo ck w ri tes to pro gram m emory a r e d one a s e ras e-
and-write operations. The write operation is edge-
aligned, and cannot occur across boundaries.
To write program data, it must first be loaded into the
buffer registers (see Figure 3-1). This is accomplished
by first writing the destination address to EEADR and
EEADRH, and then writing the data to EEDATA and
EEDATH. After the address and d ata have been set u p,
then the following sequence of events must be exe-
cuted:
1. Set the EEPGD control bit (EECON1<7>)
2. Write 55h, then AAh, to EECON2 (FLASH pro-
gramming sequence)
3. Set the WR control bit (EECON1<1>)
All four buffer register locations MUST be written to with
correct data. If only one, two, or three words are being
written to in the block of four words, then a read from
the program memory location(s) not being written to
must be performed. This takes the data from the pro-
gram location(s) not being written and loads it into the
EEDAT A and EED A TH regist ers. Then the s equence of
events to transfer data to the buffer registers must be
executed.
To transfer data from the buf fer registers to the program
memory, the EEADR and EEADRH must point to the
last location in the four-word block (EEADR<1:0> =
‘11’). Then the following sequence of events must be
executed:
1. Set the EEPGD control bit (EECON1<7>)
2. Write 55h, then AAh, to EECON2 (FLASH pro-
gramming sequence)
3. Set control bit WR (EECON1<1>) to begin the
write operation
The user mu st follow the same specific sequ ence to ini-
tiate the wri te for eac h word in the progra m blo ck , writ -
ing each program word in sequence (00,01,10,11).
When the write is performed on the last word
(EEADR<1:0> = ‘11’), the block of four words are
automatically erased, and the contents of the buffer
registers are written into the program memory.
Afte r th e “BSF EECON1,WR“ instructi on, the processor
requires tw o c ycles to se t up the era se /wr ite op era tio n.
The user must place two NOP instruct ions afte r the WR
bit is set. Sinc e dat a is being written to buf fe r registers,
the writing of the first three words of the block appears
to occur immediately. The processor will halt internal
operat io ns for the typi ca l 4 ms, only during the cy cle in
which the erase takes place (i.e., the last word of the
four-word block). This is not SLEEP mode, as the
clocks and peripherals will continue to run. After the
write cycle, the processor will resume operation with
the third i nstruction after the EECON1 write instruc tion.
If th e sequ en c e i s p erf o r med t o an y o the r l ocat i on , t he
action is ignored.
FIGURE 3-1: BLOCK WRITES TO FLASH PROGRAM MEMORY
14 14 14 14
Program Memory
Buffer Register
EEADR<1:0>
= ‘00’Buffer Register
EEADR<1:0>
= ‘01’
Buffer Register
EEADR<1:0>
= ‘10’
Buffer Register
EEADR<1:0>
= ‘11’
EEDATA
EEDATH
75 07 0
68
First word of block
to be written
Four words of FLASH
to FLASH
automatically
after this word
is wr itten
transferred
are erased, then
all buffers are
PIC16F87XA
DS39582A-page 36 Advance Information 2001 Microchip Technology Inc.
An example of the complete four-word write sequence
is shown in Example 3-4. The initial address is loaded
into the EEADRH:EEADR register pair; the four words
of data are loaded using indirect addressing.
EXAMPLE 3-4: WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
;
; 1. A valid starting address (the least significant bits = ‘00’)is loaded in ADDRH:ADDRL
; 2. The 8 bytes of data are loaded, starting at the address in DATADDR
; 3. ADDRH, ADDRL and DATADDR are all located in shared data memory 0x70 - 0x7f
;
BSF STATUS,RP1 ;
BCF STATUS,RP0 ; Bank 2
MOVF ADDRH,W ; Load initial address
MOVWF EEADRH ;
MOVF ADDRL,W ;
MOVWF EEADR ;
MOVF DATAADDR,W ; Load initial data address
MOVWF FSR ;
LOOP MOVF INDF,W ; Load first data byte into lower
MOVWF EEDATA ;
INCF FSR,F ; Next byte
MOVF INDF,W ; Load second data byte into upper
MOVWF EEDATH ;
INCF FSR,F ;
BSF STATUS,RP0 ; Bank 3
BSF EECON1,EEPGD ; Point to program memory
BSF EECON1,WREN ; Enable writes
BCF INTCON,GIE ; Disable interrupts (if using)
MOVLW 55h ; Start of required write sequence:
MOVWF EECON2 ; Write 55h
MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1,WR ; Set WR bit to begin write
NOP ; Any instructions here are ignored as processor
; halts to begin write sequence
NOP ; processor will stop here and wait for write complete
; after write processor continues with 3rd instruction
BCF EECON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts (if using)
BCF STATUS,RP0 ; Bank 2
INCF EEADR,F ; Increment address
MOVF EEADR,W ; Check if lower two bits of address are ‘00’
ANDLW 0x03 ; Indicates when four words have been programmed
XORLW 0x03 ;
BTFSC STATUS,Z ; Exit if more than four words,
GOTO LOOP ; Continue if less than four words
Required
Sequence
2001 Microchip Technology Inc. Advance Information DS39582A-page 37
PIC16F87XA
3.7 Protection Against Spurious Write
There are conditions when the device should not write
to the data EEPROM or FLASH program memory. To
protect against spurious writes, various mechanisms
have been built-in. On power-up, WREN is cleared.
Also, the Power-up T imer (72 ms d uration) preven ts an
EEPROM write.
The wri te in iti ate sequence and the WREN bi t tog eth er
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
3.8 Operation During Code Protect
When the data EEPROM is code protected, the micro-
controll er can read and writ e to th e EEPROM n ormally.
However, all external access to the EEPROM is dis-
abled. Ex tern al w ri te a cc es s to the prog ram me mo ry i s
also disabled.
When program memory is code protected, the micro-
controller can read and write to program memory nor-
mally, as well as execute instructions. Writes by the
device may be selectively inhibited to regions of the
memory, depending on t he setti ng of bits WR1:W R0 of
the configuration word (see Section 14.1 for additional
information). External access to the memory is also
disabled.
TABLE 3-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
AND FLASH PROGRAM MEMORIES
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o n
Power-on
Reset
Value on
all othe r
RESETS
10Ch EEDATA EEPROM/FLASH Data Register Low Byte xxxx xxxx uuuu uuuu
10Dh EE ADR EEPRO M /FLA SH Addres s Register Low Byte xxxx xxxx uuuu uuuu
10Eh EEDATH — — EEPROM/FLASH Data Register High Byte xxxx xxxx ---0 q000
10Fh EEADRH — — — EEPROM/F LASH Address Register High Byte xxxx xxxx ---- ----
18Ch EECON1 EEPGD ———WRERR WREN WR RD x--- x000 ---0 q000
18Dh EECON2 EEPROM Control Register2 (not a physical register) ---- ---- ---- ----
0Dh PIR2 —CMIF —EEIF BCLIF — — CCP2IF -0-0 0--0 -0-0 0--0
8Dh PIE2 —CMIE —EEIE BCLIE — — CCP2IE -0-0 0--0 -0-0 0--0
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends upon condition.
Shaded cells are not used by Data EEPROM or FLAS H Program Memor y.
PIC16F87XA
DS39582A-page 38 Advance Information 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. Advance Information DS39582A-page 39
PIC16F87XA
4.0 I/O P ORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Addit ion al inf orm atio n o n I/O por t s ma y be foun d i n th e
PICmicro™ Mid-Range Reference Manual (DS33023).
4.1 PORTA and the TRISA Register
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA b it (= 1) will make the correspondin g PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the correspon ding POR TA pin an out put (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, where as wri tin g to i t will write to the po rt latch. All
write operations are read-modify-write operations.
Therefore , a write to a port implies that the port pins are
read, the value is modified and then written to the port
data l atch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schm itt Trigger inp ut and an ope n drai n outpu t.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and the analog VREF input for both the A/D converters
and the comparators. The operation of each pin is
select ed by cl ear ing/se tting the appropr iate control bit s
in the ADCON1 and/or CMCON registers.
The TRISA register controls the direction of the port
pins, ev en when they are be ing us ed as ana lo g inputs .
The user mu st ensure the bit s in the TRISA regi ster are
maintained set when using t hem as analog inputs.
EXAMPLE 4- 1: INITIALIZI NG PORTA
FIGURE 4-1: BLOCK DIAGRAM OF
RA3:RA0 PINS
Note: On a Pow er-on Reset, these pins are con-
figured as analog inputs and read as '0'.
The comparators are in the Off (digital)
state.
BCF STATUS, RP0 ;
BCF STATUS, RP1 ; Bank0
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x06 ; Configure all pins
MOVWF ADCON1 ; as digital inputs
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6>are always
; read as ’0’.
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
RD PORTA
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Analog
Input
Mode
TTL
Input
Buffer
To A/D Converter or Comparator
TRISA
PIC16F87XA
DS39582A-page 40 Advance Information 2001 Microchip Technology Inc.
FIGURE 4-2: BLOCK DIAGRAM OF RA4/T0CKI PIN
FIGURE 4-3: BLOCK DIAGRAM OF RA5 PIN
DataBus
WR PORTA
WR TRISA
RD PORTA
Data Latch
TRIS Latch
RD
Schmitt
Trigger
Input
Buffer
N
VSS
I/O pin(1)
TMR0 Clock Input
Q
D
QCK
QD
Q
CK
EN
QD
EN
TRISA
C1OUT
Note 1: I/O pin has protection diodes to VSS only.
CMCON<2:0> = ‘x01’ or ‘011’
1
0
DataBus
WR PORTA
WRTRISA
RD PORTA
Data Latch
TRIS Latch
RD
Schmitt
Trigger
Input
Buffer
I/O pin(1)
A/D Converter or SS Inp ut
Q
D
Q
CK
QD
Q
CK
EN
QD
EN
TRISA
C2OUT
CMCON<2:0> = ‘011’ or ‘101’
1
0P
N
VSS
VDD
Note 1: I/O pin has protection diodes to VDD and VSS.
2001 Microchip Technology Inc. Advance Information DS39582A-page 41
PIC16F87XA
TABLE 4-1: PORTA FUNCTIONS
TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or analog input.
RA1/AN1 bit1 TTL Input/output or analog input.
RA2/AN2/VREF-/CVREF bit2 TTL Input/output or analog input or VREF- or C VREF.
RA3/AN3/VREF+ bit3 TTL Input/output or analog input or VREF+.
RA4/T0CKI/C1OUT bit4 ST Input/output or external clock input for Timer0 or comparator output.
Output is open drain type.
RA5/SS/AN4/C2OUT bit5 TTL Input/output or slave select input for synchronous serial port or analog
input or compar ator output.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Valu e on
all othe r
RESETS
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
9Dh CVRCON CVREN CVROE CVRR —CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes, where PCFG3:PCFG0 = 0100, 0101, 011x, 1101, 1110, 1111.
PIC16F87XA
DS39582A-page 42 Advance Information 2001 Microchip Technology Inc.
4.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the co rresponding POR TB pin an output (i.e., put
the contents of the output latch on the selected pin).
Three pins of PORTB are multiplexed with the In-
Circuit Debugger and Low Voltage Programming func-
tion: RB3/PGM, RB6/PGC and RB7/PGD. The alter-
nate functions of these pins are described in the
Special Features Section.
Each of th e POR TB pins has a we ak inte rnal pul l-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
FIGURE 4-4: BLOCK DIAGRAM OF
RB3:RB0 PINS
Four of the PORTB pins, RB7:RB4, have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following man ner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mism at c h c ond it i on wi ll co nti n ue to s et f lag bi t RB IF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt-on-mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-up on Key
Strokes” (AN552).
RB0/IN T is an ext ernal i nterrupt input pin a nd is confi g-
ured using the INTEDG bit (OPTION_REG<6>).
RB0/INT is discussed in detail in Section 14.11.1.
FIGURE 4-5: BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
RBPU(2)
P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
Weak
Pull-up
RD Port
RB0/INT
I/O
pin(1)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
RB3/PGM
Data Latch
From other
RBPU(2) P
VDD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pins
Weak
Pull-up
RD Port
Latch
TTL
Input
Buffer
pin(1)
ST
Buffer
RB7:RB6 Q3
Q1
Note 1: I/O pins have diode protec tion to V DD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
In Serial Programming Mode
2001 Microchip Technology Inc. Advance Information DS39582A-page 43
PIC16F87XA
TABLE 4-3: PORTB FUNCTIONS
TABLE 4-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input.
Internal software programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3/PGM(3) bit3 TTL Input/output pin or programming pin in LVP mode. Internal software
programmable weak pull-up.
RB4 bit4 TTL Input/output pi n (with interrupt-on- change). Interna l software programm able
weak pull-up.
RB5 bit5 TTL Input/output pi n (with interrupt-on- change). Interna l software programm able
weak pull-up.
RB6/PGC bit6 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
RB7/PGD bit7 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode or In-Circuit Debugger.
3: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB3 I/O function. LVP
must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 28-pin and
40-pin mid-range devices.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
06h, 106h PORTB RB7 RB6 RB5 R B4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC16F87XA
DS39582A-page 44 Advance Information 2001 Microchip Technology Inc.
4.3 PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make th e corresponding PO RTC pin an output (i.e., p ut
the contents of the output latch on the selected pin).
PORT C is multip lexed with s everal periphe ral function s
(Table 4-5). PORTC pins have Schmitt Trigger input
buffers.
When the I2C module is enabled, the PORTC<4:3>
pins can be configured with normal I2C levels, or with
SMBus levels, by using the CKE bit (SSPSTAT<6>).
When enabling peripheral functions, care should be
taken in defini ng TRIS bit s fo r each POR TC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
the destination, should be avoided. The user should
refer to the corresponding peripheral section for the
correct TRIS bit settings.
FIGURE 4-6: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<2:0>,
RC<7:5>
FIGURE 4-7: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<4:3>
Port/Peripheral Select(2)
Data Bus
WR
Port
WR
TRIS
RD
Data Latch
TRIS Latch
RD
Schmitt
Trigger
QD
Q
CK
QD
EN
Peripheral Data Out 0
1
QD
Q
CK
P
N
VDD
VSS
Port
Peripheral
OE(3)
Peripheral Input
I/O
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port
data and peripheral output .
3: Peripheral OE (output enable) is only activated if
Peripheral Select is active.
TRIS
Port/Peripheral Select(2)
Data Bus
WR
Port
WR
TRIS
RD
Data Latch
TRIS Latch
RD
Schmitt
Trigger
QD
Q
CK
QD
EN
Peripheral Data Out 0
1
QD
Q
CK
P
N
VDD
Vss
Port
Peripheral
OE(3)
SSPl Input
I/O
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port data
and peri pheral output.
3: Peripheral OE (output enable) is only activated if
Peripheral Select is active.
0
1
CKE
SSPSTAT<6>
Schmitt
Trigger
with
SMBus
Levels
TRIS
2001 Microchip Technology Inc. Advance Information DS39582A-page 45
PIC16F87XA
TABLE 4-5: PORTC FUNCTIONS
TABLE 4-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI
and I2C modes.
RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive or
Synchrono us D at a.
Legend: ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged
PIC16F87XA
DS39582A-page 46 Advance Information 2001 Microchip Technology Inc.
4.4 PORTD and TRISD Registers
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually co nfigureable as an input or
output.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mod e, the input buffe rs
are TTL.
FIGURE 4-8: PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
TABLE 4-7: PORTD FUNCTIONS
TABLE 4-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Note: PORTD and TRISD are not implemented
on the 28- pin devices. Data
Bus
WR
Port
WR
TRIS
RD Port
Data Latch
TRIS Latch
RD
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
QD
CK
QD
CK
EN
QD
EN
TRIS
Name Bit# Buffer Type Function
RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0.
RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1.
RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2.
RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3.
RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4.
RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5.
RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6.
RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h T RISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE IBF OBF IBOV PSPMODE —PORT E Dat a Dire cti on Bi ts 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.
2001 Microchip Technology Inc. Advance Information DS39582A-page 47
PIC16F87XA
4.5 PORTE and TRISE Register
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6,
and RE2/CS/AN7), which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
The PORTE pins become the I/O control inputs for the
microprocessor po rt when bit PSPMODE (TRISE<4>) i s
set. In this mode, the user must make certain that the
TRISE<2:0> bits are set, and that the pins are configured
as digit al input s. Also ensure that AD CON1 is configu red
for digital I/O. In this mo de, th e inp ut bu f f ers are TTL.
Register 4-1 shows the TRISE register , which also con-
trols the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. When
select ed for anal og input, these pin s will read as ’0’s.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
FIGURE 4-9: PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
TABLE 4-9: PORTE FUNCTIONS
Note: PORTE and TRISE are not implemented
on the 28- pin devices.
Note: On a Pow er-on Reset, these pins are con-
figured as analog inputs, and read as ‘0’.
Data
Bus
WR
Port
WR
TRIS
RD Port
Data Latch
TRIS Latch
RD
Schmitt
Trigger
Input
Buffer
QD
CK
QD
CK
EN
QD
EN
I/O pin(1)
Note 1: I/O pins have protecti on diodes to VDD and VSS.
TRIS
Name Bit# Buffer Type Function
RE0/RD/AN5 bit0 ST/TTL(1)
I/O port pin or read control input in Parallel Slave Port mode or analog input:
RD
1 =Idle
0 = Read operation. Contents of PORTD register are output to PORTD
I/O pins (if chip selected).
RE1/WR/AN6 bit1 ST/TTL(1)
I/O port pin or write control input in Parallel Slave Port mode or analog input:
WR
1 =Idle
0 = Write operation. Value of PORTD I/O pins is latched into PORTD
register (if chip select ed).
RE2/CS/AN7 bit2 ST/TTL(1)
I/O p ort pin or chip se lect co ntrol input in Parallel Slave Port m ode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
PIC16F87XA
DS39582A-page 48 Advance Information 2001 Microchip Technology Inc.
TABLE 4-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
REGISTER 4-1: TRISE REGISTER (ADDRESS 89h)
Addres s N a m e Bit 7 B it 6 Bi t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
RESETS
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE —PORTE Data Direction Bits 0000 -111 0000 -111
9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ’0’. Shaded cells are not used by PORTE.
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE —Bit2 Bit1 Bit0
bit 7 bit 0
Parallel Slave Port Status/Control Bits:
bit 7 IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6 OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in
software)
0 = No overflow occurred
bit 4 PSPMODE: Parallel Slave Port Mode Select bit
1 = PORTD functions in Parallel Slave Port mode
0= PORTD functions in general purpose I/O mode
bit 3 Unimplemented: Read as '0'
PORTE Data Direction Bits:
bit 2 Bit2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1 Bit1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0 Bit0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. Advance Information DS39582A-page 49
PIC16F87XA
4.6 Parallel Slave Port
The Parallel Slave Port (PSP) is not implemented on
the PIC16F873A or PIC16F876A.
PORT D operates as an 8-bit wide Parallel Slave Port or
microprocessor port, when control bit PSPMODE
(TRISE<4> ) i s set . In Slave mode, it is a sy nc hro nou sl y
readable and writa ble by the extern al world throu gh RD
control input pin, RE0/RD and WR control input pin,
RE1/WR.
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the POR TD latch a s an 8-bit latc h. Setting
bit PSPMODE enables port pin RE0/RD to be the RD
input, RE1/WR to be the WR input and RE2/CS to be
the CS (chip select) inpu t. For this function ality , th e cor-
responding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set). The
A/D port configuration bits, PCFG3:PCFG0
(ADCON1<3:0>), must be set to configure pins
RE2: RE0 as digital I/O.
There are actually two 8-bit latches: one for data out-
put, and one for data input. The user writes 8-bit data
to the PORTD data latch and reads data from the port
pin latch (note that they have the same address). In this
mode, th e TRISD regi ster is ig nored, sin ce the externa l
device is controlling the direction of data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become hi gh (level triggered ), the Input Buffer Full
(IBF) status flag bit (TRISE<7>) is set on the Q4 clock
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 4-11). The interrupt flag bit PSPIF
(PIR1<7>) is also set on the same Q4 clock cycle. IBF
can onl y be cleare d b y re adi ng the PO R TD i npu t l atc h.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
A read from t he PSP occurs when both the CS and R D
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 4-12), indicating that the PORTD latch is
waitin g to be read by the ext ernal bus. Whe n eithe r the
CS or RD pin be co me s hi gh ( lev el trigg ere d), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mo de, the IBF and OB F b it s are hel d
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the us er in fi rmware and th e
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7> ).
FIGURE 4-10: PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
Data Bus
WR
Port
RD
RDx
QD
CK
EN
QD
EN
Port
pin
One bit of PORTD
Set Interrupt Flag
PSPIF(PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
TTL
TTL
TTL
TTL
Note 1: I/O pins have protection diodes to VDD and VSS.
PIC16F87XA
DS39582A-page 50 Advance Information 2001 Microchip Technology Inc.
FIGURE 4-11: PARALLEL SLAVE PORT WRITE WAV EFORMS
FIGURE 4-12: PAR ALLEL SLAVE PORT READ WAVEFORMS
TABLE 4-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all othe r
RESETS
08h PORTD P ort Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE —PORTE Data Directi on Bits 0000 -111 0000 -111
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873A/876A; always maintain these bits clear.
2001 Microchip Technology Inc. Advance Information DS39582A-page 51
PIC16F87XA
5.0 T IMER0 MODULE
The Timer0 module timer/counter has the following
features:
•8-bit timer/counter
•Readable and writable
•8-bit software programmable prescaler
•Internal or external clock select
•Interrupt on overflow from FFh to 00h
•Edge select for external clock
Figure 5-1 is a bl ock diagram o f the T imer0 m odule and
the prescaler shared with the WDT.
Additional information on the Timer0 module is
available in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule wi ll i ncr em en t ev ery ins truction cy cle (w ith ou t pre s-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment either on every rising, or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit, T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
The prescaler is mutually exclusively shared between
the Timer0 module a nd the Watchdo g T im er. The pres-
caler i s not readabl e or wr it able. Sectio n 5.3 d eta ils th e
operation of the prescaler.
5.1 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON<2>). The interrupt can be masked
by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF
must be cleared in software by the Timer0 module
Interrupt Service Routine before re-enabling this inter-
rupt. The TM R0 interrupt c annot awake n the proce ssor
from SLEEP, since the timer is shut-off during SLEEP.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
RA4/T0CKI
T0SE
pin
M
U
X
CLKOUT (= FOSC/4)
SYNC
2
Cycles TMR0 Reg
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
PSA
WDT Enable bit
M
U
X
0
10
1
Data Bus
Set Flag Bit TMR0IF
on Overflow
8
PSA
T0CS
PRESCALER
PIC16F87XA
DS39582A-page 52 Advance Information 2001 Microchip Technology Inc.
5.2 Using Timer0 with an External
Clock
When no pr escal er is used, t he ex tern al clo ck inp ut is
the same as the pre sc al er outp ut. Th e sy nch ron iz atio n
of T0CKI with the internal phase clocks is accom-
plishe d by sampling the prescale r output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
nec es sa ry f or T 0 C KI t o be hig h f or at le as t 2Tos c ( a nd
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.3 Prescaler
There i s only one pres caler a vailable , whic h is mutu ally
exclus ively shar ed between th e T imer0 mod ule and the
Watchdog Timer. A prescaler assignment for the
T i mer0 m odule m eans that t here i s no presc aler fo r the
Watchdog Ti mer, and vice-versa. This prescaler is not
readable or writable (see Figure 5-1).
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the presca ler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the pre scaler . When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
REGISTER 5-1: OPTION_REG REGISTER
Note: Writing to TMR0, when the prescaler is
assign ed to T imer0 , will clear th e prescaler
count, but will not change the prescaler
assignment.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU
bit 6 INTEDG
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: To avoid an unintended device RESET, the instruction sequence shown in the
PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) must be exe-
cuted when changing the prescaler assignment from Timer0 to the WDT. This
sequence must be followed even if the WDT is disabled.
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Ra te WDT Rate
2001 Microchip Technology Inc. Advance Information DS39582A-page 53
PIC16F87XA
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
01h,101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ’0’. Shaded cells are not used by Timer0.
PIC16F87XA
DS39582A-page 54 Advance Information 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. Advance Information DS39582A-page 55
PIC16F87XA
6.0 T IMER1 MODULE
The Timer1 module is a 16-bi t tim er/cou nter c ons is tin g
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and roll s over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit, TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit, TMR1IE (PIE1<0>).
Timer1 can operate in one of two modes:
•As a Timer
•As a Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit, TMR1ON (T1CON<0>).
Timer1 also has an internal “RESET input”. This
RESET can be generated by either of the two CCP
modules (Section 8.0). Register 6-1 shows the Timer1
control regi ster.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored, and these pins read as ‘0’.
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7-6 Unimplemented: Read as '0 '
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabl ed
0 = Osci llator is shut-off (the oscilla tor i nverter is turned off to eliminate p ower drai n)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Ti mer1
0 = Stops Timer1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582A-page 56 Advance Information 2001 Microchip Technology Inc.
6.1 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit, T1SYNC
(T1CON<2>), has no effect, since the internal clock is
always in sync.
6.2 Timer1 Counter Operation
Timer1 may operate in either a Synchronous, or an
Asynchronous mode, depending on the setting of the
TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a ri sing edge. After T imer1
is enab led in Coun ter mode, the module must fi rst have
a falling edge before the counter begins to increment.
FIGURE 6-1: TIMER1 INCREMENTING EDGE
6.3 Timer 1 Operation in Sync hronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mod e, the timer incr ement s on every risin g edge of
clock input on pin RC1/T1OSI/CCP2 when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will contin ue to increment.
FIGURE 6-2: TIMER1 BLOCK DIAGRAM
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
TMR1H TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS1:T1CKPS0 Q Clock
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(2)
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
Set Flag bit
TMR1IF on
Overflow TMR1
2001 Microchip Technology Inc. Advance Information DS39582A-page 57
PIC16F87XA
6.4 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt-on-overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 6.4.1).
In Asynchronous Counter mode, Timer1 cannot be
used as a time-base for capture or compare
operations.
6.4.1 READING AND WRITING T IMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock, will guarantee a
valid read (taken care of in hardware). However, the
user shoul d keep i n mind that r eadi ng the 16-b it time r
in two 8-b it va lu es i t self, pose s c ert a in pro bl em s, s inc e
the timer may overflow between the reads.
For write s, it is re commend ed that the us er simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer registe r.
Reading the 16-bit value requires some care.
Exampl es 12-2 an d 12-3 in the PICmicro™ M id - Range
MCU Family Reference Manual (DS33023) show how
to read and write Timer1 when it is running in
Asynchronous mode.
6.5 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON<3>). The oscil-
lator is a low power oscillator, rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user m us t pro vi de a sof tware time delay to en su re
proper oscillator start-up.
T ABLE 6-1: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
6.6 Resetting Timer1 using a CCP
Trigger Output
If the CCP 1 or CCP2 mo dule is config ured in C ompa re
mode to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
T imer 1 must be co nfigured fo r either T i mer or Synch ro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the even t that a write to T imer1 coi ncides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of ope ration, the CCPRxH:C CPRx L regis -
ter pair effectively becomes the period register for
Timer1.
Osc Type Freq. C1 C2
LP 32 kHz 33 pF 33 pF
100 k Hz 15 pF 15 pF
200 k Hz 15 pF 15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz Epson C-2 100.00 KC-P ± 20 PPM
200 kHz STD XTL 200.000 kHz ± 20 PPM
Note 1: Higher capacitance increases the stability
of oscil lator, but also increase s the st art-up
time.
2: Since eac h resonator/crystal has its own
charact eristics , the user sho uld cons ult the
resonator/crystal manufacturer for appro-
priate values of external components.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0 >).
PIC16F87XA
DS39582A-page 58 Advance Information 2001 Microchip Technology Inc.
6.7 Resetting of Timer1 Register Pai r
(TMR1H, TMR1L)
TMR1H an d TMR1L reg isters are not rese t to 00h on a
POR, or any other RESET, except by the CCP1 and
CCP2 special event triggers.
T1CON register is reset to 00h on a Power-on Reset,
or a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
6.8 Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Addres s Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh, 18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
2001 Microchip Technology Inc. Advance Information DS39582A-page 59
PIC16F87XA
7.0 T IMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mo de of the CCP m od ule (s). The T MR2 re g-
ister is readable and writable, and is cleared on any
device RESET.
The input clock (FOSC/4) has a prescale option of
1:1, 1:4, or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1: 0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
T imer2 can b e shut-of f by clearing control bit, T MR2ON
(T2CON<2>), to mini mize power consumpti on.
Register 7-1 shows the Timer2 control register.
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
Comparator
TMR2
Sets Fla g
TMR2 Reg
Output(1)
RESET
Postscaler
Prescaler
PR2 Reg
2
FOSC/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1:TMR2 register output can be software selected by the
SSP module as a bau d cl ock.
to
T2OUTPS3:
T2OUTPS0
T2CKPS1:
T2CKPS0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: Read as '0'
bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 P ostscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Pres caler is 1
01 = Pres caler is 4
1x = Prescaler is 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582A-page 60 Advance Information 2001 Microchip Technology Inc.
7.1 Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
•a wri te to the TMR2 register
•a write to the T2CON register
•any device RESET (POR, MCLR Reset, WDT
Reset, or BOR)
TMR2 is not cleared when T2CON is written.
7.2 Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate shift
clock.
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh, 18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000
12h T2CON —TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear .
2001 Microchip Technology Inc. Advance Information DS39582A-page 61
PIC16F87XA
8.0 CAPTURE/COMPARE/PWM
MODULES
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
•16-bit Capture registe r
•16-bit Compare register
•PWM Master/Slave Duty Cycle register
Both the CCP1 and CCP2 modules are identical in
operatio n, with th e except ion being the operation of the
specia l event trigger. Table 8-1 an d Table 8-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is describe d with respec t to CCP1. CCP2 opera tes the
same as CCP1, except where noted.
CCP1 Mo dul e:
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
CCP2 Mo dul e:
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match and will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in application note AN594,
“Using the CCP Modules” (DS00594).
TABLE 8-1: CCP MODE - TI MER
RESOURCES REQUIRED
TABLE 8-2: INTERACTION OF TWO CCP MODULES
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time-base
Capture Compare The compare should be configured for the special event trigger, which clears TMR1
Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1
PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt)
PWM Capture None
PWM Compare None
PIC16F87XA
DS39582A-page 62 Advance Information 2001 Microchip Technology Inc.
REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS: 17h/1Dh)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
bit 7-6 Unimplemented: Read as '0'
bit 5-4 CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits
0000 =Capture/Compare/PWM disabled (resets CCPx module)
0100 =Capture mode, every falling edge
0101 =Capture mode, every rising edge
0110 =Capture mode, every 4th rising edge
0111 =Capture mode, every 16th rising edge
1000 =Compare mode, set output on match (CCPxIF bit is set)
1001 =Compare mode, clear output on match (CCPxIF bit is set)
1010 =Compare mode, generate software interrupt on match (CCPxIF bit is set,
CCPx pin is una f f e ct ed)
1011 =Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);
CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module
is enabled)
11xx =PWM mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. Advance Information DS39582A-page 63
PIC16F87XA
8.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of th e TMR1 r egister wh en an event occurs
on pin RC2/CCP1. An event is defined as one of the
following:
•Every falling edge
•Every rising edge
•Every 4th rising edge
•Every 16th rising edge
The type of event is configured by control bits
CCP1M3:CCP1M0 (CCPxCON<3:0>). When a cap-
ture is made, the interrupt request flag bit, CCP1IF
(PIR1<2>) is set. The interrupt flag must be cleared in
software. If another capture occurs before the value in
register CCPR1 is read, th e old ca ptured v alue is over-
written by the new value.
8.1.1 CCP PIN CONFIGURATION
In Capt ure m od e, th e R C2/CCP1 pin sh oul d b e config-
ured as an input by setting the TRISC<2> bit.
FIGURE 8-1: CAP TURE MODE
OPERATION BLOCK
DIAGRAM
8.1.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
8.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in ope rati ng mod e.
8.1.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any RESET will clear
the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleare d, therefore , the first cap ture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not gen era te the “false” interrupt.
EXAMPLE 8-1: CHANGING BETWEEN
CAPTURE PRESCALERS
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
capture co ndition.
CCPR1H CCPR1L
TMR1H TMR1L
Set Flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Qs CCP1CON<3:0>
RC2/CCP1
Prescaler
÷ 1, 4, 16
and
edge detect
pin CLRF CCP1CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load the W reg with
; the new prescaler
; move value and CCP ON
MOVWF CCP1CON ; Load CCP1CON with this
; value
PIC16F87XA
DS39582A-page 64 Advance Information 2001 Microchip Technology Inc.
8.2 Compare Mode
In C ompare mo de, t he 16- bit CC PR1 re gist er va lue is
constantly compared against the TMR1 register pair
value. Whe n a match occu rs, the RC2/CCP1 pin is:
•Driven high
•Driven low
•Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit, CCP1IF is set.
FIGURE 8-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
8.2.1 CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
8.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen , the
CCP1 pin is n ot af fecte d. The CCPIF bit is set, caus ing
a CCP interrupt (if enabled).
8.2.4 SPECIAL EVENT TRIGGER
In this mod e, an internal hardw are trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 regi ste r pai r. This allo ws the C CPR 1 re gis ter t o
ef fectively b e a 16-bit progra mmable pe riod registe r for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 regis ter pai r and starts an A/D co nv ersi on (if th e
A/D module is enabled).
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low leve l. This is not the PORTC I/O
data latch.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
Match
RC2/CCP1
TRISC<2> CCP1CON<3:0>
Mode Select
Output Enable
pin
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Note: The special event trigger from the
CCP1a nd CCP2 modul es w ill not set int er-
rupt flag bit TMR1IF (PIR1<0>).
2001 Microchip Technology Inc. Advance Information DS39582A-page 65
PIC16F87XA
8.3 PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mo de.
For a ste p-by-step proc edure on how t o set up the CC P
module for PWM operation, see Section 8.3.3.
FIGURE 8-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 8-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 8-4: PW M OUTPUT
8.3.1 PWM PE RIOD
The PWM p eriod is specifi ed by writing to the PR 2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR 2 pr e sc ale value)
PWM frequency is defined as 1 / [PWM period].
When TM R2 is equal to PR2, t he following three event s
occur on the next increment cycle:
•TMR2 is cleared
•The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
•The PWM duty cycle is latched from C CPR1L into
CCPR1H
8.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10- b i t re so l uti on is av ai l ab le. T he CC PR 1 L c ontai ns
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle =(CCPR1L:CCP1 CON<5:4>) •
TOSC • (TMR2 pre s cal e value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to dou ble buf fer th e PWM duty cycle. Thi s doubl e
buffering is essential for glitch-free PWM operation.
When t he CCP R1H an d 2-bit latch match T MR2, con-
catenate d with an in terna l 2-b it Q clo ck , or 2 bits of the
TMR2 pres caler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the formula:
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Time r,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note 1: The 8-bit timer is concatenated with 2-bit internal Q
clock, or 2 bits of the prescaler, to create 10-bit time-
base.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
Note: The Timer2 postsc al er (s ee Sec ti on 7 .1) i s
not used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
log(FPWM
log(2)
FOSC )bits
=
Resolution
PIC16F87XA
DS39582A-page 66 Advance Information 2001 Microchip Technology Inc.
8.3.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC< 2> bit.
4. Set the TMR2 prescale value and enable T imer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
TABLE 8-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFFh 0xFFh 0xFFh 0x3Fh 0x1Fh 0x17h
Maximum Resolution (bits) 10 10 10 8 7 5.5
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all othe r
RESETS
0Bh,8Bh,
10Bh, 18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRISC PORTC Dat a Directi on Register 1111 1111 1111 1111
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on 28-pin devices; always maintain these bits clear.
2001 Microchip Technology Inc. Advance Information DS39582A-page 67
PIC16F87XA
TABLE 8-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Addres s N a m e Bit 7 B i t 6 B i t 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh, 18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRIS C POR TC D ata Direc ti o n Re gi s ter 1111 1111 1111 1111
11h TMR2 Timer2 Module’s Registe r 0000 0000 0000 0000
92h PR2 Time r2 Mod ule ’s Period Register 1111 1111 1111 1111
12h T2CON —TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/ Co mpar e/P WM Re gi s ter 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Ca pt ur e/ Compare/PWM Re gi s ter 1 (MS B) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capt ur e/ Co mp ar e/P WM Re gis t er2 (L SB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Cap tur e/ Co mp ar e/P WM Re gis t er2 (MS B) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
PIC16F87XA
DS39582A-page 68 Advance Information 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. Advance Information DS39582A-page 69
PIC16F87XA
9.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
9.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
periphera l or m icroc ontroll er devic es. Th ese p eriphera l
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master Mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
•Master mode
• Multi-Master mode
• Slave mode
9.2 Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON and SSPCON2). The uses
of the se registers a nd t heir individual con fig urat ion bits
differ significantly, depending on whether the MSSP
module is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
9.3 SPI Mode
The SPI m ode allow s 8 bits o f data to be sync hronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
• Serial Data Out (SDO) - RC5/SDO
• Serial Data In (SDI) - RC4/SDI/SDA
• Serial Clock (SCK) - RC3/SCK/SCL/LVDIN
Additionally a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) - RA5/SS/AN4
Figure 9-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 9-1: MSSP BLOCK DIAGRAM
(SPI MODE)
Note: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the state of the SS pin can affect the state
read back from the TRISC<5> bit. The
Peripheral OE signal fro m the SSP module
into POR TC , con trol s th e state that i s rea d
back from the TRISC<5> bit (see
Section 4.3 for information on PORTC). If
Read-Modify-Write instructions, such as
BSF, are performed on the TRISC register
while the SS pin is high, this wil l cause the
TRISC<5> bit to be set, thus disabling the
SDO output.
Read Write
Internal
Data Bus
SSPSR reg
SSPM3:SSPM0
bit0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 output
TOSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX in SSPS R
TRIS bit
2
SMP:CKE
RC4/
RC5/SDO
RA5/
RC3/ ( )
SSPBUF reg
SDI/
SDA
SS/
AN4
SCK/
SCL/
LVDIN
Peripheral OE
PIC16F87XA
DS39582A-page 70 Advance Information 2001 Microchip Technology Inc.
9.3.1 REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
•MSSP Control Register (SSPCON)
•MSSP Status Register (SSPSTAT)
•Serial Receive/Transmit Buffer (SSPBUF)
•MSSP Shift Register (SSPSR) - Not directly
accessible
SSPCON and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON regis-
ter is readable and writable. The lower 6 bits of the
SSPSTAT are read only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double buff-
ered. A write to SSPBUF wil l write to both SSPBUF and
SSPSR.
REGISTER 9-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
bit 7 SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
bit 6 CKE: SPI Clock Edge Select bit
When CKP = 0:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
When CKP = 1:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5 D/A: Data/Address bit
Used in I2C mode only
bit 4 P: STOP bit
Used in I2C mode only . This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
bit 3 S: START bit
Used in I2C mode only
bit 2 R/W: Read/W ri te bit inf orm atio n
Used in I2C mode only
bit 1 UA: Update Address bit
Used in I2C mode only
bit 0 BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. Advance Information DS39582A-page 71
PIC16F87XA
REGISTER 9-2: SSPCON: MSSP CONTROL REGISTER1 (SPI MODE) (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word.
(Must be cleared in software.)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the dat a in SSPSR is lost. Overflow ca n only occu r in Slave mod e.The user mus t
read the SSPBUF, even if only transmitting data, to avoid setting overflow.
(Must be cleared in software.)
0 = No overflow
Note: In Master mode, the overflow bit is not set, since each new reception (and transmis-
sion) is initiated by writing to the SSPBUF register.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: When enabled, these pins must be properly configured as input or output.
bit 4 CKP: Clock Polarity Select bit
1 = IDLE state for clock is a high level
0 = IDLE state for clock is a low level
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note: Bit combinations not specifically listed here are either reserved, or implemented in I2C
mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582A-page 72 Advance Information 2001 Microchip Technology Inc.
9.3.2 OPERATION
When initializing the SPI, several options need to be
specif ied. This is done by progra mming the ap propriate
control bits (SSPCON<5:0>) and SSPSTAT<7:6>.
These control bits allow the following to be specified:
•Master mo de (SCK is the clock ou tput )
•Slave mode (SCK is the clock input)
•Clock Polarity (IDLE state of SCK)
•Data input sample phase (middle or end of data
output time)
•Clock edge (output data on rising/falling edge of
SCK)
•Clock Rate (Master mode onl y)
•Slave Select mode (Slave mode only)
The MSSP consi sts of a transm it/receive Sh ift Register
(SSPSR) and a buf fer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data tha t was written to the SSPSR,
until the received da t a is rea dy. Once the 8 bits of dat a
have bee n received, that byte is moved to the SSPBUF
register. Then, the buffer full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data tha t was just r eceived. Any write to the
SSPBUF register during transmission /reception of dat a
will b e ignored, and the wri te collis ion dete ct bit, WCO L
(SSPCON<7>), will be set. User software must clear
the WCOL bit so that it can be determin ed if the foll ow-
ing write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid da ta, the SSPBUF shoul d be read before th e next
byte of dat a to transfer is writ ten to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP Interrupt is used to
determine when the transmission/reception has com-
pleted. T he SSPBUF must be rea d and/or written. If the
interrupt method is not going to be used, then software
polling can be d one to ensure that a write collision d oes
not occur. Example 9-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable, and
can only be ac cess ed b y a ddre ssin g th e SSPBUF re g-
ister . Additionally , the MSSP status register (SSPST A T)
indicates the various status conditions.
EXAMPLE 9-1: LOADING THE SSPBUF (SSP SR) REGISTER
LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)?
BRA LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
2001 Microchip Technology Inc. Advance Information DS39582A-page 73
PIC16F87XA
9.3.3 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers, and then set the SSPEN bit. This
configures the SDI, SDO, SCK, and SS pins as serial
port pin s. For the pins t o behave as the serial p ort func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
•SDI is automatic all y controlled by the SP I mo dul e
•SDO must have TRISC<5> bit cleared
•SCK (Master mode) must have TRISC<3> bit
cleared
•SCK (Slave mode) must have TRISC<3> bit set
•SS must have TRISC<4> bit set
Any seri al port fu nction th at is no t desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) regist e r to the oppos ite va lue .
9.3.4 TYPIC AL CONNECTION
Figure 9-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to sam e Clock Polarity (CKP), then both con-
trollers would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
•Master send s data — Slave sends dumm y data
•Master send s data — Slave sends dat a
•Master sends dummy data — Slave sends data
FIGURE 9-2: SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROC ESSOR 1
SCK
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM 3:SSPM0 = 010xb
Serial Clock
PIC16F87XA
DS39582A-page 74 Advance Information 2001 Microchip Technology Inc.
9.3.5 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-2) is to broad-
cast dat a by the so ftw are protoc ol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF registe r is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal p resent on the S DI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately pro gram-
ming the CKP bi t (SSPCON<4>). This then, would giv e
waveforms for SPI communication as shown in
Figure 9-3, Figure 9 -5, a nd Fig ure 9-6, where th e M SB
is transmitted first. In Master mode, the SPI clock rate
(bit rate) is user programmable to be one of the
following:
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
•Timer2 output/2
This allows a maximum data rate (at 40 MHz) of 10.00
Mbps.
Figure 9-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
dat a is shown.
FIGURE 9-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 clock
modes
Input
Sample
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit0
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(CKE = 0)
(CKE = 1)
Next Q4 cy cle
after Q2↓
2001 Microchip Technology Inc. Advance Information DS39582A-page 75
PIC16F87XA
9.3.6 SLAVE MODE
In Slave m ode , the dat a is transmi tted and receiv ed a s
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times, as
specified in the electrical specifications.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
9.3.7 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON<3:0> = 04h). The pin must not
be driven low for the SS pin to function as an input.
The Data Latch must be high. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to a
high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an in put. This d isables transmissi ons from th e SDO.
The SDI can always be left as an input (SDI function)
since it cann ot cre ate a bus con flict.
FIGURE 9-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slave Mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: If the SPI is us ed in Slave Mo de with CK E
set, then the SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7
SDO bit7 bit6 bit7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit0
bit7 bit0
Next Q4 cycle
after Q2↓
PIC16F87XA
DS39582A-page 76 Advance Information 2001 Microchip Technology Inc.
FIGURE 9-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 9-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
optional
Next Q4 cycle
after Q2↓
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Wr i te to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
not optional
Next Q4 cycle
after Q2↓
2001 Microchip Technology Inc. Advance Information DS39582A-page 77
PIC16F87XA
9.3.8 SLEEP OP ERATION
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operat es asy nchron ously to the devi ce. Th is al lows the
device to be placed in SLEEP mode, and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP inter-
rupt flag bit will be set and if enabled, will wake the
device from SLEEP.
9.3.9 EFFECTS OF A RESET
A reset disables the MSSP module and terminates the
current transfer.
9.3.10 BUS MODE COMPATIBILITY
Table 9-1 shows the compatibility between the stan-
dard SPI modes and the st ates the CKP and CKE co n-
trol bits.
TABLE 9-1: SPI BUS MODES
There is also a SMP bit w hich co ntrols whe n the dat a is
sampled.
TABLE 9-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all othe r
RESETS
INTCON GIE/GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
SSPBUF S ync hronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA —PORTA Data Direction Register --11 1111 --11 1111
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on 28-pin devices. Always maintain these bits clear.
PIC16F87XA
DS39582A-page 78 Advance Information 2001 Microchip Technology Inc.
9.4 I2C Mode
The MSSP module in I2C mode fully implements all
master an d sla ve func tion s (includi ng ge nera l ca ll su p-
port) and pro vid es interrup ts on START and ST O P bits
in hardw are to determine a free bus (m ulti-master fun c-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
•Serial clock (SCL) - RC3/SCK/SCL
•Serial data (SDA) - RC4/SDI/SDA
The user must configure these pins as inputs or out puts
through the TRISC<4:3> bits.
FIGURE 9-7: MSSP BLOCK DIAGRAM
(I2C MODE)
9.4.1 REGISTERS
The MSSP module has six registers for I2C operation.
These are:
•MSSP Control Register (SSPCON)
•MSSP Control Register 2 (SSPCON2)
•MSSP Status Register (SSPSTAT)
•Serial Receive/Transmit Buffer (SSPBUF)
•MSSP Shift Register (SSPSR) - Not directly
accessible
•MSSP Address Register (SSPADD)
SSPCON, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read
only. The upper two bits of the SSPSTAT are read/
write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address
when the SSP is configured in I2C Sl ave m ode . Wh en
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the baud rate generator
reload value.
In receive operations, SSPSR and SSPBUF together
create a double buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double buff-
ered. A write to SSPBUF wil l write to both SSPBUF and
SSPSR.
Read Write
SSPSR reg
Match Detect
SSPADD reg
START and
STOP bit Detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/
Shift
Clock
MSb
SDI/ LSb
SDA
2001 Microchip Technology Inc. Advance Information DS39582A-page 79
PIC16F87XA
REGISTER 9-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
bit 7 SMP: Slew Rate Control bit
In Master or Slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: STOP bit
1 = Indicates that a STOP bit has been detected last
0 = STOP bit was not detected last
Note: This bit is cleared on RESET and when SSPEN is cleared.
bit 3 S: START bit
1 = Indicates that a START bit has been detected last
0 = START bit was not detected last
Note: This bit is cleared on RESET and when SSPEN is cleared.
bit 2 R/W: Read/Write bit inf ormatio n (I2C mode on ly)
In Slave mode:
1 = Read
0 = Write
Note: This bit holds the R/W bi t information followin g the last address ma tch. This bit is only
valid from the address match to the next START bit, STOP bit, or not ACK bit.
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
Note: ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is
in IDLE mode.
bit 1 UA: Update Address (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
In Receive mode:
1 = Data Transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582A-page 80 Advance Information 2001 Microchip Technology Inc.
REGISTER 9-4: SSPCON: MSSP CONTROL REGISTER1 (I2C MODE) (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started. (Must be cleared in software.)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be cleared
in software.)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t c a re” bit.
bit 6 SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 =A byte is received while the SSPBUF register is still holding the previous byte. (Must be
cleared in software.)
0 = No overflow
In Transmit mode:
This is a “don’t c a re” bit in Transmit mode.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: When enabled, the SDA and SCL pins must be properly configu red as input or output.
bit 4 CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In Master mode:
Unused in this mode
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (Slave IDLE)
1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Note: Bit combinations not specifically listed here are either reserved, or implemented in
SPI mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. Advance Information DS39582A-page 81
PIC16F87XA
REGISTER 9-5: SSPCON2: MSSP CONTROL REGISTER2 (I2C MODE) (ADDRESS 91h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
bit 7 GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
Note: Value that will be tr ansmitte d when the user in itiates an Acknow ledge sequen ce at
the end of a receive.
bit 4 ACKEN: Acknowledge Sequenc e Enab le bit (Master Receive mo de onl y)
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence IDLE
bit 3 RCEN: Receive Enable bit (Maste r mode only)
1 = Enables Receive mode for I2C
0 = Receive IDLE
bit 2 PEN: STOP Condition Enable bit (Master mode only)
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition IDLE
bit 1 RSEN: Repeated START Condition Enabled bit (Master mode only)
1 = Initiate Repeated START condition on SDA and SCL pins.
Automatically cleared by hardware.
0 = Repeated START condition IDLE
bit 0 SEN: START Condition Enabled/Stretch Enabled bit
In Maste r mode :
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition IDLE
In Slave mode:
1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)
0 = Clock stretching is enabled for Slave Transmit only (PIC16F87X compatibility)
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582A-page 82 Advance Information 2001 Microchip Technology Inc.
9.4.2 OPERATION
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON<5>).
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
• I2C Master mode, clock = OSC/4 (SSPADD +1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled
• I2C Slave mode (10 -bit address), with START and
STOP bit interrupts enabled
• I2C Firmware controlled master operation, slave
is IDLE
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. To guarantee proper oper-
ation of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
9.4.3 SLAVE MODE
In Slave mod e, the SCL and SDA pins mu st be co nfi g-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I2C Slav e m od e h ardw a re wi ll alw a ys ge nera te an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
START and STOP bits
When an address is matched or the data transfer after
an add res s mat ch i s rece ived , th e ha rdw are au tom ati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value cur-
rently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
•The buffer full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
•The overfl ow bit, SSPOV (SSPCON<6>), was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register , while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low fo r pro per op erati on. The h igh an d l ow times o f th e
I2C specification, as well as the requirement of the
MSSP modu le, i s shown in ti ming parameter #100 and
parameter #101.
9.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a START condi tion to oc cur. Followin g the START con-
dition, the 8-bi ts are shifted i nto the SS PSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The buffer full bit BF is set.
3. An ACK pulse is generated.
4. MSSP interrupt flag bit SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) on the falling
edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) o f the firs t address b yte specify if this i s a 10-b it
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The seque nce of events for 10-bit
address is as follows, with steps 7 through 9 for the
slave-transmitter:
1. Receive first (high) byte of Address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD regis ter wi th the firs t (hig h)
byte o f Addres s. I f match releas es S CL line , thi s
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated START condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
2001 Microchip Technology Inc. Advance Information DS39582A-page 83
PIC16F87XA
9.4.3.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleare d. The re ceived ad dress is loa ded in to
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the No Acknow ledge (ACK ) pulse is given. An overfl ow
condition is defined as either bit BF (SSPSTAT<0>) is
set or bit SSPOV (SSPCON<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
If SEN is enabled (SSPCON<0>=1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock mus t be release d by setting bit CK P
(SSPCON<4>). See Section 9.4.4 (“Cloc k Stretch ing ”)
for more detail.
9.4.3.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low, regardless of SEN (see “Clock Stretching”,
Section 9.4.4, for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data.The
transmit data must be loaded into the SSPBUF register ,
which also loads the SSPSR register. Then pin RC3/
SCK/SCL should be enabled by setting bit CKP
(SSPCON<4>). The eight data bits are shifted out on
the falli ng ed ge of the SC L inp ut. This en sure s th at the
SDA signal is valid during the SCL high time
(Figure 9-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the nin th SCL input pu lse. If the SDA
line is high (not ACK), then the data transfer is com-
plete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the START bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register .
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
PIC16F87XA
DS39582A-page 84 Advance Information 2001 Microchip Technology Inc.
FIGURE 9-8: I 2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S1 234 56 7891 23456789 12345 789 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus Master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP (CKP does not reset to ‘0’ when SEN = 0)
2001 Microchip Technology Inc. Advance Information DS39582A-page 85
PIC16F87XA
FIGURE 9-9: I 2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9
SSPBUF is w ritten in software
Cleared in software
SCL held low
while CPU
responds to SSPIF
From SSPIF ISR
Data in
sampled
S
ACK
Transmitting Data
R/W = 1
ACK
Receiving Address
A7 D7
9 1
D6 D5 D4 D3 D2 D1 D0
2 3 4 5 6 7 8 9
SSP BUF is writ te n in s o ft w a r e
Cleared in software From SSPIF ISR
Transmitting Data
D7
1
CKP
P
ACK
CK P is s e t in so f tw a re CK P is s e t in so f tw a re
PIC16F87XA
DS39582A-page 86 Advance Information 2001 Microchip Technology Inc.
FIGURE 9-10: I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT < 0>)
S123456789 1 23456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7 D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Clear ed in software
D2
6
(PIR1<3>) Cleared in software
Receive Second Byte of Address
Cleared by hardware
when SSPADD is updated
with low byte of address.
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address.
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus Master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
2001 Microchip Technology Inc. Advance Information DS39582A-page 87
PIC16F87XA
FIGURE 9-11: I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT< 0>)
S123456789 123456789 12345 789 P
11110A9A8 A7 A6A5A4A3A2A1A0 11110 A8
R/W=1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus Master
terminates
transfer
A9
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address.
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address.
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Tran smitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Clear ed in software
Completion of
clears BF flag
CKP (SSPCON<4>)
CKP is set in software
CKP is automatically cleared in hardware holding SCL low
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until
CKP is set to ‘1’
BF flag is clear
third address sequence
at the end of the
PIC16F87XA
DS39582A-page 88 Advance Information 2001 Microchip Technology Inc.
9.4.4 CLOCK STRETCHING
Both 7 and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
The SEN bit (SSPCON2<0>) al lows clock stretch ing to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
9.4.4.1 Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPCON register is auto-
matically cleared, forcing the SCL output to be held
low. The CKP being cleared to ‘0’ will assert the SCL
line low. The CKP bit must be set in the user’s ISR
before reception is allowed to continue. By holding the
SCL line l ow, the us er h as ti me t o s erv i ce t he IS R a nd
read the contents of the SSPBUF before the master
device can initiate another receive sequence. This will
prevent buffer overruns from occurring (see
Figure 9-13).
9.4.4.2 Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not c lea red . Duri ng t his time, if th e UA b it i s
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit a dd ress , and f oll ow in g the rec ei ve of the se con d
byte of the 10-bit address, with the R/W bit cleared to
‘0’. The re lea se of th e cloc k lin e occu rs up on upda ti ng
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
9.4.4.3 Clock Stretching for 7-bit Slave
Transmit Mode
7-bit Sl ave Transmit mo de imp lemen ts c lock str etchin g
by clearing the CKP bit after the falling edge of the
ninth clock, if the BF bit is clear. This occurs regard-
less of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 9-9).
9.4.4.4 Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence, which contains the high order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode, and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 9-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software,
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note: If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occ urs, and i f
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
stat e of the BF bit o nly occurs duri ng a data
sequence, not an address sequence.
Note 1: If the user lo ads t he contents of SSPBUF,
setting the BF bit b efore the fa lling edg e of
the ninth clock, the CKP bit will not be
cleared and clock st retching wil l not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
2001 Microchip Technology Inc. Advance Information DS39582A-page 89
PIC16F87XA
9.4.4.5 Clock Synchronization
and the CKP Bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’; however, setting the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set, and all other
devices on the I2C bus have de-asserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 9-12).
FIGURE 9-12: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX-1DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
de-asserts clock
Master device
asser ts clock
PIC16F87XA
DS39582A-page 90 Advance Information 2001 Microchip Technology Inc.
FIGURE 9-13: I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT < 0>)
SSPOV (SSPCON<6>)
S1 234 56 789 1 23456789 12345 789 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus Master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP
CKP
written
to ‘1’ in
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur.
software
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock Clock is not held low
because ACK = 1
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
2001 Microchip Technology Inc. Advance Information DS39582A-page 91
PIC16F87XA
FIGURE 9-14: I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0 >)
S123456 789 1 23456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
(PIR1<3>) Cleared in software
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
UA (S SP S TA T<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus Master
terminates
transfer
D2
6
ACK
Clear ed in software Cleared in software
SSPOV (SSPCON<6>)
CKP written to ‘1’
Note: An update of the SSP A DD
register before the falling
edge of the ninth clock will
have no effect on UA, and
UA will remain set.
Note: An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA, and
UA will remain set. in software
Clock is held low until
update of SSPADD has
taken place
of ninth clock.
of ninth clock.
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Dummy read of SSPBUF
to clear BF flag
Clock is held low until
CKP is set to ‘1’ Clock is not held low
because ACK = 1
PIC16F87XA
DS39582A-page 92 Advance Information 2001 Microchip Technology Inc.
9.4.5 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is su ch that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Ena ble bit (GCEN) is enabled (SSPCON2< 7>
set). Following a START bit detect, 8-bits are shifted
into the SSPSR and the address is compared against
the SSPADD. It is also compared to the general call
address and fixed in hardware.
If the general call address matches, the SSPSR is
transferre d to the S SPBUF, the BF f lag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF interrupt flag bit is set.
When the i nterrupt is s ervic ed, t he sou r ce f or the int er-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the secon d half of the address to match , and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set, and the slave will begin receiving data after the
Acknowledge (Figure 9-15).
FIGURE 9-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
SDA
SCL S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
Cleared in software
SSPBUF is read
R/W = 0ACK
General Call Address
Address is compared to General Call Address
GCEN (SSPCON2<7>)
Receiving data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt
’0’
’1’
2001 Microchip Technology Inc. Advance Information DS39582A-page 93
PIC16F87XA
9.4.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I2C bus may be taken w hen the
P bit is set or the bus is IDLE, with both the S and P bit s
clear.
In Firmware Controlled Master mode, user code con-
ducts all I2C bus operations based on START and
STOP bit conditions.
Once Master mode is enabled, the user has six
options.
1. Assert a START condition on SDA and SCL.
2. Assert a Repeated START condition on SDA
and SCL.
3. Write to the SSPBUF register, initiating trans-
mission of data/add res s.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a STOP Condition on SDA and SCL.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
•START condition
•STOP condition
•Data transfer byte transmitted/received
•Acknowledge Transmit
•Repeat ed START
FIGURE 9-16: MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Note: The MSSP modu le, when configure d in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indic ating tha t a write
to the SSPBUF did not occur.
Read Write
SSPSR
Start bit, Stop bit,
START bi t Detect
SSPBUF
Internal
Data Bus
Set/Reset, S, P, WCOL (SSPSTAT)
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
STOP b i t Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL
SCL In
Bus Collision
SDA In
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SS PIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0
PIC16F87XA
DS39582A-page 94 Advance Information 2001 Microchip Technology Inc.
9.4.6.1 I2C Master Mode Operation
The master device generates all of the serial clock
pulses and th e START and ST OP c onditi ons. A trans-
fer is ended with a STOP condition or with a repeated
START condition . Since th e repeate d START cond ition
is also the beginning of the next serial transfer, the I2C
bus will not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
recei vin g dev ice ( 7 bits) and the Rea d/Writ e (R/ W) bit.
In this case, the R/W bit will be logic ’0’. Serial data is
transmi tted 8 b it s at a ti me . Afte r each byte is trans mit-
ted, an Ac knowledge bit is rec eived. START and ST OP
conditions are output to indicate the beginning and the
end of a serial tran sfer.
In Master Rec eive mode, t he first byte transm itted con-
tains the slave address of the transmitting device
(7 bit s) and the R /W bit. In this case, the R/W bit wil l be
logic ’1’. Thus, the first byte transmitted is a 7-bit slave
addr ess fol lowed by a ’1’ to indicate receive bit. Serial
data is rece ived via S DA, while SCL o utp uts the se ri al
clock. Seria l data is receive d 8 bits at a time. After eac h
byte is received, an Acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
The baud rate gen erator use d for the SPI mode ope ra-
tion is used to set the SCL clock frequency for either
100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 9.4.7 (“Baud Rate Generator”) for more detail.
A typical transmit sequence would go as follows:
1. The user generates a START Condition by set-
ting the START enable bit, SEN
(SSPCON2<0>).
2. SSPIF is set. The MSSP module will wait the
required START time b efore any other o peration
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shifte d out the SDA pin unt il all 8 bits
are transmitted.
5. The MSSP Module shift s in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP modul e gene rates an int errupt at the
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shift ed out the SDA pin unt il all 8 bits are
transmitted.
9. The MSSP Module shift s in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP mo dule g enerate s an interrup t at th e
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
11. The user generates a STOP condition by setting
the STOP enable bit, PEN (SSPCON2<2>).
12. Interrupt is generated once the STOP condition
is complete.
2001 Microchip Technology Inc. Advance Information DS39582A-page 95
PIC16F87XA
9.4.7 BAUD RATE GENERATOR
In I2C Master mode, the baud rate generator (BRG)
reload value is placed in the lower 7 bits of the
SSP ADD register (Figure 9-17). When a write occurs to
SSPBUF, the baud rate generator will automatically
begin counting. The BRG counts down to 0 and stops
until an other re load h as t aken pl ace. Th e BRG c ount i s
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete, (i.e. transmis-
sion of th e last dat a bit is followed by ACK), the int ernal
clock will automatically stop counting and the SCL pin
will rema in in it s last state.
Table 15-3 demonstrates clock rates based on instruc-
tion cycles and the BRG value loaded into SSPADD.
FIGURE 9-17: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 9-3: I2C CLOCK RATE W/BRG
SSPM3:SSPM0
BRG Down Counter
CLKOUT FOSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control Reload
FCY FCY*2BRG VALUE FSCL
(2 rollovers of BRG)
10 MHz 20 MHz 19h 400 kHz(1)
10 MHz 20 MHz 20h 312.5 kHz
10 MHz 20 MHz 3Fh 100 kHz
4 MHz 8 MHz 0Ah 400 kHz(1)
4 MHz 8 MHz 0Dh 308 kHz
4 MHz 8 MHz 28h 100 kHz
1 MHz 2 MHz 03h 333 kHz(1)
1 MHz 2 MHz 0Ah 100 kHz
1 MHz 2 MHz 00h 1 MHz(1)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
PIC16F87XA
DS39582A-page 96 Advance Information 2001 Microchip Technology Inc.
9.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any
receive , transm it or Repeated START/STO P condi tion,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin i s actu all y s am ple d hi gh. W hen the SC L p in i s
sample d high, the baud rate genera tor is reloa ded wi th
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 15-18).
FIGURE 9-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
SCL de-asserted but slave holds
DX-1DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count.
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration) SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
2001 Microchip Technology Inc. Advance Information DS39582A-page 97
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9.4.8 I2C MASTER MODE START
CONDITION TIMING
To initiate a START co nditio n, the user set s the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pin s are sa mp led hig h, th e ba ud ra te g enera-
tor is reloaded with the contents of SSPADD<6:0> and
starts it s count. If SCL and SDA are both sampl ed hig h
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the baud rate generator is suspended,
leavin g the SDA l ine h eld low and the START cond ition
is complete.
9.4.8.1 WCOL Status Flag
If the user writes the SSPBUF when a START
sequenc e is in pro gress , the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-19: FIRST START BIT TIMING
Note: If, a t the begi nning of the START cond ition,
the SDA and SCL pins are already sam-
pled low, or if during the START condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag
BCLIF is set, the START condition is
aborted, and the I2C mo dule is rese t into it s
IDLE state.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
conditi on is complete .
SDA
SCL
S
TBRG
1st Bit 2nd Bit
TBRG
SDA = 1, At completion of START bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
Hardware clears SEN bit
TBRG
Write to SEN bit occurs here. Set S bit (SSPSTAT<3>)
and sets SSPIF bit
PIC16F87XA
DS39582A-page 98 Advance Information 2001 Microchip Technology Inc.
9.4.9 I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is programmed high and the I2C
logic mo dule is in the IDLE sta te. When the RSEN bit is
set, the SCL pin is asserted low. When the SCL pin is
sample d low , the bau d rate generato r is loaded w ith the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generato r count (TBRG). When the baud rat e genera tor
tim es out, if S DA is sampl ed hi gh, t he SC L pin w ill be
de-asserted (brought high). When SCL is sampled
high, the baud rate generator is reloaded with the con-
tents of SSPADD<6:0> and begins counting. SDA and
SCL mu st be samp led high f or one TBRG. Thi s action i s
then foll owed by asserti on of the SDA pin (SD A = 0) for
one TBRG, while SCL is high . Foll owin g thi s, the RSEN
bit (SSPCON2<1>) will be automatically cleared and
the baud rate generator will not be reloaded, leaving
the SDA pin h eld lo w. As soon as a START cond ition i s
detected on the SDA and SCL pins, the S bit
(SSPSTA T<3>) will be set. The S SPIF bit will no t be set
until the baud rate generator has timed out.
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the use r may then transmit an additional eight
bits of add ress (1 0-bit mod e), or ei ght bi ts o f dat a (7-b it
mode).
9.4.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
FIGURE 9-20: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated
START condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
SDA
SCL
Sr = Repeated START
Write to SSPCON2
Writ e to SSPBUF occurs here.
Falling edge of ninth clock
End of Xmit
At completion of START bit,
hardware clear RSEN bit
1st Bit
Set S (SSPSTAT<3>)
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change) SCL = 1
occurs here.
TBRG TBRG TBRG
and set SSPIF
2001 Microchip Technology Inc. Advance Information DS39582A-page 99
PIC16F87XA
9.4.10 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is acc omplished by simpl y
writing a value to the SSPBUF register. This action will
set the buffer full flag bit, BF, and allow the baud rate
generato r to begin counting and start the next transmis-
sion. Each bit of address/data will be shifted out onto
the SDA pin after the falling edge of SCL is asserted
(see data hold time specification parameter #106). SCL
is held low for one baud rate generator rollover count
(TBRG). Data should be valid before SCL is released
high (see Data setup time specification parameter
#107). W hen the SCL pin is released h igh, it is held that
way for TBRG. The data on the SDA pin must remain
stable for that duration and some hold time after the
next falling edge of SCL. After the eighth bit is shifted
out (the falling edge of the eighth clock), the BF flag is
clear ed a nd th e ma ste r rel eas es SD A. T his allo ws t he
slave device being addressed to respond with an ACK
bit during the ninth bit time, if an address match
occurred or if data was received properly. The status
of ACK is written in to the ACKDT bit on the fallin g edge
of the ninth clock. If the m aster receives an Acknowl-
edge, the Acknowledge status bit, ACKSTAT, is
cleared. If not, the bit is set. After the ninth clock, the
SSPIF bit is s et and the master c lock (b aud ra te gen er-
ator) is suspended until the next data byte is loaded
into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 9-21).
After the write to the SSPBUF, each bit of address will
be shifte d out on the falling edge of SCL, until all s even
address bits and the R/W bit ar e complet ed. On the fall-
ing edge of the eighth clock, the master will de-assert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was rec ognized by a sla ve. The st atus of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the baud rate generator is turned off until
another write to the SSPBUF takes p lace, holdi ng SCL
low and allowing SDA to float.
9.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
9.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress, (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t oc cur).
WCOL must be cleared in software.
9.4.10.3 ACKSTAT Status Flag
In T ran smit mod e, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the slave does Not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
9.4.11 I2C MASTER MODE RECEPTION
Master mode recepti on is enabl ed by progra mmin g the
receive enable bit, RCEN (SSPCON2<3>).
The baud rate generat or be gi ns c ou nti ng, and on e ac h
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF fl ag bit is se t and the b aud rate g ene ra-
tor is suspended from counting, holding SCL low. The
MSSP is now in IDLE state, awaiting the next com-
mand. W hen th e buf fer is re ad by th e C PU, the BF fla g
bit is aut om atic al ly c lea red. The u se r c an the n s en d a n
Acknowledge bit at the end of reception, by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>).
9.4.11.1 BF Status Flag
In receiv e op eration, the BF bit is set w he n an add res s
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
9.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previo us reception.
9.4.11.3 WCOL Status Fl ag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a dat a
byte), th e WCOL bi t is set an d the conte nts of th e buffer
are unchanged (the write doesn’t occur).
Note: The MSSP Module must be in an IDLE
state before the RCEN bit is set, or the
RCEN bit will be disregarded.
PIC16F87XA
DS39582A-page 100 Advance Information 2001 Microchip Technology Inc.
FIGURE 9-21: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7D6D5D4D3D2D1D0
ACK
Transmitting Data or Second Half
R/W = 0Transmit Address to Slave
123456789 123456789 P
Cleared in software service routine
SSPBUF is written in software
From SSP inter rupt
After START condition SEN cl eared by hardware.
S
SSPBUF written with 7-bit address and R/W
start transmit
SCL held low
while CPU
responds to SSPIF
SEN = 0
of 10-bit Address
Write SSPCON2<0> SEN = 1
START condition begins From Slave, clear ACKSTAT bit SSPCON2<6>
ACKSTAT in
SSPCON2 = 1
Cleared in softwar e
SSPBUF written
PEN
Cleared in software
R/W
2001 Microchip Technology Inc. Advance Information DS39582A-page 101
PIC16F87XA
FIGURE 9-22: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 12345678912345678 9 1234
Bus Master
terminates
transfer
ACK Receiving Data from Slave
Receiving Data from Slave D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 1
Transmit Address to Slave
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1)
Write to SSPBUF occurs here AC K f rom Slave
Master configured as a receiver
by programming SSPCON2<3>, (RCEN = 1) PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared in software
S t art XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Clear ed in software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
Cleared in
software
ACK from Master
Set SS PIF at end
Set SSPIF interrupt
at end of Acknowledge
sequence
Set SSPIF interrupt
at end of Acknow-
ledge sequence
of receive
Set ACKEN, start Acknowledge sequence
SSPOV is set because
SSPBUF is still full
SDA = ACK DT = 1
RCEN cleared
automatically
RCEN = 1 START
next receive
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
responds to SSPIF
ACKEN
Begin START Condition
Cleared in software
SDA = ACKDT = 0
PIC16F87XA
DS39582A-page 102 Advance Information 2001 Microchip Technology Inc.
9.4.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
is presented on t he SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (TBRG) and
the SCL pin is de-asserted (pulled high). When the SCL
pin is sampled high (clock arbitration), the baud rate
genera tor counts for T BRG. The SCL pi n is then p ulled
low. Following this, the ACKEN bit is automatically
cleared, the baud rate generator is turned off and the
MSSP module then goes into IDLE mode (Figure 9-23).
9.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffe r are unch ang ed (the write doe sn’t
occur).
9.4.13 STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit, by setting the ST OP sequence enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert th e SDA line low. When the SDA line is s am-
pled low, the baud rate generator is reloaded and
count s dow n to 0. Wh en th e bau d rat e gen era t or ti me s
out, the SCL pin will be brought high, and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be de-a sserted. Wh en the SDA pin is sa mpled hig h
while SCL is high, the P bit (SSPSTAT<4>) is set. A
TBRG later, the PEN bit is cleared and the SSPIF bit is
set (Figure 9-24).
9.4.13.1 WCOL Status Flag
If the use r writes t he SSPBUF when a STO P sequenc e
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-23: ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 9-24: STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: TBRG = one baud rate generator period.
SDA
SCL
Set SSPIF at the end
Acknowledge sequence starts here,
Write to SSPCON 2 ACKEN automatically cleared
Cleared in
TBRG TBRG
of receive
ACK
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software Set SSPIF at the end
of Acknowledge sequence
Cleared in
software
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2
Set PEN
Falling edg e of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL brought high after TBRG
Note: TBRG = one baud rate generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set
TBRG
to setup STOP condition.
ACK
P
TBRG
PEN bit (SSPCON2<2>) is clea red by
hardw ar e and the SSPIF bit is set
2001 Microchip Technology Inc. Advance Information DS39582A-page 103
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9.4.14 SLEEP OPERATION
While in SLEEP mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).
9.4.15 EFFECT OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
9.4.16 MULT I-MAST ER MODE
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP modul e is dis abl ed . Control of the I2C
bus may be taken when the P bit (SSPST AT<4>) is set,
or the bus is IDLE, with both the S and P bits clear.
When the bus is busy, enabling the SSP Interrupt will
generate the interrupt when the STOP condition
occurs.
In multi-master operation, the SDA line must be moni-
tored for arbitration, to see if the signal level is at the
expect ed output level. This c heck is perfo rmed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
•Address Transfer
•Data Transfer
•A START Condition
•A Repeated START Condition
•An Acknowledge Condition
9.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION, AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA by letting SDA float high and
another m as ter as serts a '0'. Whe n the SCL pi n fl oats
high, data should be stable. If the expected data on
SDA is a '1' an d the da ta s ampled o n the SDA pi n = '0',
then a bus collision has taken pl ace. The master wil l set
the Bus Collision Interrupt Flag, BCLIF, and reset the
I2C port to its IDLE state (Figure 9-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF c an be writte n to. W hen the user se rvices
the bus collision Interrupt Service Routine, and if the
I2C bus is free, the user c an resume com municati on by
asserting a START cond ition.
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de- assert ed, and t he respe ctiv e contro l bit s in
the SSPCON2 registe r are cleared. When the user s er-
vices the bus collision Interrupt Service Routine, and if
the I2C bus is free, the use r can resume commun ication
by asserting a START condition.
The Master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be t aken when the P bit is set in the SSPSTAT
register, or the bus is IDLE and the S and P bits are
cleared.
FIGURE 9-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source Sample SDA. While SCL is high
data doesn’t match what is driven
Set bus collision
interrupt (BCLIF).
by the master. Bus collision has occurred.
by master
Data changes
while SCL = 0
PIC16F87XA
DS39582A-page 104 Advance Information 2001 Microchip Technology Inc.
9.4.17.1 Bus Collision During a START
Condition
During a START condition, a bus collision occurs if:
a) SDA or SCL are s ampled low a t the beginni ng of
the START condition (Figure 9-26).
b) SCL is sampl ed l ow before SDA is as se rted low
(Figure 9-27).
During a START condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
•the START condition is aborted,
•the BCLIF flag is set, and
• the MSSP module is reset to its IDLE state
(Figure 9-26).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' du ring the START condit ion.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-28). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
count s down to 0, and during thi s time, if the SCL pin is
sampled as '0', a bus collision does not occur. At the
end of t he BRG co unt , the SCL pin is a sserted low.
FIGURE 9-26: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The re ason that bus coll ision is not a fact or
during a START condition, is that no two
bus mas ters can ass ert a START co ndition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This con dit ion does not c aus e a bu s
collis ion, because the two masters must be
allow ed to arbitrate t he first addres s follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START or STOP conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into IDLE state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable START
condition if SDA = 1, SCL=1
SDA = 0, SCL = 1
BCLIF
S
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software.
SSPIF and BCLIF are
cleared in software.
Set BCLIF,
START condition. Set BCLIF.
2001 Microchip Technology Inc. Advance Information DS39582A-page 105
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FIGURE 9-27: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 9-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN bus collision occurs. Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable START
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleared
in software.
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time-out,
’0’’0’
’0’’0’
SDA
SCL
SEN
Set S
Set SEN, enable START
sequence if SDA = 1, SCL = 1
Less th an TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
in software.
Set SS PIF
SDA = 0, SCL = 1
SDA pulled low by other master .
Reset BRG and assert SDA.
SCL pulled low after BRG
time-out
Set SS PIF
’0’
PIC16F87XA
DS39582A-page 106 Advance Information 2001 Microchip Technology Inc.
9.4.17.2 Bus Collision During a Repeated
START Condition
During a Repeated START condition, a bus collision
occu rs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low, indi-
cating that anoth er master is attempting to trans-
mit a data ’1’.
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>
and counts down to 0. The SCL pin is then de-asserte d,
and when sampled high, the SDA pin is sampled.
If SDA is l ow , a bus collision h as occurred (i. e., another
master is attempting to transmit a data ’0’, Figure 9-29).
If SDA is sampled high, the BRG is reloaded and
begins counting. If SDA goes from high to low before
the BRG t imes out, n o bus co llisi on occ urs bec ause no
two masters can assert SDA at exactly the same time.
If SCL goes from hig h to low bef ore th e BRG time s o ut
and SDA has not al ready been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ’1’ during the Repeated START condi-
tion (Figure 9-30).
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is
complete.
FIGURE 9-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 9-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared in software
'0'
'0'
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleare d
in software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
’0’
2001 Microchip Technology Inc. Advance Information DS39582A-page 107
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9.4.17.3 Bus Collision During a STOP
Condition
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),
the baud rate generator is loaded with SSPADD<6:0>
and count s dow n to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a d ata ’0’ (Figure 9-31). If the S CL pi n is s am ple d
low before SDA is allowed to float high, a bus collision
occurs. This is another case of anot her master attempt-
ing to drive a data ’0’ (Figure 9-32).
FIGURE 9-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 9-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
set BCLIF.
’0’
’0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high,
set BCLIF.
’0’
’0’
PIC16F87XA
DS39582A-page 108 Advance Information 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. Advance Information DS39582A-page 109
PIC16F87XA
10.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O mo dules . (USA RT is als o kno wn as a S erial Com-
munications Interface or SCI.) The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and perso nal comp uters, or it can be confi gured
as a half duple x s yn chronous s y ste m th at c an commu-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, serial EEPROMs etc.
The USART can be configured in the following modes:
•Asynchronous (full duplex)
•Synchronous - Master (half duplex)
•Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchro-
nous Receiver Transmitter.
The USART module also has a multi-processor com-
munication capability using 9-bit address detection.
REGISTER 10-1: TXST A: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC —BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: Clock Sourc e Sele ct bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 Unimplemented: Read as '0'
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data, can be Parity bit
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582A-page 110 Advance Information 2001 Microchip Technology Inc.
REGISTER 10-2: RCST A: RECEIVE ST ATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - Slave:
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and load of the receive buffer when
RSR<8> is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user firmware)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc. Advance Information DS39582A-page 111
PIC16F87XA
10.1 USART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for diff eren t US ART modes whic h on ly a ppl y
in Master mode (internal clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculate d
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
becaus e the FOSC/(16(X + 1)) equat ion c an red uce th e
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
10.1.1 SAMPLING
The dat a on the RC7/RX/D T pin is sa mpled three time s
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
TABLE 10-1: BAUD RATE FORMULA
TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0
1(Asynchronous) Baud Rate = F OSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1)) Baud Rate = FOSC/(16(X+1))
N/A
X = value in SPBRG (0 to 255)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on :
POR,
BOR
Value on
all other
RESETS
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
99h SPB RG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
PIC16F87XA
DS39582A-page 112 Advance Information 2001 Microchip Technology Inc.
TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD
RATE
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal)
0.3------- --
1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129
2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64
9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15
19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7
28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4
33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4
57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2
HIGH 1.221 - 255 0.977 - 255 0.610 - 255
LOW 312.500 - 0 250.000 - 0 156.250 - 0
BAUD
RATE
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal) KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3 0.300 0 207 0.3 0 191
1.2 1.202 0.17 51 1.2 0 47
2.4 2.404 0.17 25 2.4 0 23
9.6 8.929 6.99 6 9.6 0 5
19.2 20.833 8.51 2 19.2 0 2
28.8 31.250 8.51 1 28.8 0 1
33.6 - - - - - -
57.6 62.500 8.51 0 57.6 0 0
HIGH 0.244 - 255 0.225 - 255
LOW 62.500 - 0 57.6 - 0
TABLE 10-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD
RATE
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal)
0.3---------
1.2---------
2.4 - - - - - - 2.441 1.71 255
9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64
19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31
28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21
33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18
57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10
HIGH 4.883 - 255 3.906 - 255 2.441 - 255
LOW 1250.000 - 0 1000.000 0 625.000 - 0
BAUD
RATE
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal) KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3------
1.2 1.202 0.17 207 1.2 0 191
2.4 2.404 0.17 103 2.4 0 95
9.6 9.615 0.16 25 9.6 0 23
19.2 19.231 0.16 12 19.2 0 11
28.8 27.798 3.55 8 28.8 0 7
33.6 35.714 6.29 6 32.9 2.04 6
57.6 62.500 8.51 3 57.6 0 3
HIGH 0.977 - 255 0.9 - 255
LOW 250.000 - 0 230.4 - 0
2001 Microchip Technology Inc. Advance Information DS39582A-page 113
PIC16F87XA
10.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one START bit, eight or nine data
bits, and one STOP bit). The most common data format
is 8-bits. An on-chip, dedicated, 8-bit baud rate gener-
ator can be used to de rive st and ard baud rate freque n-
cies from the oscillator. The USART transmits and
receive s t he L S b fi rst. The t r ans mitte r and rec eiv er a re
functio nally in dependen t, but use the sam e dat a format
and baud rate. The baud rate generator produces a
clock, either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardw are, but can be implemente d in software (an d
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
•Baud Rate Ge nera tor
•Sampling Circuit
•Asynchronous Transmitter
•Asynchronous Receiver
10.2.1 USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-1. The hea rt of the tr ansmi tter is the trans mit
(serial) shift regist er (TSR). The shi ft register ob tains it s
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY) , th e T XREG r egi ster is empt y and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
( PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will re set only wh en ne w dat a is loa ded i nto the
TXREG register . While flag bit TXIF indicates the statu s
of the TXREG register , another bit, TRMT (TXST A<1>),
shows the status of the TSR register. Status bit TRMT
is a re ad onl y bit, wh ic h i s se t w he n the TSR r egi ste r i s
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR
register is empty.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 10-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 10-3).
Clearing enable bit TXEN during a transmission will
cause the tra nsm is s ion to be ab orte d a nd will re se t th e
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can resu lt in an immediate tra nsfer of the dat a to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit T XIF is set when en able bit TXEN
is set. TXIF is cle ared by loadi ng TXREG.
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG Register
TSR Register
(8) 0
TX9
TRMT SPEN
RC6/TX/CK pin
Pin Buffer
and Control
8
• • •
PIC16F87XA
DS39582A-page 114 Advance Information 2001 Microchip Technology Inc.
When setting up an Asynchronous Transmission,
follow these steps:
1. Initialize the SPBRG re gis te r for the ap prop ria te
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts trans-
mission).
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
FIGURE 10-2: ASYNCHRONOUS MASTER TRANSMISSION
FIGURE 10-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Valu e on:
POR,
BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USA RT Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
Word 1 STOP Bit
Word 1
Trans m i t Sh i f t R e g
START Bit Bit 0 Bit 1 Bit 7/8
Write to TXREG Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF b it
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
START Bit STOP Bit STAR T Bit
Transmit Shift Reg.
Word 1 Word 2
Bit 0 Bit 1 Bit 7/8 Bit 0
Note: This timing diagram shows two consecutive transmissions.
2001 Microchip Technology Inc. Advance Information DS39582A-page 115
PIC16F87XA
10.2.2 USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 10-4.
The data is receiv ed on th e R C7/R X/DT p in an d dri ve s
the data recovery block. The data recovery block is
actuall y a high speed s hifter , operating at x16 tim es the
baud rate; whereas, the main receive serial shifter
operates at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setti ng bit CRE N (RCSTA<4>).
The heart of the rece iver is the r eceive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is tra nsferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR 1<5 >) i s se t. Th e ac tua l in ter ru pt c an be enab led /
disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit, which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register (i.e., it is a two deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the STOP bit of the third byte, if the RCREG register is
still f ull, the overrun error bit OE RR (RCSTA<1>) will b e
set. The word in the RSR will be lost. The RCREG reg-
ister can be read twice to retrieve the two bytes in the
FIFO. O verrun bit OE RR ha s to b e clea red in softwar e.
This is done by resetting the receive logic (CREN is
cleared and then s et). If bit O ERR is s et, tran sfers from
the RSR register to the RCREG register are inhibited,
and no further data will be received. It is therefore,
essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a STOP bit is
detected as cle ar. Bit FERR and the 9th re cei ve bit a re
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values , the refo re, it is essent ial for the us er to re ad th e
RCSTA regis ter befo re reading the RCREG register in
order not to lose the old FERR and RX9D inform ation .
FIGURE 10-4: USA RT RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
÷64
÷16
or STOP START
(8) 710
RX9
• • •
FOSC
PIC16F87XA
DS39582A-page 116 Advance Information 2001 Microchip Technology Inc.
FIGURE 10-5: ASY NCHR ONOUS RECEPTION
When setting up an Asynchronous Reception, follow
these steps:
1. Initialize the SPBRG re gis te r for the ap prop ria te
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF wi ll b e se t w he n reception is com-
plete an d an interru pt will be generate d if enabl e
bit RCIE is set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
START
bit bit7/8
bit1bit0 bit7/8 bit0STOP
bit
START
bit START
bit
bit7/8 STOP
bit
RX (pin)
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG Word 2
RCREG
STOP
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Valu e on
all othe r
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
2001 Microchip Technology Inc. Advance Information DS39582A-page 117
PIC16F87XA
10.2.3 SETTING UP 9-BIT MODE WITH
ADDR ES S DET E C T
When setting up an Asynchronous Reception with
Address Detec t Enab led :
•Initialize the SPBRG register for the appropriate
baud r ate. If a high spee d baud rate is desire d, set
bit BRGH.
•Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
•If interrupts are desired, then set enable bit RCIE.
•Set bit RX9 to enable 9-bit reception.
•Set ADDEN to enable address detect.
•Enable the reception by setting enable bit CREN.
•Flag bit RCIF will be set when reception is com-
plete, and an interrupt will be generated if enable
bit RCIE was set.
•Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
•Read the 8-bit received data by reading the
RCREG register, to determine if the device is
being addressed.
•If any error occurred, clear the error by clearing
enable bit CREN.
•If the device has been addressed, clear the
ADDEN bi t to al low da t a b yte s an d address b ytes
to be rea d into the receive buf fer, and interrupt the
CPU.
FIGURE 10-6: USA RT RECEIVE BLOCK DIAGRAM
x64 B aud R ate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
÷ 64
÷ 16
or STOP START
(8) 710
RX9
• • •
RX9
ADDEN
RX9
ADDEN
RSR<8>
Enable
Load of
Receive
Buffer
8
8
FOSC
PIC16F87XA
DS39582A-page 118 Advance Information 2001 Microchip Technology Inc.
FIGURE 10-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
FIGURE 10-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
START
bit bit1bit0 bit8 bit0STOP
bit
START
bit bit8 STOP
bit
RC7/RX/DT (pin)
Load RSR
Read
RCIF
Word 1
RCREG
Bit8 = 0, Data Byte Bit8 = 1, Address Byte
Note: This timing diagram shows a data byte followed by an add ress byte. The data byte is not read into th e RCREG (receive buffer)
because ADDEN = 1.
START
bit bit1bit0 bit8 bit0STOP
bit
START
bit bit8 STOP
bit
RC7/RX/DT (pin)
Load RSR
Read
RCIF
Word 1
RCREG
Bit8 = 1, Address Byte Bi t8 = 0, Data Byte
Note: This timing diagram shows a da ta byte followed by an address b yte. The data byte is not read into the RCREG (receive buffer)
because ADDEN was not updated and still = 0.
Address Name Bit 7 Bit 6 Bit 5 Bi t 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
2001 Microchip Technology Inc. Advance Information DS39582A-page 119
PIC16F87XA
10.3 USART Synchronous
Master Mode
In Sync hronous Ma ster mode, the data is transmi tted in
a half-duplex manner (i.e., transmission and reception
do not occur at the sa me time). When tran smitting dat a,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode ind icates t hat the pr ocessor transmit s the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
10.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 10-6. The hea rt of the tr ansmi tter is the trans mit
(serial) shift regist er (TSR). The shi ft register ob tains it s
data from the read/write transmit buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is em pty an d inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will re set o nly when ne w dat a i s loaded into the
TXREG register . While flag bit TXIF indicates the st atus
of th e T XR EG r egi st e r, an oth er b it T RMT ( TX STA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
availa ble to the user.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The fir st data bit will be shifte d out on the next av ailable
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 10-9). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Fi gure 10-10). This is a dvant age ous wh en sl ow
baud rates are selected, since the BRG is kept in
RESET when bits TXEN, CREN and SREN are clear.
Setting enable bit TXEN will start the BRG, creating a
shift c lock immed iately. Normal ly, when trans miss ion i s
first started, the TSR register is empty, so a transfer to
the TXREG reg is ter wi ll re su lt i n an immedia te transfer
to TSR, resulting in an empty TXREG. Back-to-back
transfers are possible.
Clearing enable bit TXEN during a transmission will
cause the tra nsm is s ion to be ab orte d a nd will re se t th e
transmitter. The DT and CK pins will revert to hi-
impeda nce. If ei ther bit C REN or bi t SREN is set durin g
a transmis sion , the transm issi on is abor ted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the tran sm itte r, the user has to cle ar bi t TXEN.
If bit SREN is set (t o interrupt an on-goin g trans mission
and rec eive a sing le word ), then after th e single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from hi-
impeda nce Re ceive mode to tran smit an d sta rt driv ing.
To avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to th e TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG re gis ter for the ap prop ria te
baud rate (Section 10.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
PIC16F87XA
DS39582A-page 120 Advance Information 2001 Microchip Technology Inc.
TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
FIGURE 10-9: SY NCHRONOUS TRANSMISS ION
FIGURE 10-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
19h TX REG U SART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SP BRG Baud Rate Generat or Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
bit 0 bit 1 bit 7
Word 1
Q1Q2 Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4Q1Q2 Q3 Q4Q1 Q2 Q3 Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3 Q4Q1 Q2Q3Q4Q1Q2 Q3Q4 Q1Q2 Q3 Q4
bit 2 bit 0 bit 1 bit 7
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
(Inte rru pt Flag )
TXEN bit ’1’ ’1’
Wo rd 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words.
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
bit0 bit1 bit2 bit6 bit7
TXEN b it
2001 Microchip Technology Inc. Advance Information DS39582A-page 121
PIC16F87XA
10.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCST A<5>), or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is c ontinuous until CREN is cleared. If bo th bits are
set, CREN t akes precede nce. After clocking the last bi t,
the received data in the Receive Shift Register (RSR)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, interrupt flag bit RCIF
(PIR 1<5 >) i s se t. Th e ac tua l in ter ru pt c an be enab led /
disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit, which is
reset by the ha rdware . In thi s c ase, it i s r ese t whe n th e
RCREG register has been read and is empty. The
RCREG is a double buffered register (i.e., it is a two
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to beg in shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The ninth
receive bit is buffered the same way as the receive
data. Reading the RCREG register will load bit RX9D
with a new value, therefore, it is essential for the user
to read the RCSTA register before reading RCREG, in
order not to lose the old RX9D information.
When sett ing up a Synchronous Master Reception:
1. Initialize the SPBRG re gis ter for the ap prop ria te
baud rate (Section 10.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF w ill be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all othe r
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
PIC16F87XA
DS39582A-page 122 Advance Information 2001 Microchip Technology Inc.
FIGURE 10-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
10.4 USART Synchronous Slave Mode
Synchronous Slave mo de differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/ CK pin (inst ead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
10.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes is identical, exce pt in the case of the SLEEP mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
When setting up a Synchronous Slave Transmission,
follow these steps:
1. Enable the sync hronous s lave serial p ort by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmissi on is des ired , then set bi t TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
CREN bit
RC7/RX/DT pin
RC6/TX/CK pin
Write t o
bit SREN
SREN b i t
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRG = ’0’.
Q3Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4Q2 Q1 Q2Q3 Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1Q2Q3 Q4
’0’
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
’0’
Q1Q2Q3Q4
2001 Microchip Technology Inc. Advance Information DS39582A-page 123
PIC16F87XA
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
10.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enabl e bit RCIE bit is set, the inte rrupt generate d
will wake the chi p from SLEEP. If the global i nterrupt is
enabled , the program w ill br anch to the int errupt v ector
(0004h).
When setting up a Synchronous Slave Reception, fol-
low t hese steps:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desire d, set ena ble bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF wi ll b e se t w hen rec ept ion is com -
plete and an interrupt will be generated, if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear.
PIC16F87XA
DS39582A-page 124 Advance Information 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. Advance Information DS39582A-page 125
PIC16F87XA
11.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has five
input s for the 28-pin devi ces and eight for the 40/44-pi n
devices.
The conversion of an analog input signal results in a
corresponding 10-bit digital number. The A/D module
has high and low voltage reference input, that is soft-
ware selectable to some combination of VDD, VSS,
RA2, or RA3.
The A/D converter has a unique feature of being able
to opera te while th e device i s in SLEEP mod e. To op er-
ate in SLEEP, the A/D clock must be derived from the
A/D’s internal RC oscillator.
The A/D module has four registers. These registers are:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register0 (ADCON0)
• A/D Control Register1 (ADCON1)
The ADCON0 register, shown in Register 11-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage refer-
ence), or as digital I/O.
Addition al informa tion on usi ng the A/D mo dul e c an b e
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023).
REGISTER 11-1: ADCON0 REGIST ER (ADDRESS 1Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON
bit 7 bit 0
bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)
bit 5-3 CHS2:CHS0: Analog Channel Select bits
000 = Channel 0 (AN0)
001 = Channel 1 (AN1)
010 = Channel 2 (AN2)
011 = Channel 3 (AN3)
100 = Channel 4 (AN4)
101 = Channel 5 (AN5)
110 = Channel 6 (AN6)
111 = Channel 7 (AN7)
Note: The PIC16F873A/87 6A devices only im plement A/D c hannels 0 through 4; the unimplemented
selections are reserved. Do not select any unimplemented channels with these devices.
bit 2 GO/DONE: A/ D Conversion Status bit
When ADON = 1:
1 = A /D conversion in progress (setting this bit starts the A/D conversion which is automatically
cleared by hardware when the A/D conversion is complete)
0 = A /D conve rsion not in progress
bit 1 Un im plemen ted : Read as ’0’
bit 0 ADON: A/D On bit
1 = A/D converter module is powered up
0 = A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit W = Writabl e bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
ADCON1
<ADCS2> ADCON0
<ADCS1:ADCS0> Clock Conversion
000 FOSC/2
001 FOSC/8
010 FOSC/32
011 FRC (clock derived from the internal A/D RC oscillator)
100 FOSC/4
101 FOSC/16
110 FOSC/64
111 FRC (clock derived from the internal A/D RC oscillator)
PIC16F87XA
DS39582A-page 126 Advance Information 2001 Microchip Technology Inc.
REGISTER 11-2: ADCON1 REGIST ER (ADDRESS 9Fh)
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select.bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.
bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in shaded area and in bold)
bit 5-4 Unimplemented: Read as '0'
bit 3-0 PCFG3:PCFG0: A/D Port Configura tion Control bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: On any dev ice RESET, the port pin s that a re mult iplexed wi th anal og func tions (A Nx)
are forced to be an analog input.
ADCON1
<ADCS2> ADCON0
<ADCS1:ADCS0> Clock Conversion
000 FOSC/2
001 FOSC/8
010 FOSC/32
011 FRC (clock derived from the internal A/D RC oscillator)
100 FOSC/4
101 FOSC/16
110 FOSC/64
111 FRC (clock derived from the internal A/D RC oscillator)
A = Analog input D = Digital I/O
C / R = # of analog input channels / # of A/D voltage references
PCFG
<3:0> AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+VREF-C / R
0000 AAAA A A AAVDD VSS 8 / 0
0001 AAAAV
REF+A A AAN3VSS 7 / 1
0010 DDDA A A AAVDD VSS 5 / 0
0011 DDDAVREF+A A AAN3VSS 4 / 1
0100 DDDD A D AAV
DD VSS 3 / 0
0101 DDDDVREF+D A AAN3VSS 2 / 1
011x DDDD D D DD ——0 / 0
1000 AAAAV
REF+VREF- A A AN3 AN2 6 / 2
1001 DDAA A A AAVDD VSS 6 / 0
1010 DDAAVREF+A A AAN3VSS 5 / 1
1011 DDAAV
REF+VREF- A A AN3 AN2 4 / 2
1100 DDDAVREF+VREF- A A AN3 AN2 3 / 2
1101 DDDDVREF+VREF- A A AN3 AN2 2 / 2
1110 DDDD D D DAV
DD VSS 1 / 0
1111 DDDDVREF+VREF- D A AN3 AN2 1 / 2
2001 Microchip Technology Inc. Advance Information DS39582A-page 127
PIC16F87XA
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D convers ion. When the A/D conver sion
is compl ete, the re sult is loaded i nto this A/D re sult reg-
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/ D interrup t flag bit ADIF i s set. The bl ock dia-
gram of the A/D module is shown in Figure 11-1.
After the A/D module has been configured as desired,
the sele cted cha nne l m ust be acq uire d b efore the co n-
version is started. The analog input channels must
have the ir corres pondin g TRIS bi ts selected a s input s.
To determine sample time, see Section 11.1. After this
acquisition time has elapsed, the A/D conversion can
be started.
These steps should be followed for doing an A/D
Conversion:
1. Configu re the A/D module:
•Configure analog pins/voltage reference and
digital I/O (ADCON1)
•Select A/D input channel (ADCON0)
•Select A/D conversion clock (ADCON0)
•Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
•Clear ADIF bit
•Set ADIE bit
•Set PEIE bit
•Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
•Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
•Polling for the GO/DONE bit to be cleared
(with interrupts enabled); OR
•Waiting for the A/D interrupt
6. Read A/D result register pair
(ADRESH:ADRESL), clear bit ADIF, if required.
7. For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
defined as TAD.
FIGURE 11-1: A/D BLOCK DIAGRAM
(Input Voltage)
VAIN
VREF+
(Reference
Voltage)
VDD
PCFG3:PCFG0
CHS2:CHS0
RE2/AN7(1)
RE1/AN6(1)
RE0/AN5(1)
RA5/AN4
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
111
110
101
100
011
010
001
000
A/D
Converter
Note 1: Not available on 28-pin devices.
VREF-
(Reference
Voltage) VSS
PCFG3:PCFG0
PIC16F87XA
DS39582A-page 128 Advance Information 2001 Microchip Technology Inc.
11.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input mode l is shown in Figure 1 1-2. The source
impeda nce (RS) and the inte rnal sam pling swi tch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 11-2. The maximum recommended imped-
ance for analog sources is 10 kΩ. As the impedance
is decreased, the acquisition time may be decreased.
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be sta r ted .
To calculate the minimum acquisition time,
Equation 11-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 st eps for the A/D). The
1/2 LSb er ror is the ma ximu m error allow ed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range Reference Manual
(DS33023).
EQUATION 11-1: ACQUISITION TIME
FIGURE 11-2: ANALOG INPUT MODEL
TACQ
TC
TACQ
=
=
=
=
=
=
=
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
TAMP + TC + TCOFF
2µs + TC + [(Temperature -25°C)(0.05µs/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120p F (1k Ω + 7kΩ + 10kΩ) In(0.0004885)
16.47µs
2µs + 16.47µs + [(50°C -25°C)(0.05µs/°C)
19.72µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
CPIN
VA
RSANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I LEAKAGE
RIC ≤ 1K
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
567891011
(kΩ)
VDD
= 120 pF
± 500 nA
Legend CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
2001 Microchip Technology Inc. Advance Information DS39582A-page 129
PIC16F87XA
11.2 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The seven possible options for TAD
are:
•2TOSC
•4TOSC
•8TOSC
•16TOSC
•32TOSC
•64TOSC
•Internal A/D module RC osc il lat or (2-6 µs)
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 11-1 shows the resultant TAD times der ived f rom
the device operating frequencies and the A/D clock
sour ce se lec ted .
11.3 Configuring Analog Port Pins
The ADCON1 and TRI S register s contro l the opera tion
of the A/D port pins. The port pins that are desired as
analog i nputs , must ha ve their corre sponding TRIS bit s
set (input) . If the TRIS bit is cleared (outp ut), the dig ita l
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (ST ANDARD DEVICES (C))
Note 1: When reading the port register, any pin
configu red as an analog inpu t channel wil l
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured inp ut w i ll n ot a ffect the conver-
sion accuracy.
2: Analog le vels on any pin that is defined as
a digital input (including the AN7:AN0
pins), may cause the input buffer to con-
sume current that is out of the device
specifications.
AD Clock Source (TAD) Maximum Device Frequency
Operation ADCS2:ADCS1:ADCS0 Max.
2TOSC 000 1.25 MHz
4TOSC 100 2.5 MHz
8TOSC 001 5 MHz
16TOSC 101 10 MHz
32TOSC 010 20 MHz
64TOSC 110 20 MHz
RC(1 , 2, 3) x11 (Note 1)
Note 1: The R C source ha s a typical TAD time of 4 µs, but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recom-
mended for SLEEP operation.
3: For extended voltage devices (LC), please refer to the Electrical Characteristics (Sections 17.1 and 17.2).
PIC16F87XA
DS39582A-page 130 Advance Information 2001 Microchip Technology Inc.
11.4 A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborte d, the nex t acquis ition on th e select ed channe l
is automa tically st arted. The GO/DONE bit can the n be
set to start the conversion.
In Figure 1 1-3 , after the GO bit is set , the first time seg-
ment has a minimum of TCY and a maximum o f TAD.
FIGURE 11-3: A/D CONVERSION TAD CYCLES
11.4.1 A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D convers ion. Thi s register pair is 16-bit s wide.
The A/D mo dule gives the flexibility to left or right justif y
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figur e 11-4 shows the op erat ion of the A/D r esu lt j ust i-
fication. The extra bits are loaded with ’0’s’. When an
A/D result will not overwrite these locations (A/D dis-
able), these registers may be used as two general
purpose 8-bit registers.
FIGURE 11-4: A/D RESULT JUSTIFICATION
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1TAD2TAD3TAD4 TAD5TAD6
T
AD
7T
AD
8
TAD9
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
b9 b8 b7 b6 b5 b4 b3 b2
TAD10 TAD11
b1 b0
TCY to TAD
Conversion starts
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
10-bit Result
ADRESH ADRESL
0000 00
ADFM = 0
0
2 1 0 77
10-bit Result
ADRESH ADRESL
10-bit Result
0000 00
70 7 6 5 0
ADFM = 1
Right Justified Left Justified
2001 Microchip Technology Inc. Advance Information DS39582A-page 131
PIC16F87XA
11.5 A/D Operation During SLEEP
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switchi ng noise fro m the conv ersion. Whe n the conver-
sion i s comple ted, the GO /DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
When the A/D clock sour ce is anoth er clock optio n (not
RC), a SLEEP instruction will cause the present conver-
sion t o be aborte d and the A/D mod ule to be turned of f,
though the ADON bit will remain set.
Turnin g off the A/D pl ac es the A/D m odu le in its lowes t
current consumption state.
11.6 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion is aborted. All A/D input pins are con-
figured as analog inpu ts.
The value that is in the ADRESH:ADRESL registers is
not modified for a Power-on Reset. The
ADRESH:ADRESL registers w ill cont ain unkno wn data
after a Power-on Reset.
TABLE 11-2: REGISTERS/BITS ASSOCIATED WITH A/D
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the con-
version to occur during SLEEP, ensure the
SLEEP instruction immediately follows the
instruction that sets the GO/DONE bit.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Valu e on
POR,
BOR
Value on
MCLR,
WDT
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON 0000 00-0 0000 00-0
9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
89h(1) TRISE IBF OBF IBOV PSPMODE —PORTE Data Direction bit s 0000 -111 0000 -111
09h(1) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These registers are not available on 28-pin devices.
PIC16F87XA
DS39582A-page 132 Advance Information 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. Advance Information DS39582A-page 133
PIC16F87XA
12.0 COMPARATOR MODULE
The com pa rator modul e con tain s two an al og comp ar a-
tors. The inputs to the comparators are multiplexed
with I/O port pins RA0 through RA3, while the outputs
are mult iplexed to p ins RA4 and RA5. The on-chi p V olt-
age Reference (Section 13.0) can also be an input to
the comparators.
The CMC ON regist er (Registe r 12-1) c ontrols th e com-
parator input and output multiplexers. A block diagram
of the various comparator configurations is shown in
Figure 12-1.
REGISTER 12-1: CMCON REGISTER
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0
bit 7 C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN–
0 = C2 VIN+ < C2 VIN–
When C2INV = 1:
1 = C2 VIN+ < C2 VIN–
0 = C2 VIN+ > C2 VIN–
bit 6 C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN–
0 = C1 VIN+ < C1 VIN–
When C1INV = 1:
1 = C1 VIN+ < C1 VIN–
0 = C1 VIN+ > C1 VIN–
bit 5 C2INV: Co mparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted
bit 4 C1INV: Co mparator 1 Output Inversion bit
1 = C1 Output inverted
0 = C1 Output not inverted
bit 3 CIS: Co mparator Input Switch bit
When CM2:CM0 = 110:
1 = C1 VIN– connects to RA3/AN3
C2 VIN– connects to RA2/AN2
0 = C1 VIN– connects to RA0/AN0
C2 VIN– connects to RA1/AN1
bit 2 CM2:CM0: Comp arator Mode bit s
Figure 12-1 shows the Comparator modes and CM2:CM0 bit settings
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582A-page 134 Advance Information 2001 Microchip Technology Inc.
12.1 Comparator Configuration
There are eight modes of operation for the compara-
tors. The CMCON register is used to select these
modes. Figure 12-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator
mode is cha nged, the c om p ara tor o utput leve l ma y not
be valid for the specified mode change delay shown in
the Electrical Specifications (Section 17.0).
FIGURE 12-1: COMPARATOR I/O OPERATING MODES
Note: Comparator interrupts should be disabled
during a C omp arator mode change. O ther-
wise, a false interrupt may occur.
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 Off (Read as ’0’)
Comparators Reset (POR Default Value)
A
A
CM2:CM0 = 000
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 Off (Read as ’0’)
A
A
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 C1OUT
Two Independent Comparators
A
A
CM2:CM0 = 010
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 C2OUT
A
A
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 C1OUT
Two Common Reference Comparators
A
A
CM2:CM0 = 100
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 C2OUT
A
D
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 Off (Read as ’0’)
One Independent Comparator with Output
D
D
CM2:CM0 = 001
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 C1OUT
A
A
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 Off (Read as ’0’)
Comparators Off
D
D
CM2:CM0 = 111
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 Off (Read as ’0’)
D
D
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 C1OUT
Four Inputs Multiplexed to Two Comparators
A
A
CM2:CM0 = 110
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 C2OUT
A
A
From Comparator
CIS = 0
CIS = 1
CIS = 0
CIS = 1
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 C1OUT
Two Common Reference Comparators with Outputs
A
A
CM2:CM0 = 101
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 C2OUT
A
D
A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch.
CVREF
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 C1OUT
Two Independent Comparators with Outputs
A
A
CM2:CM0 = 011
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 C2OUT
A
A
RA4/T0CKI/C1OUT
RA5/SS/AN4/C2OUT
RA4/T0CKI/C1OUT
RA5/SS/AN4/C2OUT
RA4/T0CKI/C1OUT
VREF Module
2001 Microchip Technology Inc. Advance Information DS39582A-page 135
PIC16F87XA
12.2 Comparator Operation
A singl e com pa rator i s sho wn i n Fig ure 12-2 along wi th
the relationship between the analog input levels and
the digit al ou tput. When the an alog input a t VIN+ is less
than the analog input VIN–, the output of the
comp arator is a d igital low le vel. Whe n the an alog inp ut
at VIN+ is gr eater than the anal og input VIN–, the outp ut
of the comparator is a digital high level. The shaded
areas of the output of the comparator in Figure 12-2
represent the uncertainty due to input offsets and
response time.
12.3 Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog si gnal pres ent at VIN– i s co mp ared to the si gna l
at VIN+, and the digital output of the comparator is
adjusted acco rdin gly (Figure 12- 2).
FIGURE 12-2: SINGLE COMP ARATOR
12.3.1 EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same, or different reference
sour ces. How ever , th resho ld detecto r applica tions ma y
require th e s am e re fere nce. Th e reference s ign al m us t
be betw een VSS and VDD, an d can be applie d to eith er
pin of the comparator(s).
12.3.2 INTERNAL REFERENCE SIGNAL
The com p a r ato r m odu le also al low s th e sel ec tio n of an
internally generated voltage reference for the
comp ara tors . Sec ti on 13.0 cont ai ns a detailed des cri p-
tion of the Comparator Voltage Reference Module that
provides this signal. The internal reference signal is
used when comparators are in mode CM<2:0> = 110
(Figure 12-1). In this mode, the internal voltage refer-
ence is applied to the VIN+ pin of both c omparators.
12.4 Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (Section 17.0).
12.5 Comparator Outputs
The comparator outputs are read through the CMCON
Register. These bits are read only. The comparator
output s may al so be dire ctly output to the RA4 a nd RA5
I/O pins . When enab led, multipl exors in th e output p ath
of the RA4 and RA5 pins will switch and the output of
each pin will be th e unsynchronized outp ut o f the com -
parator. The uncertainty of each of the comparators is
related t o the input of fset volta ge and the resp onse time
given in the s pecific ations. F igure 12-3 shows the com-
parator output block diagram.
The TRISA bits will still function as an output
enable/disable for the RA4 and RA5 pins while in this
mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<4:5 >).
–
+
VIN+
VIN–Output
V
IN–
V
IN+
utput
Output
VIN+
VIN–
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input, according to the
Schmitt Trigger input specification.
2: Analog l evels o n any p in defin ed as a dig-
ital input, may cause the input buffer to
consume more current than is specified.
3: RA4 is an open collector I/O pin. When
used as an output, a pull-up resistor is
required.
PIC16F87XA
DS39582A-page 136 Advance Information 2001 Microchip Technology Inc.
FIGURE 12-3: COMPARATOR OUTPUT BLOCK DIAGRAM
12.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
stat us of the out put bits, as rea d from CMCON<7:6> , to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the comparator interrupt flag. The
CMIF bit must be RESET by clearing it (‘0’). Si nc e it is
also po ssible t o write a '1' to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE reg isters) and the PEIE bit (INTC ON
register ) must be set to ena ble the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
The user , in the Interrupt Service Routine, can clear the
interrupt in the following man ner:
a) Any read or write of CMCON will end the mis-
match condition.
b) Clear flag bit CMIF.
A mismatc h co ndi tio n will co nti nue to set fla g bit CMIF.
Readi ng C M CO N will end the mi sm atc h c on dition, an d
allow flag bit CMIF to be cleared.
DQ
EN
To RA4 or
RA5 Pin
Bus
Data
Read CMCON
Set
MULTIPLEX
CMIF
bit
-+
DQ
EN
CL
Port Pins
Read CMCON
RESET
From
Other
Comparator
CxINV
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR regis-
ters) interrupt flag may not get set.
2001 Microchip Technology Inc. Advance Information DS39582A-page 137
PIC16F87XA
12.7 Comparator Operation During
SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the in ter rupt is fu nct ion al, if enab led . Th is in terr upt will
wake-u p the device from SL EEP mode, w hen ena bled.
While the comparator is powered up, higher SLEEP
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current, as shown in the com-
parat or specifi cations. To minim ize power consumptio n
while in SLEEP mode, turn off the comparators,
CM<2:0> = 111, before entering SLEEP. If the device
wakes up from SLEEP, the contents of the CMCON
register are not affected.
12.8 Effects of a RESET
A device RESET forces the CMCON register to its
RESET state, causing the comparator module to be in
the comparator off mode, CM<2:0> = 111. This
ensures compatibility to the PIC16F87X devices.
12.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 12-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. Th e analog input, th erefore, must be betw een
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is rec-
ommended for the analog sources. Any external com-
ponent connected to an analog input pin, such as a
capacitor or a Zener diode, should have very little
leakage current.
FIGURE 12-4: ANALOG INPUT MODEL
VA
RS < 10K
AIN CPIN
5 pF
VDD
VT = 0.6 V
VT = 0.6 V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN = Input Capacitance
VT= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS= Source Impedance
VA = Analog Voltage
PIC16F87XA
DS39582A-page 138 Advance Information 2001 Microchip Technology Inc.
TABLE 12-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR
Value on
All Other
RESETS
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
9Dh CVRCON CVREN CVROE CVRR —CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
0Bh, 8Bh,
10Bh,18Bh INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INTIE RBIE TMR0IF INTIF RBIF 0000 000x 0000 000u
0Dh PIR2 —CMIF — — BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000
8Dh PIE2 —CMIE — — BCLIE LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as “0”. Shaded cells are unused by the comparator module.
2001 Microchip Technology Inc. Advance Information DS39582A-page 139
PIC16F87XA
13.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The Comparator Voltage Reference Generator is a
16-tap resistor ladder network that provides a fixed
voltage reference when the comparators are in mode
110. A programmable register controls the function of
the reference generator . Register 13-1 lists the bit func-
tions of the CVRCON register.
As shown in Figure 13-1, the resistor ladder is seg-
mented to provide tw o ranges of C VREF values and has
a power-down function to conserve power when the
reference is not bein g used. The comp arat or refer ence
supply voltage (also referred to as CVRSRC) comes
directly from VDD. It should be noted, however, that the
volt age at the top of the ladder is CV RSRC - VSAT, where
VSAT is the saturat ion volt ag e of the powe r switch tra n-
sistor. This reference will only be as accurate as the
values of CVRSRC and VSAT.
The output of the reference generator may be con-
nected to the RA2/AN2/VREF-/CVREF pin. This can be
used as a simpl e D/A function by the user , if a very high
impedance load is used. The primary purpose of this
function is to provide a test path for testing the refer-
ence generator function.
REGISTER 13-1: CVRCON CONTROL REGISTER (ADDRESS 9Dh)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE CVRR —CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 =CV
REF circuit powered on
0 =CV
REF circuit powered down
bit 6 CVROE: Comparator VREF Output Enable bit
1 =CVREF voltage level is output on RA2/AN2/VREF-/CVREF pin
0 =CV
REF voltage level is disconnected from RA2/AN2/VREF-/CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.75 CVRSRC, with CV RSRC/24 step size
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4 Unimplemented: Read as ‘0’
bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits 0 ≤ VR3:VR0 ≤ 15
When CVRR = 1:
CVREF = (VR<3:0>/ 24) • (CVRSRC)
When CVRR = 0:
CVREF = 1/4 • (CVRSRC) + (VR3:VR0/ 32) • (CV RSRC)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582A-page 140 Advance Information 2001 Microchip Technology Inc.
FIGURE 13-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
TABLE 13-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
CVRR
8R
CVR3
CVR0
16:1 Analog MUX
8R RRRR
CVREN
CVREF
16 Stages
Input to
Comparator
CVROE
RA2/AN2/VREF-/CVREF
VDD
CVR2
CVR1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value On
POR
Value On
All Other
RESETS
9Dh CVRCON CVREN CVROE CVRR —CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
Legend: x = unknown, u = unchanged, - = unimplemented, read as “0”.
Shaded cells are not used with the comparator voltage reference.
2001 Microchip Technology Inc. Advance Information DS39582A-page 141
PIC16F87XA
14.0 SPECIAL FEATURES OF THE
CPU
All PIC16F87XA devices have a host of features
intended to maximize system reliability, minim ize cost
through elimination of external components, provide
power saving operating modes and offer code protec-
tion. Th ese are:
•Oscillato r Selection
•RESET
- Pow er- on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Ti mer (OST)
- Brown-out Reset (BOR)
•Interrupts
•Watchdog Timer (WDT)
•SLEEP
•Code Protection
•ID Locations
•In-Circuit Serial Programming
•Low Voltage In-Circuit Serial Programming
•In-Circuit Debugger
PIC16F87XA devices have a Watchdog Timer, which
can be shut-off only through configuration bits. It runs
off its own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nomi-
nal) on pow er-up on ly. It is designed to keep th e par t in
RESET while the power supply stabilizes. With these
two tim ers on -ch ip, mo st applicati on s n eed no ext erna l
RESET circuitry.
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up, or through an interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits is used to
select various options.
Additional information on special features is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
14.1 Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. The erased, or unprogrammed
value of the configuration word is 3FFFh. These bits
are mapped in program memory loc ati on 2007h.
It is impo rtant to n ote that addre ss 2007h is be yond the
user program memory space, which can be accessed
only during programming.
PIC16F87XA
DS39582A-page 142 Advance Information 2001 Microchip Technology Inc.
REGISTER 14-1: CONFIGURATION WORD (ADDRESS 2007h)(1)
R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
CP —DEBUG WRT1 WRT0 CPD LVP BOREN — — PWRTEN WDTEN F0SC1 F0SC0
bit13 bit0
bit 13 CP: FLASH Program Memory Code Protection bit
1 = Code protection off
0 = All program memory code protected
bit 12 Unimplemented: Read as ‘1’
bit 11 DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger
bit 10-9 WRT1:WRT0 FLASH Program Memory Write Enable bits
For PIC16F876A/877A:
11 = Write protection off; all program memory may be written to by EECON control
10 = 0000h to 00FFh write protected; 0100h to 1FFFh may be written to by EECON control
01 = 0000h to 07FFh write protected; 0800h to 1FFFh may be written to by EECON control
00 = 0000h to 0FFFh write protected; 1000h to 1FFFh may be written to by EECON control
For PIC16F873A/874A:
11 = Write protection off; all program memory may be written to by EECON control
10 = 0000h to 00FFh write protected; 0100h to 0FFFh may be written to by EECON control
01 = 0000h to 03FFh write protected; 0400h to 0FFFh may be written to by EECON control
00 = 0000h to 07FFh write protected; 0800h to 0FFFh may be written to by EECON control
bit 8 CPD: Data EEPROM Memory Code Protect ion bit
1 = Data EEPROM code protection off
0 = Data EEPROM code protected
bit 7 LVP: Low Voltage In-Circuit Serial Programming Enable bit
1 = RB3/PGM pin has PGM function; low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6 BOREN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
bit 5-4 Unimplemented: Read as ‘1’
bit 3 PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0 FOSC1:FOSC0: Os cillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: The erased (unprogramm ed) value of the configuration word is 3FFFh.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
2001 Microchip Technology Inc. Advance Information DS39582A-page 143
PIC16F87XA
14.2 Oscillator Configurations
14.2.1 OSCILLATOR TYPES
The PIC16F87XA can be operated in four different
oscill ator mod es. The u ser can p rogram two c onfigu ra-
tion bits (FOSC1 and FOSC0) to select one of these
four modes:
•LP Low Power Crystal
•XT Crystal/Resonator
•HS High Speed Crystal/Resonator
•RC Resistor/Capacitor
14.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 14-1). The
PIC16F87XA oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 14-2).
FIGURE 14-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
FIGURE 14-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
TABLE 14-1: CERAMIC RESONATORS
Note 1: See Table 14-1 and Table 14-2 for recom-
mended values of C1 and C2.
2: A series resistor (Rs) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
SLEEP
To
Logic
PIC16F87XA
Rs(2)
Internal
Ranges Tested:
Mode Freq. OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
These v alues are for design gu idance o nly.
See notes following Table 14-2.
Reson ators U sed :
455 kHz Panasonic EFO-A455K04B ± 0.3%
2.0 MHz Murata Erie CSA2.00MG ± 0.5%
4.0 MHz Murata Erie CSA4.00MG ± 0.5%
8.0 MHz Murata Erie CSA8.00 MT ± 0.5%
16.0 MHz Murata Erie CSA16.00MX ± 0.5%
All resonators used did not have built-in ca pacitors.
OSC1
OSC2
Open
Clock from
Ext. Sy stem PIC16F87XA
PIC16F87XA
DS39582A-page 144 Advance Information 2001 Microchip Technology Inc.
TABLE 14-2: CAP ACITOR SELECTION FOR
CRYSTAL OSCILLATOR 14.2.3 RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers ad diti ona l cos t savings. The RC oscil lator
frequenc y is a fun ction of the sup pl y vo ltage, the re sis -
tor (REXT) and capacitor (CEXT) values, and the opera t-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
vari ati on d ue to to ler anc e of e xte rn al R and C c ompo -
nents used. Figure 14-3 shows how the R/C combina-
tion is connected to the PIC16F87XA.
FIGURE 14-3: RC OSCILLATOR MODE
Osc Type Crystal
Freq. Cap. Range
C1 Cap. Range
C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15-33 p F
20 M Hz 15-33 pF 15-33 pF
These value s are for desi gn guidance only.
See notes following this table.
Crystals Used
32 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000KHz ± 20 PPM
1 MHz ECS ECS-10-13-1 ± 50 PPM
4 MHz ECS ECS-40-20-1 ± 50 PPM
8 MHz EPSON CA-301 8.000M-C ± 30 PPM
20 MHz EPSON CA-301 20.000M-C ± 30 PPM
Note 1: Higher cap acita nce increase s the st ability
of oscillator, but also increases the start-
up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external com ponent s.
3: Rs may be required in HS mode, as well
as XT mode, to av oid ov erdrivi ng crys tal s
with low drive level specification.
4: When migrating from other PICmicro®
devices, oscillator performance should be
verified.
OSC2/CLKOUT
CEXT
REXT
PIC16F87XA
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20pF
2001 Microchip Technology Inc. Advance Information DS39582A-page 145
PIC16F87XA
14.3 RESET
The PIC16F87XA differentiates between various kinds
of RESET:
•Power-on Reset (POR)
•MCLR Reset during normal operation
•MCLR Reset during SLEEP
•WDT Reset (during normal operation)
•WDT Wake-up (during SLEEP)
•Brown-out Reset (BOR)
Some registers are not affected in any RESET condi-
tion. Their status is unknown on POR and unchanged
in any othe r RESET. Mo st other reg isters are reset to a
“RESET state” on Power-on Reset (POR), on the
MCLR and WDT Reset, on MCLR Reset during
SLEEP, and Brown-out Reset (BOR). They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different RESET situa-
tions, a s indica ted in Table 14-4. Th ese bit s are us ed in
software to determine the nature of the RESET. See
Table 14-6 for a full description of RESET states of all
registers.
A simplif ied block diagra m of the On-Chip Rese t Circu it
is sh own in Figure 14-4.
FIGURE 14-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR
VDD
OSC1
WDT
Module
VDD Rise
Detect
OST/PWRT
On-chip
RC OSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
10-bit Ripple Counter
Reset
Enable OST
Enable PWRT
SLEEP
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
Brown-out
Reset BODEN
(1)
PIC16F87XA
DS39582A-page 146 Advance Information 2001 Microchip Technology Inc.
14.4 MCLR
PIC16F87XA devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
differs from previous devices of this family. Voltages
applied to the pin that exceed its specification can
result in both RESETS and current consumption out-
side of device specification during the RESET event.
For this rea son, Microc hip recomme nds that the MC LR
pin no long er be tied direc tly to VDD. The us e of an RC
network, as sh own in Figure 14-5, is suggested.
FIGURE 14-5: REC OMME NDED MCLR
CIRCUIT
14.5 Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, tie the MCLR pin to VDD
through an RC network, as described in Section 14.4.
A maximum rise time for VDD is specified. See
Section 17.0 (“Elect ric al Spec ifi ca tio ns ”) for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met. Brown -out Res et may be us ed to meet
the st art-up conditio ns. For add itional i nformation , refer
to Application Note, AN007, “Power-up Trouble
Shooting”, (DS00007).
14.6 Power-up Ti me r (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in RESET as long as the PWRT is active.
The PWR T’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable or
disable the PWRT.
The pow er-up time de lay will v ary from chi p to chip due
to VDD, temperature and process variation. See
Section 17.0 for details (TPWRT, parameter #33).
14.7 Oscillator Start-up Timer (OST)
The Oscill ator S tart-up Time r (OST) provides a de lay of
1024 oscillator cycles (from OSC1 input) after the
PWR T delay is over (if PWRT i s enabled). This helps to
ensure that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or Wa ke-up from
SLEEP.
14.8 Brown-out Reset (BOR)
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(param eter #35, abo ut 100 µS), the bro wn-out situatio n
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in RESET for
TPWRT (parameter #33, about 72 mS). If VDD should
fall below VBOR during TPWRT, the Brown-out Reset
process will restart when VDD rises above VBOR with
the Power-up Timer Reset. The Power-up Timer is
always enabled when the Brown-out Reset circuit is
enabled, regardless of the state of the PWRT configu-
ration bit.
14.9 Time- out Sequence
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR Reset
occurs. Then, OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
If MCLR is kept low long enough, the time-outs will
expire. Bring ing MCLR high will begin execution imme-
diately . This is useful for testing purposes or to synchro-
nize more than one PIC16F87XA device operating in
parallel.
Table 14-5 shows the RESET conditions for the
STATUS, PCON and PC registers, while Table 14-6
shows the RESET conditions for all the registers.
C1
0.1 µF
R1
1 kΩ (or greater)
(not critical)
VDD
MCLR
PIC16F87XA
2001 Microchip Technology Inc. Advance Information DS39582A-page 147
PIC16F87XA
14.10 Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON, has up to
two bit s dep end ing upon the dev ic e.
Bit0 is the Brown-out Reset Status bit, BOR. The BOR
bit is unknow n on a Power-on R eset. It must then be set
by the user and checked on subsequent RESETS to see
if it has been cleared, indicating that a BOR has
occurred. When the Brown-out Reset is disabled, the
state of the BOR bit is unpredictable and is, therefore,
not valid at any time.
Bit1 is POR (Power-on Reset S tatus bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
TABLE 14-3: TIME-OUT IN VARIOUS SITUATIONS
TABLE 14-4: STATUS BITS AND THEIR SIGNIFICANCE
TABLE 14-5: RESET CONDITION FOR SPECIAL REGISTERS
Oscillator Co nfigu ration Power-up Brown-out Wake-up from
SLEEP
PWRTE = 0 PWRTE = 1
XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC
RC 72 ms —72 ms —
POR BOR TO PD
0x11Power-on Reset
0x0xIllegal, TO is set on POR
0xx0Illegal, PD is set on POR
1011Brown-out R ese t
1101WDT Reset
1100WDT Wake-up
11uuMCLR Reset during normal operation
1110MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Legend: x = don’t care, u = unchanged
Condition Program
Counter STATUS
Register PCON
Register
Power-on Reset 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu
WDT Reset 000h 0000 1uuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 000h 0001 1uuu ---- --u0
Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
PIC16F87XA
DS39582A-page 148 Advance Information 2001 Microchip Technology Inc.
TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Devices Power-on Rese t,
Brown-out Reset MCLR Resets,
WDT Reset Wake-up via WDT or
Interrupt
W 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
INDF 73A 74A 76A 77A N/A N/A N/A
TMR0 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
PCL 73A 74A 76A 77A 0000 0000 0000 0000 PC + 1(2)
STATUS 73A 74A 76A 77A 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 73A 74A 76A 77A --0x 0000 --0u 0000 --uu uuuu
PORTB 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
PORTD 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
PORTE 73A 74A 76A 77A ---- -xxx ---- -uuu ---- -uuu
PCLATH 73A 74A 76A 77A ---0 0000 ---0 0000 ---u uuuu
INTCON 73A 74A 76A 77A 0000 000x 0000 000u uuuu uuuu(1)
PIR1 73A 74A 76A 77A r000 0000 r000 0000 ruuu uuuu(1)
73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu(1)
PIR2 73A 74A 76A 77A -0-0 0--0 -0-0 0--0 -u-u u--u(1)
TMR1L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 73A 74A 76A 77A --00 0000 --uu uuuu --uu uuuu
TMR2 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
T2CON 73A 74A 76A 77A -000 0000 -000 0000 -uuu uuuu
SSPBUF 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
CCPR1L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 73A 74A 76A 77A --00 0000 --00 0000 --uu uuuu
RCSTA 73A 74A 76A 77A 0000 000x 0000 000x uuuu uuuu
TXREG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
RCREG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
CCPR2L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
ADRESH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 73A 74A 76A 77A 0000 00-0 0000 00-0 uuuu uu-u
OPTION_REG 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu
TRISA 73A 74A 76A 77A --11 1111 --11 1111 --uu uuuu
TRISB 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu
TRISC 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu
TRISD 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu
TRISE 73A 74A 76A 77A 0000 -111 0000 -111 uuuu -uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition,
r = reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-5 for RESET value for specific condition.
2001 Microchip Technology Inc. Advance Information DS39582A-page 149
PIC16F87XA
FIGURE 14-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK)
PIE1 73A 74A 76A 77A r000 0000 r000 0000 ruuu uuuu
73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
PIE2 73A 74A 76A 77A -0-0 0--0 -0-0 0--0 -u-u u--u
PCON 73A 74A 76A 77A ---- --qq ---- --uu ---- --uu
SSPCON2 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
PR2 73A 74A 76A 77A 1111 1111 1111 1111 1111 1111
SSPADD 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 73A 74A 76A 77A --00 0000 --00 0000 --uu uuuu
TXSTA 73A 74A 76A 77A 0000 -010 0000 -010 uuuu -uuu
SPBRG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
CMCON 73A 974 76A 77A 0000 0111 0000 0111 uuuu uuuu
CVRCON 73A 74A 76A 77A 000- 0000 000- 0000 uuu- uuuu
ADRESL 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
ADCON1 73A 74A 76A 77A 00-- 0000 00-- 0000 uu-- uuuu
EEDATA 73A 74A 76A 77A 0--- 0000 0--- 0000 u--- uuuu
EEADR 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
EEDATH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
EEADRH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
EECON1 73A 74A 76A 77A x--- x000 u--- u000 u--- uuuu
EECON2 73A 74A 76A 77A ---- ---- ---- ---- ---- ----
TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Devices Power-on Reset,
Brown-out Reset MCLR Resets,
WDT Reset Wake-up via WDT or
Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition,
r = reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-5 for RESET value for specific condition.
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PIC16F87XA
DS39582A-page 150 Advance Information 2001 Microchip Technology Inc.
FIGURE 14-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 14-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 14-9: SLOW RISE TIME (MCLR TIED TO VDD VIA RC NETWORK)
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-O UT
OST TIME-OUT
INTERNAL RESET
0V 1V
5V
TPWRT
TOST
2001 Microchip Technology Inc. Advance Information DS39582A-page 151
PIC16F87XA
14.11 Interrupts
The PIC16F87XA family has up to 15 sources of inter-
rupt. The interrupt control register (INTCON) records
indivi dual in terrupt r equ est s in fl ag bit s. It also h as ind i-
vidual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts, or disables (if
cleared ) all i nterrupt s. W hen bit GIE i s enab led, a nd an
interrupt’s flag bit and mask bit are s et, the int errupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enable s inte rrup t s.
The RB0/INT pin interrupt, the RB port change inter-
rupt, and the TMR0 overflow interrupt flags are con-
tained in the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interr upt enabl e bit is conta ined in sp ecial function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pu sh ed o nto the s t ac k a nd the PC is lo ade d
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the i nterr upt flag bits. T he inte rrupt flag bi t(s) mu st be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the s ame for one or two -cy cle in struct ion s. Indi vidua l
interrupt flag bits are set, regardless of the status of
their corresponding mask bit, PEIE bit, or GIE bit.
FIGURE 14-10: INTERRUPT LOGIC
Note: Indiv idual interrupt fl ag bits are s et, regard-
les s of the status of t heir corresponding
mask bit, or the GIE bit.
PSPIF(1)
PSPIE(1)
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
TMR0IF
TMR0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
CCP2IE
CCP2IF
BCLIE
BCLIF
EEIF
EEIE
CCP1IF
CCP1IE
CMIE
CMIF
Note 1: PSP interrupt is implemented only on PIC16F874A/877A devices.
PIC16F87XA
DS39582A-page 152 Advance Information 2001 Microchip Technology Inc.
14.11.1 INT INTERRUPT
External interrupt on the RB0/INT p in is edg e triggere d,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or fall ing , if th e IN TEDG bit i s cl ea r. When a valid edg e
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routin e before re-enablin g this interrupt. The INT in ter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit, GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 14.14 for details on SLEEP
mode.
14.11.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit
TMR0IE (INTCON<5>) (Section 5.0).
14.11.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>)
(Section 4.2).
14.12 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. T y pically, users m ay wish to s ave key re g-
isters d uri ng a n i nterrupt, (i.e., W reg ist er a nd S TATUS
register). This wil l h ave to b e im pl em ent ed i n so ftw ar e.
For the PIC16F873A/874A devices, the register
W_TEMP must be defined in both banks 0 and 1 and
must be de fine d at the s ame offset from the ban k b as e
address (i.e., If W_TEMP is defined at 0x20 in bank 0,
it must also be defined at 0xA0 in bank 1). The regis-
ters, PCLATH_TEMP and STATUS_TEMP, are only
defined in bank 0.
Since the upper 16 bytes of each bank are common in
the PIC1 6F876A/877A dev ices, temporary holding reg-
isters W_TEMP, STATUS_TEMP, and PCLATH_TEMP
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
text save and restore. The same code shown in
Example 14-1 can be used.
EXAMPLE 14-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3
MOVWF PCLATH_TEMP ;Save PCLATH into W
CLRF PCLATH ;Page zero, regardless of current page
:
:(ISR) ;(Insert user code here)
:
MOVF PCLATH_TEMP, W ;Restore PCLATH
MOVWF PCLATH ;Move W into PCLATH
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
2001 Microchip Technology Inc. Advance Information DS39582A-page 153
PIC16F87XA
14.13 Wat chdog Timer (WDT)
The W atchdog T imer is a free running on -chip RC oscil-
lator, which does not requ ire any exte rnal co mpone nt s.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/
CLKOUT pins of the device has been stopped, for
exampl e, by ex ecu tion of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (W atchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-u p) . T he TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 14.1).
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
FIGURE 14-11: WATC HDOG TIMER BLOCK DIAGRAM
TABLE 14-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device
RESET condition.
2: When a CLRWDT instruction is executed
and the pre scaler is assi gned to the WDT,
the prescaler count will be cleared, but
the pr es ca ler ass ig nm ent is no t c han ged.
From TMR0 Clock Source
(Figure 5-1)
To TMR0 (Figure 5-1)
Postscaler
WDT Timer
WDT
Enable Bit
0
1M
U
X
PSA
8 - to - 1 MUX PS2:PS0
01
MUX PSA
WDT
Time-out
8
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog T i me r.
Note 1: See Register 14-1 for operation of these bits.
PIC16F87XA
DS39582A-page 154 Advance Information 2001 Microchip Technology Inc.
14.14 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keep s runni ng, the PD bi t ( STATUS<3>) is clea red , th e
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitr y is dr awing cu rrent from th e I/O pi n, powe r-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid s witchi ng curre nts caus ed by fl oating input s. Th e
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
The MCLR pin must be at a logic high level (VIHMC).
14.14.1 WAKE-UP FROM SLEE P
The device can wake-up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or
peripheral interrupt.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execut ion and c aus e a “wake-up”. The T O and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
powe r-up, is cleared w hen SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
The follo wing periph eral interrupt s can wake the device
from SLEEP:
1. PSP read or write (PIC16F874/877 only).
2. TMR1 interrupt. T im er1 must be operating a s an
asynchronous counter.
3. CCP Capture mode interrupt.
4. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
5. SSP (START/STOP) bit detect interrupt.
6. SSP transmit or receive in Slave mode
(SPI/I2C).
7. USART RX or TX (Synchronous Slave mode).
8. A/D conversion (when A/D clock source is RC).
9. EEPROM write operation completion.
10. Comparator output changes state.
Other per ipherals cann ot generate interrup ts since d ur-
ing SLEEP, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up thro ugh an interrupt eve nt, the co rres pon din g
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
14.14.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llow ing wil l occur:
•If the interrupt occurs before the execution of a
SLEEP instr uct ion , the SLEEP instruction will com-
plete as a NOP. Therefore, the WDT and WDT
pos tscaler will not be cleared, the TO bit will not
be set and PD bits will not be cle are d.
•If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, the device will imme-
diately wake-up from SLEE P. T he SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
pos tscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT inst ruc-
tion should be executed before a SLEEP instruction.
2001 Microchip Technology Inc. Advance Information DS39582A-page 155
PIC16F87XA
FIGURE 14-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT
14.15 In-Circuit Debugger
When the DEBUG bit in the configuration word is pro-
grammed to a ’0’, the In-Circuit Debugger functionality
is enabled. This function allows simple debugging func-
tions when used with MPLAB® ICD. When the micro-
controller has this feature enabled, some of the
resourc es ar e not ava ilable for genera l use. Table 14-8
shows which features are consumed by the back-
ground debugger.
TABLE 14-8: DEBUGGER RESOURCES
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip, or one of
the third party development tool companies.
14.16 Program Verification/Code
Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
14.17 ID Locations
Four memo ry locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 Least Significant bits of the ID
loc ation are used.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency(2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST(2)
PC+2
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
I/O pins RB6, RB7
Stack 1 level
Program Memory Address 0000h must be NOP
Last 100h word s
Data Memory 0x070 (0x0F0, 0x170, 0x1F0)
0x1EB - 0x1EF
PIC16F87XA
DS39582A-page 156 Advance Information 2001 Microchip Technology Inc.
14.18 In-Circuit Serial Progra mming
PIC16F87XA microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with tw o lines for cl ock and data and thre e
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also all ows the m ost recent fi rmwa re, or a custom firm-
ware to be programmed.
When usin g IC SP, the pa r t mu st be supp li ed at 4. 5V to
5.5V, if a bulk erase will be executed. This includes
reprogramming of the code protect, both from an on-
state to off-state. For all other cases of ICSP, the part
may be programmed at the normal operating voltages.
This m eans c alibration values, unique u ser ID s, or us er
code can be reprogrammed or added.
For complete details of serial programming, please
refer to t he EEPROM Mem ory Programming Specifica-
tion for the PIC16F 87XA.
14.19 Low Voltage ICSP Programming
The LVP bit of the configu r ati on word ena bl es l ow vo lt-
age ICSP programming. This mode allows the micro-
controller to be programmed via ICSP using a VDD
source i n the op erating vo ltage ra nge. This o nly means
that VPP does not have to be brought to VIHH, but can
instead be left at the normal operating voltage. In this
mode, the RB3/PGM pin is dedicated to the program-
ming function and ceases to be a general purpose I/O
pin. During programming, VDD is applied to the MCLR
pin. To enter Pro gramming mode, VDD m ust b e applie d
to the RB3/PGM, provided the LVP bit is set. The LVP
bit defaults to on (‘1’) from the factory.
If Low V ol tage Program ming mode is not us ed, the L V P
bit can be programmed to a '0' an d RB3/PGM beco mes
a digital I/O pin. How ev er, the LVP bit may o nly b e p ro-
grammed when programming is entered with VIHH on
MCLR. The LVP bit can only be charged when using
high voltage on MCLR.
It should be noted, that once the L VP bit is programmed
to 0, onl y the High Voltage Programming m ode is avai l-
able and onl y High Voltage Pro gramming mo de can be
used to program the device.
When using low volt age ICSP, the part must be supplied
at 4.5V to 5.5V, if a bulk erase will be executed. This
includes reprogramming of the code protect bit s from an
on-state to off-state. For all other cases of low voltage
ICSP, the part may be programmed at the normal oper-
ating voltage. This means calibration values, unique
user IDs, or user code can be reprogram med or added .
Note 1: The High Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
2: While in Low Voltage ICSP mode, the
RB3 pin can no longer be used as a gen-
eral purpose I/O pin.
3: When using low voltage ICSP program-
ming (LVP) and the pull-ups on PORTB
are enabled, bit 3 in the TRISB register
must be cleared to disable the pull-up on
RB3 and ensure the proper operation of
the device.
4: RB3 should not be allowed to float if LVP
is enabled. An external pull-down device
should be used to default the device to
normal operating mode. If RB3 floats
high, the PIC16F87XA device will enter
Programming mode.
5: LVP mode is enabled by default on all
device s shippe d from Microchi p. It can b e
disabled by clearing the LVP bit in the
CONFIG register.
6: Disabling LVP will provide maximum com-
patibility to other PIC1 6CXXX devices.
2001 Microchip Technology Inc. Advance Information DS39582A-page 157
PIC16F87XA
15.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC16 instruction is a 14-bit word divided into an
opcode which specifies the instru ction type, and one or
more operands which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 15-1, while the various opcode
fields are sum m ariz ed in Table 15-1.
Table 13-2 lists the instructions recognized by the
MPASMTM Assembler. A complete description of each
instruction is also available in the PICmicro™ Mid-
Range Reference Manual (DS33023).
For byte-oriented instructions, ‘f’ represents a file re g-
ister designator and ‘d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W re gister . If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the bit affected by the opera-
tion, w hile ‘f’ represent s the address of the fi le in which
the bit is located.
For literal and control operations, ‘k’ represents an
eight- or eleven-bit constant or literal value
One instr uction cycle co nsists of four os cillator periods ;
for an oscillator frequency o f 4 MHz, t his gives a normal
instruction execution time of 1 µs. All instructions are
execut ed within a single instruction cycle, unless a con-
ditional test is true or the program counter is changed
as a r esu lt of an in struc tion. W he n this occurs , the exe-
cution takes two instruction cycles with the second
cycle executed as a NOP.
All instruction ex am ple s u se t he fo rm at ‘0xhh’ to repre-
sent a he xadecim al n umber, where ‘h’ signifies a hexa-
dec i mal digit.
15.1 READ-MODIFY-WRITE
OPERATIONS
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
For example, a “clrf PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the unin-
tended result that the condition that sets the RBIF flag
would be cleared.
TABLE 15-1: OPCODE FIELD
DESCRIPTIONS
FIGURE 15-1: GENERAL FORMAT FOR
INSTRUCTIONS
Note: To maintain upward compatibility with
future PIC16F87XA products, do not use
the OPTION and TRIS instructions.
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon't care loc ati on (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC Program Counter
TO Time-out bit
PD Power-down bit
Byte-orie nted file register oper a tions
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operati ons
13 10 9 7 6 0
OPCODE b (BIT # ) f (FIL E #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal )
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16F87XA
DS39582A-page 158 Advance Information 2001 Microchip Technology Inc.
TABLE 15-2: PIC16F87XA INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move litera l to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).
2001 Microchip Technology Inc. Advance Information DS39582A-page 159
PIC16F87XA
15.2 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [ label ] ADDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) + k → (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are ad ded to the eight-bi t literal ’k’
and the result is placed in the W
register.
ADDWF Add W and f
Synta x: [ label ] ADDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) + (f) → (destination)
Status Affected: C, DC, Z
Desc ription: Add the con tents of the W regis ter
with regi ster ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in
register ’f’.
ANDLW AND Literal with W
Syntax: [ label ] ANDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .AND. (k) → (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight-bit literal
'k'. The result is placed in the W
register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .AND. (f) → (destination)
Status Affected: Z
Description: AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W regist er. If 'd' is 1, the re sult
is stored back in register 'f'.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 0 → (f<b>)
Status Affe cte d: None
Description: Bit 'b' in register 'f' is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 1 → (f<b>)
Status Affe cte d: None
Description: Bit 'b' in register 'f' is set.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b < 7
Operation: skip if (f<b>) = 1
Status Affe cte d: None
Descr ipti on : If bit 'b' in regi ster 'f' is '0 ', the nex t
instructi on is ex ecuted.
If bit 'b' is '1', then the next instruc-
tion is discarded and a NOP is
executed instead, making this a
2TCY instruction.
BTFSC Bit Test, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: skip if (f<b>) = 0
Status Affe cte d: None
Description: If bit 'b' in register 'f' is '1', the next
instruction is executed.
If bit 'b', in register 'f', is '0', the
next instru ction is discar de d, and
a NOP is executed instead, making
this a 2TCY instruction.
PIC16F87XA
DS39582A-page 160 Advance Information 2001 Microchip Technology Inc.
CALL Call Subroutin e
Syntax: [ label ] CALL k
Operands: 0 ≤ k ≤ 2047
Operation: (PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immedi-
ate a ddress is loade d into P C bit s
<10:0>. The upper bits of the PC
are load ed from PCLA TH. CALL is
a two-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 ≤ f ≤ 127
Operation: 00h → (f)
1 → Z
Status Affected: Z
Desc ript ion : The conten t s of regi ste r ’f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h → (W)
1 → Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affe cte d: TO, PD
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (destination)
Status Affe cte d: Z
Description: The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W . If ’d’ is 1, the
result is stored back in register ’f’.
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination)
Status Affe cte d: Z
Description: Decrement register ’f’. If ’d’ is 0,
the result is stored in the W
register. If ’d’ is 1, the result is
stored back in register ’f’.
2001 Microchip Technology Inc. Advance Information DS39582A-page 161
PIC16F87XA
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ’f’ are
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOP is executed instead,
making it a 2TCY instruction .
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 ≤ k ≤ 2047
Operation: k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The e le ven -bi t im me dia t e v al ue i s
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two-
cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (destination)
Status Affected: Z
Description: The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W regis ter. If ’d’ is
1, the result is placed back in
register ’f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (destination),
skip if result = 0
Status Affe cte d: None
Description: The contents of register ’f’ are
incremen ted. If ’d’ is 0 , the result is
placed in the W register. If ’d’ is 1,
the result is placed back in
register ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOP is e xecuted i nstead, ma king
it a 2TCY instruction.
IORLW Inclusive OR Literal with W
Syntax: [ label ] IORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .OR. k → (W)
Status Affe cte d: Z
Descr iption: The con tents of t he W register a re
OR’ed with the eight-bit literal 'k'.
The result is placed in the W
register.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .OR. (f) → (destination)
Status Affe cte d: Z
Description: Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in
register 'f'.
PIC16F87XA
DS39582A-page 162 Advance Information 2001 Microchip Technology Inc.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (desti nati on )
Status Affected: Z
Description: The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0,
destination is W register. If d = 1,
the destination is file register f itself.
d = 1 is useful to test a file register,
since status flag Z is affected.
MOVLW Move Literal to W
Syntax: [ label ] MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W)
Status Affected: None
Description: The eight-bit literal ’k’ is loaded
into W register. The don’t cares
will assemble as 0’s.
MOVWF Mo ve W to f
Syntax: [ label ] MOVWF f
Operands: 0 ≤ f ≤ 127
Operation: (W) → (f)
Status Affected: None
Description: Move data from W register to
register 'f'.
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affe cte d: None
Description: No operation.
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS → PC,
1 → GIE
Status Affe cte d: None
RETLW Return with Literal in W
Syntax: [ label ] RETLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W);
TOS → PC
Status Affe cte d: None
Description: The W register is loaded with the
eight-bit literal 'k'. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
2001 Microchip Technology Inc. Advance Information DS39582A-page 163
PIC16F87XA
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ’f’ are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0, the re sult is pl aced in
the W register . If ’d’ is 1, the result is
stored back in register ’f’.
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS → PC
Status Affected: None
Description: Return from subroutine. The st ack
is POPed an d t he top o f th e s t a ck
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Desc ript ion : The contents of registe r ’f’ are
rotat ed one bit to the r ight throug h
the C arry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
Register fC
Register fC
SLEEP
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affe cte d: TO , PD
Descripti on: The powe r-down status bit , PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleare d.
The proce ssor is put into SLEEP
mode with th e oscillator sto pped.
SUBLW Subtract W from Literal
Syntax: [ label ] SUBLW k
Operands: 0 ≤ k ≤ 255
Operation: k - (W) → (W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s
complement method) from the
eight-bit literal 'k'. The result is
placed in the W register.
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - (W) → (destination)
Status
Affected: C, DC, Z
Description: Subtract (2’s com plement method)
W register from regi ster 'f'. If 'd' is 0,
the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
PIC16F87XA
DS39582A-page 164 Advance Information 2001 Microchip Technology Inc.
SWAPF Swap Nibbles in f
Syntax: [ la bel ] SWAPF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ’f’ are ex changed. If ’d’ is 0,
the result is placed in the W regis-
ter. If ’d’ is 1, the result is placed in
register ’f’.
XORLW Exclusive OR Literal with W
Syntax: [ label ] XORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the eight-b it
literal 'k'. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .XOR. (f) → (destination)
Status Affe cte d: Z
Description: Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
2001 Microchip Technology Inc. Advance Information DS39582A-page 165
PIC16F87XA
16.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full ran ge of hardware a nd softwa re develo pment to ols:
•Integrated Development Environment
- MPLAB® IDE Software
•Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
•Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
•In-Circuit Debugger
- MPLAB ICD
•Device Programmers
-PRO MATE
® II Universa l Devi ce Pr o gr a mm er
- PICSTART® Plus Entry-Level Development
Programmer
•Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demons trati on Boar d
- PICDEM 17 Demonstration Board
-K
EELOQ® Demonstration Board
16.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
•An interface to debugging t ools
- simulator
- programmer (so ld sep ara tely )
- em ulator (sold separately)
- in-circuit debugger (sold separately)
•A full-featured editor
•A project manager
•Customizable toolbar and key mapping
•A status bar
•On-line help
The MPLAB IDE allows you to:
•Edit your source files (eithe r assembly o r ‘C’)
•One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
matically updates all project information)
•Debug us ing :
- source file s
- absolute li sting fi le
- machine code
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
16.2 MPASM Assembler
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be us ed through MPLAB ID E. The MP ASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
The MPASM assembler features include:
•Integration into MPLAB IDE projects.
•User-defined macros to streamline assembly
code.
•Conditional assembly for multi-purpose source
files.
•Directives that allow complete control over the
assembly p rocess.
16.3 MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C1 7 and MP LAB C18 Code De vel op me nt
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microc ontrollers, re spectively. Thes e compiler s provide
powerful integration capabilities and ease of use not
found with other compilers.
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
PIC16F87XA
DS39582A-page 166 Advance Information 2001 Microchip Technology Inc.
16.4 MPLINK Object Linker/
MPLIB Object Librari an
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine w ill be linked in with the ap plicatio n. This allo ws
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLINK object linker features include:
•Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
•Allows a ll m emo ry are as t o be defined as se ctio ns
to provide l ink -time flex ibi lity.
The MPLIB object librarian features include:
•Easier linking because single libraries can be
included instead of many smaller files.
•Helps keep code maintainable by grouping
related modules together.
•Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
16.5 MPLAB SIM Software Simulator
The MPLAB SIM sof tware simula tor allows code deve l-
opment in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined ke y press, to an y of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MP ASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laborat ory envir onment, making it an excelle nt multi-
project software development tool.
16.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editi ng, buildin g, downlo ading and so urce
debugging from a single environment.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
featur es. Interchangea ble processo r modules al low the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmic ro mi cro con trol le rs.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
16.7 ICEPIC In-Circuit Emulator
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
T ime-Programmable (OTP) microcontrollers. The mod-
ular sy stem can su pport dif feren t subset s of PIC16 C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
applic atio n circ ui try bei ng pres en t.
2001 Microchip Technology Inc. Advance Information DS39582A-page 167
PIC16F87XA
16.8 MPLAB ICD In-Circuit Debugger
Microchip’s In-Circuit Debugger , MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based o n the F LASH PICmicro MCUs an d can be used
to devel op for this and other PICmicro mic rocontrollers.
The MPLAB IC D u tili ze s th e in -circuit d ebu ggi ng c apa-
bility built into the FLASH devices. This feature, along
with Microchip’s In-Circui t Serial ProgrammingTM proto-
col, offers cost-effective in-circuit FLASH debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by watch-
ing variables, si ngl e-s tep pin g and setting brea k poi nt s .
Runni ng at full sp eed enab les tes ting hardwa re in real-
time.
16.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
16.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Inte grated Dev elopmen t En vironme nt so ftware makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76 X, may be suppor ted with an adap ter socket.
The PICSTART Plus development programmer is CE
compliant.
16.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s mic rocon trollers . The micro contro llers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulato r and do wnload the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
16.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may a lso be used with the PICDEM 2 demonstra tion
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches , a poten tiomet er for simula ted anal og inpu t, a
serial EEPROM to d emonstrate u sage o f the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
PIC16F87XA
DS39582A-page 168 Advance Information 2001 Microchip Technology Inc.
16.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-p in PLCC micro controlle rs with an LCD Mo d-
ule. All the necessary hardware and software is
includ ed to r un the basic dem onstrat ion pro grams . The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer , o r a PICST AR T Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may a lso be used with the PICDEM 3 demon stration
board to test firmware. A prototype area has been pro-
vided t o the use r for ad ding hardwa re and con necting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commo ns and 1 2 segment s , tha t is capable of d isp lay-
ing time, temperature and day of the week. The
PICDEM 3 d emons tration board pr ovi des an add itiona l
RS-232 interface and Windows software for showing
the demul tiplexed LC D signals on a PC. A simp le serial
interface allows the user to construct a hardware
demultip lexer for the LCD signals.
16.14 PICDEM 17 Demonstration Board
The P ICDEM 17 de mo ns t rat i on bo a rd is an ev al u at i on
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hard ware is inc luded to ru n basic d emo progra ms,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstratio n board supports download ing of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMAST ER emulator and al l of the sample progr ams
can be run and modified using either emulator . Addition-
ally, a generous prototype area is available for user
hardware.
16.15 KEELOQ Evaluati on and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
2001 Microchip Technology Inc. Advance Information DS39582A-page 169
PIC16F87XA
TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP
PIC12CXXX
PIC14000
PIC16C5X
PIC16C6X
PIC16CXXX
PIC16F62X
PIC16C7X
PIC16C7XX
PIC16C8X
PIC16F8XX
PIC16C9XX
PIC17C4X
PIC17C7XX
PIC18CXX2
PIC18FXXX
24CXX/
25CXX/
93CXX
HCSXXX
MCRFXXX
MCP2510
Soft war e To ol s
MPLAB® Integrated
Development Environment
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
MPLAB® C17 C Compiler
9
9
MPLAB® C18 C Compiler
9
9
MPASMTM Assembler/
MPLINKTM Obje ct Lin ke r
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Emulators
MPLAB® ICE In-Circuit Emulator
9
9
9
9
9
9
**
9
9
9
9
9
9
9
9
9
ICEPICTM In-Circuit Emulator
9
9
9
9
9
9
9
9
Debugger
MPLAB® ICD In-Circuit
Debugger
9
*
9
*
9
9
Programmers
PICSTART® Plus Entry Level
Devel opment Programmer
9
9
9
9
9
9
**
9
9
9
9
9
9
9
9
9
PRO MATE® II
Universal Device Programmer
9
9
9
9
9
9
**
9
9
9
9
9
9
9
9
9
9
9
Demo Boards and Eval Kits
PICDEMTM 1 Demonstration
Board
9
9
9
†
9
9
PICDEMTM 2 Demonstration
Board
9
†
9
†
9
9
PICDEMTM 3 Demonstration
Board
9
PICDEMTM 14A Demonstration
Board
9
PICDEMTM 17 Demonstration
Board
9
KEELOQ® Evaluation Ki t
9
KEELOQ® Transp on d er Kit
9
microIDTM Programmer’s Kit
9
125 kHz microIDTM
Developer’s Kit
9
125 kHz Anticollision microIDTM
Developer’s Kit
9
13.56 MHz Antic olli sion
microIDTM Developer’s Kit
9
MCP2510 CAN Developer’s Kit
9
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
** Contact Microchip Technology Inc. for availability date.
†Development tool is available on select devices.
PIC16F87XA
DS39582A-page 170 Advance Information 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. Advance Information DS39582A-page 171
PIC16F87XA
17.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) .........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +14V
Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum curr ent out of VSS pin ...........................................................................................................................300 mA
Maximum curr ent into VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA
Output clamp cur rent, IOK (VO < 0 or VO > VDD).............................................................................................................± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin....................................................................................................25 mA
Maximum curr ent sunk by PORTA, PORTB, and PORTE (combined) (Note 3)...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................200 mA
Note 1: Power dissipation is calculate d as fo llo w s: Pd is = VDD x { IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a s eries res istor o f 50-100 Ω shou ld be u sed w hen a pplyi ng a “low” level to the M CLR pin, ra ther than
pulling this pin directly to VSS.
3: PORTD and PORTE are not implemented on PIC16F873A/876A devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC16F87XA
DS39582A-page 172 Advance Information 2001 Microchip Technology Inc.
FIGURE 17-1: PIC16F87XA VOLTAGE-FREQUENCY GRAPH
FIGURE 17-2: PIC16LF87XA VOLTAGE-FREQUENCY GRAPH
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
20 MHz
5.0 V
3.5 V
3.0 V
2.5 V
PIC16F87XA
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
5.0 V
3.5 V
3.0 V
2.5 V
FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the applicat ion.
4 MHz 10 MHz
Note 2: FMAX has a maximum frequency of 10 MHz.
PIC16LF87XA
2001 Microchip Technology Inc. Advance Information DS39582A-page 173
PIC16F87XA
17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial)
PIC16LF873A/874A/876A/877A (Industrial )
PIC16LF873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated)
Ope rati ng temperature -40°C ≤ TA ≤ +85°C for industrial
PIC16F873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Symbol Characteristic/
Device Min Typ†Max Units Conditions
VDD Supply Voltage
D001 16LF87XA 2.0 —5.5 V LP, XT, RC osc configuration
(DC to 4 MHz)
D001 16F87XA 4.0 —5.5 VLP, XT, RC osc configuration
D001A 4.5 5.5 VHS osc configuration
VBOR 5.5 VBOR enabled, FMAX = 14 MHz(7)
D002 VDR RAM Data Retention
Voltage(1) —1.5 — V
D003 VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
— VSS —V See section on Power-on Reset for
details
D004 SVDD VDD Rise Rate to ens ure
internal Power-on Reset
signal
0.05 ——V/ms See section on Power-on Reset for
details
D005 VBOR Brown-out Reset
Voltage 3.65 4.0 4.35 V BODEN bit in configuration word
enabled
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only, and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC o sc co nfigura tion, current through REXT is not in cl uded. T he cu rrent thro ugh th e resi stor can b e esti -
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the spe cific ati on. Thi s val ue is from chara c-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
PIC16F87XA
DS39582A-page 174 Advance Information 2001 Microchip Technology Inc.
IDD Supply Current(2,5)
D010 16LF87XA —0.6 2.0 mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V
D010 16F87XA —1.6 4mA RC osc configurations
FOSC = 4 MHz, VDD = 5.5V
D010A 16LF87XA —20 35 µA LP osc configuration
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
D013 16F87XA — 7 15 mA HS osc configuration,
FOSC = 20 MHz, VDD = 5.5V
D015 ∆IBOR Brown-out
Reset Curre nt(6) —85 200 µA BOR enabled, VDD = 5.0V
17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial)
PIC16LF873A/874A/876A/877A (Industrial) (Continued)
PIC16LF873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated)
Ope rati ng temperature -40°C ≤ TA ≤ +85°C for industrial
PIC16F873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Symbol Characteristic/
Device Min Typ†Max Units Conditions
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only, and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC o sc co nfigur ation, cur rent thro ugh REXT is no t incl uded. T he cu rrent through the re sisto r can b e est i-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the spe cific ati on. Thi s val ue is from chara c-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2001 Microchip Technology Inc. Advance Information DS39582A-page 175
PIC16F87XA
IPD Power-down Current(3,5)
D020 16LF87XA —7.5 30 µAVDD = 3.0V, WDT enabled,
-40°C to +85°C
D020 16F87XA —10.5 42 µA VDD = 4.0V, WDT enabled,
-40°C to +85°C
D021 16LF87XA —0.9 5 µAV
DD = 3.0V, WDT disabled,
0°C to +70°C
D021 16F87XA —1.5 16 µA VDD = 4.0V, WDT disabled,
-40°C to +85°C
D021A 16LF87XA 0.9 5 µAV
DD = 3.0V, WDT disabled,
-40°C to +85°C
D021A 16F87XA 1.5 19 µA VDD = 4.0V, WDT disabled,
-40°C to +85°C
D023 ∆IBOR Brown-out
Reset Curre nt(6) —85 200 µA BOR enabled, VDD = 5.0V
17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial)
PIC16LF873A/874A/876A/877A (Industrial ) (Continued)
PIC16LF873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated)
Ope rati ng temperature -40°C ≤ TA ≤ +85°C for industrial
PIC16F873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Symbol Characteristic/
Device Min Typ†Max Units Conditions
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only, and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC o sc co nfigura tion, current through REXT is not in cl uded. T he cu rrent thro ugh th e resi stor can b e esti -
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the spe cific ati on. Thi s val ue is from chara c-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
PIC16F87XA
DS39582A-page 176 Advance Information 2001 Microchip Technology Inc.
17.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industri al)
PIC16LF873A/874A/876A/877A (Industri al)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temp erature - 40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in DC specification
(Section 17.1)
Param
No. Sym Characteristic Min Typ†Max Units Conditions
VIL Input Low Volt ag e
I/O ports
D030 with TTL buffer Vss —0.15VDD V For entire VDD range
D030A Vss —0.8V V 4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer Vss —0.2VDD V
D032 MCLR, OSC1 (in RC mode) VSS —0.2VDD V
D033 OSC1 (in XT and LP modes) VSS —0.3V V (Note 1)
OSC1 (in HS mode) VSS —0.3VDD V
Ports RC3 and RC4 —
D034 with Schmitt Trigger buffer Vss —0.3VDD V For entire VDD range
D034A with SMBus -0.5 —0.6 V for VDD = 4.5 to 5.5V
VIH Input High Voltage
I/O ports —
D040 with TTL buffer 2.0 — VDD V4.5V ≤ VDD ≤ 5.5V
D040A 0.25VDD
+ 0.8V — VDD V For entire VDD range
D041 with Schmitt Trigger buffer 0.8VDD — VDD V For entire VDD range
D042 MCLR 0.8VDD — VDD V
D042A OSC1 (in XT and LP modes) 1.6V — VDD V(Note 1)
OSC1 (in HS mode) 0.7VDD — VDD V
D043 OSC1 (in RC mo de) 0.9VDD — VDD V
Ports RC3 and RC4
D044 with Schmitt Trigger buffer 0.7VDD — VDD V For entire VDD range
D044A with SMBus 1.4 —5.5 V for VDD = 4.5 to 5.5V
D070 IPURB PORTB Weak Pull-up Current 50 250 400 µAVDD = 5V, VPIN = VSS,
-40°C TO +85°C
IIL Input Leak age Current(2, 3)
D060 I/O ports ——±1µAVss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061 MCLR, RA4/T0CKI ——±5µAVss ≤ VPIN ≤ VDD
D063 OSC1 ——±5µAVss ≤ VPIN ≤ VDD, XT, HS
and LP osc configuration
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: In RC oscillato r config uration , the O SC1/CL KIN pi n is a Schm itt Trigger inpu t. It is not rec ommende d that the
PIC16F87XA be driven with external clock in RC mode.
2: The leakage current on the MC LR pin is s trongly depend ent on the applied voltage level. The spe cified lev els
represent normal operating condi tions. Higher leaka ge current may be meas ured at different input volt ages.
3: Negative current is defined as current sourced by the pin.
2001 Microchip Technology Inc. Advance Information DS39582A-page 177
PIC16F87XA
VOL Output Low Voltage
D080 I/O ports ——0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D083 OSC2/CLKOUT (RC osc config) ——0.6 V IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
VOH Output High Voltage
D090 I/O ports(3) VDD - 0.7 —— VIOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 —— VIOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
D150* VOD Open-Drain High Voltage ——8.5 V RA4 pin
Capacitive Loading Specs on
Output Pins
D100 COSC2 OSC2 pin ——15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101
D102 CIO
CBAll I/O pins and OSC2 (RC
mode) SCL, SDA (I2C mode) —
——
—50
400 pF
pF
Data EEPROM Memory
D120 EDEndurance 100K 1M —E/W -40°C to +85°C
D121 VDRW VDD for read/write VMIN —5.5 V Using EECON to read/write
VMIN = min. operating voltage
D122 TDEW Erase/wr ite cycle time —48ms
Program FLASH Memory
D130 EPEndurance 10K 100K —E/W -40°C to +85°C
D131 VPR VDD for read VMIN —5.5 V VMIN = min operating voltage
D132A VDD for erase/write VMIN —5.5 V Using EECON to read/write,
VMIN = min. operating voltage
D133 TPEW Erase/Write cycle time —48ms
17.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industri al)
PIC16LF873A/874A/876A/877A (Industri al) (Continued)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temp erature - 40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in DC specification
(Section 17.1)
Param
No. Sym Characteristic Min Typ†Max Units Conditions
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: In RC oscillato r config uration , the O SC1/CL KIN pin is a Sc hmitt Trigger inpu t. It is not rec ommende d tha t the
PIC16F87XA be driven with external clock in RC mode.
2: The leakage current on the MC LR pin is s trongly depend ent on the applied voltage level. The spe cified lev els
represent normal operating condi tions. Higher leaka ge current may be measu re d at dif ferent input v olt ages.
3: Negative current is defined as current sourced by the pin.
PIC16F87XA
DS39582A-page 178 Advance Information 2001 Microchip Technology Inc.
TABLE 17-1: COMPARATOR SPECIFICATIONS
TABLE 17-2: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C, unless otherwise stated.
Param
No. Characteristics Sym Min Typ Max Units Comments
D300 Input Of fs et Volta ge VIOFF —± 5.0 ± 10 mV
D301 Input Common Mode Voltage* VICM 0-VDD - 1.5 V
D302 Common Mode Rejection Ratio* CMRR 55 - —dB
300
300A Response Time(1)* TRESP —150 400
600 ns
ns PIC16F87XA
PIC16LF87XA
301 Compar ato r Mode C han ge to
Output Valid* TMC2OV ——10 µs
* The se parameters are charact erized but not tested.
Note: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from
VSS to VDD.
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C, unless otherwise stated.
Spec
No. Characteristics Sym Min Typ Max Units Comments
D310 Resolution VRES VDD/24 — VDD/32 LSb
D311 Absolute Accuracy VRAA —
——
—1/4
1/2 LSb
LSb Low Range (VRR = ‘1’)
High Range (VRR = ‘0’)
D312 Unit Resistor Value (R)* VRUR —2k —Ω
310 Settling Time(1)*TSET — — 10 µs
* These parameters are characterized but not tested.
Note: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
2001 Microchip Technology Inc. Advance Information DS39582A-page 179
PIC16F87XA
17.3 Timing Parameter Symbology
The timing parameter symbols have been created
following one of the following formats:
FIGURE 17-3: LOA D CONDITIONS
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
SFFall PPeriod
HHigh RRise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL= 464 Ω
CL= 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports,
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on PIC16F873A/876A de vices.
Load Condition 1 Load Condition 2
PIC16F87XA
DS39582A-page 180 Advance Information 2001 Microchip Technology Inc.
FIGURE 17-4: EXTERNAL CLOCK TIMING
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
TABLE 17-3: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ†Max Units Conditions
FOSC External CLKIN Frequ enc y
(Note 1) DC —4 MHz XT and RC osc mode
DC —20 MHz HS osc mode
DC —200 kHz LP osc mode
Oscillator Frequency
(Note 1) DC —4 MHz RC osc mode
0.1 —4MHzXT osc mode
4
5—
—20
200 MHz
kHz HS osc mode
LP osc mode
1T
OSC External CLKIN Period
(Note 1) 250 ——ns XT and RC osc mode
50 ——ns HS osc mode
5——µs L P osc mode
Oscillator Period
(Note 1) 250 ——ns RC osc mode
250 —10,000 ns XT osc mode
100 —250 ns HS osc mode
50 —250 ns HS osc mode
5——µs L P osc mode
2T
CY Instruction Cycle Time
(Note 1) 200 TCY DC ns TCY = 4/FOSC
3 TosL,
TosH External Clock in (OSC1) High or
Low Time 100 ——ns XT oscillator
2.5 ——µs LP oscillator
15 ——ns HS oscillator
4TosR,
TosF External Clock in (OSC1) R ise or
Fall Time — — 25 ns XT oscillator
— — 50 ns LP oscillator
—— 15 ns HS oscillator
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instr uction cy cle per iod (TCY) equals four times the input osc illator tim e-base period. All specifi ed values are
based on characterization data for that particular oscillator type under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or h igh er tha n e xp ec ted cu rren t cons um ption. Al l dev ic es are te st ed to ope rate a t " mi n." v alu es with an
external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time
limit is "DC" (no clock) for all devices.
2001 Microchip Technology Inc. Advance Information DS39582A-page 181
PIC16F87XA
FIGURE 17-5: CLKOUT AND I/O TIMING
TABLE 17-4: CLKOUT AND I/O TIMING REQUIREMENTS
Note: Refer to Figure 17-3 for load conditions.
OSC1
CLKOUT
I/O Pin
(Input)
I/O Pin
(Output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12 16
Old Value New Value
Param
No. Symbol Characteristic Min Typ†Max Units Conditions
10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns (Note 1)
11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns (Note 1)
12* TckR CLKOUT rise time —35 100 ns (Note 1)
13* TckF CLKOUT fall time —35 100 ns (Note 1)
14* Tck L2ioV CLKOUT ↓ to Port out valid ——0.5TCY + 20 ns (Note 1)
15* TioV2ckH Port in valid before CLKOUT↑ TOSC + 200 ——ns (Note 1)
16* TckH2ioI Port in hold after CLKOUT↑ 0——ns (No te 1)
17* TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid —100 255 ns
18* TosH2ioI OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
S tandard (F) 100 ——ns
Extended (LF) 200 ——ns
19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 ——ns
20* TioR Port output rise time Standard ( F) — 10 40 ns
Extended (LF)——145 ns
21* TioF Port output fall time S tandard (F) — 10 40 ns
Extended (LF)——145 ns
22††* Tinp INT pin high or low time TCY ——ns
23††* Trbp RB7:RB4 change INT high or low time TCY ——ns
* These parameters are characterized but not tested.
†Data in "Typ " column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
PIC16F87XA
DS39582A-page 182 Advance Information 2001 Microchip Technology Inc.
FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMI NG
FIGURE 17-7: BROWN-OUT RESET TIMING
TABLE 17-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 17-3 for load conditions.
VDD VBOR
35
Parameter
No. Symbol Characteristic Min Typ†Max Units Conditions
30 TMCLMCLR Pulse Width (low) 2 ——µsVDD = 5V, -40°C t o +8 5°C
31* TWDT Watchdog Ti mer T ime-out Period
(No Prescaler) 71833msVDD = 5V, -40°C t o +8 5°C
32 TOST Oscillation Start-up Timer Period —1024 TOSC ——TOSC = OSC1 period
33* TPWRT P ower-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C
34 TIOZ I/O Hi-impedanc e from MCLR Low
or Watchdog Timer Reset ——2.1 µs
35 TBOR B rown-out Reset pulse width 100 ——µsVDD ≤ VBOR (D005)
* These parameters are characterized but not tested.
†Data in "Typ " column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2001 Microchip Technology Inc. Advance Information DS39582A-page 183
PIC16F87XA
FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 17-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Symbol Characteristic Min Typ†Max Units Conditions
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 ——ns Must also meet
parameter 42
With Pre scal e r 10 ——ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 ——ns Must also meet
parameter 42
With Pre scal e r 10 ——ns
42* Tt0P T0CKI Period No Prescaler TCY + 40 ——ns
With Prescaler Greater of:
20 or TCY + 40
N
——ns N = prescale value
(2, 4,..., 256)
45* Tt1H T1CKI High Time Synchrono us, Prescaler = 1 0.5TCY + 20 ——ns Must also meet
parameter 47
Synchronous,
Prescaler = 2,4, 8 Standard(F)15——ns
Extended(LF)25——ns
Asynchronous Standard(F)30——ns
Extended(LF)50——ns
46* Tt1L T 1CKI Low Time Synchronous, Pr escaler = 1 0.5 TCY + 20 ——ns Must also meet
parameter 47
Synchronous,
Prescaler = 2,4, 8 Standard(F)15——ns
Extended(LF)25——ns
Asynchronous Standard(F)30——ns
Extended(LF)50——ns
47* Tt1P T1CKI input
period Synchronous Standard(F) Greater of:
30 OR TCY + 40
N
——ns N = prescale value
(1, 2, 4, 8)
Extended(LF) Greater of:
50 OR TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous Standard(F)60——ns
Extended(LF) 100 ——ns
Ft1 Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz
48 T CKEZt mr1 Delay from external clock edge to timer increment 2TOSC —7TOSC —
* These parameters are characterized but not tested.
†Data in "Typ" co lumn is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note: Refer to Figure 17-3 for load conditions.
46
47
45
48
41
42
40
RA4/T0CKI
RC0/T1OSO/T1CKI
TMR0 o r
TMR1
PIC16F87XA
DS39582A-page 184 Advance Information 2001 Microchip Technology Inc.
FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 17-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Note: Refer to Figure 17-3 for load conditions.
and RC2/CCP1
(Capture Mode)
50 51
52
53 54
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
RC1/T1OSI/CCP2
Param
No. Sym Characteristic Min Typ†Max Units Conditions
50* TccL CCP1 and CCP2
input low time No Prescaler 0.5TCY + 20 ——ns
With Prescal er Standard(F)10——ns
Extended(LF)20——ns
51* TccH CCP1 and CCP2
input high time No Prescaler 0.5TCY + 20 ——ns
With Prescal er Standard(F)10——ns
Extended(LF)20——ns
52* TccP CCP1 and CCP2 input period 3TCY + 40
N——ns N = prescale
value (1, 4 or 16)
53* TccR CCP1 and CCP2 output rise time Standard(F) — 10 25 ns
Extended(LF) — 25 50 ns
54* TccF CCP1 and CCP2 output fall time Standard(F) — 10 25 ns
Extended(LF) — 25 45 ns
* These parameters are charact erized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2001 Microchip Technology Inc. Advance Information DS39582A-page 185
PIC16F87XA
FIGURE 17-10: PARALLEL SLAVE PORT TIMING (PIC16F874A/877A ONLY)
TABLE 17-8: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874A/877A ONLY)
Note: Refer to Figure 17-3 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
Parameter
No. Symbol Characteristic Min Typ†Max Units Conditions
62 T dtV2wr H D a ta in v a l i d before WR ↑ or CS↑ (se tup time) 20 ——ns
63* TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) St andard( F)20——ns
Extended(LF)35——ns
64 TrdL2dtV RD↓ and CS↓ to data–out valid ——80 ns
65 TrdH2dtI RD↑ or CS↓ to data–out invalid 10 —30 ns
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
PIC16F87XA
DS39582A-page 186 Advance Information 2001 Microchip Technology Inc.
FIGURE 17-11: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
FIGURE 17-12: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
BIT6 - - - - - -1
MSb IN LSb IN
BIT6 - - - -1
Note: Refer to Figure 17-3 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb IN
BIT6 - - - - - -1
LSb IN
BIT6 - - - -1
LSb
Note: Refer to Figure 17-3 for load conditions.
2001 Microchip Technology Inc. Advance Information DS39582A-page 187
PIC16F87XA
FIGURE 17-13: SPI SLAVE MODE TIMING (CKE = 0)
FIGURE 17-14: SPI SLAVE MODE TIMING (CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
SDI
MSb LSb
BIT6 - - - - - -1
MSb IN BI T6 - - - -1 LSb IN
83
Note: Refer to Figure 17-3 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSb BIT6 - - - - - -1 LSb
77
MSb IN BIT6 - - - -1 LSb IN
80
83
Note: Refer to Figure 17-3 for load conditions.
PIC16F87XA
DS39582A-page 188 Advance Information 2001 Microchip Technology Inc.
TABLE 17-9: SPI MODE REQUI REMENTS
FIGURE 17-15 : I2C BUS START/STOP BITS TIMING
Param
No. Symbol Characteristic Min Typ†Max Units Conditions
70* TssL2scH,
TssL2scL SS↓ to SCK↓ or SCK↑ input Tcy ——ns
71* TscH SCK input high time (Slave mod e) TCY + 20 ——ns
72* TscL SCK input low time (Slave mode) TCY + 20 ——ns
73* TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK edge 100 ——ns
74* TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 ——ns
75* TdoR SDO data output rise time Standard(F)
Extended(LF)—
—10
25 25
50 ns
ns
76* TdoF SDO data output fall time —10 25 ns
77* TssH2doZ SS↑ to SDO output hi-impedance 10 —50 ns
78* TscR SCK output rise time (Master mode) Standard(F)
Extended(LF)—
—10
25 25
50 ns
ns
79* TscF S C K output fall time (Master mode) —10 25 ns
80* TscH2doV,
TscL2doV SDO data output valid after SCK
edge Standard(F)
Extended(LF)—
——
—50
145 ns
81* TdoV2scH,
TdoV2scL SDO data output setup to SCK edge Tcy ——ns
82* TssL2doV SDO data output valid after SS↓ edge ——50 ns
83* TscH2ssH,
TscL2ssH SS↑ after SCK edge 1.5TCY + 40 ——ns
* These parameters are characterized but not tested.
†Data in "Typ " column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note: Refer to Figure 17-3 for load conditions.
91 93
SCL
SDA
START
Condition STOP
Condition
90 92
2001 Microchip Technology Inc. Advance Information DS39582A-page 189
PIC16F87XA
TABLE 17-10: I2C BUS START/STOP BITS REQUIREMENTS
FIGURE 17-16 : I2C BUS DATA TIMING
Parameter
No. Symbol Characteristic Min Typ Max Units Conditions
90 Tsu:sta START condition 100 kHz mode 4700 —— ns Only relevant for Repeated
START condition
Setup time 400 kHz mode 600 ——
91 Thd:sta START condition 100 kHz mode 4000 —— ns After this period, the first clock
pulse is generated
Hold time 400 kHz mode 600 ——
92 Tsu:sto STOP condition 100 kHz mode 4700 —— ns
Setup time 400 kHz mode 600 ——
93 Thd:sto STOP condition 100 kHz mode 4000 —— ns
Hold time 400 kHz mode 600 ——
Note: Refer to Figure 17-3 for load conditions.
90
91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
PIC16F87XA
DS39582A-page 190 Advance Information 2001 Microchip Technology Inc.
TABLE 17-11: I2C BUS DATA REQUIREMENTS
Param
No. Sym Characteristic Min Max Units Conditions
100 THIGH Clock high time 100 kHz mode 4.0 —µs Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 —µs Device must operate at a
minimum of 10 MHz
SSP Module 0.5TCY —
101 TLOW Clock low time 100 kHz mode 4.7 —µs Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 —µs Device must operate at a
minimum of 10 MHz
SSP Module 0.5TCY —
102 TRSDA and SCL rise
time 100 kHz mode —1000 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10 to 400 pF
103 TFSDA and SCL fall time 100 kHz mode —300 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10 to 400 pF
90 Tsu:sta START condition
setup time 100 kHz mode 4.7 —µs Only relevant for Repeated
START condition
400 kHz mode 0.6 —µs
91 Thd:sta START condition hold
time 100 kHz mode 4.0 —µs After this period, the first clock
pulse is generated
400 kHz mode 0.6 —µs
106 Thd:dat Data input hold time 100 kHz mode 0 —ns
400 kHz mode 0 0.9 µs
107 Tsu:dat Data input setup time 100 kHz mode 250 —ns (Note 2)
400 kHz mode 100 —ns
92 Tsu:sto STOP condition setup
time 100 kHz mode 4.7 —µs
400 kHz mode 0.6 —µs
109 TAA Output valid from
clock 100 kHz mode —3500 ns (Note 1)
400 kHz mode ——ns
110 TBUF Bus free time 100 kHz mode 4.7 —µs Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 —µs
CBBus capacitive loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement that
Tsu:dat ≥250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+ Tsu:dat = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is
released.
2001 Microchip Technology Inc. Advance Information DS39582A-page 191
PIC16F87XA
FIGURE 17-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 17-18: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 17-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Note: Refer to Figure 17-3 for load conditions.
121 121
122
RC6/TX/CK
RC7/RX/DT
Pin
Pin
120
Param
No. Sym Characteristic Min Typ†Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
Standard(F)——80 ns
Extended(LF)——100 ns
121 Tckrf Clock out rise time and fall time
(Master mode) Standard(F)——45 ns
Extended(LF)——50 ns
122 Tdtrf Data out rise time and fall time Standard(F)——45 ns
Extended(LF)——50 ns
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note: Refer to Figure 17-3 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Parameter
No. Sym Characteristic Min Typ†Max Units Conditions
125 Td tV2c k L SYNC RCV (MASTER & SLAVE)
Dat a setup before CK↓ (DT setup time) 15 ——ns
126 TckL2dtl Data hold after CK↓ (DT hold time) 15 ——ns
†Data in “Typ” column is at 5V, 25°C unl es s o the rw is e s t at ed. These p a ram eters are f or design gu ida nc e o nly
and are not tested.
PIC16F87XA
DS39582A-page 192 Advance Information 2001 Microchip Technology Inc.
TABLE 17-14: A/D CONVERTER CHARACTERISTICS:PIC16F873A/874A/876A/877A (INDUSTRIAL)
PIC16LF873A/874A/876A/877A (INDUSTRIAL)
Param
No. Sym Characteristic Min Typ†Max Units Conditions
A01 NRResolution ——10-bits bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03 EIL Integral linearity error ——< ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04 EDL Differential linearity error ——< ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06 EOFF Offset error ——< ± 2 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A07 EGN Gain e rror ——< ± 1 LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10 —Monotonicity —guaranteed(3) ——VSS ≤ VAIN ≤ VREF
A20 VREF Reference voltage (VREF+ - VREF-) 2.0 — VDD + 0.3 V Absolute minimum electrical
spec. To ensure 10-bit
accuracy.
A21 VREF+ Reference voltage High AVDD - 2.5V AVDD + 0.3V V
A22 VREF- Reference voltage Low AVSS - 0.3V VREF+ - 2.0V V
A25 VAIN Analog input voltage VSS - 0.3 V — VREF + 0.3 V V
A30 ZAIN Recommended impedance of
analog voltage source ——10.0 kΩ
A40 IAD A/D conversion
current (VDD)Standard —220 —µA Average current consumption
when A/D is on (Note 1)
Extended —90 —µA
A50 IREF VREF input current (Note 2) 10
—
—
—
1000
10
µA
µA
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 11.1.
During A/D Conversion cycle
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.
2001 Microchip Technology Inc. Advance Information DS39582A-page 193
PIC16F87XA
FIGURE 17-19: A/D CONVERSION TIMING
TABLE 17-15: A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPE D
DONE
NEW_DATA
(TOSC/2)(1)
987 210
Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts . This allows the SLEEP
instruction to be executed.
1 TCY
. . . . . .
Param
No. Sym Characteristic Min Typ†Max Units Conditions
130 TAD A/D clock period Standard(F)1.6——µsTOSC based, VREF ≥ 3.0V
Extended(LF)3.0——
µsTOSC based, V REF ≥ 2.0V
Standard(F) 2.0 4.0 6.0 µs A/D RC mode
Extended(LF) 3.0 6.0 9.0 µs A /D RC mode
131 TCNV Conversion time (not including S/H time)
(Note 1) —12 TAD
132 TACQ Acquisition time (Note 2)
10*
40
—
—
—
µs
µs The minimum time is the
amplifier settling time. This may
be used if the "new" input volt-
age has not changed by more
than 1 LSb (i.e., 20.0 mV @
5.12V) from the last sampled
voltage (as stated on CHOLD).
134 TGO Q4 to A/D clock start — TOSC/2 §— —If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
§This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.1 for minimum conditions.
PIC16F87XA
DS39582A-page 194 Advance Information 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. Advance Information DS39582A-page 195
PIC16F87XA
18.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs are not available at this time.
PIC16F87XA
DS39582A-page 196 Advance Information © 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. Advance Information DS39582A-page 197
PIC16F87XA
19.0 PACKAGING INFORMATION
19.1 Package Marking Information
XXXXXXXXXXXXXXXXXX
YYWWNNN
40-Lead PDIP Example
44-Lead TQFP
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX
Example
44-Lead PLCC Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX
XXXXXXXXXX
PIC16F877A-/P
0112017
-/PT
0111017
PIC16F877A
-20/L
0103017
PIC16F877A
Legend: XX...X Customer specific information*
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event th e full Mi croch ip p art numbe r canno t be marke d on one li ne, it w ill
be carried o ver to the ne xt line thus lim iting the nu mb er of a vai la ble cha rac ters
for customer specific information.
*Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
PIC16F87XA
DS39582A-page 198 Advance Information 2001 Microchip Technology Inc.
Package Marking Information (Cont’d)
28-Lead SOIC
YYWWNNN
Example
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead PDIP (Skinny DIP) Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
0117017
PIC16F876A-/SP
XXXXXXXXXXXXXXXXX 0110017
PIC16F876A-/SO
28-Lead SSOP
YYWWNNN
Example
XXXXXXXXXXXX
28-Lead MLF Example
XXXXXXXX
XXXXXXXX
YYWWNNN
1
PIC16F873A
-I/ML
0112017
1
XXXXXXXXXXXX 0110017
PIC16F876A
-/SO
2001 Microchip Technology Inc. Advance Information DS39582A-page 199
PIC16F87XA
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 17.2716.5115.75.680.650.620eBOverall Row Spacing §0.560.460.36.022.018.014BLower Lea d Width 1.781.270.76.070.050.030B1Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thic kness 3.433.303.05.135.130.120LTip to Seating Plane 52.4552.2651.942.0652.0582.045DOverall Length 14.2213.8413.46.560.545.530E1Molded Package Width 15.8815.2415.11.625.600.595EShoulder to Shoulder Width 0.38.015
A1
Base to Seating Plane 4.063.813.56.160.150.140A2Molded Package Thickness 4.834.454.06.190.175.160ATop to Seating Plane 2.54.100
p
Pitch 4040
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
A2
1
2
D
n
E1
c
β
eB
E
α
p
L
B
B1
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
§ Significant Characteristic
PIC16F87XA
DS39582A-page 200 Advance Information 2001 Microchip Technology Inc.
44-Lead Plastic Thin Quad Flatp ack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
* Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
1.140.890.64.045.035.025CHPin 1 Corner Chamfer
1.00.039
(F)
Footprint (Reference)
(F)
A
A1 A2
α
E
E1
#leads=n1
p
B
D1 D
n
1
2
φ
c
βL
Units INCHES MILLIMETERS*
Dim ension Limi ts MIN NOM MAX MIN NOM MAX
Numb er of Pin s n44 44
Pitch p.031 0.80
Overall Height A .039 .043 .047 1.00 1.10 1.20
Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05
Standoff §A1 .002 .004 .006 0.05 0.10 0.15
Foot Length L .018 .024 .030 0.45 0.60 0.75
Foot A ngle φ03.5 7 03.5 7
Overall Width E .463 .472 .482 11.75 12.00 12.25
Overall Length D .463 .472 .482 11.75 12.00 12.25
Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10
Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10
Pins per Side n1 11 11
Lead Thickness c.004 .006 .008 0.09 0.15 0.20
Lead Width B .012 .015 .0 17 0.3 0 0.38 0.44
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
CH x 45°
§ Significant Characteristic
2001 Microchip Technology Inc. Advance Information DS39582A-page 201
PIC16F87XA
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
CH2 x 45°CH1 x 45°
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.530.510.33.021.020.013B0.810.740.66.032.029.026B1Upper Lead Width 0.330.270.20.013.011.008
c
Lead Thickness
1111n1Pins per Side
16.0015.7514.99.630.620.590
D2
Footprint Length 16.0015.7514.99.630.620.590E2Footprint Width 16.6616.5916.51.656.653.650D1Molded Package Length 16.6616.5916.51.656.653.650E1Molded Package Width 17.6517.5317.40.695.690.685DOverall Length 17.6517.5317.40.695.690.685EOverall Width 0.250.130.00.010.005.000CH2Corner Chamfer (others) 1.271.141.02.050.045.040CH1Corner Chamfer 1 0.860.740.61.034.029.024
A3
Side 1 Chamfer Height 0.51.020A1Standoff §A2
Molded Package Thickness 4.574.394.19.180.173.165AOverall Height
1.27.050
p
Pitch 4444
n
Number of Pins MAXNOMMINMAXNOMMINDime nsion Limits MILLIMETERSINCHES*Units
β
A2
c
E2
2
D
D1
n
#leads=n1
E
E1
1
α
p
A3
A
35°
B1
B
D2
A1
.145 .153 .160 3.68 3.87 4.06
.028 .035 0.71 0.89
Lower Lead Width
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
§ Significant Characteristic
PIC16F87XA
DS39582A-page 202 Advance Information 2001 Microchip Technology Inc.
28-Lead Skinny Plasti c Dual In-line (SP) – 300 mil (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 10.928.898.13.430.350.320
eB
Overall Row Spacing §0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Length 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125A2Molded Package Thickness 4.063.813.56.160.150.140ATop to Seating Plane 2.54.100
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units
2
1
D
n
E1
c
eB
β
E
α
p
L
A2
B
B1
A
A1
Notes:
JEDEC Equivalent: MO-095
Drawing No. C04-070
* Controlling Parameter
Dimension D and E1 do not include mo ld flash or protrusion s. Mold flash or protrusions shall not excee d
.010” (0.254 mm ) per s ide.
§ Significant Characteristic
2001 Microchip Technology Inc. Advance Information DS39582A-page 203
PIC16F87XA
28-Lead Plastic Small Outline (SO) –Wide, 300 mil (SOIC)
Foot Angle Top φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff §2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limi ts MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
β
45°
h
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
§ Significant Characteristic
PIC16F87XA
DS39582A-page 204 Advance Information 2001 Microchip Technology Inc.
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
10501050Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840
φ
Foot Angle 0.250.180.10.010.007.004
c
Lead Thickness 0.940.750.56.037.030.022LFoot Length 10.3410.2010.06.407.402.396DOvera ll Length 5.385.255.11.212.207.201E1Molded Package Width 8.107.857.59.319.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff §1.831.731.63.072.068.064A2Molded Package Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDim en sion Li mits MILLIMETERS*INCHESUnits
2
1
D
p
n
B
E1
E
L
β
c
φ
α
A2
A1
A
β
§ Significant Characteristic
2001 Microchip Technology Inc. Advance Information DS39582A-page 205
PIC16F87XA
28-Lead Plastic Micro Leadframe Package (MF) 6x6 mm Body (MLF) — Packaging
Lead Width
*Con tro ll ing Pa ra me ter
Notes:
Mold Draft Angle Top
B
α
.009
12
.011 .014 0.23
12
0.28 0.35
D
Pitch
Number of Pins
Overall Width
Standoff
Molded Package Length
Overall Length
Molded Package Width
Molded Package Thickness
Overall Height
MAX
Units
Dimension Limits
A2
A1
E1
D
D1
E
n
p
A.026
.236 BSC
.000
.226 BSC
INCHES
.026 BSC
MIN 28
NOM MAX
0.65
.031
.002 0.00
6.00 BSC
5.75 BSC
MILLIMETERS*
.039
MIN 28
0.65 BSC
NOM
0.80
0.05
1.00
E
E1
n
1
2
D1
A
A2
EXPOSED
METAL
PADS
BOTTOM VIEW
.008 REF.Base Thickness A3 0.20 REF.
TOP VI EW
0.85.033
.0004 0.01
.236 BSC
.226 BSC 6.00 BSC
5.75 BSC
Q
L
Lead Length
Tie Bar Width L .020.024.0300.500.600.75
R .005.007.0100.130.170.23
T ie Bar Length Q.012 .016 .026 0.30 0.40 0.65
Chamfer CH .009.017.0240.240.420.60
R
p
A1
A3
α
CH x 45
B
D2
E2
E2
D2
Exposed Pa d Width
Exposed Pa d Len gth .140 .146 .152 3.55 3.70 3.85
.140 .146 .152 3.55 3.70 3.85
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC equivalent: pending
Drawing No. C04-114
PIC16F87XA
DS39582A-page 206 Advance Information 2001 Microchip Technology Inc.
28-Lead Plastic Micro Leadframe Package (MF) 6x6 mm Body (MLF) — Solder Pads
Pad Width
*Controlling Parameter
Drawing No. C04-2114
B .009 .011 .014 0.23 0.28 0.35
Pitch MAX
Units
Dimension Limits
p
INCHES
.026 BSC
MIN NOM MAX
MILLIMETERS*
MIN 0.65 BSC
NOM
Pad Length
Pad to Solder Mask L .020 .024 .030 0.50 0.60 0.75
M .005 .006 0.13 0.15
L
p
M
M B
PACKAGE
EDGE
SOLDER
MASK
2001 Microchip Technology Inc. Advance Information DS39582A-page 207
PIC16F87XA
APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE
DIFFERENCES
The differenc es between the dev ices in this dat a she et
are listed in Table B-1.
TABLE B-1: DIFFERENCES BETWEEN DEVICES IN THE PIC16F87XA FAMILY
Version Date Revision Description
A 11/2001 Original revision.
The devices presented are
enhanced versions of the
PIC16F87X mi cro con trol ler s dis -
cussed in the “P IC16F87X Data
Sheet” (DS30292) .
PIC16F873A PIC16F874A PIC16F876A PIC16F877A
FLASH P rogram Memory
(14-bit words) 4K 4K 8K 8K
Data Memory (bytes) 192 192 368 368
EEPROM Data Memory (bytes) 128 128 256 256
Interrupts 14 15 14 15
I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E
Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART
Parallel Slave Port no yes no yes
10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels
Packages 28-pin PDIP
28-pin SOIC
28-p in SSOP
28-pin MLF
40-pin PDIP
44-pin PLCC
44-pin QFP
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin MLF
40-pin PDIP
44-pin PLCC
44-pin QF P
PIC16F87XA
DS39582A-page 208 Advance Information 2001 Microchip Technology Inc.
APPENDIX C: CONVERSION
CONSIDERATIONS
Considerations for converting from previous versions
of de vices to the one s listed in this dat a sheet are liste d
in Table C-1.
TABLE C-1: CONVERSION CONSIDERATIONS
Characteristic PIC16C7X PIC16F87X PIC16F87XA
Pins 28/40 28/40 28/40
Timers 3 3 3
Interrupts 11 or 12 13 or 14 14 or 15
Communication PSP, USART, SSP
(SPI, I2C Slave) PSP, USART, SSP
(SPI, I2C Master/Sla ve) PSP, USART, SSP
(SPI, I2C Master/Slave)
Frequency 20 MHz 20 MHz 20 MHz
Voltage 2.5V - 5.5V 2.2V - 5.5V 2.0V - 5.5V
A/D 8-bit,
4 convers ion clock selects 10-bit,
4 conver si on clo ck select s 10-bit,
7 conve rsi on clock sele cts
CCP 2 2 2
Comparator —— 2
Comparator Voltage
Reference ——yes
Program Memory 4K, 8K EPROM 4K, 8K FLASH
(Erase/Write on
single word)
4K, 8K FLASH
(Erase/Write on
four-word blo cks)
RAM 192, 368 bytes 192, 368 bytes 192, 368 bytes
EEPROM data None 128, 256 bytes 128, 256 bytes
Code Protectio n On/Of f Segmented, s tarting at end
of pr ogram memory On/Off
Program Memory
Write Protection —On/Off Segmented, starting at
beginning of
program memory
Other In-Circuit Debugger,
Low Voltage Programming In-Circuit Debugge r,
Low Voltage Programming
2001 Microchip Technology Inc. Advance Information DS39582A-page 209
PIC16F87XA
INDEX
A
A/D ...................................................................................125
Acquisition Requirements ........................................128
ADCON0 Register ....................................................125
ADCON1 Register ....................................................125
ADIF bit ....................................................................127
ADRESH Register ....................................................125
ADRESL Register ....................................................125
Analog Port Pins .................................................. 47, 49
Associated Registers and Bits .................................131
Calculating Acquisition Time ....................................128
Configuring Analog Port Pins ...................................129
Configuring the Interrupt ..........................................127
Configuring the Module ............................................127
Conversion Clock .....................................................129
Conversions .............................................................130
Converter Characteristics ........................................192
Delays ......................................................................128
Effects of a RESET ..................................................131
GO/DONE bit ...........................................................127
Internal Sampling Switch (Rss) Impedance .............128
Operation During SLEEP .........................................131
Result Registers .......................................................130
Source Impedance ...................................................128
Time Delays .............................................................128
A/D Conversion Requirements .........................................193
Absolute Maximum Ratings .............................................171
ACKSTAT ...........................................................................99
ADCON0 Register ..............................................................17
ADCON1 Register ..............................................................18
Addressable Universal Synchronous Async h ronous
Receiver Transmitter. See USART.
ADRESH Register ..............................................................17
ADRESL Register ..............................................................18
Analog-to-Digital Converter. See A/D.
Application Notes
AN552 (Implementing Wake-up on Key Strokes
Using PIC16CXXX) ....................................42
AN556 (Implementing a Table Read) ........................28
Assembler
MPASM Ass e mbler ..................................................165
Asynchronous Reception
Associated Registers ....................................... 116, 118
Asynchronous Transmission
Associated Registers ...............................................114
B
Banking, Data Memory ................................................. 14, 20
Baud Rate Generator .........................................................95
Associated Registers ...............................................111
BCLIF .................................................................................26
BF .......................................................................................99
Block Diagram
RA3:RA0 Port Pins ....................................................39
Block Diagrams ..................................................................56
A/D ...........................................................................127
Analog Input Model .......................................... 128, 137
Baud Rate Generator .................................................95
Capture Mode Operation ...........................................63
Comparator I/O Operating Modes ............................134
Comparator Output ..................................................136
Comparator Voltage Reference ...............................140
Compare Mode Operation .........................................64
Crystal/Ceramic Resonator Operation (HS, XT
or LP Osc Configuration) ......................... 143
External Clock Input Operation (HS, XT
or LP Osc Configuration) ......................... 143
Interrupt Logic .......................................................... 151
MSSP
I2C Mode ........................................................... 78
MSSP (SPI Mode) ..................................................... 69
On-Chip RESET Circuit ........................................... 145
PIC16F873A/PIC16F 876A Arc hitecture ...................... 6
PIC16F874A/PIC16F 877A Arc hitecture ...................... 7
PORTC
Peripheral Output Override
(RC 0:2, 5:7) Pins .............................. 44
Peripheral Output Override
(RC 3:4) Pins ..................................... 44
PORTD (in I/O Port Mode) ......................................... 46
PORTD and PORTE (Parallel Slave Port) ................. 49
PORTE (In I/O Port Mode) ......................................... 47
RA4/T0CKI Pin .......................................................... 40
RA5 Pin ..................................................................... 40
RB3:RB0 Port Pins .................................................... 42
RC Oscillator Mode .................................................. 144
Recommended MCLR Circui t .................................. 146
Simplified PWM Mode ............................................... 65
Timer0/WDT Prescaler .............................................. 51
Timer2 ....................................................................... 59
USART Receive ................................................115, 117
USART Transmi t ...................................................... 113
Watchdog Timer ...................................................... 153
BOR. See Brown-out Reset.
BRG. See Baud Rate Generator.
BRGH Bit ......................................................................... 111
Brown-out Reset (BOR) .................... 141, 145, 146, 147, 148
BOR Status (BOR Bit) ............................................... 27
Bus Collision During a Repeated START
Condition ................................................................. 106
Bus Collision During a START Condition ........................ 104
Bus Collision During a STOP Condition .......................... 107
Bus Collision Interrupt Flag bit, BCLIF ............................... 26
Bus Collision Timing for Transmit and
Acknowledge ........................................................... 103
C
Capture/Compare/PWM (CCP) ......................................... 61
Associated Registers
Capture, Compare and Timer1 .......................... 66
PWM and Timer2 ............................................... 67
Capture Mode ............................................................ 63
CCP1IF .............................................................. 63
Prescaler ........................................................... 63
CCP Timer Resources ............................................... 61
Compare
Special Trigger Output of CCP1 ........................ 64
Special Trigger Output of CCP2 ........................ 64
Compare Mode .......................................................... 64
Software Interrupt Mode .................................... 64
Special Event Trigger ........................................ 64
Interaction of Two CCP Modules (Table) ................... 61
PWM Mo de ................................................................ 65
Duty Cycle ......................................................... 65
Example Frequencies/Resolution s (Table) ........ 66
PWM Period ...................................................... 65
Special Event Trigger and A/D Conversions ............. 64
PIC16F87XA
DS39582A-page 210 Advance Information 2001 Microchip Technology Inc.
Capture/Compare/PWM Requirements
(CCP1 and CCP2) ....................................................184
CCP. See Capture/Compare/PWM.
CCP1CON ..........................................................................19
CCP1CON Register ...........................................................17
CCP2CON ..........................................................................19
CCP2CON Register ...........................................................17
CCPR1H Register .................................................. 17, 19, 61
CCPR1L Register ................................................... 17, 19, 61
CCPR2H Register ........................................................17, 19
CCPR2L Register .........................................................17, 19
CCPxM0 bit ........................................................................62
CCPxM1 bit ........................................................................62
CCPxM2 bit ........................................................................62
CCPxM3 bit ........................................................................62
CCPxX bit ...........................................................................62
CCPxY bit ...........................................................................62
CLKOUT and I/O Timing Requirements ...........................181
CMCON Register ...............................................................18
Code Examples
Call of a Subroutine in Page 1 from Page 0 ...............28
Indirect Addressing ....................................................29
Initia li z ing PORTA ......................................................39
Loading the SSPBUF (SSPSR ) Register ...................72
Reading Data EEPROM .............................................33
Reading FLASH Program Memory ............................34
Saving STATUS, W and PCLATH Registers ...........152
Writing to Data EEPROM ...........................................33
Writing to FLASH Program Memory ...........................36
Code Protection .......................................................141, 155
Comparator Module .........................................................133
Analog Input Connection Considerations .................137
Associated Registers ...............................................138
Configuration ............................................................134
Effects of RE SE T .....................................................137
Interrupts ..................................................................136
Operation .................................................................135
Operation During SLEEP .........................................137
Outputs .....................................................................135
Reference .................................................................135
Response Time ........................................................135
Comparator Voltage Reference .......................................139
Associated Registers ...............................................140
Computed GOTO ...............................................................28
Configuration Bits .............................................................141
Configuration Word ..........................................................142
Conversion Considerations ..............................................208
CVRCON Register .............................................................18
D
Data EEPROM and FLASH Program Memory
EEADR Register ........................................................31
EEADRH Register ......................................................31
EECON1 Register ......................................................31
EECON2 Register ......................................................31
EEDATA Register ......................................................31
EEDATH Register ......................................................31
Data EEPROM Memory
Associated Registers ................................................. 37
EEADR Register ........................................................ 31
EEADRH Register ..................................................... 31
EECON1 Register ...................................................... 31
EECON2 Register ...................................................... 31
Operation During Code Protect ................................. 37
Protection Against Spurious Writes ........................... 37
Reading ..................................................................... 33
Write Complete Flag (EEIF Bit) ................................. 31
Writing ........................................................................ 33
Data Memory ..................................................................... 14
Ban k Select (RP1:RP0 Bits ) .................................14, 20
General Purpose Registers ....................................... 14
Register File Map ..................................................15, 16
Special Function Registers ........................................ 17
DC and AC Characteristics Graphs and Tables .............. 195
DC Characteristics ....................................................173–177
Development Support ...................................................... 165
Device Differences ........................................................... 207
Device Overview .................................................................. 5
Direct Addressing ............................................................... 29
E
EEADR Register ...........................................................19, 31
EEADRH Register .........................................................19, 31
EECON1 Register .........................................................19, 31
EECON2 Register .........................................................19, 31
EEDATA Register .............................................................. 19
EEDATH Register .............................................................. 19
Electrical Characteristics .................................................. 171
Errata ................................................................................... 4
External Interrupt Input (RB0/INT). See Interrupt Sources.
External Reference Signal ............................................... 135
F
Firmware Instructions ....................................................... 157
FLASH Program Memory
Associated Registers ................................................. 37
EECON1 Register ...................................................... 31
EECON2 Register ...................................................... 31
Reading ..................................................................... 34
Writing ........................................................................ 35
FSR Register ....................................................17, 18, 19, 29
G
General Call Address Support ........................................... 92
I
I/O Por ts ............................................................................. 39
I2C Bus Data Requirements ............................................ 190
I2C Bus START/STOP Bit s Requirement s ....................... 189
I2C Mode
Registers .................................................................... 78
I2C Mode ............................................................................ 78
ACK Pulse ............................................................82, 83
Acknowledge Sequence Timing .............................. 102
Baud Rate Generator ................................................. 95
Bus Collision
Repeated START Condition ............................ 106
START Condition ............................................. 104
STOP Condition ............................................... 107
Clock Arbitration ........................................................ 96
Effect of a RESE T .................................................... 103
2001 Microchip Technology Inc. Advance Information DS39582A-page 211
PIC16F87XA
General Call Address Support ...................................92
Master Mode ..............................................................93
Operation ...........................................................94
Repeated START Timing ...................................98
Master Mode Reception .............................................99
Master Mode START Condition .................................97
Master Mode Transmission ........................................99
Multi-Master Communication, Bus Collision
and Arbitration .........................................103
Multi-Master Mode ...................................................103
Read/Write Bit Information (R/W Bit) ................... 82, 83
Serial Clock (RC3/SCK/SCL) .....................................83
Slave Mode ................................................................82
Addressing .........................................................82
Reception ...........................................................83
Transmission ......................................................83
SLEEP Operation .....................................................103
STOP Condition Timing ...........................................102
ICEPIC In - Circuit Emulato r ..............................................166
ID Locations ............................................................. 141, 155
In-Circuit Debugger .................................................. 141, 155
Resources ................................................................155
In-Circuit Serial Programming (ICSP) ...................... 141, 156
INDF ...................................................................................19
INDF Register .........................................................17, 18, 29
Indirect Addressing ............................................................29
FSR Register .............................................................14
Instruction Format ............................................................157
Instruction Set ..................................................................157
ADDLW ....................................................................159
ADDWF ....................................................................159
ANDLW ....................................................................159
ANDWF ....................................................................159
BCF ..........................................................................159
BSF ..........................................................................159
BTFSC .....................................................................159
BTFSS .....................................................................159
CALL ........................................................................160
CLRF ........................................................................160
CLRW ......................................................................160
CLRWDT ..................................................................160
COMF ......................................................................160
DECF .......................................................................160
DECFSZ ...................................................................161
GOTO ......................................................................161
INCF .........................................................................161
INCFSZ ....................................................................161
IORLW .....................................................................161
IORWF .....................................................................161
MOVF .......................................................................162
MOVLW ...................................................................162
MOVWF ...................................................................162
NOP .........................................................................162
RETFIE ....................................................................162
RETLW ....................................................................162
RETURN ..................................................................163
RLF ..........................................................................163
RRF ..........................................................................163
SLEEP .....................................................................163
SUBLW ....................................................................163
SUBWF ....................................................................163
SWAPF ....................................................................164
XORLW ....................................................................164
XORWF ....................................................................164
Summary Table ........................................................158
INT In t e rr up t (RB0/INT) . See Interrupt Sources.
INTCON ............................................................................. 19
INTCON Register ............................................................... 22
GIE Bit ....................................................................... 22
INTE Bit ..................................................................... 22
INTF Bit ..................................................................... 22
PEIE Bit ..................................................................... 22
RBIE Bit ..................................................................... 22
RBIF Bit ................................................................22, 42
TMR0IE Bit ................................................................ 22
TMR0IF Bit ................................................................. 22
Inter-Integrated Circuit. See I2C.
Internal Reference Signal ................................................ 135
Internal Sampling Switch (Rss) Impedance ..................... 128
Interrupt Sources ......................................................141, 151
Interrupt-on-Change (RB7:RB4 ) ............................... 42
RB0/INT Pin, External .....................................9, 11, 152
TMR0 Overflow ........................................................ 152
USART Receive/Transmit Complete ....................... 109
Interrupts
Bus Collision Interrupt ................................................ 26
Synchronous Serial Port Interrupt .............................. 24
Interrupts, Context Saving During .................................... 152
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit) ........................22, 151
Interrupt-on-Change (RB7:RB4) Enable
(RBIE Bit) ............................................22, 152
Peripheral Interrupt Enable (PEIE Bit) ....................... 22
RB0/INT Enable (INTE Bit) ........................................ 22
TMR0 Overflow Enable (TMR0IE Bit) ........................ 22
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ......................................22, 42, 152
RB0/INT Flag (INTF Bit) ............................................ 22
TMR0 Overflow Flag (TMR0IF Bit) .....................22, 152
K
KEELOQ Evaluation and Programming Tools ................... 168
L
Loading of PC .................................................................... 28
Low Voltage ICSP Programming ..................................... 156
Low Voltage In-Circuit Serial Programming ..................... 141
M
Master Clear (MCLR) ........................................................... 8
MCLR Reset, Normal Operation ...............145, 147, 148
MCLR Reset, SLEEP ................................145, 147, 148
Master Synchronous Serial Port (MSSP).
See MS SP .
Master Synchronous Serial Port. See MSSP
MCLR ............................................................................... 146
MCLR/VPP ......................................................................... 10
Memory Organization ........................................................ 13
Data EEPROM Memory ............................................. 31
Data Memory ............................................................. 14
FLASH Program Memory .......................................... 31
Program Memory ....................................................... 13
MPLAB C17 and MPLAB C18 C Compilers .................... 165
MPLAB ICD In-Circuit Debugger ..................................... 167
MPLAB ICE High Performance Universal In-Circuit
Emulator with MPLAB IDE ....................................... 166
MPLAB Integrated Development Environment
Software .................................................................. 165
MPLINK Object Linker/MPLIB Object Librarian ............... 166
PIC16F87XA
DS39582A-page 212 Advance Information 2001 Microchip Technology Inc.
MSSP .................................................................................69
I2C Mode. See I2C.
SPI Mode ...................................................................69
SPI Mode. See SPI
MSSP Mode
SPI Slave Mode .........................................................75
MSSP Module
Clock Stretching .........................................................88
Clock Synchronization and the CKP Bit .....................89
Control Registers (General) .......................................69
Operation ...................................................................82
Overview ....................................................................69
SPI Master Mode .......................................................74
SSPBUF .....................................................................74
SSPSR .......................................................................74
Multi-Master Mode ...........................................................103
N
nternal Reference Signal ..................................................135
O
On-Line Support ...............................................................217
OPCODE Field Descriptions ............................................157
OPTION_REG Register .....................................................21
INTEDG Bit ................................................................21
PS2:PS0 Bits ..............................................................21
PSA Bit .......................................................................21
T0CS Bit .....................................................................21
T0SE Bit .....................................................................21
OSC1/CLKI Pin ..................................................................10
OSC1/CLKIN Pin ..................................................................8
OSC2/CLKOUT Pin ........................................................8, 10
Oscillator Configuration ....................................................141
HS ....................................................................143, 147
LP .....................................................................143, 147
RC ............................................................ 143, 144, 147
XT .....................................................................143, 147
Oscillator, WDT ................................................................153
Oscillators
Capacitor Selection ..................................................144
Ceramic Resonator Selection ..................................143
Crystal and Ceramic Resonators .............................143
RC ............................................................................144
P
Package Marking Information ..........................................197
Packaging Information .....................................................197
Paging, Program Memory ..................................................28
Parallel Slave Port (PSP) ....................................... 12, 46, 49
Associated Registers .................................................50
Block Diagram ............................................................49
RE0/RD/AN5 Pin ..................................................47, 49
RE1/WR/AN6 Pi n .................................................47, 49
RE2/CS/AN7 Pin ..................................................47, 49
Select (PSPMODE Bit) ..............................46, 47, 48, 49
Parallel Slave Port Requirements
(PIC16F874A/877A Only) ........................................185
PCL Register .......................................................... 17, 18, 28
PCLATH Register ..............................................17, 18, 19, 28
PCON Register .................................................... 18, 27, 147
BOR Bit ......................................................................27
POR Bit ......................................................................27
PIC16F87XA Product Identification System .....................219
PICDEM 1 Low Cost PICmicro
Demonstration Board ...............................................167
PICDEM 17 Demonstration Board ...................................168
PICDEM 2 Low Cost PIC16CXX
Demonstration Board ............................................... 167
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board ............................................... 168
PICSTA RT Plus Ent ry Level
Development Programmer ....................................... 167
PIE1 Register ................................................................18, 23
PIE2 Register ................................................................18, 25
Pinout Descriptions
PIC16F873A/PIC16F876A ........................................... 8
PIR1 Register ...............................................................17, 24
PIR2 Register ...............................................................17, 26
POP ................................................................................... 28
POR. See Power-on Reset
PORTA .....................................................................8, 10, 19
Associated Registers ................................................. 41
Functions ................................................................... 41
PORTA Register ...................................................17, 39
TRISA Register .......................................................... 39
PORTB .....................................................................9, 11, 19
Associated Registers ................................................. 43
Block Diagrams
RB7:RB4 Port Pins ............................................ 42
Functions ................................................................... 43
PORTB Register ...................................................17, 42
RB0/INT Edge Select (INTEDG Bit) .......................... 21
RB0/INT Pin, External .....................................9, 11, 152
RB7:RB4 Interrupt-on-Change ................................ 152
RB7:RB4 Interrupt-on-Change Enable
(RBIE Bit) ............................................22, 152
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) .....................................22, 42, 152
TRISB Register .....................................................19, 42
PORTB Register ................................................................ 19
PORTC .....................................................................9, 11, 19
Associated Registers ................................................. 45
Functions ................................................................... 45
PORTC Register ...................................................17, 44
RC3/SCK/SCL Pin ..................................................... 83
RC6/TX/CK Pin ........................................................ 110
RC7/RX/DT Pin .................................................110, 111
TRISC Register ...................................................44, 109
PORTD ...................................................................12, 19, 49
Associated Registers ................................................. 46
Functions ................................................................... 46
Parallel Slave Port (PSP) Function ............................ 46
PORTD Register ...................................................17, 46
TRISD Register .......................................................... 46
PORTE .........................................................................12, 19
Analog Port Pins ...................................................47, 49
Associated Registers ................................................. 48
Functions ................................................................... 47
Input Buffer Full Status (IBF Bit) ................................ 48
Input Buffer Overflow (IBOV Bit) ................................ 48
Output Buffer Full Status (OBF Bit) ........................... 48
PORTE Register ...................................................17, 47
PSP Mode Select (PSPMODE Bit) ...........46, 47, 48, 49
RE0/RD/AN5 Pin ..................................................47, 49
RE1/WR/AN6 Pin ..................................................47, 49
RE2/CS/AN7 Pin ...................................................47, 49
TRISE Register .......................................................... 47
Postscaler, WDT
Assignment (PSA Bit) ................................................ 21
Rate Select (PS2:PS0 Bits) ....................................... 21
Power-down Mode. See SLEEP.
2001 Microchip Technology Inc. Advance Information DS39582A-page 213
PIC16F87XA
Power-on Reset (POR) .....................141, 145, 146, 147, 148
Oscillator Start-up Timer (OST) ....................... 141, 146
POR Status (PO R Bit) ................................................27
Power Control (PCON) Register ..............................147
Power-down (PD Bit) ......................................... 20, 145
Pow e r-up Ti mer (PWR T ) ................................. 141, 146
Time-out (TO Bit) ............................................... 20, 145
PR2 Register ................................................................ 18, 59
Prescaler, Timer0
Assignment (PSA Bit) ................................................21
Rate Se lec t (PS 2 :PS0 Bits) .......................................21
PRO MATE II Universal Device Programmer ..................167
Program Counter
Reset Conditions ......................................................147
Program Mem ory ...............................................................13
Interrupt Vector ..........................................................13
Paging ........................................................................28
Program Memo ry Map and Stack
(PIC16F873A/874A) ..................................13
Program Memo ry Map and Stack
(PIC16F876A/877A) ..................................13
RESE T Vector ............................................................13
Program Verification .........................................................155
Programming Pin (Vpp) ........................................................8
Programming, Device Instructions ...................................157
PSP. See Para llel Sla ve Por t. ............................................49
Pulse Width Modulation.See Capture/Compare/PW M,
PWM Mode.
PUSH .................................................................................28
R
RA0/AN0 Pin ........................................................................8
RA0/ANO Pin .....................................................................10
RA1/AN1 Pin .................................................................. 8, 10
RA2/AN2/VREF-/CVREF ......................................................10
RA2/AN2/VREF-/CVREF PIN ..................................................8
RA3/AN3/VREF+ .................................................................10
RA3/AN3/VREF+ Pin .............................................................8
RA4/T0CKI/C1OUT Pin .................................................. 8, 10
RA5/SS/AN4 /C2OU T Pi n ............................................... 8, 10
RAM. See Data Memory .
RB0/INT Pin ................................................................... 9, 11
RB1 Pin .......................................................................... 9, 11
RB2 Pin .......................................................................... 9, 11
RB3/PGM Pin ................................................................. 9, 11
RB4 Pin .......................................................................... 9, 11
RB5 Pin .......................................................................... 9, 11
RB6/PGC Pin ................................................................. 9, 11
RB7/PGD Pin ................................................................. 9, 11
RC0/T1OSO/T1CKI Pin ................................................. 9, 11
RC1/T1OSI/CCP2 Pin .................................................... 9, 11
RC2/CCP1 Pin ............................................................... 9, 11
RC3/SCK/SCL Pin ......................................................... 9, 11
RC4/SDI/SDA Pin .......................................................... 9, 11
RC5/SDO Pin ................................................................. 9, 11
RC6/TX/CK Pin .............................................................. 9, 11
RC7/RX/DT Pin .............................................................. 9, 11
RCREG ..............................................................................19
RCREG Register ................................................................17
RCSTA Register ...........................................................17, 19
ADDEN Bit ............................................................... 110
CREN Bit ................................................................. 110
FERR Bit .................................................................. 110
OERR Bit ................................................................. 110
RX9 Bit .................................................................... 110
RX9D Bit .................................................................. 110
SPEN Bit ...........................................................109, 110
SREN Bit ................................................................. 110
RD0/PSP0 Pin ................................................................... 12
RD1/PSP1 Pin ................................................................... 12
RD2/PSP2 Pin ................................................................... 12
RD3/PSP3 Pin ................................................................... 12
RD4/PSP4 Pin ................................................................... 12
RD5/PSP5 Pin ................................................................... 12
RD6/PSP6 Pin ................................................................... 12
RD7/PSP7 Pin ................................................................... 12
RE0/RD/AN5 Pin ............................................................... 12
RE1/WR/AN6 Pin ............................................................... 12
RE2/CS/AN7 Pin ................................................................ 12
Reader Response ............................................................ 218
Read-Modify-Write Operations ........................................ 157
Register File ....................................................................... 14
Register File Map (PIC16F873A/874A) ............................. 16
Register File Map (PIC16F876A/877A) ............................. 15
Registers
ADCON0 (A/D Control 0) Register .......................... 125
ADCON1 (A/D Control 1) Register .......................... 126
CCP1CON/CCP2CON (CCP Control 1 and
CCP Control 2) Register ............................ 62
CMCON (Comparator Control) Register .................. 133
CVRCON (Voltage Reference Control)
Register ................................................... 139
EECON1 (EEPROM Control) Register ...................... 32
FSR ........................................................................... 29
INTCON Register ....................................................... 22
OPTION_R EG Register ........................................21, 52
PCON (Power Control) Register ................................ 27
PIE1 (Peripheral Interrupt Enable 1) Register ........... 23
PIE2 (Peripheral Interrupt Enable 2) Register ........... 25
PIR1 (Peripheral Interrupt Request 1) Register ......... 24
PIR2 (Peripheral Interrupt Request 2) Register ......... 26
RCSTA (Receive Status and Control)
Register ................................................... 110
Special Function, Summary ....................................... 17
SSPCON (MS SP Control) Register1
(I2C Mode) ................................................. 80
SSPCON (MS SP Control) Register1
(SPI Mode) ................................................ 71
SSPCON2 (M SSP Control) Register2
(I2C Mode) ................................................. 81
SSPSTAT (MSSP Status) Register
(I2C Mode) ................................................. 79
SSPSTAT (MSSP Status) Register
(SPI Mode) ................................................ 70
STATUS Register ...................................................... 20
T1CON (Timer1 Control) Register ............................. 55
T2CON (Timer2 Control Register) ............................. 59
TRISE Register .......................................................... 48
TXSTA (Transmit Status and Control) Register ....... 109
RESET ......................................................................141, 145
MCLR Reset. See MCLR.
PIC16F87XA
DS39582A-page 214 Advance Information 2001 Microchip Technology Inc.
Reset
Brown-out Reset (BOR).
See Brown-out Rese t (BOR).
Power-on Reset (POR).
See Power-on Reset (POR).
RESET Conditions for PCON Register ....................147
RESET Conditions for Program Counter .................147
RESET Conditions for STATUS Register ................147
WDT Reset. See Watchdog Timer (WDT)
RESET, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer, and Brown-out
Reset Requirements ................................................182
Revision History ...............................................................207
S
Sales and Support ............................................................219
SCI. See USART
SCK ....................................................................................69
SDI .....................................................................................69
SDO ...................................................................................69
Serial Clock, SCK ...............................................................69
Serial Communication Interface. See USART.
Serial D a ta In , SD I .............................................................69
Serial D a ta O u t, SDO .........................................................69
Serial Peripheral Interface. See SPI.
Slave Select Synchronization .............................................75
Slave Select, SS ................................................................69
SLEEP .............................................................. 141, 145, 154
Softwa re Simu lator (MP LAB SIM ) ....................................166
SPBRG Register ................................................................18
Special Features of the CPU ............................................141
Special Function Registers ................................................17
Special Function Registers (SFRs ) ....................................17
Speed, Operating .................................................................1
SPI Mode .....................................................................69, 75
Associated Registers .................................................77
Bus Mode Compatibility .............................................77
Effects of a RESET ....................................................77
Enabling SPI I/O .........................................................73
Master Mode ..............................................................74
Master/Slave Connection ...........................................73
Serial Clock ................................................................69
Serial D a ta In .............................................................69
Serial Data Out ...........................................................69
Slave Select ...............................................................69
Slave Select Synchronization .....................................75
SLEEP Operation .......................................................77
SPI Clock ...................................................................74
Typical Connection .....................................................73
SPI Mode Requirements ..................................................188
SS ......................................................................................69
SSP SPI Master/Slave Connection ....................................73
SSPADD Register ..............................................................18
SSPBUF .............................................................................19
SSPBUF Register ..............................................................17
SSPCON Register ..............................................................17
SSPCON2 Register ............................................................18
SSPIF .................................................................................24
SSPOV ...............................................................................99
SSPSTAT Register ............................................................18
R/W Bit .................................................................82, 83
Stack ..................................................................................28
Overflows ...................................................................28
Underflow ...................................................................28
STATUS Register
C Bit ........................................................................... 20
DC Bit ........................................................................ 20
IRP Bit ........................................................................ 20
PD Bit ..................................................................20, 145
RP1:RP0 Bits ............................................................. 20
TO Bit ..................................................................20, 145
Z Bit ........................................................................... 20
Synchronous Master Reception
Associated Registers ............................................... 121
Synchronous Master Transmission
Associated Registers ............................................... 120
Synchronous Serial Port Interrupt ...................................... 24
Synchronous Slave Reception
Associated Registers ............................................... 123
Synchronous Slave Transmission
Associated Registers ............................................... 123
T
T1CKPS0 bit ...................................................................... 55
T1CKPS1 bit ...................................................................... 55
T1CON ............................................................................... 19
T1CON Register ...........................................................17, 19
T1OSCEN bit ..................................................................... 55
T1SYNC bit ........................................................................ 55
T2CKPS0 bit ...................................................................... 59
T2CKPS1 bit ...................................................................... 59
T2CON Register ...........................................................17, 19
TAD ................................................................................... 129
Time-out Sequence ......................................................... 146
Timer0 ................................................................................ 51
Associated Registers ................................................. 53
Clock Source Edge Select (T0SE Bit ) ....................... 21
Clock Source Sel ect (T0CS Bit) ................................. 21
External Clock ............................................................ 52
Interrupt ..................................................................... 51
Overflow Enable (TMR0IE Bit) ................................... 22
Overflow Flag (TMR0IF Bit) ................................22, 152
Overflow Interrupt .................................................... 152
Prescaler .................................................................... 52
T0CKI ......................................................................... 52
Timer0 and Timer1 External Clock
Requirements .......................................................... 183
Timer1 ...........................................................................55, 56
Associated Registers ................................................. 58
Asynchronous Counter Mode .................................... 57
Reading and Writing to ...................................... 57
Counter Operation ..................................................... 56
Operation in Timer Mode ........................................... 56
Oscillator .................................................................... 57
Capacitor Selection ............................................ 57
Prescaler .................................................................... 58
Resetting of Timer1 Registers ................................... 58
Resetting Timer1 using a CCP
Trigger Output ........................................... 57
Synchronized Counter Mode ..................................... 56
TMR1H ...................................................................... 57
TMR1L ....................................................................... 57
Timer2 ................................................................................ 59
Associated Registers ................................................. 60
Output ........................................................................ 60
Postscaler .................................................................. 59
Prescaler .................................................................... 59
Timijg Diagrams
SPI Master Mode (CKE = 1, SMP = 1) .................... 186
2001 Microchip Technology Inc. Advance Information DS39582A-page 215
PIC16F87XA
Timing Diagrams ..............................................................103
A/D Conversion ........................................................193
Acknowledge Sequence ..........................................102
Asynchronous Master Transmission ........................114
Asynchronous Master Transmission
(Back to Back) .........................................114
Asynchronous Reception .........................................116
Asynchronous Reception with
Address Byte Frist ...................................118
Asynchronous Reception with
Address Detect ........................................118
Baud Rate Generator with Clock Arbitration ..............96
BRG Reset Due to SDA Arbitration During
START Condition .....................................105
Brown-out Reset ......................................................182
Bus Collision During a Repeated START
Condition (Case 1) ...................................106
Bus Collision During Repeated START
Condition (Case 2) ...................................106
Bus Collision During START Condition
(SCL = 0) .................................................105
Bus Collision During START Condition
(SDA Only) ...............................................104
Bus Collision During STOP Condition
(Case 1) ...................................................107
Bus Collision During STOP Condition
(Case 2) ...................................................107
Capture/Compare/PWM (CCP1 and CCP2) ............184
CLKOUT and I/O ......................................................181
Clock Synchronization ...............................................89
First ST ART Bit Timi ng ..............................................97
I2C Bus Data ............................................................189
I2C Bus STAR T/ ST O P Bit s ......................................188
I2C Master Mode (Reception,
7-bit Address) ..........................................101
I2C Master Mode (Transmission, 7 or
10-bit Address) ........................................100
I2C Slave Mode Timing (Transmission,
10-bit Address) ..........................................87
I2C Slave Mode Timing (Transmission,
7-bit Address) ............................................85
I2C Slave Mode Timing SEN = 1 (Reception,
10-bit Address) ..........................................91
I2C Slave Mode Timing with SEN = 0
(Reception, 10-bit Address) .......................86
I2C Slave Mode Timing with SEN = 0
(Reception, 7-bit Address) .........................84
I2C Slave Mode Timing with SEN = 1
(Reception, 7-bit Address) .........................90
Parallel Slave Port (PSP)
Read Waveforms ...............................................50
Write Waveforms ...............................................50
Parallel Slave Port Timing
(PIC16F874A/877A Only) ........................185
Power-up Timer .......................................................182
Repeat START Condition ..........................................98
RESET .....................................................................182
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) ........................92
Slave Synchronization ...............................................75
Slow Rise Time (MCLR Tied to VDD via
RC Network) ............................................150
SPI Master Mode (CKE = 0, SMP = 0) ....................186
SPI Mode Timing (Master Mode) ...............................74
SPI Mode Timing (Slave Mode with CKE = 0) ...........76
SPI Mode Timing (Slave Mode with CKE = 1) ........... 76
SPI Slave Mode (CKE = 0) ...................................... 187
SPI Slave Mode (CKE = 1) ...................................... 187
Start-up Timer .......................................................... 182
STOP Condition Receive or Transmit Mode ............ 102
Synchronous Reception (Master Mode, SREN) ...... 122
Synchronous Transmission ..................................... 120
Synchronous Transmiss ion (Through TXEN) .......... 120
Time-out Sequence on Power-up
(MCLR No t Ti e d to V DD)
Case 1 ............................................................. 150
Case 2 ............................................................. 150
Time-out Sequence on Power-up (MCLR Tied to
VDD via RC Network) ............................... 149
Timer0 ..................................................................... 183
Timer1 ..................................................................... 183
USART Synchronous Receive (Master/Slave) ........ 191
USART Synchronous Transmission
(Master/Slave) ......................................... 191
Wake-up from SLEEP via Interrupt .......................... 155
Watchdog Timer ...................................................... 182
TMR0 ................................................................................. 19
TMR0 Register ................................................................... 17
TMR1CS bit ....................................................................... 55
TMR1H .............................................................................. 19
TMR1H Register ................................................................ 17
TMR1L ............................................................................... 19
TMR1L Register ................................................................. 17
TMR1ON bit ....................................................................... 55
TMR2 ................................................................................. 19
TMR2 Register ................................................................... 17
TMR2ON bit ....................................................................... 59
TMRO Register .................................................................. 19
TOUTPS0 bit ..................................................................... 59
TOUTPS1 bit ..................................................................... 59
TOUTPS2 bit ..................................................................... 59
TOUTPS3 bit ..................................................................... 59
TRISA Register .................................................................. 18
TRISB Register .................................................................. 18
TRISC Register .................................................................. 18
TRISD Register .................................................................. 18
TRISE Register .............................................................18, 47
IBF Bit ........................................................................ 48
IBOV Bit ..................................................................... 48
OBF Bit ...................................................................... 48
PSPMO D E Bi t ...........................................46, 47, 48, 49
TXREG .............................................................................. 19
TXREG Register ................................................................ 17
TXSTA Register ................................................................. 18
BRGH Bit ................................................................. 109
CSRC Bit ................................................................. 109
SYNC Bit ................................................................. 109
TRMT Bit .................................................................. 109
TX9 Bit ..................................................................... 109
TX9D Bit .................................................................. 109
TXEN Bit .................................................................. 109
PIC16F87XA
DS39582A-page 216 Advance Information 2001 Microchip Technology Inc.
U
USART .............................................................................109
Address Detect Enable (ADDEN Bit) .......................110
Asynchronous Mode ................................................113
Asynchronous Re ceive (9-bit Mode) ........................117
Asynchronous R eceive with Address
Detect. SeeAsynchronous
Receive (9-bit Mode)..
Asynchronous Receiver ...........................................115
Asynchronous Reception .........................................116
Asynchronous Transmitter .......................................113
Baud Rate Generator (BRG) ....................................111
Baud Rate Formula ..........................................111
Baud Rates, Asynchronous Mode
(BRGH = 0) ......................................112
Baud Rates, Asynchronous Mode
(BRGH = 1) ......................................112
High Baud Rate Select (BRGH Bit) ..................109
Sampling ..........................................................111
Clock Source Select (CSRC Bit) ..............................109
Continuous Receive Enable (CREN Bit) ..................110
Framing Error (FERR Bit) .........................................110
Mode Select (SYNC Bit) ...........................................109
Overrun Error (OERR Bit ) ........................................110
Receive Data, 9th bit (RX9D Bit) ..............................110
Receive Enab le, 9-bit (R X9 Bit ) ...............................110
Serial Port Enable (SPEN Bit) ..........................109, 110
Single Receive Enable (SREN Bit) ..........................110
Synchronous Master Mode ......................................119
Synchronous Master Reception ...............................121
Synchronous Master Transmission ..........................119
Synchronous Slave Mode ........................................122
Synchronous Slave Reception .................................123
Synchronous Slave Transmit ...................................122
Transmit Data, 9th Bit (TX9D) ..................................109
Transmit Enable (TXEN Bit) .....................................109
Transmit Enable, Nine-bit (TX9 Bit) .........................109
Transmit Shift Register Status (TRMT Bit) ...............109
USART Synchronous Receive Requirements ..................191
V
VDD Pin ...........................................................................9, 12
VSS Pin ...........................................................................9, 12
W
Wake-up from SLEEP ...............................................141, 154
Interrupts ...........................................................147, 148
MCLR Reset ............................................................ 148
WDT Reset .............................................................. 148
Wake-Up Using Interrupts ................................................ 154
Watchdog Timer
Register Summary ................................................... 153
Watchdog Timer (WDT) ............................................141, 153
Enable (WDTE Bit) .................................................. 153
Postscaler. See Postscaler, WDT
Programming Considerations .................................. 153
RC Oscillator ............................................................ 153
Time-out Period ....................................................... 153
WDT Reset, Normal Operation .................145, 147, 148
WDT Reset, SLEEP ..................................145, 147, 148
WCOL ...................................................................97, 99, 102
WCOL Status Flag ............................................................. 97
WWW, On-Line Support ...................................................... 4
2001 Microchip Technology Inc. Advance Information DS39582A-page 217
PIC16F87XA
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used b y Micr ochip as a me ans to mak e
files and information easily available to customers. To
view t he site, the user must have acce ss to the In ternet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
fa vo rite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
•Latest Microchip Press Releases
•Technical Support Section with Frequently Asked
Questions
•Design Tips
•Device Errata
•Job Postin gs
•Microchi p Cons ultant Program Member Listing
•Links to other useful web sites related to
Microchip Products
•Confere nces for prod ucts, Dev elopment Systems,
technical information and more
•Listing of seminars and events
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
013001
PIC16F87XA
DS39582A-page 218 Advance Information 2001 Microchip Technology Inc.
READER RESPONSE
It is ou r intentio n to pro vi de you with the bes t do cu me ntation po ss ib le to ens ure suc c es sful use of your Mic roc hip pro d-
uct. If y ou w ish to p rov ide y our co mmen ts on org aniza tion, c larity, subje ct ma tter, and ways i n wh ich o ur docum enta tio n
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Would you like a reply? Y N
Device: Literature Num ber:
Questions:
FAX: (______) _________ - _________
DS39582A
PIC16F87XA
1. Wha t are the best features of this docu ment?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
2001 Microchip Technology Inc. Advance Information DS39582A-page 219
PIC16F87XA
PIC16F87XA PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC16F87XA(1), PIC16F87XAT(2); VDD range 4.0V to 5.5V
PIC16LF87XA(1), PIC16LF87XAT(2 ) ; V DD range 2.0V to 5.5V
Temper atu re R ang e I = -40°C to +85°C (Industrial)
Package ML = MLF (Metal Lead Frame)
PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny plastic DIP
P=PDIP
L=PLCC
Examples:
a) PIC16F873A - I/P 301 = Industrial temp., PDIP
package, normal VDD limits, QTP pattern #301.
b) PIC16LF 876A - I /SO = Indus trial temp. , SOIC
package, Extend ed VDD limits.
c) PIC16F877A - I/P = Industrial temp., PDIP
package, 10MHz, nor mal V DD limits.
Note 1: F = CMOS FLASH
LF = Low Power CMOS FLASH
2: T = in tape and reel - SOIC, PLCC,
TQFP packages only.
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microc hip sales office
2. The Microchip Corporate Literature Center U.S. F AX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip. com /cn) to receive the most current information on our products.
DS39582A-page 220 Advance Information 2001 Microchip Technology Inc.
M
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10/01/01
WORLDWIDE SALES AND SERVICE
PIC16F877A Buy/Sample Options
PIC16F877A Buy/Sample Options
Resources
Features Sample Buy Part Number Lead
Count Package
Type Environmental
Friendly Temperature
Grade Packing
Media Availability Budgetary
Pricing
Buy PIC16F877A-
E/L 44 PLCC SnPb Automotive-
40C to
+125C TUBE Available 6.07
Buy PIC16F877A-
E/ML 44 QFN SnPb Automotive-
40C to
+125C TUBE Available 5.93
Buy PIC16F877A-
E/P 40 PDIP SnPb Automotive-
40C to
+125C TUBE Available 5.15
Buy PIC16F877A-
E/PT 44 TQFP SnPb Automotive-
40C to
+125C TRAY Available 5.93
Sample Buy PIC16F877A-I/L 44 PLCC SnPb Industrial-
40C to +85C TUBE Available 5.51
Buy PIC16F877A-
I/ML 44 QFN SnPb Industrial-
40C to +85C TUBE Available 5.40
Sample Buy PIC16F877A-
I/P 40 PDIP SnPb Industrial-
40C to +85C TUBE Available 4.68
Sample Buy PIC16F877A-
I/PT 44 TQFP SnPb Industrial-
40C to +85C TRAY Available 5.40
Buy PIC16F877AT-
I/L 44 PLCC SnPb Industrial-
40C to +85C T/R Available 5.67
Buy PIC16F877AT-
I/ML 44 QFN SnPb Industrial-
40C to +85C T/R Available 5.65
Buy PIC16F877AT-
I/PT 44 TQFP SnPb Industrial-
40C to +85C T/R Available 5.53
Buy PIC16LF877A-
I/L 44 PLCC SnPb Industrial-
40C to +85C TUBE Available 5.80
Sample Buy PIC16LF877A-
I/ML 44 QFN SnPb Industrial-
40C to +85C TUBE Available 5.65
Sample Buy PIC16LF877A-
I/P 40 PDIP SnPb Industrial-
40C to +85C TUBE Available 4.92
Sample Buy PIC16LF877A-
I/PT 44 TQFP SnPb Industrial-
40C to +85C TRAY Available 5.65
Buy PIC16LF877AT-
I/L 44 PLCC SnPb Industrial-
40C to +85C T/R Available 5.94
Buy PIC16LF877AT-
I/PT 44 TQFP SnPb Industrial-
40C to +85C T/R Available 5.81
http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1953&device=en010242 [11/3/2004 4:29:30 PM]
