INNOVATIVE IM1250Y-100 512K X 8 NO POWER SRAM FEATURES * Data Retention in the absence of power * Automatic data protection during power PIN CONFIGURATION A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Gnd failure * Data Retention over 10 years * Unlimited write cycles * Conventional SRAM write cycles * Low power CMOS * Equal read/write cycle times * +5V only read/write * Operating voltage range +10% * Direct replacement for 512K X 8 SRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 A17 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 or EPROM * Standard 32 pin DIP JEDEC Pinout PIN NAMES Functional Description The IM 1250Y-100 is a 4,194,304 bit, fully static NP RAM organized as 512K X 8 using CMOS and an internal lithium energy source. This `NO POWER' RAM has all the normal characteristics of a CMOS static RAM with an important benefit of data being retained in the absence of power. Data retention current is so small that a miniature lithium cell contained within the package provides an energy source to preserve data. Protection against data loss has also been incorporated to maintain data integrity during power on/off conditions. The IM 1250Y-100 RAM can be directly used in place of existing static RAMs. There is no limit to the number of write cycles that can be executed and no additional support circuitry is required for interface to a microprocessor. NC OE Gnd I/O0 - I/O7 Vcc WE A0 - A18 No Connection Output Enable Ground Data in/ Data Out Power Supply +5V Write Enable Address Inputs CE Chip Enable INNOVATIVE MICROTECHNOLOGY INC.Phone/Fax-440-322-8083.Website:www.innovativemicrotechnology.com INNOVATIVE IM1250Y-100 512K X 8 NO POWER SRAM READ MODE The IM 1250Y-100 performs a read cycle whenever WE high and CE low. The unique address specified by the 19 address inputs A0-A18 defines which of the 4,194,304 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within access time tACC after the last address input is stable, provided that CE and OE access times are satisfied. If OE or CE access times are not satisfied, data access will be measured from the limiting parameter (tCO or tOE), rather than address. The state of the eight data I/ O lines is controlled by the OE and CE control signals. The data lines may be in an indeterminate state between tOH and tAA but the data lines will always have valid data at tAA. WRITE MODE The IM 1250Y-100 is in the write mode whenever CE and WE inputs are held low. The latter occurring falling edge of either CE or WE determines the start of a write cycle. A write is terminated by the earlier rising edge of CE or WE. The address must be held valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another Read or Write cycle can be initiated. CE or WE is high during power on to perfect memory after Vcc reaches Vcc (min) but before the processor stabilizes. Maximum Ratings Operating Temperature....0oC to 70oC Storage Temperature.......0oC to 70oC Soldering Temperature And Time......................260oC for 10 sec Supply Voltage................ 0V to 7.0V Input Voltage..................-0.5V to 7.0V Input/ Output Voltage.......-0.5V to Vcc + 0.3V Power Dissipation............1.0W Recommended D.C. Operating Conditions Parameter Symbol Min. Supply Voltage Vcc 4.5 Gnd 0 Typ 5.0 - Max. 5.5 0 Unit V V Input Voltage Vcc +0.3 0.8 V V VIH 2.2 3.5 VIL 0 - FRESHNESS SEAL AND SHIPPING DATA RETENTION The IM 1250Y-100 provides full functional capability for Vcc greater than 4.5V and write protects at 4.25V. Data is retained in the absence of Vcc without any additional support circuitry. The SRAM constantly monitors Vcc. The moment Vcc decays, the RAM automatically write protects itself. All inputs to the RAM become "don't care" and all outputs re in high impedance-state. As Vcc falls below approximately 3.0V the power switching circuit connects the lithium energy source to RAM to retain data. During power-on, when Vcc rises above approximately 3.0V the power switching circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc becomes greater than 4.5V. The IM1250Y - 100 is shipped from INNOVATIVE MICROTECHONOLOGY INC. with the lithium energy source disconnected , guaranteeing full energy capacity. When Vcc is first applied at a level of greater than 4.5 volts, the lithium energy source is enabled for battery back-up operation. INNOVATIVE IM1250Y-100 512K X 8 NO POWER SRAM Electrical Characeteristics Parameter Description ILI I OCA Input Leakage Vi = 0 to Vcc Average operating Current CE = Vcc CE = VIH,IIO = 0mA Operatng Supply current CE = VIL,IIO = 0mA Output Leakage CE = VIH or Vcc Vi/o = Gnd to Vcc High level output voltage IOH = - 1.0 mA Low level output voltage IOL = 2.1 mA Write protection voltage - 2.4 4.25 0.2 4.37 Vcc - 0.1 0.4 4.49 V V V Parameter Description Test conditons Min. Typ Max Unit CADD CI CI/O Address capacitance Input capacitance I/O capacitance VADD = 0V Vi =0V VIO = 0V - 3 5 6 5 6 7 pF pF pF Ivcc I LO VOH V OL VTP Test conditons Min. Typ Max Unit -1 -1 45 1 - 1 80 3 50 1 A A mA mA A Capacitance INNOVATIVE IM1250Y-100 512K X 8 NO POWER SRAM Switching Characteristics over the operating range Parameter Description Min Max Unit t RC tACC tOE t co tCOE tOD tOH Read cycle time 100 Address access time Output enable access time CE to output valid OE or CE to output valid 5 Output High Z from Deselection Output hold from adds change 5 100 50 100 35 - ns ns ns ns ns ns ns t WC tAW tWP tWR tODW tOEW t DS t DH1 Write cycle time Address setup time Write pulse-width Write recovery time Output High Z from WE Output Active from WE Input data setup time Input data hold time 35 ns ns ns ns ns ns ns ns 100 0 75 5 5 40 15 - INNOVATIVE IM1250Y-100 512K X 8 NO POWER SRAM READ CYCLE tRC VIH VIH Address VIL VIL tACC tOH tCO VIH CE VIH VIL tOD tOE VIH OE VIH VIL tOD tCOE VOH VOH tCOE D OUT OUTPUT DATA VALID VOL VOL WRITE CYCLE 1 tWC ADDRESS VIH VIH VIL VIL tAW CE VIL VIL tWR tWP WE VIH VIL VIL tODW tOEW High Impedance D OUT tDS VIH DIN VIL tDH1 Data In Stable VIH VIL INNOVATIVE IM1250Y-100 512K X 8 NO POWER SRAM WRITE CYCLE 2 ADDRESSES VIH VIH VIL VIL tWR tAW tWP CE VIH WE VIL VIL tCOE VIH VIL VIL tODW DOUT tDS VIH DIN tDH Data In Stable VIL FIG. D VIH VIL POWER - DOWN/ POWER -ON CONDITION 4.75V -------------------------------------------------------------------------------------------------- tF tR 3.2V ---------------------------------------------------------------------------------------------------- tPD LI Cell Leakage Current tREC Data Retention Time t DR Notes: 1. 2. 3. WE is to be high during read cycle. During write cycle that is controlled by CE, output buffer is in high impedance state irrespective of whether OE is high or low level. During write cycle that is controlled by WE, output buffer is in high impedance state if OE is high. INNOVATIVE IM1250Y-100 512K X 8 NO POWER SRAM INNOVATIVE IM 1250Y - 100 NO POWER SRAM B mm - yy J H A C F G D E DIM IN INCHES MIN. MAX. A B C D E F G H J 1.754 0.74 0.415 0.12 0.021 0.16 0.11 0.63 0.012 1.72 0.72 0.395 0.09 0.015 0.12 0.09 0.59 0.008