User's Guide
SNVA483B–October 2011–Revised May 2013
AN-2148 LM5051MAEVAL Evaluation Board
1 Introduction
The LM5051 evaluation board is designed to demonstrate the capabilities of the LM5051 OR-ing diode
controller. One low-side N-channel power MOSFET is used per channel. The LM5051 evaluation board
schematic is shown in Figure 7. The evaluation board is designed to highlight applications with a small
solution size. For more information about LM5051 functional and electrical characteristics, see the
LM5051 Low Side OR-ing FET Controller Data Sheet (SNVS702).
2 Operating Range
• Input Voltage: 48V
• Output Current Range: 0A to 5A
• Ambient Temperature Range 0°C to 50°C
• Board Size 2.25 inches x 2.60 inches
To aid in the demonstration and evaluation of low-side OR-ing diode controller solution based on the
LM5051.
The load current capability is limited at 5A by the ratings of the MOSFETs, the banana jacks, and the PCB
copper area and weight. The PCB layout has not been tested for currents above 5A, so this should only
be done with some degree of caution.
The maximum input voltage is limited by the breakdown voltage rating of the two input protection diodes
(D1,D2), and the breakdown voltage rating of the output protection diode (D4).
Typical evaluation board performance and characteristics curves are shown in Figure 2 through Figure 3.
The PCB layout is shown in Figure 9 and Figure 10. An on-board push-button switch invokes the FET test
mode on both channels simultaneously, while individual test points are provided for monitoring the FET
test status output.
3 Evaluation Board Start-Up
Before applying power to the LM5051 evaluation board, all external connections should be verified. The
external power supplies must be turned off and connected with proper polarity to the INPUT A+/B+ and
INPUT A-/B- terminals. A common load is connected to the 48V+ OUT and 48V- OUT terminals.
The evaluation board will be in the normal operating mode when power is applied.
All trademarks are the property of their respective owners.
1
SNVA483B–October 2011–Revised May 2013 AN-2148 LM5051MAEVAL Evaluation Board
Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
-5 0 5 10 15 20 25
-2
0
2
4
6
8
10
12
14
VOLTS (V)
TIME (s)
INPUT B- Shorted
INPUT A-
INPUT B-
GATE Q1
GATE Q2
X.XXX V
2.000 A
PRODIGIT 3314
³$´
48.0V @ 5A
³%´
48.5V @ 3A
Inductive Kick-Back Protection
www.ti.com
Figure 1. Typical Board Connections
4 Inductive Kick-Back Protection
Diode D1 and capacitor C3 serve as inductive kick-back protection to limit negative transient voltage
spikes generated on the input when the INPUT A supply voltage is abruptly taken to zero volts. Diode D2
and capacitor C4 serve the same protective function on the INPUT B supply voltage.
Diode D4 and capacitors C5/C6 serve as inductive kick-back protection to limit positive transient voltage
spikes generated on the output when an input supply voltage is abruptly taken to zero volts.
5 OR-ing Transfer
An example of OR-ing transfer is shown in Figure 2. In this example one 48.5V supply (INPUT B) is
powering a 2A load at the output, while a 48.0V supply (INPUT A) is connected, but is idle. The OR-ing
transfer begins when the 48.5V supply is shorted (INPUT B- is shorted to INPUT B+). This short causes
reverse current through the MOSFET (Q2) and creates the required voltage (VSD(REV)+ΔVSD(REV) ) on the
LM5051 INN pin (U2) that will immediately cause the discharge the gate of the Q2 MOSFET.
Figure 2. Forward and Reverse Waveforms
2AN-2148 LM5051MAEVAL Evaluation Board SNVA483B–October 2011–Revised May 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
012345
0
20
40
60
80
100
120
140
160
0
2
4
6
8
10
12
14
16
VSD(mV)
ISD(A)
VGATE(V)
VGATE
VSD
VSD(REG)
Q1 = IRF7495PDF
www.ti.com
Off TEST Push-Button, S1
With Q2 off, the output voltage will fall until it is just below the second supply voltage by the VSD(REV)
threshold voltage. When this happens, the gate of the MOSFET (Q1) will begin charging from the LM5051
(U1). Note that the Q1 gate voltage may not rise all the way to the maximum voltage, since the VSD(REG)
threshold will needs to be exceeded for that to happens, see Figure 3. The gate voltage may initially settle
at some intermediate value and then slowly rise as internal heating of the MOSFET causes the RDS(ON) to
rise which, in turn, causes the drain to source voltage to rise and, in response, the LM5051 increases the
gate voltage in an effort to keep the drain to source voltage regulated.
Figure 3. Gate Drive vs Drain to Source Voltage
6 Off TEST Push-Button, S1
The single push-button (S1) provided on the LM5051 evaluation board is used to control the operation of
both LM5051 devices. The LM5051 Eval board has an on-board 5V (with respect to the 48V- OUT
terminal) reference that is used to drive the OFF pins of both LM5051 devices to shut down the gate
drives, as well as provide a voltage bias for the nFGD status output pins. For more details, see the
LM5051 Low Side OR-ing FET Controller Data Sheet (SNVS702).
In normal operation, the LM5051 OFF pin is left open. The LM5051 internal OFF pin pull-down will ensure
that both of the LM5051 devices are operating in the default active mode.
To disable both LM5051 devices, simply press the TEST push-button. Typical behavior is shown in
Figure 4 and Figure 5.
The typical OFF behavior is shown in Figure 4. Pressing the TEST button applies approximately 5V to the
OFF pin of both LM5051 devices. After the OFF pin rises above the VOFF(IH) threshold the MOSFET gate
will be quickly discharged. As the gate discharges, the voltage across the MOSFET drain to source pins
will increase. Since all measurements are referenced to the LM5051 INP/VSS pin, the INN pin will appear
to be going negative. When the INN pin has gone more negative than the VSD(TST) threshold (typically -
260mV), the nFGD pin go low. The INN pin voltage will be clamped at about -600mV by the MOSFET
body diode.
3
SNVA483B–October 2011–Revised May 2013 AN-2148 LM5051MAEVAL Evaluation Board
Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
-20 -10 0 10 20 30 40 50 60 70 80
-2
0
2
4
6
8
10
12
14
VOLTS (V)
TIME (s)
VOFF=1.50V
INN
OFF
GATE
nFGD
-100 0 100 200 300 400 500 600 700
-2
0
2
4
6
8
10
12
14
VOLTS (V)
TIME (ns)
VOFF= 1.50V
INN
OFF
GATE
nFGD
Off TEST Push-Button, S1
www.ti.com
Figure 4. OFF pin Going High, Gate OFF
Typical behavior when the TEST button is released is shown in Figure 5. In this case, the OFF pin relies
on the internal pull-down (typically 4.6 µA) to discharge any stray capacitance, as well as the probe
capacitance. Once the OFF pin has fallen below the VOFF(IL) threshold, the gate drive circuitry will become
active. Since, in this case, the INN pin is well below the VSD(REV) threshold the MOSFET gate will
immediately begin charging. As the gate voltage increases the INN pin voltage will fall below the VSD(TST)
threshold and the nFGD pin will go high. Note that the gate voltage may not rise all the way to the
maximum voltage, since the VSD(REG) threshold needs to be exceeded for that to happen, see Figure 3. The
gate voltage may initially settle at some intermediate value and then slowly rise as internal heating of the
MOSFET causes the RDS(ON) to rise which, in turn, causes the drain to source voltage to rise and, in
response, the LM5051 increases the gate voltage in an effort to keep the drain to source voltage regulated
at the VSD(REG) threshold.
Figure 5. OFF pin Going Low, Gate Drive Active
4AN-2148 LM5051MAEVAL Evaluation Board SNVA483B–October 2011–Revised May 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
+
+
1
2
3
4 5
6
7
8LINE GATE
INN
INP/VSS
VCC
OFF
nFGD
INP/VSS
TP1
D1
60V C3
1 PF
C1
0.1 PF
R1
10.0 k:
Q1
IRF7495
SD
G
1
2
3
4 5
6
7
8LINE GATE
INN
INP/VSS
VCC
OFF
nFGD
INP/VSS
TP2
D2
60V C4
1 PF
C2
0.1 PF
R2
10.0 k:
Q2
IRF7495
SD
G
S1
D3
5.1V
D4
68V
C5
22 PF
C6
22 PF
R3
10.0 k:
J1
J2
J3
J4 J5
J6
+OUT
-OUT
IN A+
IN B+
IN A-
IN B-
U1
LM5051
U2
LM5051
LINE
VCC
nFGD
OFF
GATE
INP/VSS
INP/VSS
INN
1
2
3
45
6
7
8
LM5051
MA
www.ti.com
Off TEST Push-Button, S1
Device Pin 5 is internally connected to Device Pin 7
Figure 6. Connection Diagram
Figure 7. Schematic Diagram
5
SNVA483B–October 2011–Revised May 2013 AN-2148 LM5051MAEVAL Evaluation Board
Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Bill of Materials (BOM)
www.ti.com
7 Bill of Materials (BOM)
ID Description Manufacturer Mfgr Part Number
U1, U2 IC; Ideal OR-ing Diode Controller Texas Instruments LM50501
Capacitor, 0.1uF, Ceramic, ±10%, 25V, X7R,
C1,C2 AVX Corporation 08053C104KAT2A
0805
Capacitor: MLCC; 1.0µF; ±10%; 100V; X7R;
C3,C4 Vishay/Vitramon VJ1825Y105KBBAT4X
1825
Capacitor: 22 µF; ±20%; 100V; Aluminum
C5, C6 Panasonic/ECG EEE-FK2A220P
Electrolytic; SMT ON Semiconductor SS16T3G
D1, D2 Diode: Schottky Barrier Rectifier; 1A: 60V; SMA Micro Commercial Components SS16-TP
D3 Diode: Zener, 5.1V, 500mW, SOD-123 ON Semiconductor MMSZ4689T1G
D4 Diode: Zener, 68V, 3W, SMB ON Semiconductor 1SMB5945BT3G
J1, J2, J5 Jack: Standard Banana, Insulated, Red Keystone Electronics 6091
J3, J4, J6 Jack: Standard Banana, Insulated, Black Keystone Electronics 6092
Q1, Q2 MOSFET N-CH, 100V 0.018Ω, 7.3A SO-8 International Rectifier IRF7495PDF
Resistor: 10.0 kΩ, ±1%, 0.125W, 0805, Thick
R1, R2 Vishay/Dale CRCW080510K0FKEA
Film
Resistor: 10.0 kΩ, ±1%, 0.250W, 1206, Thick
R3 Vishay/Dale CRCW120610K0FKEA
Film
S1 Switch, SPST-NO, Momentary, Tactile, SMD C&K Components KSR221GLFS
Test Point Terminal: Miniature, 0.040in Dia Mtg
TP1, TP2 Keystone Electronics 5002
Hole; White
8AN-2148 LM5051MAEVAL Evaluation Board SNVA483B–October 2011–Revised May 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
