WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 1 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
FIGURE 1 – PIN CONFIGURATION FOR WF2M32-XHX5
Top View
Block Diagram
2M x 8
8
I/O0-7
2M x 8
8
I/O8-15
2M x 8
8
I/O16-23
2M x 8
8
I/O24-31
A
0-20
OE#
WE1# CS1# WE2# CS2# WE3# CS3# WE4# CS4#
2Mx32 5V NOR FLASH MODULE
FEATURES
Access Time of 90, 120, 150ns
Packaging:
• 66 pin, PGA Type, 1.185" square, Hermetic Ceramic HIP
(Package 401).
• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880") square
(Package 510) 3.56mm (0.140") height. Designed to fi t
JEDEC 68 lead 0.990" CQFJ footprint (FIGURE 3)
Sector Architecture
• 32 equal size sectors of 64KBytes per each 2Mx8 chip
• Any combination of sectors can be erased. Also supports
full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 2Mx32
Commercial, Industrial, and Military Temperature Ranges
5 Volt Read and Write. 5V ± 10% Supply.
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle completion.
Supports reading or programming data to a sector not being
erased.
RESET# pin resets internal state machine to the read
mode.
Built in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation, Separate Power and Ground Planes to
improve noise immunity
* This product is subject to change without notice.
Note: For programming information refer to Flash Programming 16M5 Application Note.
RESET# internally tied to VCC in the HIP package for this pin confi guration. See
Alternate Pin Confi guration with RESET# tied to pin 12 for system control of reset
(FIGURE 10, page 11).
I/O8
I/O9
I/O10
A14
A16
A11
A0
A18
I/O0
I/O1
I/O2
WE2#
CS2#
GND
I/O11
A10
A9
A15
VCC
CS1#
A19
I/O3
I/O15
I/O14
I/O13
I/O12
OE#
A17
WE1#
I/O7
I/O6
I/O5
I/O4
I/O24
I/O25
I/O26
A7
A12
A20
A13
A8
I/O16
I/O17
I/O18
VCC
CS4#
WE4#
I/O27
A4
A5
A6
WE3#
CS3#
GND
I/O19
I/O31
I/O30
I/O29
I/O28
A1
A2
A3
I/O23
I/O22
I/O21
I/O20
11 22 33 44 55 66
1 12 23 34 45 56
Pin Description
I/O0-31 Data Inputs/Outputs
A0-20 Address Inputs
WE1-4# Write Enables
CS1-4# Chip Selects
OE# Output Enable
VCC Power Supply
GND Ground
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 2 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
FIGURE 2 – PIN CONFIGURATION FOR WF2M32-XG2UX5
Block Diagram
Top View
The WEDC 68 lead G2U CQFP fi lls the same fi t and function as the JEDEC 68 lead CQFJ
or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form.
2M x 8
8
I/O0-7
2M x 8
8
I/O8-15
2M x 8
8
I/O16-23
2M x 8
8
I/O24-31
A
0-20
OE#
RESET#
WE1# CS1# WE2# CS2# WE3# CS3# WE4# CS4#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VCC
A11
A12
A13
A14
A15
A16
CS1#
OE#
CS2#
A17
WE2#
WE3#
WE4#
A18
A19
A20
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
RESET#
A0
A1
A2
A3
A4
A5
CS3#
GND
CS4#
WE1#
A6
A7
A8
A9
A10
VCC
Pin Description
I/O0-31 Data Inputs/Outputs
A0-20 Address Inputs
WE1-4# Write Enables
CS1-4# Chip Selects
OE# Output Enable
VCC Power Supply
GND Ground
RESET# Reset
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 3 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Ratings Unit
Voltage on Any Pin Relative to VSS V
T-2.0 to +7.0 V
Power Dissipation PT8W
Storage Temperature Tstg -65 to +125 °C
Short Circuit Output Current IOS 100 mA
Endurance – Write/Erase Cycles
(Extended Temp)
100,000 min cycles
Data Retention 20 years
RECOMMENDED DC OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 00 0V
Input High Voltage VIH 2.0 - VCC + 0.5 V
Input Low Voltage VIL -0.5 - +0.8 V
Operating Temperature (Mil.) TA-55 - +125 °C
Operating Temperature (Ind.) TA-40 - +85 °C
CAPACITANCE
TA = +25°C, f = 1.0MHz
Parameter Symbol Max Unit
OE# capacitance COE 50 pF
WE1-4# capacitance
HIP (PGA) CWE 20 pF
HIP (Alternate pinout) CWE 50 pF
CQFP G4T CWE 50 pF
CQFP G2U CWE 20 pF
G2U (Alternate pinout) CWE 50 pF
CS1-4# capacitance CCS 20 pF
Data I/O capacitance CI/O 20 pF
Address input capacitance CAD 50 pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS – CMOS COMPATIBLE
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol Conditions Min Max Unit
Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 μA
Output Leakage Current ILOx32 VCC = 5.5, VIN = GND to VCC 10 μA
VCC Active Current for Read (1) ICC1 CS# = VIL, OE# = VIH, f = 5MHz 160 mA
VCC Active Current for Program or Erase (2) ICC2 CS# = VIL, OE# = VIH 240 mA
VCC Standby Current ICC3 VCC = 5.5, CS# = VIH, f = 5MHz, RESET# = VCC ± 0.3V 8.0 mA
Output Low Voltage VOL IOL = 12.0 mA, VCC = 4.5 0.45 V
Output High Voltage VOH IOH = -2.5 mA, VCC = 4.5 0.85xVCC V
Low VCC Lock-Out Voltage VLKO 3.2 4.2 V
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE# at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 4 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol -90 -120 -150 Unit
Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 90 120 150 ns
Chip Select Setup Time tELWL tCS 000ns
Write Enable Pulse Width tWLWH tWP 45 50 50 ns
Address Setup Time tAVWL tAS 000ns
Data Setup Time tDVWH tDS 45 50 50 ns
Data Hold Time tWHDX tDH 000ns
Address Hold Time tWLAX tAH 45 50 50 ns
Write Enable Pulse Width High tWHWL tWPH 20 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 μs
Sector Erase (2) tWHWH2 15 15 15 sec
Read Recovery Time before Write tGHWL 000μs
VCC Setup Time tVCS 50 50 50 μs
Chip Programming Time 44 44 44 sec
Chip Erase Time (3) 256 256 256 sec
Output Enable Hold Time (4) tOEH 10 10 10 ns
RESET# Pulse Width (5) tRP 500 500 500 ns
NOTES:
1. Typical value for tWHWH1 is 7μs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
5. RESET# internally tied to VCC for the default pin confi guration in the HIP package.
AC CHARACTERISTICS – READ-ONLY OPERATIONS
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol -90 -120 -150 Unit
Min Max Min Max Min Max
Read Cycle Time tAVAV tRC 90 120 150 ns
Address Access Time tAVQV tACC 90 120 150 ns
Chip Select Access Time tELQV tCE 90 120 150 ns
Output Enable to Output Valid tGLQV tOE 40 50 55 ns
Chip Select High to Output High Z (1) tEHQZ tDF 20 30 35 ns
Output Enable High to Output High Z (1) tGHQZ tDF 20 30 35 ns
Output Hold from Addresses, CS# or OE# Change,
whichever is First
tAXQX tOH 000ns
RST Low to Read Mode (1,2) tReady 20 20 20 μs
NOTES:
1. Guaranteed by design, not tested.
2. RESET# internally tied to VCC for the default pin confi guration in the HIP package.
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 5 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
FIGURE 3 – AC TEST CIRCUIT AC TEST CONDITIONS
Parameter Typ Unit
Input Pulse Levels VIL = 0, VIH = 3.0 V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 ý.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Current Source
Current Source
IOL
IOH
Ceff = 50 pf
D.U.T. VZ ≈ 1.5V
(Bipolar Supply)
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol -90 -120 -150 Unit
Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 90 120 150 ns
Write Enable Setup Time tWLEL tWS 000ns
Chip Select Pulse Width tELEH tCP 45 50 50 ns
Address Setup Time tAVEL tAS 000ns
Data Setup Time tDVEH tDS 45 50 50 ns
Data Hold Time tEHDX tDH 000ns
Address Hold Time tELAX tAH 45 50 50 ns
Chip Select Pulse Width High tEHEL tCPH 20 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 μs
Sector Erase Time (2) tWHWH2 15 15 15 sec
Read Recovery Time tGHEL 000μs
Chip Programming Time 44 44 44 sec
Chip Erase Time (3) 256 256 256 sec
Output Enable Hold Time (4) tOEH 10 10 10 ns
NOTES:
1. Typical value for tWHWH1 is 7μs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
FIGURE 4 – RESET TIMING DIAGRAM
RESET#
tRP
tReady
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 6 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
FIGURE 5 – AC WAVEFORMS FOR READ OPERATIONS
CS#
OE#
WE#
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 7 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
CS#
Data# Polling
OE#
D7#
WE#
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
FIGURE 6 – WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 8 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
CS#
OE#
WE#
FIGURE 7 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
NOTE:
1. SA is the sector address for Sector Erase.
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 9 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
FIGURE 8 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM OPERATIONS
CS#
OE#
WE#
tOE
tCE
tCH
tOH
D7# D7 =
Valid Data
High Z
D0-D6 = Invalid D0-D7
Valid Data
tDF
D7
D0-D6
tOEH
tWHWH 1 or 2
Data
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 10 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
CS#
Data# Polling
OE#
D7#
WE#
tGHEL
tCP
tWS tCPH
Notes:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
FIGURE 9 – ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 11 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
FIGURE 10 – ALTERNATE PIN CONFIGURATION FOR WF2M32I-XHX5
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-20 Address Inputs
WE# Write Enable
CS1-4# Chip Selects
OE# Output Enable
VCC Power Supply
GND Ground
RESET# Reset
FIGURE 11 – ALTERNATE PIN CONFIGURATION FOR WF2M32U-XG2UX5
BLOCK DIAGRAM
TOP V I E W
The WEDC 68 lead G2U CQFP fi lls the same fi t and function as the JEDEC 68 lead CQFJ
or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form.
2M x 8
8
I/O0-7
2M x 8
8
I/O8-15
2M x 8
8
I/O16-23
2M x 8
8
I/O24-31
A0-20
OE#
RESET#
CS#
WE#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VCC
A11
A12
A13
A14
A15
A16
CS#
OE#
NC
A17
NC
NC
NC
A18
A19
A20
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
RESET#
A0
A1
A2
A3
A4
A5
NC
GND
NC
WE#
A6
A7
A8
A9
A10
VCC
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-20 Address Inputs
WE# Write Enable
CS# Chip Select
OE# Output Enable
VCC Power Supply
GND Ground
RESET# Reset
TOP VIEW
I/O8
I/O9
I/O10
A14
A16
A11
A0
A18
I/O0
I/O1
I/O2
RESET#
CS2#
GND
I/O11
A10
A9
A15
VCC
CS1#
A19
I/O3
I/O15
I/O14
I/O13
I/O12
OE#
A17
WE#
I/O7
I/O6
I/O5
I/O4
I/O24
I/O25
I/O26
A7
A12
NC
A13
A8
I/O16
I/O17
I/O18
VCC
CS4#
NC
I/O27
A4
A5
A6
A20
CS3#
GND
I/O19
I/O31
I/O30
I/O29
I/O28
A1
A2
A3
I/O23
I/O22
I/O21
I/O20
11 22 33 44 55 66
1 12 23 34 45 56
BLOCK DIAGRAM
2M x 8
8
I/O0-7
CS1# CS2# CS3# CS4#
2M x 8
8
I/O8-15
2M x 8
8
I/O16-23
2M x 8
8
I/O24-31
A0-20
OE#
WE#
RESET#
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 12 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
FIGURE 12 – PIN CONFIGURATION FOR WF2M32I-XG2UX5
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-20 Address Inputs
WE# Write Enable
CS1-4# Chip Selects
OE# Output Enable
VCC Power Supply
GND Ground
RESET# Reset
BLOCK DIAGRAM
2M x 8
8
I/O0-7
CS1# CS2# CS3# CS4#
2M x 8
8
I/O8-15
2M x 8
8
I/O16-23
2M x 8
8
I/O24-31
A0-20
OE#
WE#
RESET#
The WEDC 68 lead G2U CQFP fi lls the same fi t and function as the JEDEC 68 lead CQFJ
or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form.
TOP VIEW
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VCC
A11
A12
A13
A14
A15
A16
CS1#
OE#
CS2#
A17
NC
NC
NC
A18
A19
A20
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
RESET#
A0
A1
A2
A3
A4
A5
CS3#
GND
CS4#
WE#
A6
A7
A8
A9
A10
VCC
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 13 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
30.1 (1.185) ± 0.38 (0.015) SQ
1.27 (0.050) ± 0.1 (0.005)
0.46 (0.018) ± 0.05 (0.002) DIA
1.27 (0.050) TYP DIA
0.76 (0.030) ± 0.1 (0.005)
25.4 (1.0) TYP
25.4 (1.0) TYP
15.24 (0.600) TYP
6.22 (0.245)
MAX
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
3.81 (0.150)
±0.1 (0.005)
2.54 (0.100)
TYP
PACKAGE 401 – 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 14 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
23.876 (0.940) TYP
PACKAGE 510 – 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
The WEDC 68 lead G2U CQFP fi lls the same fi t and function as the
JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and
lead inspection advantage of the CQFP form.
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 15 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
ORDERING INFORMATION
MICROSEMI CORPORATION
FLASH
ORGANIZATION, 2M X 32
User confi gurable as 4M x 16 or 8M x 8
(Except WF2M32U-XG2UX which is 32 bit wide only.)
IMPROVEMENT MARK
• For HIP Package
Blank = 4CS# and 4WE#
I = 4CS# and 1WE#
• For G2U Package
Blank = 4CS# and 4WE#
U = 1CS# and 1WE#
I = 4CS# and 1WE#
ACCESS TIME (ns)
PACKAGE TYPE:
H = Ceramic Hex In line Package, HIP (Package 401)
G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510)
DEVICE GRADE:
Q = Compliant -55°C to +125°C
M = Military -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C
VPP PROGRAMMING VOLTAGE
5 = 5 V
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
W F 2M32 X - XXX X X 5 X
WF2M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 16 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 8 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
Document Title
2Mx32 5V NOR FLASH MODULE
Revision History
Rev # History Release Date Status
Rev 6 Change (Pg. 15)
6.1 Remove "RESET#" from ordering information November 2009 Final
Rev 7 Change (Pg. 1-16)
7.1 Change document layout from White Electronic Designs to Microsemi July 2011 Final
Rev 8 Change (Pg. 1, 16)
8.1 Add "NOR" to headline August 2011 Final
