1
LTC1850/LTC1851
18501i
8-Channel, 10-Bit/12-Bit,
1.25Msps Sampling ADCs
December 2001
The 10-bit LTC
®
1850 and 12-bit LTC1851 are complete
8-channel data acquisition systems. They include an
extremely flexible 8-channel multiplexer, a 1.25Msps
successive approximation analog-to-digital converter with
sample-and-hold, an internal 2.5V reference and refer-
ence buffer amplifier, and a parallel output interface. The
multiplexer can be configured for single-ended or differ-
ential inputs, two gain ranges and unipolar or bipolar
operation.
The ADCs have a scan mode that will repeatedly cycle
through all 8 multiplexer channels and can also be
programmed with a sequence of up to 16 addresses and
configurations that can be scanned in succession. The
sequence memory can also be read back. The reference
and buffer amplifier provide pin strappable ranges of
4.096V, 2.5V and 2.048V. The parallel output includes
the 10-bit or 12-bit conversion result plus the 4-bit
multiplexer address. The digital outputs are powered
from a separate supply allowing for easy interface to 3V
digital logic. Typical power consumption is 40mW at
1.25Msps from a single 5V supply.
■
Flexible 8-Channel Multiplexer
■
Single-Ended or Differential Inputs
■
Two Gain Ranges Plus Unipolar and Bipolar
Operation
■
1.25Msps Sampling Rate
■
Single 5V Supply and 40mW Power Dissipation
■
Scan Mode and Programmable Sequencer
■
Pin Compatible 10-Bit LTC1850 and 12-Bit LTC1851
■
True Differential Inputs Reject Common Mode Noise
■
Internal 2.5V Reference
■
Parallel Output Includes MUX Address
■
Easy Interface to 3V Logic
■
Nap and Sleep Shutdown Modes
■
High Speed Data Acquisition
■
Test and Measurement
■
Imaging Systems
■
Telecommunications
■
Industrial Process Control
■
Spectrum Analysis
Final Electrical Specifications
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
BLOCK DIAGRA
W
BUSY
DIFF
OUT
/S6
A2
OUT
/S5
A1
OUT
/S4
A0
OUT
/S3
D11/S2
D10/S1
D9/S0
D8
D7
D6
D5
D4
D3
D2
D1
D0
M1
SHDN
CS
CONVST
RD
WR
DIFF
A2
A1
A0
UNI/BIP
PGA
M0
OUTPUT
DRIVERS
DATA
LATCHES
OGND
1851 BD
OV
DD
COMP
S/H AMP
12-BIT
CAPACITIVE
DAC
REF AMP
REFCOMP
REFIN
REFOUT
COM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
SUCCESSIVE APPROXIMATION REGISTER
8-CHANNEL
MULTIPLEXER
2.5V
REFERENCE
INTERNAL
CLOCK
GAIN
LTC1851
CONTROL LOGIC
AND
PROGRAMMABLE
SEQUENCER
, LTC and LT are registered trademarks of Linear Technology Corporation.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
2
LTC1850/LTC1851
18501i
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
IS
Supply Voltage (V
DD
)................................................. 6V
Analog Input Voltage (Note 3) .....–0.3V to (V
DD
+ 0.3V)
Digital Input Voltage (Note 4) ....................–0.3V to 10V
Digital Output Voltage.................. –0.3V to (V
DD
+ 0.3V)
Power Dissipation.............................................. 500mW
WU
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
LTC1850CFW
LTC1850IFW
T
JMAX
= 150°C, θ
JA
= 110°C/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TOP VIEW
FW PACKAGE
48-LEAD PLASTIC TSSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
REFOUT
REFIN
REFCOMP
GND
V
DD
V
DD
GND
DIFF
OUT
/S6
A2
OUT
/S5
A1
OUT
/S4
A0
OUT
/S3
D11/S2
D10/S1
D9/S0
D8
M1
SHDN
CS
CONVST
RD
WR
DIFF
A2
A1
A0
UNI/BIP
PGA
M0
OV
DD
OGND
BUSY
D0
D1
D2
D3
D4
D5
D6
D7
OVDD = VDD (Notes 1, 2)
Ambient Operating Temperature Range
LTC1850C/LTC1851C ............................ 0°C to 70°C
LTC1850I/LTC1851I .......................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
ORDER PART
NUMBER
LTC1851CFW
LTC1851IFW
T
JMAX
= 150°C, θ
JA
= 110°C/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TOP VIEW
FW PACKAGE
48-LEAD PLASTIC TSSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
REFOUT
REFIN
REFCOMP
GND
V
DD
V
DD
GND
DIFF
OUT
/S6
A2
OUT
/S5
A1
OUT
/S4
A0
OUT
/S3
D9/S2
D8/S1
D7/S0
D6
M1
SHDN
CS
CONVST
RD
WR
DIFF
A2
A1
A0
UNI/BIP
PGA
M0
OV
DD
OGND
BUSY
NC
NC
D0
D1
D2
D3
D4
D5
Consult LTC Marketing for parts specified with wider operating temperature ranges.
3
LTC1850/LTC1851
18501i
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Analog Input Range (Note 9) 4.75V ≤ V
DD
≤ 5.25V
Unipolar, Gain = 1 (PGA = 1) 0 – REFCOMP V
Unipolar, Gain = 2 (PGA = 0) 0 – REFCOMP/2 V
Bipolar, Gain = 1 (PGA = 1) ±REFCOMP/2 V
Bipolar, Gain = 2 (PGA = 0) ±REFCOMP/4 V
I
IN
Analog Input Leakage Current V
IN
> 0V < V
DD
, All Channels ●±1µA
C
IN
Analog Input Capacitance Between Conversions (Gain = 1) 15 pF
Between Conversions (Gain = 2) 25 pF
During Conversions 5 pF
t
ACQ
Sample-and-Hold Acquisition Time 50 150 ns
t
S(MUX)
Multiplexer Settling Time (Includes t
ACQ
) 50 150 ns
t
AP
Sample-and-Hold Aperature Delay Time –0.5 ns
t
jitter
Sample-and-Hold Aperature Delay Time Jitter 2 ps
RMS
CMRR Analog Input Common Mode Rejection Ratio 0V < (A
IN–
= A
IN+
) < 5V 60 dB
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
A ALOG I PUT
UU
LTC1850 LTC1851
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Resolution (No Missing Codes) ●10 12 Bits
Integral Linearity Error (Note 7) ●±0.25 ±0.5 ±0.35 ±1LSB
Differential Linearity Error ●±0.25 ±0.5 ±0.25 ±1LSB
Offset Error (Bipolar and Unipolar) (Note 8)
Gain = 1 (PGA = 1) REFCOMP ≥ 2V 5LSB
Gain = 1 (PGA = 1) REFCOMP ≥ 2V ●±0.5 ±2±1±7LSB
Gain = 2 (PGA = 0) ●±1±4±2±10 LSB
Offset Error Match ±0.5 ±1LSB
Unipolar Gain Error With External 4.096V Reference
Gain = 1 (PGA = 1) Applied to REFCOMP (Note 12) ±2±6LSB
Gain = 2 (PGA = 0) ±4±10 LSB
Unipolar Gain Error Match ±0.5 ±1LSB
Bipolar Gain Error With External 4.096V Reference
Gain = 1 (PGA = 1) Applied to REFCOMP (Note 12) ±2±6LSB
Gain = 2 (PGA = 0) ±4±10 LSB
Bipolar Gain Error Match ±0.5 ±1LSB
Full-Scale Error Temperature Coefficient 15 15 ppm/°C
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 6)
CO VERTER CHARACTERISTICS
U
4
LTC1850/LTC1851
18501i
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Analog Positive Supply Voltage (Note 10) ●4.75 5.25 V
V
DD
Digital Positive Supply Voltage (Note 10) ●4.75 5.25 V
OV
DD
Output Positive Supply Voltage (Note 10) ●2.7 5.25 V
I
DD
Positive Supply Current V
DD
= V
DD
= OV
DD
= 5, ●810mA
f
SAMPLE
= 1.25MHz
P
DISS
Power Dissipation ●40 50 mW
Power Down Positive Supply Current
Nap Mode SHDN = 0V, CS = 0V 1 mA
Sleep Mode SHDN = 0V, CS = 5V 50 µA
Power Down Power Dissipation
Nap Mode SHDN = 0V, CS = 0V 5 mW
Sleep Mode SHDN = 0V, CS = 5V 0.25 mW
PARAMETER CONDITIONS MIN TYP MAX UNITS
REFOUT Output Voltage I
OUT
= 0 2.48 2.50 2.52 V
REFOUT Output Temperature Coefficient I
OUT
= 0 ±15 ppm/°C
REFOUT Line Regulation 0.01 LSB/V
Reference Buffer Gain V
REFCOMP
/V
REFIN
1.636 1.638 1.640 V/V
REFCOMP Output Voltage External 2.5V Reference 4.09 4.096 4.1 V
Internal 2.5V Reference 4.06 4.096 4.132 V
REFCOMP Impedance REFIN = V
DD
6.4 kΩ
TA = 25°C. (Notes 5, 6)
I TER AL REFERE CE
UU U
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
DD
= 5.25V ●2.4 V
V
IL
Low Level Input Voltage V
DD
= 4.75V ●0.8 V
I
IN
Digital Input Current V
IN
= 0V to V
DD
●±5µA
C
IN
Digital Input Capacitance 2pF
V
OH
High Level Output Voltage V
DD
= 4.75V, I
O
= –10µA 4.5 V
V
DD
= 4.75V, I
O
= –200µA●4.0 V
V
OL
Low Level Output Voltage V
DD
= 4.75V, I
O
= 160µA 0.05 V
V
DD
= 4.75V, I
O
= 1.6mA ●0.10 0.4 V
I
OZ
Hi-Z Output Leakage D11 to D0 V
OUT
= 0V to V
DD
, CS High ●±10 µA
C
OZ
Hi-Z Capacitance D11 to D0 CS High (Note 9) ●15 pF
I
SOURCE
Output Source Current V
OUT
= 0V –20 mA
I
SINK
Output Sink Current V
OUT
= V
DD
30 mA
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
POWER REQUIRE E TS
WU
5
LTC1850/LTC1851
18501i
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency ●1.25 MHz
Acquisition + Conversion ●800 ns
t
CONV
Conversion Time ●650 ns
t
ACQ
Acquisition Time ●150 ns
t
1
CS to RD Setup Time (Notes 9, 10) ●0ns
t
2
CS to CONVST Setup Time (Notes 9, 10) ●10 ns
t
3
CS to SHDN Setup Time (Notes 9, 10) 200 ns
t
4
SHDN to CONVST Wake-Up Time Nap Mode (Note 10) 200 ns
Sleep Mode, 10µF REFCOMP 10 ms
Bypass Capacitor (Note 10)
t
5
CONVST Low Time (Notes 10, 11) ●50 ns
t
6
CONVST to BUSY Delay C
L
= 25pF 10 ns
●60 ns
t
7
Data Ready Before BUSY 20 35 ns
●15 ns
t
8
Delay Between Conversions (Note 10) ●50 ns
t
9
Wait Time RD After BUSY ●–5 ns
t
10
Data Access Time After RD C
L
= 25pF 20 35 ns
●45 ns
C
L
= 100pF 25 45 ns
●60 ns
t
11
BUS Relinquish Time 10 30 ns
0°C to 70°C●35 ns
–40°C to 85°C●40 ns
t
12
RD Low Time ●t
10
ns
t
13
CONVST High Time (Note 10) ●50 ns
t
14
Latch Setup Time (Notes 9, 10) ●10 ns
t
15
Latch Hold Time (Notes 9, 10) ●10 ns
t
16
WR Low Time (Note 10) ●50 ns
t
17
WR High Time (Note 10) ●50 ns
t
18
M1 to M0 Setup Time (Notes 9, 10) ●10 ns
t
19
M0 to BUSY Delay M1 High 20 ns
t
20
M0 to WR (or RD) Setup Time (Notes 9, 10) ●t
19
ns
t
21
M0 High Pulse Width (Note 10) ●50 ns
t
22
RD High Time Between Readback Reads (Note 10) ●50 ns
t
23
Last WR (or RD) to M0 (Note 10) ●10 ns
t
24
M0 to RD Setup Time (Notes 9, 10) ●t
19
ns
t
25
M0 to CONVST (Note 10) ●t
19
ns
t
26
Aperture Delay –0.5 ns
t
27
Aperture Jitter 2ps
RMS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
TI I G CHARACTERISTICS
UW
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND, OGND and
GND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above V
DD
,
they will be clamped by internal diodes. This product can handle input
currents of 100mA below ground or above V
DD
without latchup.
6
LTC1850/LTC1851
18501i
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents of
100mA below ground without latchup. These pins are not clamped to V
DD
.
Note 5: V
DD
= 4.75V to 5.25V, f
SAMPLE
= 1.25MHz, t
r
= t
f
= 2ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended input on any channel with COM grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0111 1111 1111 and 1000 0000 0000 for
LTC1851 and between 01 1111 1111 and 10 0000 0000 for LTC1850.
ELECTRICAL CHARACTERISTICS
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
the best results, ensure that CONVST returns high either within 400ns
after the start of the conversion or after BUSY rises.
Note 12: The analog input range is determined by the voltage on
REFCOMP. The gain error specification is tested with an external 4.096V
but is valid for any value of REFCOMP.
UU
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PI FU CTIO S
CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can
be used single ended relative to the analog input common
pin or differentially in pairs (CH0 and CH1, CH2 and CH3,
CH4 and CH5, CH6 and CH7).
COM (Pin 9): Analog Input Common Pin. For single-ended
operation (DIFF = 0), COM is the “–” analog input. COM is
disabled when DIFF is high.
REFOUT (Pin 10): Internal 2.5V Reference Output. Re-
quires bypass to analog ground plane with 1µF.
REFIN (Pin 11): Reference Mode Select/Reference Buffer
Input. REFIN selects the Reference mode and acts as the
reference buffer Input. REFIN tied to ground (Logic 0) will
produce 2.048V on the REFCOMP pin. REFIN tied to the
positive supply (Logic 1) disables the reference buffer to
allow REFCOMP to be driven externally. For voltages
between 1V and 2.6V, the reference buffer produces an
output voltage on the REFCOMP pin equal to 1.6384 times
the voltage on REFIN (4.096V on REFCOMP for a 2.5V
input on REFIN).
REFCOMP (Pin 12): Reference Buffer Output. REFCOMP
sets the full-scale input span. The reference buffer pro-
duces an output voltage on the REFCOMP pin equal to
1.6384 times the voltage on the REFIN pin (4.096V on
REFCOMP for a 2.5V input on REFIN). REFIN tied to
ground will produce 2.048V on the REFCOMP pin.
REFCOMP can be driven externally if REFIN is tied to the
positive supply. Requres bypass to analog ground plane
with 10µF tantalum in parallel with 0.1µF ceramic or 10µF
ceramic.
GND (Pin 13): Ground. Tie to analog ground plane.
V
DD
(Pin 14): 5V Supply. Bypass to analog ground plane
with 10µF tantalum in parallel with 0.1µF ceramic or 10µF
ceramic.
V
DD
(Pin 15): 5V Supply. Bypass to GND with 10µF
tantalum in parallel with 0.1µF ceramic or 10µF ceramic.
GND (Pin 16): Ground for Internal Logic. Tie to analog
ground plane.
DIFF
OUT
/S6 (Pin 17): Three-State Digital Data Output.
Active when RD is low. Following a conversion, the single-
ended/differential bit of the present conversion is available
on this pin concurrent with the conversion result. In
Readback mode, the single-ended/differential bit of the
current sequencer location (S6) is available on this pin.
The output swings between OV
DD
and OGND.
A2
OUT
/S5, A1
OUT
/S4, A0
OUT
/S3 (Pins 18 to 20): Three-
State Digital MUX Address Outputs. Active when RD is
low. Following a conversion, the MUX address of the
present conversion is available on these pins concurrent
with the conversion result. In Readback mode, the MUX
address of the current sequencer location (S5-S3) is
available on these pins. The outputs swing between OV
DD
and OGND.
7
LTC1850/LTC1851
18501i
UU
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PI FU CTIO S
D9/S2 (Pin 21, LTC1850): Three-State Digital Data Out-
put. Active when RD is low. Following a conversion, bit 9
of the present conversion is available on this pin. In
Readback mode, the unipolar/bipolar bit of the current
sequencer location (S2) is available on this pin. The output
swings between OV
DD
and OGND.
D11/S2 (Pin 21, LTC1851): Three-State Digital Data Out-
put. Active when RD is low. Following a conversion, bit 11
of the present conversion is available on this pin. In
Readback mode, the unipolar/bipolar bit of the current
sequencer location (S2) is available on this pin. The output
swings between OV
DD
and OGND.
D8/S1 (Pin 22, LTC1850): Three-State Digital Data Out-
puts. Active when RD is low. Following a conversion, bit 8
of the present conversion is available on this pin. In
Readback mode, the gain bit of the current sequencer
location (S1) is available on this pin. The output swings
between OV
DD
and OGND.
D10/S1 (Pin 22, LTC1851): Three-State Digital Data Out-
puts. Active when RD is low. Following a conversion, bit 10
of the present conversion is available on this pin. In
Readback mode, the gain bit of the current sequencer
location (S1) is available on this pin. The output swings
between OV
DD
and OGND.
D7/S0 (Pin 23, LTC1850): Three-State Digital Data Out-
puts. Active when RD is low. Following a conversion, bit 7
of the present conversion is available on this pin. In
Readback mode, the end of sequence bit of the current
sequencer location (S0) is available on this pin. The output
swings between OV
DD
and OGND.
D9/S0 (Pin 23, LTC1851): Three-State Digital Data Out-
puts. Active when RD is low. Following a conversion, bit 9
of the present conversion is available on this pin. In
Readback mode, the end of sequence bit of the current
sequencer location (S0) is available on this pin. The output
swings between OV
DD
and OGND.
D6 to D0 (Pins 24 to 30, LTC1850): Three-State Digital
Data Outputs. Active when RD is low. The outputs swing
between OV
DD
and OGND.
D8 to D0 (Pins 24 to 32, LTC1851): Three-State Digital
Data Outputs. Active when RD is low. The outputs swing
between OV
DD
and OGND.
NC (Pins 31, 32, LTC1850): No Connect. There is no
internal connection to these pins.
BUSY (Pin 33): Converter Busy Output. The BUSY output
has two functions. At the start of a conversion, BUSY will
go low and remain low until the conversion is completed.
The rising edge may be used to latch the output data. BUSY
will also go low while the part is in Program/Readback
mode (M1 high, M0 low) and remain low until M0 is
brought back high. The output swings between OV
DD
and
OGND.
OGND (Pin 34): Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.
OV
DD
(Pin 35): Digital Data Output Supply. Normally tied
to 5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10µF tantalum in parallel with 0.1µF ceramic
or 10µF ceramic.
M0 (Pin 36): Mode Select Pin 0. Used in conjunction with
M1 to select operating mode.
PGA (Pin 37): Gain Select Input. A high logic level selects
gain = 1, a low logic level selects gain = 2.
UNI/BIP (Pin 38): Unipolar/Bipolar Select Input. Logic low
selects a unipolar input span, a high logic level selects a
bipolar input span.
A0 to A2 (Pins 39 to 41): MUX Address Input Pins.
DIFF (Pin 42): Single-Ended/Differential Select Input. A
low logic level selects single ended, a high logic level
selects differential.
8
LTC1850/LTC1851
18501i
WR (Pin 43): Write Input. In Direct Address mode, WR low
enables the MUX address and configuration input pins
(Pins 37 to 42). WR can be tied low or the rising edge of
WR can be used to latch the data. In Program mode, WR
is used to program the sequencer. WR low enables the
MUX address and configuration input pins (Pins 37 to 42).
The rising edge of WR latches the data and increments the
counter to the next sequencer location.
RD (Pin 44): Read Input. During normal operation, RD
enables the output drivers when CS is low. In Readback
mode (M1 high, M0 low), RD going low reads the current
sequencer location, RD high advances to the next se-
quencer location.
UU
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PI FU CTIO S
CONVST (Pin 45): Conversion Start Input. This active low
signal starts a conversion on its falling edge.
CS (Pin 46): Chip Select Input. The chip select input must
be low for the ADC to recognize the CONVST and RD
inputs. If SHDN is low, a low logic level on CS selects Nap
mode; a high logic level on CS selects Sleep mode.
SHDN (Pin 47): Power Shutdown Input. A low logic level
will invoke the Shutdown mode selected by the CS pin. CS
low selects Nap mode, CS high selects Sleep mode. Tie
high if unused.
M1 (Pin 48): Mode Select Pin 1. Used in conjunction with
M0 to select operating mode.
9
LTC1850/LTC1851
18501i
UU
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PI FU CTIO S
NOMINAL (V) ABSOLUTE MAXIMUM (V)
PIN NAME DESCRIPTION MIN TYP MAX MIN MAX
1 to 8 CH0 to CH7 Analog Inputs 0 V
DD
–0.3 V
DD
+ 0.3
9 COM Analog Input Common Pin 0 V
DD
–0.3 V
DD
+ 0.3
10 REFOUT 2.5V Reference Output 2.5 – 0.3 V
DD
+ 0.3
11 REFIN Reference Buffer Input 0 2.5 V
DD
–0.3 V
DD
+ 0.3
12 REFCOMP Reference Buffer Output 4.096 –0.3 V
DD
+ 0.3
13 GND Ground, Substrate Ground 0 –0.3 V
DD
+ 0.3
14 V
DD
Supply 4.75 5 5.25 –0.3 6
15 V
DD
Supply 4.75 5 5.25 –0.3 6
16 GND Ground 0 –0.3 V
DD
+ 0.3
17 DIFF
OUT
/S6 Single-Ended/Differential Output OGND OV
DD
–0.3 V
DD
+ 0.3
18 A2
OUT
/S5 MUX Address Output OGND OV
DD
–0.3 V
DD
+ 0.3
19 A1
OUT
/S4 MUX Address Output OGND OV
DD
–0.3 V
DD
+ 0.3
20 A0
OUT
/S3 MUX Address Output OGND OV
DD
–0.3 V
DD
+ 0.3
21 D9/S2 (LTC1850) Data Output OGND OV
DD
–0.3 V
DD
+ 0.3
21 D11/S2 (LTC1851) Data Output OGND OV
DD
–0.3 V
DD
+ 0.3
22 D8/S1 (LTC1850) Data Output OGND OV
DD
–0.3 V
DD
+ 0.3
22 D10/S1 (LTC1851) Data Output OGND OV
DD
–0.3 V
DD
+ 0.3
23 D7/S0 (LTC1850) Data Output OGND OV
DD
–0.3 V
DD
+ 0.3
23 D9/S0 (LTC1851) Data Output OGND OV
DD
–0.3 V
DD
+ 0.3
24 to 30 D6 to D0 (LTC1850) Data Outputs OGND OV
DD
–0.3 V
DD
+ 0.3
24 to 32 D8 to D0 (LTC1851) Data Outputs OGND OV
DD
–0.3 V
DD
+ 0.3
31 to 32 NC (LTC1850)
33 BUSY Converter Busy Output OGND OV
DD
–0.3 V
DD
+ 0.3
34 OV
DD
Output Supply 2.7 5 5.25 –0.3 6
35 OGND Output Ground 0 –0.3 V
DD
+ 0.3
36 M0 Mode Select Pin 0 0 V
DD
–0.3 10
37 PGA Gain Select Input 0 V
DD
–0.3 10
38 UNI/BIP Unipolar/Bipolar Input 0 V
DD
–0.3 10
39 to 41 A0 to A2 MUX Address Inputs 0 V
DD
–0.3 10
42 DIFF Single-Ended/Differential Input 0 V
DD
–0.3 10
43 WR Write Input, Active Low 0 V
DD
–0.3 10
44 RD Read Input, Active Low 0 V
DD
–0.3 10
45 CONVST Conversion Start Input, Active Low 0 V
DD
–0.3 10
46 CS Chip Select Input, Active Low 0 V
DD
–0.3 10
47 SHDN Shutdown Input, Active Low 0 V
DD
–0.3 10
48 M1 Mode Select Pin 1 0 V
DD
–0.3 10
10
LTC1850/LTC1851
18501i
APPLICATIO S I FOR ATIO
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The LTC1850/LTC1851 are complete and very flexible data
acquisition systems. They consist of a 10-bit/12-bit,
1.25Msps capacitive successive approximation A/D con-
verter with a wideband sample-and-hold, a configurable
8-channel analog input multiplexer, an internal reference
and reference buffer amplifier, a 16-bit parallel digital
output and digital control logic including a programmable
sequencer.
CONVERSION DETAILS
T
he core analog-to-digital converter in the LTC1850/
LTC1851 uses a successive approximation algorithm and
an internal sample-and-hold circuit to convert an analog
signal to a 10-bit/12-bit parallel output. Conversion start
is controlled by the CS and CONVST inputs. At the start of
the conversion, the successive approximation register
(SAR) is reset. Once a conversion cycle is begun, it cannot
be restarted. During the conversion, the internal differen-
tial 10-bit/12-bit capacitive DAC output is sequenced by
the SAR from the most significant bit (MSB) to the least
significant bit (LSB). The outputs of the analog input
multiplexer are connected to the sample-and-hold ca-
pacitors (CSAMPLE) during the acquire phase and the
comparator offset is nulled by the zeroing switches. In
this acquire phase, a minimum delay of 150ns will provide
enough time for the sample-and-hold capacitors to ac-
quire the analog signal. During the convert phase, the
comparator zeroing switches are open, putting the com-
parator into compare mode. The input switches connect
CSAMPLE to ground, transferring the differential analog
input charge onto the summing junction. This input
charge is successively compared with the binary weighted
charges supplied by the differential ca
pacitive DAC. Bit
decisions are made by the high speed comparator. At the
end of the conversion, the differential DAC output bal-
ances the input charges. The SAR contents (a 10-bit/
12-bit data word), which represents the difference of the
analog input multiplexer outputs, and the 4-bit address
word are loaded into the 14-bit/16-bit output latches.
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency. The effective number of bits (ENOBs) is a
measurement of the resolution of an ADC and is directly
related to the S/(N + D) by the equation:
ENOB = [S/(N + D) – 1.76]/6.02
where ENOB is the effective number of bits and S/(N + D)
is expressed in dB. At the maximum sampling rate of
1.25MHz, the LTC1850/LTC1851 maintain near ideal
ENOBs up to and beyond the Nyquist input frequency of
625kHz.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD Log VVV Vn
V
=+++
20 234
1
222 2
...
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. The LTC1850/LTC1851
have good distortion performance up to the Nyquist fre-
quency and beyond.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD.
IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
11
LTC1850/LTC1851
18501i
APPLICATIO S I FOR ATIO
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If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc.
For example, the 2nd order IMD terms include (fa ± fb).
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:
IMD fa fb Log Amplitude at fa fb
Amplitude at fa
±
()
=±
()
20
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC.
This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB for the LTC1851 (11
effective bits) or 56dB for the LTC1850 (9 effective bits).
The LTC1850/LTC1851 have been designed to optimize
input bandwidth, allowing the ADC to undersample input
signals with frequencies above the converter’s Nyquist
frequency. The noise floor stays very low at high frequen-
cies; S/(N + D) becomes dominated by distortion at
frequencies far beyond Nyquist.
ANALOG INPUT MULTIPLEXER
The analog input multiplexer is controlled using the single-
ended/differential pin (DIFF), three MUX address pins (A2,
A1, A0), the unipolar/bipolar pin (UNI/BIP) and the gain
select pin (PGA). The single-ended/differential pin (DIFF)
allows the user to configure the MUX as eight single-
ended channels relative to the analog input common pin
(COM) when DIFF is low or as four differential pairs (CH0
and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) when
DIFF is high. The channels (and polarity in the differential
case) are selected using the MUX address inputs as shown
in Table 1. Unused inputs (including the COM in the
differential case) should be grounded to prevent noise
coupling.
Table 1. Multiplexer Address Table
MUX ADDRESS SINGLE-ENDED CHANNEL SELECTION
DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
0000+ –
0001 + –
0010 + –
0011 + –
0100 + –
0101 + –
0110 + –
0111 + –
MUX ADDRESS DIFFERENTIAL CHANNEL SELECTION
DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
1000+ – *
1001– + *
1010 + – *
1011 – + *
1100 + – *
1101 – + *
1110 + – *
1111 – + *
*Not used in differential mode. Connect to GND.
In addition to selecting the MUX channel, the
LTC1850/
LTC1851 also allows the user to select between two gains
and unipolar or bipolar inputs for a total of four input
spans. PGA high selects a gain of 1 (the input span is equal
to the voltage on REFCOMP). PGA low selects a gain of 2
where the input span is equal to half of the voltage on
REFCOMP. UNI/BIP low selects a unipolar input span,
UNI/BIP high selects a bipolar input span. Table 2 summa-
rizes the possible input spans.
Table 2. Input Span Table
INPUT SPAN
UNI/BIP PGA REFCOMP = 4.096V
0 0 0 – REFCOMP/2 0 – 2.048V
0 1 0 – REFCOMP 0 – 4.096V
10±REFCOMP/4 ±1.024V
11±REFCOMP/2 ±2.048V
12
LTC1850/LTC1851
18501i
It should be noted that the bipolar input span of the
LTC1850/LTC1851 does not allow negative inputs with
respect to ground. The LTC1850/LTC1851 have a unique
differential sample-and-hold circuit that allows rail-to-rail
inputs.
The ADC will always convert the difference of the
“+” and “–” inputs independent of the common mode
voltage.
The common mode rejection holds up to high
frequencies.
The only requirement is that both inputs can
not exceed the V
DD
power supply voltage or ground. When
a bipolar input span is selected the “+” input can swing
±full scale relative to the “–” input but neither input can
exceed V
DD
or go below ground.
Integral nonlinearity errors (INL) and differential nonlin-
earity errors (DNL) are
independent of the common mode
voltage, however, the bipolar zero error (BZE) will vary.
The change in BZE is typically less than 0.1% of the
common mode voltage.
Some AC applications may have their performance lim-
ited by distortion. The ADC and many other circuits exhibit
higher distortion when signals approach the supply or
ground. THD will degrade as the inputs approach either
power supply rail. Distortion can be reduced by reducing
the signal amplitude and keeping the common mode
voltage at approximately midsupply.
Driving the Analog Inputs
The inputs of the
LTC1850/
LTC1851 are easy to drive.
Each of the analog inputs can be used as a single-ended
input relative to the input common pin (CH0-COM, CH1-
COM, etc.) or in pairs (CH0 and CH1, CH2 and CH3, CH4
and CH5, CH6 and CH7) for differential inputs. Regardless
of the MUX configuration, the “+” and “–” inputs are
sampled at the same instant. Any unwanted signal that is
common mode to both inputs will be reduced by the
common mode rejection of the sample-and-hold circuit.
The inputs draw only one small current spike while charg-
ing the sample-and-hold capacitors at the end of conver-
sion.
During conversion, the analog inputs draw only a
small leakage current.
If the source impedance of the
driving circuit is low, then the
LTC1850/
LTC1851 inputs
can be driven directly.
As source impedance increases, so
will acquisition time.
For minimum acquisition time with
high source impedance, a buffer amplifier should be used.
The only requirement is that the amplifier driving the
analog input(s) must settle after the small current spike
before the next conversion starts (settling time must be
150ns for full throughput rate).
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain of
+1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz should be less than 100Ω.
The second requirement is that the closed-loop bandwidth
must be greater than 20MHz to ensure adequate small-
signal settling for full throughput rate. The following list is
a summary of the op amps that are suitable for driving the
LTC1850/
LTC1851, more detailed information is available
in the Linear Technology Databooks, the LinearView
TM
CD-ROM and on our web site at www.linear-tech.com.
LT
®
1360: 50MHz Voltage Feedback Amplifier. ±2.5V to
±15V supplies. 5mA supply current. Low distortion.
LT1363: 70MHz Voltage Feedback Amplifier. ±2.5V to
±15V supplies. 7.5mA supply current. Low distortion.
LT1364/LT1365: Dual and Quad 70MHz Voltage Feedback
Amplifiers. ±2.5V to ±15V supplies. 7.5mA supply current
per amplifier. Low distortion.
LT1468/LT1469: Single and Dual 90MHz Voltage Feed-
back Amplifier. ±5V to ±15V supplies. 7mA supply current
per amplifier. Lowest noise and low distortion.
LT1630/LT1631: Dual and Quad 30MHz Rail-to-Rail Volt-
age Feedback Amplifiers. Single 3V to ±15V supplies.
3.5mA supply current per amplifier. Low noise and low
distortion.
LT1632/LT1633: Dual and Quad 45MHz Rail-to-Rail Volt-
age Feedback Amplifiers. Single 3V to ±15V supplies.
4.3mA supply current per amplifier. Low distortion.
LT1806/LT1807: Single and Dual 325MHz Rail-to-Rail
Voltage Feedback Amplifier. Single 3V to ±5V supplies.
13mA supply current. Lowest distortion.
APPLICATIO S I FOR ATIO
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LinearView is a trademark of Linear Technology Corporation.
13
LTC1850/LTC1851
18501i
LT1809/LT1810: Single and Dual 180MHz Rail-to-Rail
Voltage Feedback Amplifier. Single 3V to ±15V supplies.
20mA supply current. Lowest distortion.
LT1812/LT1813: 100MHz Voltage Feedback Amplifier.
Single 5V to ±5V supplies. 3.6mA supply current. Low
noise and low distortion.
Input Filtering
The noise and the distortion
of the input amplifier and
other circuitry must
be considered since they will add to
the
LTC1850/
LTC1851 noise and distortion.
Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise.
A simple 1-pole RC filter is
sufficient for
many applications.
For instance, a 100Ω source resistor
and a 1000pF capacitor to ground on the input will limit the
input bandwidth to 1.6MHz. The capacitor also acts as a
charge reservoir for the input sample-and-hold and iso-
lates the ADC input from sampling glitch sensitive cir-
cuitry.
High quality capacitors and resistors should be
used since these components can add distortion.
NPO and
silver mica type dielectric capacitors have excellent linear-
ity.
Carbon surface mount resistors can also generate
distortion from self heating and from damage that may
occur during soldering.
Metal film surface mount resistors
are much less susceptible to both problems.
REFERENCE
The LTC1850/LTC1851 include an on-chip, temperature
compensated, curvature corrected, bandgap reference
that is factory trimmed to 2.500V and has a very flexible
3-pin interface. REFOUT is the 2.5V bandgap output,
REFIN is the input to the reference buffer and REFCOMP
is the reference buffer output. The input span is deter-
mined by the voltage appearing on the REFCOMP pin as
shown in Table 2. The reference buffer has a gain of
1.6384 and is factory trimmed by forcing an external
2.500V on the REFIN pin and trimming REFCOMP to
4.096V. The 3-pin interface allows for three pin-strappable
Reference modes as well as two additional external Ref-
erence modes. For voltages on the REFIN pin ranging
from 1V to 2.6V, the output voltage on REFCOMP will
equal 1.6384 times the voltage on the REFIN pin. In this
mode, the REFIN pin can be tied to REFOUT to utilize the
APPLICATIO S I FOR ATIO
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internal 2.5V reference to get 4.096V on REFCOMP or
driven with an external reference or DAC. If REFIN is tied
low, the internal 2.5V reference divided by 2 (1.25V) is
connected internally to the input of the reference buffer
resulting in 2.048V on REFCOMP. If REFIN is tied high, the
reference buffer is disabled and REFCOMP can be tied to
REFOUT to achieve a 2.5V span or driven with an external
reference or DAC. Table 3 summarizes the Reference
modes.
Table 3. Reference Mode Table
MODE REFIN REFCOMP
REFIN Tied Low = GND 2.048V Output
REFIN is Buffer Input 1V to 2.6V Input 1.6384V to 4.26V Output
(1.6384 • REFIN)
REFIN Tied High = V
DD
Input, 6.4kΩ to Ground
Full Scale and Offset
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero during
a calibration sequence. Offset error must be adjusted
before full-scale error. Zero offset is achieved by adjusting
the offset applied to the “–” input. For single-ended inputs,
this offset should be applied to the COM pin. For differen-
tial inputs, the “–” input is dictated by the MUX address.
For zero offset error, apply 0.5LSB (actual voltage will vary
with input span selected) to the “+” input and adjust the
offset at the “–” input until the output code flickers
between 0000 0000 0000 and 0000 0000 0001 for the
LTC1851 and between 00 0000 0000 and 00 0000 0001 for
the LTC1850.
As mentioned earlier, the internal reference is factory
trimmed to 2.500V. To make sure that the reference buffer
gain is not compensating for trim errors in the reference,
REFCOMP is trimmed to 4.096V with an accurate external
2.5V reference applied to REFIN. Likewise, to make sure
that the full-scale gain trim is not compensating for errors
in the reference buffer gain, the input full-scale gain is
trimmed with an accurate 4.096V reference applied to
REFCOMP (REFIN = 5V to disable the reference buffer).
This allows the use of either a 2.5V reference applied to
REFIN or a 4.096V reference applied to REFCOMP to
achieve accurate results. Full-scale errors can be trimmed
to zero by adjusting the appropriate reference voltage. For
14
LTC1850/LTC1851
18501i
unipolar inputs, an input voltage of FS – 1.5LSBs should
be applied to the “+” input and the appropriate reference
adjusted until the output code flickers between 1111 1111
1110 and 1111 1111 1111 for the LTC1851 and between
11 1111 1110 and 11 1111 1111 for the LTC1850.
For bipolar inputs, an input voltage of FS – 1.5LSBs should
be applied to the “+” input and the appropriate reference
adjusted until the output code flickers between 0111 1111
1110 and 0111 1111 1111 for the LTC1851 and between
01 1111 1110 and 01 1111 1111 for the LTC1850.
These adjustments as well as the factory trims affect all
channels. The channel-to-channel offset and gain error
matching are guaranteed by design to meet the specifica-
tions in the Converter Characteristics table.
OUTPUT DATA FORMAT
The
LTC1850/
LTC1851 have a 14-bit/16-bit parallel out-
put. The output word normally consists of a 10-bit/12-bit
conversion result data word and a 4-bit address (three
address bits A2
OUT
, A1
OUT
, A0
OUT
and the DIFF
OUT
bit).
The output drivers are enabled when RD is low provided
the chip is selected (CS is low). All 14/16 data output pins
and BUSY are supplied by OV
DD
and OGND to allow easy
interface to 3V or 5V digital logic.
The data format of the conversion result is automatically
selected and determined by the UNI/BIP input pin. If the
UNI/BIP pin is low indicating a unipolar input span
(0 – REFCOMP assuming PGA = 1), the format for the
data is straight binary with 1 LSB = FS/4096 (1mV for
REFCOMP = 4.096V) for the LTC1851 and 1LSB = FS/
1024 (4mV for REFCOMP = 4.096V) for the LTC1850.
If the UNI/BIP pin is high indicating a bipolar input span
(±REFCOMP/2 for PGA = 1), the format for the data is
two’s complement binary with 1 LSB = [(+FS) – (–FS)]/
4096 (1mV for REFCOMP = 4.096V) for the LTC1851 and
1LSB = [(+FS) – (–FS)]/1024 (4mV for REFCOMP =
4.096V) for the LTC1850.
In both cases, the code transitions occur midway between
successive integer LSB values (i.e., –FS + 0.5LSB,
–FS + 1.5LSB, ... –1.5LSB, –0.5LSB, 0.5LSB, 1.5LSB, ...
FS – 1.5LSB, FS – 0.5LSB).
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The three most significant bits of the data word (D11,
D10, and D9 for the LTC1851; D9, D8 and D7 for the
LTC1850) also function as output bits when reading the
contents of the programmable sequencer. During
readback, a 7-bit status word (S6-S0) containing the
contents of the current sequencer location is available
when RD is low. The individual bits of the status word are
outlined in Figure 1. During readback, the D8 to D0 pins
(LTC1851) or D6 to D0 pins (LTC1850) remain high
impedance irrespective of the state of RD.
BOARD LAYOUT AND BYPASSING
To obtain the best performance from the LTC1850/
LTC1851, a printed circuit board with ground plane is
required. The ground plane under the ADC area should be
as free of breaks and holes as possible, such that a low
impedance path between all ADC grounds and all ADC
decoupling capacitors is provided. It is critical to prevent
digital noise from being coupled to the analog inputs,
reference or analog power supply lines. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particu-
lar, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 34 (OGND), Pin 13 (GND), Pin 16 (ADC’s GND) and all
other analog grounds should be connected to this single
analog ground point. The bypass capacitors should also
be connected to this analog ground plane. No other digital
grounds should be connected to this analog ground plane.
In some applications, it may be desirable to connect the
OV
DD
to the logic system supply and OGND to the logic
system ground. In these cases, OV
DD
should be bypassed
to OGND instead of the analog ground plane.
Low impedance analog and digital power supply common
returns are essential to the low noise operation of the ADC
and the foil width for these tracks should be as wide as
possible. In applications where the ADC data outputs and
control signals are connected to a continuously active
microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough
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LTC1850/LTC1851
18501i
APPLICATIO S I FOR ATIO
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The
LTC1850/
LTC1851 have differential inputs to mini-
mize noise coupling. Common mode noise on the “+” and
“–” inputs will be rejected by the input CMRR. The
LTC1850/
LTC1851 will hold and convert the difference between
whichever input is selected as the “+” input and whichever
input is selected as the “–” input. Leads to the inputs
should be kept as short as possible.
SUPPLY BYPASSING
High quality, low series resistance ceramic 10µF bypass
capacitors should be used. Surface mount ceramic ca-
pacitors such as Murata GRM235Y5V106Z016 provide
excellent bypassing in a small board space. Alternatively,
10µF tantalum capacitors in parallel with 0.1µF ceramic
capacitors can be used. Bypass capacitors must be lo-
cated as close to the pins as possible. The traces connect-
ing the pins and the bypass capacitors must be kept short
and should be made as wide as possible.
DIGITAL INTERFACE
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs.
The internal
clock is factory trimmed to achieve a typical conversion
time of 550ns, and a maximum conversion time over the
full operating temperature range of 650ns.
No external
adjustments are required. The guaranteed maximum ac-
quisition time is 150ns. In addition, a throughput time of
800ns and a minimum sampling rate
of 1.25Msps is
guaranteed.
SINGLE-ENDED/
DIFFERENTIAL BIT UNIPOLAR/
BIPOLAR BIT
S6 S5
A2 A0
END OF
SEQUENCE BIT
PGA BIT
1851 F01
A1
MUX ADDRESS
S4 S3 S2 S1 S0
Figure 1. Readback Status Word
Unipolar Transfer Characteristic
(UNI/BIP = 0)
Bipolar Transfer Characteristic
(UNI/BIP = 1)
INPUT VOLTAGE (V)
0 FS – 1LBS
OUTPUT CODE
1111...1111
1111...1110
1111...1101
1000...0001
1000...0000
0111...1111
0111...1110
0000...0010
0000...0001
0000...0000
1851 F01A
FS = V
REFCOMP
INPUT VOLTAGE (V)
–FS –1LBS 0 1LBS FS – 1LBS
OUTPUT CODE
0111...1111
0111...1110
0111...1101
0000...0001
0000...0000
1111...1111
1111...1110
1000...0010
1000...0001
1000...0000
1851 F01B
BIPOLAR
ZERO
FS = V
REFCOMP
2
from the microprocessor to the successive approximation
comparator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversions or
by using three-state buffers to isolate the ADC bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
CS
SHDN
t3
1851 F02
Figure 2. CS to SHDN Timing
16
LTC1850/LTC1851
18501i
Power Shutdown
The
LTC1850/
LTC1851 provide two power shutdown
modes, Nap and Sleep, to save power during inactive
periods.
The Nap mode reduces the power to 5mW and
leaves only the digital logic and reference powered up.
The
wake-up time from Nap to active is 200ns.
In Sleep mode,
all bias currents are shut down and only leakage current
remains—about 50µA.
Wake-up time from sleep mode is
much slower since the reference circuit must power-up
and settle to 0.005% for full 12-bit accuracy (0.02% for full
10-bit accuracy).
Sleep mode wake-up time is dependent
on the value of the capacitor connected to the REFCOMP
(Pin 12).
The wake-up time is 10ms with the recom-
mended 10µF capacitor.
Shutdown is controlled by Pin 47 (SHDN); the ADC is in
shutdown when it is low.
The shutdown mode is selected
with Pin 46 (CS); low selects Nap.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD.
A transition
from 1 to 0 applied to the CONVST pin will start a
conversion after the ADC has been selected (i.e., CS is
low).
Once initiated, it cannot be restarted until the conver-
sion is complete.
Converter status is indicated by the
BUSY output. BUSY is low during a conversion. If CONVST
returns high at a critical point during the conversion it can
create small errors. For the best results, ensure that
CONVST returns high either within 400ns after the start of
the conversion or after BUSY rises.
Figures 5 through 9 show several different modes of
operation.
In modes 1a and 1b (Figures 5 and 6),
CS and RD are both tied low.
The falling edge of
CONVST starts the conversion. The data outputs are
always enabled and data can be latched with the
BUSY rising edge.
Mode 1a shows operation with a narrow
logic low CONVST pulse.
Mode 1b shows a narrow logic
high CONVST pulse.
In mode 2 (Figure 7), CS is tied low.
The falling edge of
CONVST signal again starts the conversion.
Data outputs
are in three-state until read by the MPU with the
RD signal.
Mode 2 can be used for operation with a shared
MPU databus.
In slow memory and ROM modes (Figures 8 and 9), CS is
tied low and CONVST and RD are tied together.
The MPU
starts the conversion and reads the output with the RD
signal.
Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode, the processor applies a logic low
to RD ( = CONVST), starting the conversion.
BUSY goes
low, forcing the processor into a Wait state.
The previous
conversion result appears on the data outputs.
When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high releasing the
processor, and the processor takes RD ( = CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD ( = CONVST) low,
starting a conversion and reading the previous conversion
result.
After the conversion is complete, the processor can
read the new result and initiate another conversion.
APPLICATIO S I FOR ATIO
WUUU
CS
CONVST
t
2
t
1
1851 F04
RD
Figure 4. CS to CONVST Setup Timing
SHDN
CONVST
t4
1851 F03
Figure 3. SHDN to CONVST Wake-Up Timing
17
LTC1850/LTC1851
18501i
APPLICATIO S I FOR ATIO
WUUU
CONVST
CS = RD = LOW
BUSY
DATA DATA (N – 1) DATA N
1851 F06
t
13
t
6
t
6
t
7
t
8
t
CONV
t
5
Figure 6. Mode 1b CONVST Starts a Conversion. Data is Read by RD
CONVST
BUSY
RD
DATA
t
5
t
13
t
8
t
CONV
t
10
DATA N
1851 F07
t
9
t
11
t
6
t
12
CS = LOW
Figure 7. Mode 2 CONVST Starts a Conversion. Data is Read by RD
CONVST
CS = RD = LOW
BUSY
t
6
t
7
DATA DATA (N – 1) DATA N
1851 F05
t
5
t
CONV
t
8
Figure 5. Mode 1a CONVST Starts a Conversion. Data Outputs Always Enabled
18
LTC1850/LTC1851
18501i
APPLICATIO S I FOR ATIO
WUUU
RD = CONVST
BUSY
DATA
t
8
t
CONV
1851 F09
DATA (N – 1) DATA N
t
6
t
11
t
10
CS = LOW
Figure 9. ROM Mode Timing
MODES OF OPERATION
Direct Address Mode
The simplest mode of operation is the Direct Address
mode. This mode is selected when both the M1 and M0
pins are low. In this mode, the address input pins directly
control the MUX and the configuration input pins directly
control the input span. The address and configuration
input pins are enabled when WR is low. WR can be tied low
if the pins will be constantly driven or the rising edge of WR
can be used to latch and hold the inputs for as long as WR
is held high.
Scan Mode
Scan mode is selected when M1 is low and M0 is high. This
mode allows the converter to scan through all of the input
channels sequentially and repeatedly without the user
having to provide an address. The address input pins (A2
to A0) are ignored but the DIFF, PGA and UNI/BIP pins are
still enabled when WR is low. As in the direct address
mode, WR can be held low or the rising edge of WR can be
used to latch and hold the information on these pins for as
long as WR is held high. The DIFF pin selects the scan
pattern. If DIFF is held low, the scan pattern will consist of
all eight channels in succession, single-ended relative to
t
6
t
10
t
7
t
11
t
8
RD = CONVST
BUSY
DATA DATA (N – 1) DATA (N + 1)DATA N DATA N
1851 F08
t
CONV
CS = LOW
Figure 8. Slow Memory Mode Timing
19
LTC1850/LTC1851
18501i
APPLICATIO S I FOR ATIO
WUUU
COM (CH0-COM, CH1-COM, CH2-COM, CH3-COM, CH4-
COM, CH5-COM, CH6-COM, CH7-COM, repeat). At the
maximum conversion rate the throughput rate for each
channel would be 1.25Msps/8 or 156.25ksps. If DIFF is
held high, the scan pattern will consist of four differential
pairs (CH0-CH1, CH2-CH3, CH4-CH5, CH6-CH7, repeat).
At the maximum conversion rate, the throughput rate for
each pair would be 1.25Msps/4 or 312.5ksps. It is pos-
sible to drive the DIFF input pin while the part is in Scan
mode to achieve combinations of single-ended and differ-
ential inputs. For instance, if the A0
OUT
pin is tied to the
DIFF input pin, the scan pattern will consist of four single-
ended inputs and two differential pairs (CH0-COM single-
ended, CH1-COM single-ended, CH2-CH3 differential,
CH4-COM single-ended, CH5-COM single-ended, CH6-
CH7 differential, repeat).
The scan counter is reset to zero whenever the M0 pin
changes state so that the first conversion after M0 rises
will be MUX Address 000 (CH0-COM single-ended or CH0-
CH1 differential depending on the state of the DIFF pin). A
conversion is initiated by the falling edge of CONVST. After
each conversion, the address counter is advanced (by one
if DIFF is low, by two if DIFF is high) and the MUX address
for the present conversion is available on the address
output pins (DIFF
OUT
, A2
OUT
to A0
OUT
) along with the
conversion result.
Program/Readback Mode
The
LTC1850/
LTC1851 include a sequencer that can be
programmed to run a sequence of up to 16 locations
containing a MUX address and input configuration. The
MUX address and input configuration for each location are
programmed using the DIFF, A2 to A0, UNI/BIP and PGA
pins and are stored in memory along with an end-of-
sequence (EOS) bit that is generated automatically. The
six input address and configuration bits plus the EOS bit
can be read back by accessing the 7-bit readback status
word (S6-S0) through the data output pins. The sequencer
memory is a 16 × 7 block of memory represented by the
block diagram in Figure 10.
The sequencer is accessed by taking the M1 mode pin
high. With M1 high, the sequencer memory is accessed by
taking the M0 mode pin low. This will cause BUSY to go
low, disabling conversions during the programming and
readback of the sequencer. The sequencer is reset to
location 0000 whenever M1 or M0 changes state. One of
these signals should be cycled prior to any read or write
operation to guarantee that the sequencer will be pro-
grammed or read starting at location 0000.
The sequencer is programmed sequentially starting from
location 0000. RD and WR should be held high, the
appropriate signals applied to the DIFF pin, the A2 to A0
MUX address pins, the UNI/BIP pin and the PGA pin and
WR taken low to write to the memory. WR going high will
latch the data into memory and advance the pointer to the
next sequencer location. Up to 16 locations can be pro-
grammed and the last location written before M0 is taken
back high will be the last location in the sequence. After 16
writes, the pointer is reset to location 0000 and any
subsequent writes will erase all of the previous contents
and start a new sequence.
The sequencer memory can be read by holding WR high
and using RD. Taking RD low accesses the sequencer
LOCATION 0000
DIFF A2 A1 A0 UNI/BIP PGA EOS
LOCATION 0001
LOCATION 0010
LOCATION 1110
LOCATION 1111
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1851 F10
Figure 10. Sequencer Memory Block Diagram
20
LTC1850/LTC1851
18501i
APPLICATIO S I FOR ATIO
WUUU
Table 5
OPERATION MODE M1 M0 WR RD COMMENTS
Direct Address 0 0 0 OE Address and Configuration are Driven from External Pins
0 0 OE Address and Configuration are Latched on Rising Edge of WR or Falling Edge of CONVST
Scan 0 1 0 OE Address is Provided by Internal Scan Counter, Configuration is Driven from External Pins
0 1 OE Configuration is Latched on Rising Edge of WR or Falling Edge of CONVST
Program 1 0 1 Write Sequencer Location, WR Low Enables Inputs, Rising Edge of WR Latches Data and
Advances to Next Location
Readback 1 0 1 Read Sequencer Location, Falling Edge of RD Enables Output, Rising Edge of RD
Advances to Next Location
Sequence Run 1 1 X OE Run Programmed Sequence, Falling Edge of CONVST Starts Conversion and Advances to
Next Location
memory and enables the data output pins. The sequencer
should be reset to location 0000 before beginning a read
operation. The seven output bits will be available on the
DIFF
OUT
/S6, A2
OUT
/S5, A1
OUT
/S4, A0
OUT
/S3, D11/S2, D10/
S1 and D9/S0 pins (LTC1851) or DIFF
OUT
/S6, A2
OUT
/S5,
A1
OUT
/S4, A0
OUT
/S3, D9/S2, D8/S1 and D7/S0 pins
(LTC1850). The D8 to D0 (LTC1851) or D6 to D0 (LTC1850)
data output pins will remain high impedance during
readback. RD going high will return the data output pins to
a high impedance state and advance the pointer to the next
location. A logic 1 on the D9/S0 (or D7/S0) pin indicates
the last location in the current sequence but all 16 loca-
tions can be read by continuing to clock RD. After 16 reads,
the pointer is reset to location 0000. When all program-
ming and/or reading of the sequencer memory is com-
plete, M0 is taken high. BUSY will come back high enabling
CONVST and indicating that the part is ready to start a
conversion.
Sequence Run Mode
Once the sequencer is programmed, M0 is taken high.
BUSY will also come back high enabling CONVST and the
next falling CONVST will begin a conversion using the MUX
address and input configuration stored in location 0000 of
the sequencer memory. After each conversion, the se-
quencer pointer is advanced by one and the MUX address
(the actual channel or channels being converted, not the
sequencer pointer) for the present conversion is available
on the address output pins along with the conversion
result. When the sequencer finishes converting the last
programmed location, the sequencer pointer will return to
location 0000 for the next conversion. The sequencer will
also reset to location 0000 anytime the M1 or M0 pin
changes state.
The contents of the sequencer memory will be retained as
long as power is continuously applied to the part. This
allows the user to switch from Sequence Run mode to
either Direct Address or Scan Mode and back without
losing the programmed sequence. The part can also be
disabled using CS or shutdown in Nap or Sleep mode
without losing the programmed sequence. Table 5 out-
lines the operational modes of the
LTC1850/
LTC1851.
Figures 11 and 12 show the timing diagrams for writing to,
reading from and running a sequence.
21
LTC1850/LTC1851
18501i
APPLICATIO S I FOR ATIO
WUUU
L0CATION 0000 L0CATION 0001 L0CATION n
L0CATION 0000 L0CATION 0001 L0CATION n
L0CATION 0000 L0CATION 0001 L0CATION n
L0CATION 0000 L0CATION 0001 L0CATION n
LOCATION
0000 LOCATION
0001 LOCATION
nLOCATION
n + 1
t
18
M1
CONVST
t
20
t
17
t
16
t
14
t
23
t
23
1851 F11
t
11
t
10
t
19
t
15
t
24
t
22
t
12
WR
RD
DIFF
A2 TO A0
UNI/BIP
PGA
M0
BUSY
S6 TO S0 Hi-Z
Hi-Z
D6 TO D0 (LTC1850)
D8 TO D0 (LTC1851)
Figure 11. Sequencer I/O
22
LTC1850/LTC1851
18501i
APPLICATIO S I FOR ATIO
WUUU
Figure 12. Programming and Running a Sequence
L0CATION 0000 L0CATION 0001
L0CATION 0000 L0CATION 0001
L0CATION 0000 L0CATION 0001
L0CATION 0000 L0CATION 0001 L0CATION 0010
L0CATION 0010
L0CATION 0010
L0CATION 0010
DATA
0000 DATA
0001 DATA
0010 DATA
0000
t
18
M1
CONVST
t
20
t
16
t
14
t
17
t
15
t
23
t
8
t
5
1851 F12
t
7
t
11
t
10
t
19
t
6
t
25
CONVERT
0000 CONVERT
0001 CONVERT
0010 CONVERT
0000
WR
RD
DIFF
A2 TO A0
UNI/BIP
PGA
Hi-Z
M0
BUSY
DIFF
OUT
A2
OUT
TO A0
OUT
D9 TO D0 (LTC1850)
D11 TO D0 (LTC1851)
23
LTC1850/LTC1851
18501i
U
PACKAGE DESCRIPTIO
FW Package
48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651)
FW48 TSSOP 0501
.09 – .20
(.0035 – .008)
0° – 8°
.45 – .75
(.018 – .029) .17 – .27
(.0067 – .0106)
.50
(.0197)
BSC
6.0 – 6.2**
(.236 – .244)
7.9 – 8.3
(.311 – .327)
134
5678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
12.4 – 12.6*
(.488 – .496)
1.20
(.0473)
MAX
.05 – .15
(.002 – .006)
2
48 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 2547
C.10
-T-
-C-
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
*
**
24
LTC1850/LTC1851
18501i
LINEAR TECHNOLOGY CORPOR ATION 2001
LT/TP 1201 1.5K • PRINTED IN THE USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
U
TYPICAL APPLICATIO
BUSY
DIFF
OUT
/S6
A2
OUT
/S5
A1
OUT
/S4
A0
OUT
/S3
D11/S2
D10/S1
D9/S0
D8
D7
D6
D5
D4
D3
D2
D1
D0
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
M1
M0
SHDN
CS
CONVST
RD
WR
DIFF
A2
A1
A0
UNI/BIP
PGA
48
36
47
46
45
44
43
42
41
40
39
38
37
OUTPUT
DRIVERS
DATA
LATCHES
OGND 34
1851 TA01
OV
DD
35
COMP
S/H AMP
12-BIT
CAPACITIVE
DAC
REF AMP
GND GND
1.6384X
REFCOMP
13 16
REFIN
REFOUT
12
11
10
2.5V
4.096V
COM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
14
V
DD
9
8
7
6
5
4
3
2
1
SUCCESSIVE APPROXIMATION REGISTER
8-CHANNEL
MULTIPLEXER
INPUT CONFIGURATION:
ALL 8 CHANNELS
SINGLE ENDED TO COM
CH0–CH7: 0V TO 4.096V
15
0.1µF
V
DD
5V 5V
2.5V
REFERENCE
INTERNAL
CLOCK
PGA
LTC1851
CONTROL LOGIC
AND
PROGRAMMABLE
SEQUENCER
10µF
1µF
0.1µF10µF
0.1µF
10µF
3V TO 5V
5V
5V
CONVERT
CLOCK
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