© Semiconductor Components Industries, LLC, 2011
March, 2011 − Rev. 7
1Publication Order Number:
MC34060A/D
MC34060A, MC33060A
Fixed Frequency, PWM,
Voltage Mode Single Ended
Controllers
The MC34060A is a low cost fixed frequency, pulse width
modulation control circuit designed primarily for single−ended
SWITCHMODEt power supply control.
The MC34060A is specified over the commercial operating
temperature range of 0° to +70°C, and the MC33060A is specified
over an automotive temperature range of −40° to +85°C.
Features
•Complete Pulse Width Modulation Control Circuitry
•On−Chip Oscillator with Master or Slave Operation
•On−Chip Error Amplifiers
•On−Chip 5.0 V Reference, 1.5% Accuracy
•Adjustable Dead−Time Control
•Uncommitted Output Transistor Rated to 200 mA Source or Sink
•Undervoltage Lockout
•These are Pb−Free and Halide−Free Devices
PIN CONNECTIONS
(Top View)
Error
Amp
Error
Amp
12
+
-
+
-
VCC
5.0 V
ref
0.1V
Oscillator
Q1
Noninv
Input
Inv
Input
Compen/PWM
Comp Input
Dead-Time
Control
CT
RT
Ground
Noninv
Input
Inv
Input
Vref
N.C.
VCC
C
E
1
2
3
4
5
6
78
9
10
11
12
13
14
MARKING
DIAGRAMS
PDIP−14
P SUFFIX
CASE 646
SOIC−14
D SUFFIX
CASE 751A
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
ORDERING INFORMATION
x = 3 or 4
A = Assembly Location
WL = Wafer Lot
Y, YY = Year
WW = Work Week
G = Pb−Free Package
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14
1
MC3x060ADG
AWLYWW
1
14
14
1
MC3x060AP
AWLYYWWG
1
14
MC34060A, MC33060A
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2
MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted.)
Rating Symbol Value Unit
Power Supply Voltage VCC 42 V
Collector Output Voltage VC42 V
Collector Output Current (Note 3) IC500 mA
Amplifier Input Voltage Range Vin −0.3 to +42 V
Power Dissipation @ TA ≤ 45°C PD1000 mW
Operating Junction Temperature TJ125 °C
Storage Temperature Range Tstg −55 to +125 °C
Operating Ambient Temperature Range
For MC34060A
For MC33060A
TA
0 to +70
−40 to +85
°C
ESD Capability
Machine Model
Human Body Model
200
2.0
V
kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1– 14: Human Body Model 2000 V per JEDEC Standard JESD22−A114E.
Pins 1– 8: Machine Model Method 200 V per JEDEC Standard JESD22−A115−A.
2. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78.
THERMAL CHARACTERISTICS
Characteristics Symbol
P Suffix
Package
D Suffix
Package Unit
Thermal Resistance, Junction−to−Ambient RqJA 80 120 °C/W
Derating Ambient Temperature TA45 45 °C
RECOMMENDED OPERATING CONDITIONS
Condition/Value Symbol Min Typ Max Unit
Power Supply Voltage VCC 7.0 15 40 V
Collector Output Voltage VC−30 40 V
Collector Output Current IC− − 200 mA
Amplifier Input Voltage Vin −0.3 −VCC −2 V
Current Into Feedback Terminal Ifb − − 0.3 mA
Reference Output Current Iref − − 10 mA
Timing Resistor RT1.8 47 500 kW
Timing Capacitor CT0.00047 0.001 10 mF
Oscillator Frequency fosc 1.0 25 200 kHz
PWM Input Voltage (Pins 3 and 4) − −0.3 −5.3 V
3. Maximum thermal limits must be observed.
MC34060A, MC33060A
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ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted. For typical values TA = 25°C,
for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
REFERENCE SECTION
Reference Voltage (IO = 1.0 mA, TA 25°C)
TA = Tlow to Thigh − MC34060A
TA = Tlow to Thigh − MC33060A
Vref 4.925
4.9
4.85
5.0
−
−
5.075
5.1
5.1
V
Line Regulation (VCC = 7.0 V to 40 V, IO = 10 mA) Regline −2.0 25 mV
Load Regulation (IO = 1.0 mA to 10 mA) Regload −2.0 15 mV
Short Circuit Output Current (Vref = 0 V) ISC 15 35 75 mA
OUTPUT SECTION
Collector Off−State Current (VCC = 40 V, VCE = 40 V) IC(off) −2.0 100 mA
Emitter Off−State Current (VCC = 40 V, VCE = 40 V, VE = 0 V) IE(off)− − −100 mA
Collector−Emitter Saturation Voltage (Note 4)
Common−Emitter
(VE = 0 V, IC = 200 mA)
Emitter−Follower
(VC = 15 V, IE = −200 mA)
Vsat(C)
Vsat(E)
−
−
1.1
1.5
1.5
2.5
V
Output Voltage Rise Time (TA = 25°C)
Common−Emitter (See Figure 12)
Emitter−Follower (See Figure 13)
tr
−
−
100
100
200
200
ns
Output Voltage Fall Time (TA = 25°C)
Common−Emitter (See Figure 12)
Emitter−Follower (See Figure 13)
tr
−
−
40
40
100
100
ns
ERROR AMPLIFIER SECTION
Input Offset Voltage (VO[Pin 3] = 2.5 V) VIO −2.0 10 mV
Input Offset Current (VC[Pin 3] = 2.5 V) IIO −5.0 250 nA
Input Bias Current (VO[Pin 3] = 2.5 V) IIB − −0.1 −2.0 mA
Input Common Mode Voltage Range
(VCC = 40 V)
VICR 0 to
VCC −2.0
− − V
Inverting Input Voltage Range VIR(INV) −0.3 to
VCC−2.0
− − V
Open−Loop Voltage Gain
(DVO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 kW)
AVOL 70 95 −dB
Unity−Gain Crossover Frequency
(VO = 0.5 V to 3.5 V, RL = 2.0 kW)
fc−600 −kHz
Phase Margin at Unity−Gain
(VO = 0.5 V to 3.5 V, RL = 2.0 kW)
φm−65 −deg.
Common Mode Rejection Ratio
(VCC = 40 V, Vin = 0 V to 38 V))
CMRR 65 90 −dB
Power Supply Rejection Ratio
(DVCC = 33 V, VO = 2.5 V, RL = 2.0 kW)
PSRR −100 −dB
Output Sink Current (VO[Pin 3] = 0.7 V) IO−0.3 0.7 −mA
Output Source Current (VO[Pin 3] = 3.5 V) IO+−2.0 −4.0 −mA
4. Low duty cycle techniques are used during test to maintain junction temperature as close to ambient temperatures as possible.
Tlow = −40°C for MC33060A Thigh = +85°C for MC33060A
= 0°C for MC34060A = +70°C for MC34060A
MC34060A, MC33060A
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4
ELECTRICAL CHARACTERISTICS (continued) (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted.
For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
PWM COMPARATOR SECTION (Test circuit Figure 11)
Input Threshold Voltage
(Zero Duty Cycle)
VTH −3.5 4.5 V
Input Sink Current
(V[Pin 3] = 0.7 V)
II0.3 0.7 −mA
DEAD−TIME CONTROL SECTION (Test circuit Figure 11)
Input Bias Current (Pin 4)
(Vin = 0 V to 5.25 V)
IIB(DT) − −1.0 −10 mA
Maximum Output Duty Cycle
(Vin = 0 V, CT = 0.01 mF, RT = 12 kW)
(Vin = 0 V, CT = 0.001 mF, RT = 47 kW)
DCmax
90
−
96
92
100
−
%
Input Threshold Voltage (Pin 4)
(Zero Duty Cycle)
(Maximum Duty Cycle)
VTH
−
0
2.8
−
3.3
−
V
OSCILLATOR SECTION
Frequency
(CT = 0.01 mF, RT = 12 kW, TA = 25°C)
TA = Tlow to Thigh − MC34060A
TA = Tlow to Thigh − MC33060A
(CT = 0.001 mF, RT = 47 kW)
fosc
9.7
9.5
9.0
−
10.5
−
−
25
11.3
11.5
11.5
−
kHz
Standard Deviation of Frequency*
(CT = 0.001 mF, RT = 47 kW)
σfosc −1.5 −%
Frequency Change with Voltage
(VCC = 7.0 V to 40 V)
Dfosc(DV) −0.5 2.0 %
Frequency Change with Temperature
(DTA =Tlow to Thigh)
(CT = 0.01 mF, RT = 12 kW)
Dfosc(DT)
−
−
4.0
−
−
−
%
UNDERVOLTAGE LOCKOUT SECTION
Turn−On Threshold (VCC increasing, Iref = 1.0 mA) Vth 4.0 4.7 5.5 V
Hysteresis VH50 150 300 mV
TOTAL DEVICE
Standby Supply Current
(Pin 6 at Vref, all other inputs and outputs open)
(VCC = 15 V)
(VCC = 40 V)
ICC
−
−
5.5
7.0
10
15
mA
Average Supply Current
(V[Pin 4] = 2.0 V, CT = 0.001 mF, RT = 47 kW). See Figure 11.
IS−7.0 −mA
*Standard deviation is a measure of the statistical distribution about the mean as derived from the formula; σ =
N
Σ (xn −x)2
n − 1
N−1
MC34060A, MC33060A
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Figure 1. Block Diagram
+
6
5
4
RTCT
Dead-Time
Control
Oscillator
0.12V
0.7V
≈ 0.7mA
1
12 3
2
Dead-Time
Comparator
PWM.
Comparator
13 14
Reference
Regulator
7 GND
10
12
9
8
Q1
Ref Out
VCC
Error Amp
1
Feedback/PWM
Comparator Input
Error Amp
2
+
++
-
-
--
Emitter
Collector
+
-
VTH
Undervoltage
Lockout
This device contains 46 active transistors.
Description
The MC34060A is a fixed−frequency pulse width
modulation control circuit, incorporating the primary
building blocks required for the control of a switching power
supply (see Figure 1). An internal−linear sawtooth oscillator
is frequency−programmable by two external components,
RT and CT. The approximate oscillator frequency is
determined by:
fosc ^1.2
RT • CT
For more information refer to Figure 3.
Output pulse width modulation is accomplished by
comparison of the positive sawtooth waveform across
capacitor CT to either of two control signals. The output is
enabled only during that portion of time when the sawtooth
voltage is greater than the control signals. Therefore, an
increase in control−signal amplitude causes a corresponding
linear decrease of output pulse width. (Refer to the Timing
Diagram shown in Figure 2.)
Figure 2. Timing Diagram
Capacitor CT
Feedback/P.W.M.
Comparator
Dead-Time Control
Output Q1,
Emitter
MC34060A, MC33060A
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APPLICATIONS INFORMATION
The control signals are external inputs that can be fed into
the dead−time control, the error amplifier inputs, or the
feed−back input. The dead−time control comparator has an
effective 120 mV input offset which limits the minimum
output dead time to approximately the first 4% of the
sawtooth−cycle time. This would result in a maximum duty
cycle of 96%. Additional dead time may be imposed on the
output by setting the dead time−control input to a fixed
voltage, ranging between 0 V to 3.3 V.
The pulse width modulator comparator provides a means
for the error amplifiers to adjust the output pulse width from
the maximum percent on−time, established by the dead time
control input, down to zero, as the voltage at the feedback
pin varies from 0.5 V to 3.5 V. Both error amplifiers have a
common mode input range from −0.3 V to (VCC −2.0 V), and
may be used to sense power supply output voltage and
current. The error−amplifier outputs are active high and are
ORed together at the noninverting input of the pulse−width
modulator comparator. With this configuration, the
amplifier that demands minimum output on time, dominates
control of the loop.
The MC34060A has an internal 5.0 V reference capable
of sourcing up to 10 mA of load currents for external bias
circuits. The reference has an internal accuracy of ±5% with
a typical thermal drift of less than 50 mV over an operating
temperature range of 0° to +70°C.
Figure 3. Oscillator Frequency
versus Timing Resistance
Figure 4. Open Loop Voltage Gain and Phase
versus Frequency
Figure 5. Percent Deadtime versus
Oscillator Frequency
Figure 6. Percent Duty Cycle versus
Dead−Time Control Voltage
f, FREQUENCY (Hz)
, OPEN LOOP VOLTAGE GAIN (dB)
VOL
AVOL
q
1.0 10 100 1.0 k 10 k 100 k 1.0 M
θ, EXCESS PHASE (DEGREES)
A
VCC = 15 V
DVO = 3.0
V
RL = 2.0 kW
DEAD-TIME CONTROL VOLTAGE (V)
PERCENT DUTY CYCLE (%)
0 1.0 2.0 3.0 3.5
VCC = 15 V
CT = 0.001
RT = 47 k
VCC = 15 V
RT
, TIMING RESISTANCE (W)
, OSCILLATOR FREQUENCY (Hz)
osc
1.0 k 2.0 k 5.0 k 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
f
1.0 mF
0.001 mF
CT = 0.01 mF
fosc, OSCILLATOR FREQUENCY (Hz)
% DT, PERCENT DEAD‐TIME, Q1 OUTPUT
500 10 k 100 k 500 k
CT = 0.001 mF
0.01 mF
1.0 k
100
90
80
70
60
50
40
30
20
10
0
100
80
60
40
20
0
500 k
100 k
10 k
1.0 k
500
20
18
16
14
12
10
8.0
6.0
4.0
2.0
0
110
120
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
MC34060A, MC33060A
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7
Figure 7. Emitter−Follower Configuration
Output Saturation Voltage versus
Emitter Current
Figure 8. Common−Emitter Configuration
Output Saturation Voltage versus
Collector Current
IE, EMITTER CURRENT (mA)
, SATURATION VOLTAGE (V)
CE(SAT)
0 100 200 300 400 500
V
, SATURATION VOLTAGE (V)
CE(SAT)
V
IC, COLLECTOR CURRENT (mA)
0 100 200 300 400 500
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
Figure 9. Standby Supply Current
versus Supply Voltage
Figure 10. Undervoltage Lockout Thresholds
versus Reference Load Current
0 5.0 10 15 20 25 30 35 40
VCC, SUPPLY VOLTAGE (V)
, SUPPLY CURRENT (mA)
CC
I
0 5.0 10 15 20 25 30 35 40
, UNDERVOLTAGE LOCKOUT THRESHOLD (V)
TH
IL, REFERENCE LOAD CURRENT (mA)
V
Turn On
Turn Off
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
6.0
5.5
5.0
4.5
4.0
9.0
10
MC34060A, MC33060A
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8
Figure 11. Error Amplifier Characteristics Figure 12. Deadtime and Feedback Control
Figure 13. Common−Emitter Configuration
and Waveform
+
-
+
-
Vin
Vref
Error Amplifier
Under Test
Feedback
Terminal
(Pin 3)
Other Error
Amplifier
Test
Inputs
VCC = 15V
150W
2W
Output
50kW
Dead-
Time
VCC
RT
CT
(+)
(-)
(+)
(-)
Error
C
E
Gnd
Ref
Out
Feedback
Output
Transistor
C
E
15V
RL
68W
VC
CL
15pF
90% 90%
VC
10% 10%
trtf
90% 90%
VE
10% 10%
trtf
Output
Transistor
C
E
15V
RL
68W
CL
15pF
VE
Figure 14. Emitter−Follower Configuration
and Waveform
MC34060A, MC33060A
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9
Figure 15. Error Amplifier Sensing Techniques
Figure 16. Deadtime Control Circuit Figure 17. Soft−Start Circuit
Figure 18. Slaving Two or More Control Circuits
+
-
+
-
VOTo Output
Voltage of
System
R1
1
2
R2
Vref
3
Error
Amp
Positive Output Voltage
VO = Vref (1 + R1
Negative Output Voltage
3
Error
Amp
1
2
Vref
R2
R1
To Output
Voltage of
System
VO
) VO = -Vref (1 + R1)
Output Q
Vref
DT
RTCT
65
47k 0.001
4
R1
R2
Max % On Time ≈ 92 -
160
1 + R1
+
-
Output Q DT
Vref
4
R1CS
R2
RTCT
6
5
RT
CT
Vref
Master
Vref
6
5
RT
CT
(Additional
Circuits)
Slave
R2R2
R2
MC34060A, MC33060A
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10
Vin = 8.0V to 40V
50/50
+
0.01
47k
1.0M
0.01
4.7k 4.7k
150 390
4.7k
+
10/16V 4
4.7k
1
2
3
14
13
12
56
0.001
47k
7
8
9
10
47
75
Tip 32
150mH @ 2.0A
MR850
0.1
Vout
5.0V/1.0A
+
1000
6.3V
VCC
+
-
Comp
+
-
Vref
DTCTRT
C
E
GND
MC34060A
Test Conditions Results
Line Regulation Vin = 8.0 V to 40 V, IO = 1.0 A 25 mV 0.5%
Load Regulation Vin = 12 V, IO = 1.0 mA to 1.0 A 3.0 mV 0.06%
Output Ripple Vin = 12 V, IO = 1.0 A 75 mV p−p P.A.R.D.
Short Circuit Current Vin = 12 V, RL = 0.1 W1.6 A
Efficiency Vin = 12 V, IO = 1.0 A 73%
Figure 19. Step−Down Converter with Soft−Start
and Output Current Limiting
MC34060A, MC33060A
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11
Vin = 8.0V to 26V
50/35V
390
4
1
2
3
14
13
12
56
0.001
150mH @ 4.0A
Vout
+
-
Comp
+
-
Vref
DTCTRT
C
E
GND
MC34060A
47k
22k
0.05
33k
2.7M
3.9k
4.7k
7
8
9
10
20mH @ 1.0A
MR850 *
28V/
0.5A
300
0.1
470
Tip 111
+
470/
35V
470/
35V
*
++
4.7k
VCC
Test Conditions Results
Line Regulation Vin = 8.0 V to 26 V, IO = 0.5 A 40 mV 0.14%
Load Regulation Vin = 12 V, IO = 1.0 mA to 0.5 A 5.0 mV 0.18%
Output Ripple Vin = 12 V, IO = 0.5 A 24 mV p−p P.A.R.D.
Efficiency Vin = 12 V, IO = 0.5 A 75%
*Optional circuit to minimize output ripple
Figure 20. Step−Up Converter
MC34060A, MC33060A
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12
Vin = 8.0V to 40V
50/50V
+
0.01
47k
1.0M
0.01
10k
47k
820
4.7k
10/16V 4
1
2
3
14
13
12
56
47k
7
8
9
10
47
75
Tip 32C
1.0
Vout
VCC
+
-
Comp
+
-
Vref
DTCTRT
C
E
GND
30k
MR851
20mH *
@ 1.0A -15V/
0.25A
3.3k
150mH
@ 2.0A +
+
*
330/
16V
0.001
7.5k
MC34060A 330/
16V
Test Conditions Results
Line Regulation Vin = 8.0 V to 40 V, IO = 250 mA 52 mV 0.35%
Load Regulation Vin = 12 V, IO = 1.0 to 250 mA 47 mV 0.32%
Output Ripple Vin = 12 V, IO = 250 mA 10 mV p−p P.A.R.D.
Short Circuit Current Vin = 12 V, RL = 0.1 W330 mA
Efficiency Vin = 12 V, IO = 250 mA 86%
*Optional circuit to minimize output ripple
Figure 21. Step−Up/Down Voltage Inverting Converter
with Soft−Start and Current Limiting
MC34060A, MC33060A
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Figure 22. 33 W Off−Line Flyback Converter with Soft−Start and Primary Power Limiting
3 each
0.0047 UL/CSA
1N4003
1N4001
3/200
Vac
T1
*
*
*
*
*Optional R.F.I. Filter
T
1.0A
115 Vac
20%±
15
Cold
Ω
1N4742
+
180/200V
22k
7.5k
2.2M 33k
0.01
1N4687 6.8k
8.2k
1.5k 10
+
27k 11k
1N4148 2.7k
47k
0.001
V
5.0k
out P
25k
out
0.01
1
2
3
14
13
12
456
7
8
9
10
200 47
1.0
MPS
A55
+
MPS
A05
10/25V MJE
13005
47/25V
1N4934
+
1N4937 1N4934
1000/25V
1000/25V
1N4934
1N5824
2200/10V
+
+
+
+
+
+
L1
L2
L3
100/10V
10/35V
10/35V
5.0V/3.0A
12/075A
Common
-12/0.75A
T2
Test Conditions Results
Line Regulation 5.0 V
Line Regulation
Load Regulation 5.0 V
Load Regulation
Output Ripple 5.0 V
Output Ripple
Efficiency
12 V
12 V
12 V
±
±
±
Vin = 95 Vac to 135 Vac, IO= 3.0 A
Vin = 95 Vac to 135 Vac, IO=±0.75 A
Vin = 115 Vac, IO= 1.0 A to 4.0 A
Vin = 115 Vac, IO=±0.4 A to ±0.9 A
Vin = 115 Vac, IO= 3.0 A
Vin = 115 Vac, IO=±0.75 A
Vin = 115 Vac, IO5.0 V = 3.0 A
IO±12 V = ±0.75 A
20 mV 0.40%
52 mV 0.26%
476 mV 9.5%
300 mV 2.5%
45 mV p−p P.A.R.D.
75 mV p−p P.A.R.D.
74%
T1 − Coilcraft W2961
T2 − Core: Coilcraft 11−464−16,
0.025 gap in each leg.″
Bobbin: Coilcraft 37−573
Windings:
Primary, 2 each, 75 turns #25 Awg Bifilar wound
Feedback: 15 turns #26 Awg
Secondary, 5.0 V, 6 turns @33 Awg Bifilar wound
Secondary, 2 each, 14 turns #24 Awg Bifilar wound
L1 − Coilcraft Z7156, 15 H @ 5.0 Aμ
L2, L3 − Coilcraft Z7157, 25 H @ 1.0 Aμ
C
E
GND
+
-
Comp
+
-
Vref
DTCTRT
MC34060A
VCC
MC34060A, MC33060A
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14
ORDERING INFORMATION
Device
Operating
Temperature Range Package Shipping†
MC34060ADG
TA= 0° to +70°C
SOIC−14
(Pb−Free) 55 Units / Rail
MC34060ADR2G SOIC−14
(Pb−Free) 2500 / Tape & Reel
MC34060APG PDIP−14
(Pb−Free) 25 Units / Rail
MC33060ADG
TA= −40° to +85°C
SOIC−14
(Pb−Free) 55 Units / Rail
MC33060ADR2G SOIC−14
(Pb−Free) 2500 / Tape & Reel
MC33060APG PDIP−14
(Pb−Free) 25 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC34060A, MC33060A
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15
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
7X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC34060A, MC33060A
http://onsemi.com
16
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 19.56
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M−−− 10 −−− 10
N0.015 0.039 0.38 1.01
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG D
K
C
SEATING
PLANE
N
−T−
14 PL
M
0.13 (0.005)
L
M
J
0.290 0.310 7.37 7.87
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