MC33174DG - ON Semiconductor

August, 2012 − Rev. 12

1Publication Order Number:

MC33171/D

MC33171, 2, 4,

NCV33172, 4

Single Supply 3.0 V to 44 V,

Low Power Operational

Amplifiers

Quality bipolar fabrication with innovative design concepts are

employed for the MC33171/72/74, NCV33172/74 series of

monolithic operational amplifiers. These devices operate at 180 mA

per amplifier and offer 1.8 MHz of gain bandwidth product and 2.1

V/ms slew rate without the use of JFET device technology. Although

this series can be operated from split supplies, it is particularly suited

for single supply operation, since the common mode input voltage

includes ground potential (VEE). With a Darlington input stage, these

devices exhibit high input resistance, low input offset voltage and high

gain. The all NPN output stage, characterized by no deadband

crossover distortion and large output voltage swing, provides high

capacitance drive capability, excellent phase and gain margins, low

open loop high frequency output impedance and symmetrical

source/sink AC frequency response.

The MC33171/72/74, NCV33172/74 are specified over the

industrial/automotive temperature ranges. The complete series of

single, dual and quad operational amplifiers are available in plastic as

well as the surface mount packages.

Features

•Low Supply Current: 180 mA (Per Amplifier)

•Wide Supply Operating Range: 3.0 V to 44 V or ±1.5 V to ±22 V

•Wide Input Common Mode Range, Including Ground (VEE)

•Wide Bandwidth: 1.8 MHz

•High Slew Rate: 2.1 V/ms

•Low Input Offset Voltage: 2.0 mV

•Large Output Voltage Swing: −14.2 V to +14.2 V

(with ±15 V Supplies)

•Large Capacitance Drive Capability: 0 pF to 500 pF

•Low Total Harmonic Distortion: 0.03%

•Excellent Phase Margin: 60°

•Excellent Gain Margin: 15 dB

•Output Short Circuit Protection

•ESD Diodes Provide Input Protection for Dual and Quad

•NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

PDIP−8

P SUFFIX

CASE 626

SO−8

D, VD SUFFIX

CASE 751

PDIP−14

P, VP SUFFIX

CASE 646

SO−14

D, VD SUFFIX

CASE 751A

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

TSSOP−14

DTB SUFFIX

CASE 948G

See general marking information in the device marking

section on page 10 of this data sheet.

DEVICE MARKING INFORMATION

http://onsemi.com

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

SINGLE

(Single, Top View)

(Top View)

Offset Null 1

Noninv. Input

VEE

VCC

Output

Offset Null

Inv. Input

VEE

Inputs 1

Inputs 2

Output 2

Output 1 VCC

QUAD

Inputs 1

Output 1

VCC

Inputs 2

Output 2

Output 4

Inputs 4

VEE

Inputs 3

Output 3

(Top View)

PIN CONNECTIONS

DUAL

Q3 Q4 Q5 Q6 Q7

VCC

R1 C1 R2

Q9 Q10

Inputs

Q11

Q17

R6 R7

Q18

C2 D3

Output

Q19

Q16Q15

Q14

Q13

Q12

R3 R4

Current

Limit

VEE/GND

Offset Null

(MC33171)

Bias

Figure 1. Representative Schematic Diagram

(Each Amplifier)

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Voltage VCC/VEE ±22 V

Input Differential Voltage Range VIDR (Note 1) V

Input Voltage Range VIR (Note 1) V

Output Short Circuit Duration (Note 2) tSC Indefinite sec

Operating Ambient Temperature Range TA(Note 3) °C

Operating Junction Temperature TJ+150 °C

Storage Temperature Range Tstg −65 to +150 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL connected to ground, TA = +25°C, unless otherwise noted.)

Characteristics Symbol Min Typ Max Unit

Input Offset Voltage (VCM = 0 V)

VCC = +15 V, VEE = −15 V, TA = +25°C

VCC = +5.0 V, VEE = 0 V, TA = +25°C

VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh (Note 3)

VIO

−

2.0

2.5

−

4.5

5.0

6.5

Average Temperature Coefficient of Offset Voltage DVIO/DT−10 −mV/°C

Input Bias Current (VCM = 0 V)

TA = +25°C

TA = Tlow to Thigh (Note 3)

IIB

−

100

200

Input Offset Current (VCM = 0 V)

TA = +25°C

TA = Tlow to Thigh (Note 3)

IIO

−

5.0

−

Large Signal Voltage Gain (VO = ±10 V, RL = 10 k)

TA = +25°C

TA = Tlow to Thigh (Note 3)

AVOL

500

−

V/mV

Output Voltage Swing

VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C

VCC = +15 V, VEE = −15 V, RL = 10 k, TA = +25°C

VCC = +15 V, VEE = −15 V, RL = 10 k, TA = Tlow to Thigh (Note 3)

VOH

3.5

13.6

13.3

4.3

14.2

−

VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C

VCC = +15 V, VEE = −15 V, RL = 10 k, TA = +25°C

VCC = +15 V, VEE = −15 V, RL = 10 k, TA = Tlow to Thigh (Note 3)

VOL −

−

0.05

−14.2

−

0.15

−13.6

−13.3

Output Short Circuit (TA = +25°C)

Input Overdrive = 1.0 V, Output to Ground

Source

Sink

ISC

3.0

5.0

−

Input Common Mode Voltage Range

TA = +25°C

TA = Tlow to Thigh (Note 3)

VICR

VEE to (VCC −1.8)

VEE to (VCC −2.2)

Common Mode Rejection Ratio (RS ≤ 10 k), TA = +25°C CMRR 80 90 −dB

Power Supply Rejection Ratio (RS = 100 W), TA = +25°CPSRR 80 100 −dB

Power Supply Current (Per Amplifier)

VCC = +5.0 V, VEE = 0 V, TA = +25°C

VCC = +15 V, VEE = −15 V, TA = +25°C

VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh (Note 3)

−

180

220

−

250

300

1. Either or both input voltages must not exceed the magnitude of VCC or VEE.

2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.

3. MC3317x Tlow = −40°CT

high = +85°C

MC3317xV, NCV3317x Tlow = −40°CT

high = +125°C

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL connected to ground, TA = +25°C, unless otherwise noted.)

Characteristics Symbol Min Typ Max Unit

Slew Rate (Vin = −10 V to +10 V, RL = 10 k, CL = 100 pF)

AV +1

AV −1

1.6

−

2.1

−

V/ms

Gain Bandwidth Product (f = 100 kHz) GBW 1.4 1.8 −MHz

Power Bandwidth

AV = +1.0 RL = 10 k, VO = 20 Vpp, THD = 5%

BWp

−35 −

kHz

Phase Margin

RL = 10 k

RL = 10 k, CL = 100 pF

−

Deg

Gain Margin

RL = 10 k

RL = 10 k, CL = 100 pF

−

5.0

−

Equivalent Input Noise Voltage

RS = 100 W, f = 1.0 kHz

en−32 −nV

√

Equivalent Input Noise Current (f = 1.0 kHz) In−0.2 −pA/ Hz√

Differential Input Resistance

Vcm = 0 V

Rin

−300 −

Input Capacitance Cin −0.8 −pF

Total Harmonic Distortion

AV = +10, RL = 10 k, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz

THD

−0.03 −

Channel Separation (f = 10 kHz) CS −120 −dB

Open Loop Output Impedance (f = 1.0 MHz) zo−100 −W

Figure 2. Input Common Mode Voltage Range

versus Temperature

Figure 3. Split Supply Output Saturation

versus Load Current

V , INPUT

N M

DE V

LTA

E RAN

E (V)

ICR

TA, AMBIENT TEMPERATURE (°C)

VCC

VCC/VEE = ±1.5 V to ±22 V

DVIO = 5.0 mV

V, OUTPUT SATURATION VOLTAGE (V)

sat

IL, LOAD CURRENT (±mA)

Source

Sink

VEE

VCC

VEE

VCC/VEE = ±5.0 V to ±22 V

TA = 25°C

-2.4

0.1

-0.8

-1.6

-1.0

1.0

-55 -25 0 25 50 75 100 125 0 1.0 2.0 3.0 4.0

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

1. TA = -55°C

2. TA = 25°C

3. TA = 125°C

Dual

Quad

Single

VCC/VEE = ±15 V

AV = +1.0

RL = 10 k

CL = 100 pF

TA = 25°C

AV = 1000

AV = 100

AV = 10 AV = 1.0

Figure 4. Open Loop Voltage Gain and

Phase versus Frequency

Figure 5. Phase Margin and Percent

Overshoot versus Load Capacitance

Figure 6. Normalized Gain Bandwidth Product

and Slew Rate versus Temperature

Figure 7. Small and Large Signal

Transient Response

Figure 8. Output Impedance and Frequency Figure 9. Supply Current versus Supply Voltage

5.0 ms/DIV

50 mV/DIV10 V/DIV

5.0 ms/DIV

f, FREQUENCY (Hz)

, EXCESS PAHSE (DEGREES)

120

140

160

180

200

220

, OPEN LOOP VOLTAGE GAIN (dB)

VOL

Gain

Margin

= 15 dB

Phase

Margin

= 58°

VCC/VEE = ±15 V

RL = 10 k

Vout = 0 V

TA = 25°C

1 - Phase

2 - Phase, CL = 100 pF

3 - Gain

4 - Gain, CL = 100 pF

m, PHASE MARGIN (DEGREES)

CL, LOAD CAPACITANCE (pF)

%, PERCENT OVERSHOOT

VCC/VEE = ±15 V

AVOL = +1.0

RL = 10 k

DVO = 20 mVpp

TA = 25°C

TA, AMBIENT TEMPERATURE (°C)

GBW AND SR (NORMALIZED)

GBW

VCC/VEE = ±15 V

RL = 10 k

f, FREQUENCY (Hz)

z , OUTPUT IMPEDANCE ()Ω

VCC/VEE, SUPPLY VOLTAGE (±V)

I, I, POWER SUPPLY CURRENT (mA)

-10

-20

-30

1.3

1.2

1.1

1.0

0.9

0.8

0.7

140

120

100

1.1

0.9

0.7

0.5

0.3

0.1

100 k 1.0 M 10 M 10 20 50 100 200 500 1.0 k

-55 -25 0 25 50 75 100 125

200 2.0 k 20 k 200 k 2.0 M 0 5.0 10 15 20 25

VCC/VEE = ±15 V

VCM = 0 V

VO = 0 V

DIO = ±0.5 mA

TA = 25°C

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

APPLICATIONS INFORMATION − CIRCUIT DESCRIPTION/PERFORMANCE FEATURES

Although the bandwidth, slew rate, and settling time of the

MC33171/72/74 amplifier family is similar to low power op

amp products utilizing JFET input devices, these amplifiers

offer additional advantages as a result of the PNP transistor

differential inputs and an all NPN transistor output stage.

Because the input common mode voltage range of this

input stage includes the VEE potential, single supply

operation is feasible to as low as 3.0 V with the common

mode input voltage at ground potential.

The input stage also allows differential input voltages up

to ±44 V, provided the maximum input voltage range is not

exceeded. Specifically, the input voltages must range

between VCC and VEE supply voltages as shown by the

maximum rating table. In practice, although not

recommended, the input voltages can exceed the VCC

voltage by approximately 3.0 V and decrease below the VEE

voltage by 0.3 V without causing product damage, although

output phase reversal may occur. It is also possible to source

up to 5.0 mA of current from VEE through either inputs’

clamping diode without damage or latching, but phase

reversal may again occur. If at least one input is within the

common mode input voltage range and the other input is

within the maximum input voltage range, no phase reversal

will occur. If both inputs exceed the upper common mode

input voltage limit, the output will be forced to its lowest

voltage state.

Since the input capacitance associated with the small

geometry input device is substantially lower (0.8 pF) than

that of a typical JFET (3.0 pF), the frequency response for

a given input source resistance is greatly enhanced. This

becomes evident in D−to−A current to voltage conversion

applications where the feedback resistance can form a pole

with the input capacitance of the op amp. This input pole

creates a 2nd Order system with the single pole op amp and

is therefore detrimental to its settling time. In this context,

lower input capacitance is desirable especially for higher

values of feedback resistances (lower current DACs). This

input pole can be compensated for by creating a feedback

zero with a capacitance across the feedback resistance, if

necessary, to reduce overshoot. For 10 kW of feedback

resistance, the MC33171/72/74 family can typically settle to

within 1/2 LSB of 8 bits in 4.2 ms, and within 1/2 LSB of 12

bits in 4.8 ms for a 10 V step. In a standard inverting unity

gain fast settling configuration, the symmetrical slew rate is

typically ±2.1 V/ms. In the classic noninverting unity gain

configuration the typical output positive slew rate is also

2.1 V/ms, and the corresponding negative slew rate will

usually exceed the positive slew rate as a function of the fall

time of the input waveform.

The all NPN output stage, shown in its basic form on the

equivalent circuit schematic, offers unique advantages over

the more conventional NPN/PNP transistor Class AB output

stage. A 10 kW load resistance can typically swing within

0.8 V of the positive rail (VCC) and negative rail (VEE),

providing a 28.4 Vpp swing from ±15 V supplies. This large

output swing becomes most noticeable at lower supply

voltages.

The positive swing is limited by the saturation voltage of

the current source transistor Q7, the VBE of the NPN pull−up

transistor Q17, and the voltage drop associated with the

short circuit resistance, R5. For sink currents less than

0.4 mA, the negative swing is limited by the saturation

voltage of the pull−down transistor Q15, and the voltage

drop across R4 and R5. For small valued sink currents, the

above voltage drops are negligible, allowing the negative

swing voltage to approach within millivolts of VEE. For sink

currents (> 0.4 mA), diode D3 clamps the voltage across R4.

Thus the negative swing is limited by the saturation voltage

of Q15, plus the forward diode drop of D3 (≈VEE +1.0 V).

Therefore an unprecedented peak−to−peak output voltage

swing is possible for a given supply voltage as indicated by

the output swing specifications.

If the load resistance is referenced to VCC instead of

ground for single supply applications, the maximum

possible output swing can be achieved for a given supply

voltage. For light load currents, the load resistance will pull

the output to VCC during the positive swing and the output

will pull the load resistance near ground during the negative

swing. The load resistance value should be much less than

that of the feedback resistance to maximize pull−up

capability.

Because the PNP output emitter−follower transistor has

been eliminated, the MC33171/72/74 family offers a 15 mA

minimum current sink capability, typically to an output

voltage of (VEE +1.8 V). In single supply applications the

output can directly source or sink base current from a

common emitter NPN transistor for current switching

applications.

In addition, the all NPN transistor output stage is

inherently faster than PNP types, contributing to the bipolar

amplifier’s improved gain bandwidth product. The

associated high frequency low output impedance (200 W typ

@ 1.0 MHz) allows capacitive drive capability from 0 pF to

400 pF without oscillation in the noninverting unity gain

configuration. The 60° phase margin and 15 dB gain margin,

as well as the general gain and phase characteristics, are

virtually independent of the source/sink output swing

conditions. This allows easier system phase compensation,

since output swing will not be a phase consideration. The AC

characteristics of the MC33171/72/74 family also allow

excellent active filter capability, especially for low voltage

single supply applications.

Although the single supply specification is defined at

5.0 V, these amplifiers are functional to at least 3.0 V @

25°C. However slight changes in parametrics such as

bandwidth, slew rate, and DC gain may occur.

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

If power to this integrated circuit is applied in reverse

polarity, or if the IC is installed backwards in a socket, large

unlimited current surges will occur through the device that

may result in device destruction.

As usual with most high frequency amplifiers, proper lead

dress, component placement and PC board layout should be

exercised for optimum frequency performance. For

example, long unshielded input or output leads may result in

unwanted input/output coupling. In order to preserve the

relatively low input capacitance associated with these

amplifiers, resistors connected to the inputs should be

immediately adjacent to the input pin to minimize additional

stray input capacitance. This not only minimizes the input

pole for optimum frequency response, but also minimizes

extraneous “pick up” at this node. Supply decoupling with

adequate capacitance immediately adjacent to the supply pin

is also important, particularly over temperature, since many

types of decoupling capacitors exhibit great impedance

changes over temperature.

The output of any one amplifier is current limited and thus

protected from a direct short to ground. However, under

such conditions, it is important not to allow the device to

exceed the maximum junction temperature rating. Typically

for ±15 V supplies, any one output can be shorted

continuously to ground without exceeding the maximum

temperature rating.

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

Figure 10. AC Coupled Noninverting Amplifier

with Single +5.0 V Supply

Figure 11. AC Coupled Inverting Amplifier

with Single +5.0 V Supply

Figure 12. DC Coupled Inverting Amplifier

Maximum Output Swing with Single

+5.0 V Supply

Figure 13. Offset Nulling Circuit

Figure 14. Active High−Q Notch Filter Figure 15. Active Bandpass Filter

2.2 k 510 k

VCC

100 k

Cin

Vin

1.0 k

3.6 Vpp

AV = 101

BW ( -3.0 dB) = 20 kHz

VO 0

100 k 100 k

VCC

100 k CO

10 k

Cin

Vin

AV = 10

BW ( -3.0 dB) = 200 kHz

10 k

100 k

100 k VCC

50 k

4.7 k +

100 k 1.0 M

Vin

4.2 Vpp

VO 2.5 V

AV = 10

BW ( -3.0 dB) = 200 kHz

VCC

410 k

VEE

Offset Nulling range is approximately ±80 mV with

a 10 k potentiometer, MC33171 only.

Vin

+VO

0.01

0.02 2R

32 k

fo = 1.0 kHz

fo = 1

4 p RC

Vin ≥ 0.2 Vdc

0.02

16 k16 k

Vin

1.1 k

5.6 k

2.2 k

0.047

0.4

VCC

fo = 30 kHz

Q = 10

HO = 1.0

R1 = R3

2 HO

R2 =

R3 = Q

p foC

R1 R3

4Q2R1 -R3

Qo fo

GBW < 0.1

Given fo = center frequency

Ao = Gain at center frequency

Choose Value fo, Q, Ao, C

For less than 10% error for operational amplifier, where fo and GBW are expressed in Hz.

0.047

100 kRL

VCC Then:

3.8 Vpp

VO 0

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

ORDERING INFORMATION

Op Amp

Function Device

Operating

Temperature Range Package Shipping†

Single

MC33171DG

TA = −40° to +85°C

SO−8

(Pb−Free) 98 Units/Rail

MC33171DR2G SO−8

(Pb−Free) 2500 / Tape & Reel

MC33171PG PDIP

(Pb−Free) 50 Units/Rail

Dual

MC33172DG

TA = −40° to +85°C

SO−8

(Pb−Free) 98 Units/Rail

MC33172DR2G SO−8

(Pb−Free) 2500 / Tape & Reel

MC33172PG PDIP

(Pb−Free) 50 Units/Rail

MC33172VDG

TA = −40° to +125°C

SO−8

(Pb−Free) 98 Units/Rail

MC33172VDR2G SO−8

(Pb−Free) 2500 / Tape & Reel

NCV33172DR2G* SO−8

(Pb−Free) 2500 / Tape & Reel

Quad

MC33174DG

TA = −40° to +85°C

SO−14

(Pb−Free) 55 Units/Rail

MC33174DR2G SO−14

(Pb−Free) 2500 / Tape & Reel

MC33174DTBG TSSOP−14

(Pb−Free) 96 Units/Rail

MC33174DTBR2G TSSOP−14

(Pb−Free) 2500 / Tape & Reel

MC33174PG PDIP

(Pb−Free) 25 Units/Rail

MC33174VDG

TA = −40° to +125°C

SO−14

(Pb−Free) 55 Units/Rail

MC33174VDR2G SO−14

(Pb−Free) 2500 / Tape & Reel

MC33174VPG PDIP

(Pb−Free) 25 Units/Rail

NCV33174DTBR2G* TSSOP−14

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NCV prefix for automotive and other applications requiring site and change controls.

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

MARKING DIAGRAMS

PDIP−8

P SUFFIX

CASE 626

x = 1 or 2

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or  = Pb−Free Package

SO−8

D SUFFIX

CASE 751

SO−8

MC33172VD

NCV33172D

CASE 751

PDIP−14

P SUFFIX

CASE 646

MC33174P

AWLYYWWG

PDIP−14

VP SUFFIX

CASE 646

SO−14

D SUFFIX

CASE 751A

MC33174DG

AWLYWW

SO−14

VD SUFFIX

CASE 751A

TSSOP−14

DTB SUFFIX

CASE 948G

MC3317xP

AWL

YYWWG

3317x

ALYW



MC33

174

ALYW 



3317V

ALYW



MC33174VP

AWLYYWWG

MC33174VDG

AWLYWW

(Note: Microdot may be in either location)

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

PACKAGE DIMENSIONS

8 LEAD PDIP

CASE 626−05

ISSUE M

NOTE 5

TOP VIEW

CSEATING

PLANE

0.010 CA

SIDE VIEW

END VIEW

NOTE 3

DIM MIN NOM MAX

INCHES

A−−−− −−−− 0.210

A1 0.015 −−−− −−−−

b0.014 0.018 0.022

C0.008 0.010 0.014

D0.355 0.365 0.400

D1 0.005 −−−− −−−−

e0.100 BSC

E0.300 0.310 0.325

L0.115 0.130 0.150

−−−− −−−− 5.33

0.38 −−−− −−−−

0.35 0.46 0.56

0.20 0.25 0.36

9.02 9.27 10.02

0.13 −−−− −−−−

2.54 BSC

7.62 7.87 8.26

2.92 3.30 3.81

MIN NOM MAX

MILLIMETERS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. DIMENSION E IS MEASURED WITH THE LEADS RE-

STRAINED PARALLEL AT WIDTH E2.

4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

E1 0.240 0.250 0.280 6.10 6.35 7.11

E3 −−−− −−−− 0.430 −−−− −−−− 10.92

0.300 BSC 7.62 BSC

e/2

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AK

SEATING

PLANE

X 45 

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS



1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

PACKAGE DIMENSIONS

PDIP−14

CASE 646−06

ISSUE P

14 8

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

M−−− 10 −−− 10

N0.015 0.039 0.38 1.01



NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

HG D

SEATING

PLANE

−T−

14 PL

0.13 (0.005)

0.290 0.310 7.37 7.87

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.127

(0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

−A−

−B−

P7 PL

14 8

0.25 (0.010) B M

0.25 (0.010) A S

−T−

RX 45

SEATING

PLANE D14 PL K

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

 

7.04

14X

0.58

14X

1.52

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC33171, 2, 4, NCV33172, 4

http://onsemi.com

PACKAGE DIMENSIONS

TSSOP−14

CASE 948G

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.



U0.15 (0.006) T

2X L/2

0.10 (0.004) V S

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

ÉÉÉ

DETAIL E

−W−

0.25 (0.010)

PIN 1

IDENT.

U0.15 (0.006) T

−V−

14X REFK

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

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