IEEE 488.2 Controller Chip
Description
The NAT9914 IEEE 488.2 controller chip can perform all the
interface functions defined by the IEEE Standard 488.1-1987,
and
also meets the additional requirements and recommendations
of the IEEE Standard 488.2-1987. Connected between the
processor and the IEEE 488 bus, the NAT9914 provides high-
level management of the IEEE 488 bus, significantly increases
the throughput of driver software, and simplifies both the
hardware and software design. The NAT9914 performs
complete IEEE 488 Talker, Listener, and Controller functions. In
addition to its numerous improvements, the NAT9914 is also
completely pin compatible with the TI TMS 9914A and
software compatible with the NEC µPD7210 and TI TMS9914A
controller chips.
IEEE 488.2 Overview
The IEEE 488.2 standard r emoves the ambiguities of IEEE 488.1
by standardizing the way instruments and contr ollers operate. It
defines data formats, status reporting, error handling, and
common configuration commands to which all IEEE 488.2
instruments must respond in a precise manner. It also defines a
set of controller requirements. With IEEE 488.2, you gain the
benefits of reduced development time and cost because systems
are more compatible and reliable. The NAT9914 brings the full
power of IEEE 488.2 to the design engineer along with
numerous other design and performance benefits, while
retaining the 40-pin and 44-pin hardware configurations of the
TI TMS 9914A.
General
The NAT9914 manages the IEEE 488 bus. You program the
IEEE 488 bus by writing control words into the appropriate
registers. CPU-readable status registers supply operational
feedback. The NAT9914 mode determines the function of
these registers. On power up or reset, the NAT9914 registers
resemble those of the TMS9914A set, with additional r egisters that
supply extra functionality and IEEE 488.2 compatibility. In this
mode, the NAT9914 is completely pin compatible with
the TI TMS9914A. If you enable the 7210 mode, the registers
resemble those of the NEC µPD7210 set, with additional r egisters
that supply extra functionality and IEEE 488.2 compatibility. This
mode is not pin compatible with the NECµPD7210. Figure 4
shows the key components of the NA T9914.
NAT9914
Pin compatible with TI TMS9914A
Software compatible with
NEC µPD7210 or TI TMS9914A
controller chips
Low power consumption
Meets all IEEE 488.2 requirements
Bus line monitoring
Preferred implementation of
requesting service
Will not send messages when there
are no Listeners
Performs all IEEE 488.1
interface functions
Programmable data transfer rate
(T1 delays of 350 ns, 500 ns,
1.1 µs, and 2 µs)
Automatic EOS and/or NL message
detection
Direct memory access (DMA)
Automatically processes IEEE 488
commands and reads
undefined commands
TTL-compatible CMOS device
Programmable clock rate
20 MHz maximum
Reduces driver overhead
Does not lose a data byte
if A TN is asserted while
transmitting data
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IEEE 488.2 Controller Chip
National Instruments
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2
Pin Identification
Pin Number
PLCC DIP QFP Mnemonic Type Description
11, 12, 13, 10, 11, 12, 16, 17, 18, D(7-0) I/O†Bidirectional 3-state data bus transfers
14, 15, 16, 13, 14, 15, 19, 20, 21, commands, data, and status between the
17, 19 16, 17 22, 24 NAT9914 and the CPU.
D0 is the most significant bit.
4 3 9 CE* I Chip Enable gives access to the register
selected by a read or write operation, and the
register selects RS(2-0).
6 5 11 DBIN I†With the Data Bus Input, you can place the
contents of the register selected by RS(2-0)
and CE* onto the data bus D(7-0). The polarity
of DBIN is reversed for DMA operation.
5 4 10 WE* I The Write input latches the contents of the
data bus D(7-0) into the register selected by
RS(2-0).
3 2 8 ACCGR* I†The Access Grant signal selects the DIR or
CDOR for the current read or write cycle.
2 1 7 ACCRQ* O The Access Request output asserts to request
a DMA Acknowledge cycle.
20 18 25 CLK I†The CLK input can be up to 20 MHz.
21 19 26 RESET* I†Asserting the RESET* input places the
NAT9914 in an initial, idle state.
10 9 15 INT* O The Interrupt output asserts when one of the
(OC) unmasked interrupt conditions is true.The
NAT9914 does not drive INT* high. The INT*
pin must be pulled up by an external resistor.
9, 8, 7 8, 7, 6 14, 13, 12 RS(2-0) I††† The Register Selects determine which register
to access during a read or write operation.
25 23 30 IFC* I/O†,†† Bidirectional control line initializes the
(OC) IEEE 488 interface functions.
24 22 29 REN* I/O†Bidirectional control line selects either remote
(OC) or local control of devices.
31 28 36 ATN* I/O†Bidirectional control line indicates whether
data on the DIO lines is an interface or device-
dependent message.
32 29 37 SRQ* I/O†Bidirectional control line requests service from
the controller.
34, 35, 36, 31, 32, 33, 39, 40, 41, DIO(8-1)* I/O†8-bit bidirectional IEEE 488 data bus
37, 38, 39, 34, 35, 36 42, 43, 44,
41, 42 37, 38 2, 3
29 26 34 DAV* I/O†Handshake line indicates that the data on the
DIO(8-1)* lines is valid.
27 25 32 NRFD* I/O†Handshake line indicates that the device is
ready for data.
26 24 31 NDAC* I/O†Handshake line indicates the completion of a
message reception.
30 27 35 EOI* I/O†Bidirectional control line indicates the last byte
of a data message or executes a parallel poll.
23 21 28 TE O†T alk Enable controls the direction of the
IEEE 488 data transceiver.
ACCRQ
RESET
CLK
D0
D1
D2
D3
D4
D5
D6
D7
RS2
RS1
RS0
DBIN
WE
CE
ACCGR
INT
VSS
VDD
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
CONT
DIO8
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
TR
NAT9914BPD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RS0
D1
D2
D4
D5
D6
D7
INT
RS2
RS1 DIO3
DAV
EOI
ATN
SRQ
CONT
DIO8
DIO7
DIO6
DIO5
DIO4
D3
NC
NC
NRFD
IFC
REN
TE
VSS
RESET
CLK
D0
NDAC
DBIN
NC
DIO2
TR
VDD
NC
CE
WE
DIO1
ACCRQ
ACCGR
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
6 5 4 3 2 1 44 43 42 4140
18 19 20 21 22 2324 25 26 2728
NAT9914BPL
Figure 1. NAT9914BPD
Pin Configuration
Figure 2. NAT9914BPL
Pin Configuration
DAV
DIO3
DIO4
DIO6
DIO7
DIO8
CONT
SRQ
ATN
EOI D1
RS0
RS1
RS2
INT
D7
D6
D5
D4
D3
D2
DIO5
NC
DBIN
WE
ACCGR
ACCRQ
NC
TR
DIO1
DIO2
CE
NC
NC
D0
RESET
V
TE
NDAC
NRFD
CLK
REN
IFC
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
33 32 31 30 29 2827 26 25 2423
1234567891011
NAT9914BPQ
V
DD
SS
Figure 3. NAT9914BPQ
Pin Configuration
Pin Number
PLCC DIP QFP Mnemonic Type Description
43 39 4 TR O†Trigger asserts when one of the trigger conditions is satisfied.
33 30 38 CONT* O†Controller asserts when the NAT9914 is Controller -In-Charge.
44 40 5 VDD – Power pin – +5 V (±5%)
22 20 27 VSS – Ground pin – 0 V
1, 18, – 1, 6, NC – No connect
28,40 23, 33
OC= Open collector.
†The pin contains an internal pull-up resistor of 25 kΩto 100 kΩ.
* Active low .
†† In controller applications where the CLK signal frequency is > 8 MHz, IFC* should be pulled up with a 4.7 kΩresistor.
††† RS0 and RS1 contain an internal pull-up resistor of25 kΩto 100 kΩ. RS2 does not contain an internal pull-up or pull-down resistor .
IEEE 488.2 Controller Chip
National Instruments
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Interface
Functions
SH1
AH1
T5/TE5
L3/LE3
SR1
RL1
PP1/PP2
DC1
DT1
C1-C5
RSV Gen
EOI Gen
STB Out
SYNC
D(7-0)
CE*
RS(2-0)
DBIN
WE*
ACCRQ*
ACCGR*
INT*
CLK
Data-In
Command Pass Through
Command/Data Out
Address Status
Address Mode
Address
End-of-String
Interrupt Mask 0, 1, 2
Interrupt Status 0, 1, 2
Serial Poll
Parallel Poll
Aux A, B, E, F, G, I
SASR
Version
Auxiliary
Command Decoder
RESET*
Bus Status
and Control
DIO(8-1)*
GPIB
Control
CONT*
TE
TR
Internal Count
Internal Count 2
Message
Decoder
CompareCompare
Read/
Write
Control
Figure 4. NAT9914 Block Diagram
IEEE 488.2 Controller Chip
National Instruments
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4
9914 Mode Registers
In 9914 mode, the NAT9914 registers consist of all the
TI TMS9914A registers and two types of additional registers – newly
defined registers and paged-in registers. The NAT9914 maps the newly
defined registers into the unused portion of the 9914 address space.
Each paged-in register appears at Of fset 2 immediately after you issue an
auxiliary page-in command, and it remains ther e until you page another
register into the same space or you issue a reset. The table below lists all
the registers in the 9914 r egister set. See the NAT9914 Refer ence Manual
available at ni.com for more information.
7210 Mode Registers
The NAT9914 registers include all the NEC µPD7210 registers plus two
types of additional registers – extra auxiliary registers and paged-in
registers. You write the extra auxiliary registers the same as standard
µPD7210 auxiliary registers. On issuing an auxiliary page-in command,
the paged-in registers appear at the same offsets as existing µPD7210
registers. At the end of the next CPU access, the chip pages out the
paged-in registers. The following table lists all the registers in the 7210
mode register set. See the NAT9914 Reference Manual available at
ni.com for more information.
Register PAGE-IN RS(2-0) WE* DBIN CE* ACCGR*
Interrupt Status 0 U 0 0 0 1 1 0 1
Interrupt Mask 0 U 0 0 0 0 0 0 1
Interrupt Status 1 U 0 0 1 1 1 0 1
Interrupt Mask 1 U 0 0 1 0 0 0 1
Address Status U 0 1 0 1 1 0 1
Interrupt Mask 2†P 0 1 0 0 0 0 1
End-of-String†P 0 1 0 0 0 0 1
Bus Control
†
P 0 1 0 0 0 0 1
Accessory†P 0 1 0 0 0 0 1
Bus Status U 0 1 1 1 1 0 1
Auxiliary Command U 0 1 1 0 0 0 1
Interrupt Status 2†P 1 0 0 1 1 0 1
Address U 1 0 0 0 0 0 1
Serial Poll Status†P 1 0 1 1 1 0 1
Serial Poll Mode U 1 0 1 0 0 0 1
Command Pass Through U 1 1 0 1 1 0 1
Parallel Poll U 1 1 0 0 0 0 1
Data-In U 1 1 1 1 1 0 1
Data-In U X X X X 0 X 0
Command/Data Out U 1 1 1 0 0 0 1
Command/Data Out U X X X 0 1 X 0
The '†' symbol denotes features (such as registers and auxiliary commands) that are not available in the TMS9914A.
Notes for the PAGE-IN column:
U = Page-in auxiliary commands do not affect
the register of fset.
P = The register of fset is valid only after a page-in
auxiliary command.
Register PAGE-IN A(2-0) WE* DBIN CE*
ACCGR*
Data-In U 0 0 0 1 1 0 1
Data-In X X X X X 0 X 0
Command/Data Out U 0 0 0 0 0 0 1
Command/Data Out X X X X 0 1 X 0
Interrupt Status 1 U 0 0 1 1 1 0 1
Interrupt Mask 1 U 0 0 1 0 0 0 1
Interrupt Status 2 U 0 1 0 1 1 0 1
Interrupt Mask 2 U 0 1 0 0 0 0 1
Serial Poll Status N 0 1 1 1 1 0 1
Serial Poll Mode N 0 1 1 0 0 0 1
Version P 0 1 1 1 1 0 1
Internal Counter 2 P 0 1 1 0 0 0 1
Address Status U 1 0 0 1 1 0 1
Address Mode U 1 0 0 0 0 0 1
Command Pass Through N 1 0 1 1 1 0 1
Auxiliary Mode U 1 0 1 0 0 0 1
Source/Acceptor Status†P1011101
Address 0 N 1 1 0 1 1 0 1
Address N 1 1 0 0 0 0 1
Interrupt Status 0†P1101101
Interrupt Mask 0†P1100001
Address 1 N 1 1 1 1 1 0 1
End-of-String N 1 1 1 0 0 0 1
Bus Status†P1111101
Bus Control†P1110001
The '
†
' symbol denotes features (such as registers and auxiliary commands) that are not available in the NEC7210.
Notes for the PAGE-IN column:
U = The page-in auxiliary command does not affect
the register.
N = The register of fset is always valid except for immediately
after a page-in auxiliary command.
P = The register is valid only immediately after a page-in
auxiliary command.
9914 Register Set 7210 Register Set
Capacitance
TA0 to 70 °C; VCC = 5 V ±5%
Limits Test
Parameter Symbol Min Max Unit Condition
Input CIN –10pF –
capacitance
Output COUT –10pF –
capacitance
I/O capacitance
CI/O –10pF –
Absolute Maximum Ratings
Property Range
Supply voltage, VDD -0.5 to +7.0 V
Input voltage, VI-0.5 to VDD +0.5 V
Operating temperature, TOPR 0 to +70° C
Storage temperature, TSTG -40 to +125° C
Comment: Exposing the device to stresses above those listed could cause permanent damage. The
device is not meant to be operated under conditions outside the limits described in the operational
section. Exposure to absolute maximum rating conditions for extended periods may affect reliability .
AC Characteristics
TA0 to 70 °C; VCC = 5 V ±5%
Limits Test
Parameter Symbol Min Max Unit Condition
Address hold from CE, WE,and DBIN tAH 0–ns –
Address setup to CE , WE, and DBIN tAS 0–ns –
Data float from CE or DBIN tDF –20ns –
Data delay from DBIN↓tDR – 75 ns ACCGR=0
ACCRQ unassertion tDU –20ns –
Data delay from CE↓tRD – 80 ns ACCGR=1
CE recovery width tRR 80 – ns –
CE pulse width tRW 80 – ns –
Data hold from WE↑tWH 0–ns –
Data setup to WE↑tWS 60 – ns –
IEEE 488.2 Controller Chip
National Instruments
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Preliminary DC Characteristics
TA0 to 70 °C; VCC = 5 V ±5%
Limits Test
Parameter Symbol Min Max Unit Condition
Voltage input low VIL -0.5 +0.8 V –
Voltage input high VIH +2.0 VCC V–
Voltage output low VOL 0 0.4 V –
Voltage output high VOH +2.4 VCC V –
Input/output – -10 +10 µA without
Leakage current
internal pull-up
Input/output – -200 +200 µA
with internal
Leakage current pull-up
Supply current – – 45 mA –
Output current low
All pins except ACCRQ
IOL 2 – mA 0.4 V @ IOL
ACCRQ IOL 4 – mA 0.4 V @ IOL
Input current low IIL – - 0.5 mA –
Supply voltage VDD 4.75 5.25 V –
Figure 5. CPU Read
Figure 6. DMA Read
Notes:
•tAS is the setup time to CE↓or WE↓, whichever is later.
•tAH is the hold time from WE↑or CE↑, whichever is earlier.
Timing Waveforms
Figure 7. CPU Write
RS2-0 tAS
tRR
tRD tDF
tAH
tRW
DBIN
CE
D7-0
ACCRQ tDU
tDR tDF
ACCGR
DBIN
D7-0
RS2-RS0
tAS tAH
tWS tWH
CE
WE
D7-0
Figure 8. DMA Write
ACCRQ
ACCGR tDU
tWS tWH
D7-0
DBIN
WE
IEEE 488.2 Controller Chip
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6
Parallel Poll Limits (ns) T est
Parameter Symbol Min Max Condition
EOI↓to DIO↓valid tED 90 PPSS →PPAS
EOI↓to TE↑tET 30 PPSS →PPAS
EOI↑to TE↓tTE 30 PP AS →PPSS
Response to ATN Limits (ns) T est
Parameter Symbol Min Max Condition
ATN↑to NRFD↓tAF 35 Acceptor handshake
holdoff
ATN↓to NDAC↓tAN 35 AIDS →ANRS
ATN↓to TE↓tAT 30 T ACS →TADS
Acceptor Handshake Limits (ns) T est
Parameter Symbol Min Max Condition
DAV
↓
to NDAC↑tDD 35+3T
DAV
↑
to NDAC
↓
tDF 25
DAV
↓
to INT
↓
or ACCRQ
↓
tDI 50+2T INT(DIIE Bit=1),
ACCGR (DMAI Bit=1)
DAV
↓
to NRFD
↓
tDR 20
DBIN↑to NRFD↑tNR 35 Read of DIR, not in
Holdoff state
Source Handshake Limits (ns) T est
Parameter Symbol Min Max Condition
NDAC↑to DAV↑t
ND
–40 –
NDAC↑to INT↓or ACCRQ↓t
NI
– 40 INT(DOIE Bit=1)
ACCGR (DMAO Bit=1)
WE↑to DAV↓t
WD
2000 2180 2 µs T1, 5MHz
WE↑to DAV↓t
WD
1200 1380 1.1 µs T1, 5MHz
WE↑to DAV↓t
WD
600 780 500 ns T1, 5MHz
WE↑to DAV↓t
WD
400 580 350 ns T1, 5MHz
Figure 11. ATN Response Timing
Figure 12. Parallel Poll Response Timing
Figure 10. Acceptor Handshake Timing
Figure 9. Source Handshake Timing
Note: T = one clock period
ATN
EOI
TE
DIO
tET
tTE
tED
WE
D7-0
INT/ACCGR
tWD
tND
tNI
NDAC
DAV
DIO 8-1
ATN
TE
NDAC
NRFD
tAT
tAN
tAF
DAV
NDAC tDD
tDI
tNR
tDF
tDR
DBIN
INT/ACCRQ
NRFD
IEEE 488.2 Controller Chip
National Instruments
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Decode
A23-0 D15-0
74573
74573
Interrupt
Control
D15-0
A23-0
IPL2-0
RESET
DTACKN
UDSN
R/WN
ASN
LDSN
74245
A0
D7-0
CE*
A2
A1
RESET*
INT*
UDSN
LDSN
R/WN
ASN
UAS
OWN
DBEN
DDIR
RDYN
DTACKN
A23/D15 - A8/D0
A7-A1
A3
A2
A1
DBIN
WE*
GND
OSC CLK
DRQ
ACK
ACCRQ*
ACCGR*
68440
CPU(68000)
DRQ
RD*
WR*
INT0
ACCRQ*
DBIN
WE*
INT*
DEN
DT/R
AD15-0 D7-0
A2
A1
A0
RESET RESET*
CE*
D7-0 A15-0
74573
OSC CLK
A1
A2
A3
ACCGR*
CPU(80186) NAT9914
D8
D7
D6
D5
D4
D3
D2
D1
NDAC
NRFD
REN
IFC
DAV
EOI
ATN
SRQ
TE
TE
PE
DC
TE
CONT*
75162
75160
DIO8
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
GPIB
REN
NDAC
NRFD
DAV
EOI
ATN
SRQ
D8
D7
D6
D5
D4
D3
D2
D1
NDAC
NRFD
REN
IFC
DAV
EOI
ATN
SRQ
TE
TE
PE
DC
TE
CONT*
75162
75160
DIO8
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
GPIB
REN
NDAC
NRFD
DAV
EOI
ATN
SRQ
IFC
NAT9914
SC
+5 V
SC
+5 V
Othe r
DTACK
Sources
+5 V
+5 V
IFC
Decode
74245
Figure 13. Typical CPU Systems with NA T9914
IEEE 488.2 Controller Chip
National Instruments
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8
Figure 14. Mechanical Data 40-Pin Plastic DIP
Figure 15. Mechanical Data 44-Pin PLCC
IEEE 488.2 Controller Chip
National Instruments
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Dimensions Tolerance Value (in mm)
A max. 2.35
A1– 0.25 max.
A2+ 0.10/-0.05 2.00
D ± 0.25 17.20
D1± 0.10 14.00
E ± 0.25 17.20
E1± 0.10 14.00
L + 0.15/- 0.10 0.88
e basic 1.00
b ± 0.05 0.35
θ– 0 to 7°
ddd – 0.20 nom.
ccc max. 0.10
Figure 16. Mechanical 44-pin QFP.
IEEE 488.2 Controller Chip
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All National Instruments data acquisition, computer-based
instrument, VXIbus, and MXI™bus pr oducts are covered by a one-
year warranty. GPIB hardware products are covered by a
two-year warranty from the date of shipment. The warranty
covers board failures, components, cables, connectors, and
switches, but does not cover faults caused by misuse. The owner
may return a failed assembly to National Instruments for repair
during the warranty period. Extended warranties are available
at an additional charge.
Information furnished by National Instruments is believed to
be accurate and reliable. National Instruments r eserves the right
to change product specifications without notice.
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© Copyright 2001 National Instruments Corporation. All rights reserved. Product and company names listed are trademarks or trade names of their respective companies. 041001
ni.com/gpi (512) 794-0100
*340497D-01*
340497D-01
Ordering Information
NAT9914BPD
NAT9914BPL
NAT9914BPQ
Part Number Legend
abcde
NAT 9914 B P D
a. Family name – NAT = 8-bit GPIB
Talker/Listener/Controller interface
b. Device number – 9914 = TI TMS9914A
pin-compatible part
c. Revision
d. Package material – P = plastic
e. Package type – D = Dual Inline Package (DIP)
L = Plastic Leaded Chip Carrier (PLCC)
Q = Quad Flatpack (QFP)
NA T9914 Pr ogrammer Reference Manual......visit ni.com
