July 2001 1/86
Rev. 2.9
ST62T55C
ST62T65C/E65C
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
SAFE RESE T, AUTO-RELOAD TIMER, EEPROM AND SPI
■3.0 to 6.0V Supply Operating Range
■8 MHz Maximum Clock Frequency
■-40 to +125°C Operating Te mpe rature Range
■Run, Wait and Stop Modes
■5 Interrupt Vectors
■Look-up Table capability in Program Memory
■Data Storage in Program Memory:
User selectable size
■Data RAM: 128 bytes
■Data EEPROM: 128 bytes (none o n ST62T55C )
■User Program mab le Options
■21 I/O pins, fully programmab le as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■8 I/O lines can sink up to 30mA to drive LEDs or
TRIACs directly
■8-bit Timer/Counter with 7-bit programmable
prescaler
■8-bit Auto-reload Timer wi th 7-bit programmable
prescaler (AR Timer)
■Digital Watchdog
■Oscillator Safe Guard
■Low Voltag e Detecto r fo r Safe Reset
■8-bit A/D Converter with 13 analog inputs
■8-b it Synchronous Pe ripheral Interface (SPI)
■On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■User configurable Power-on Reset
■One external Non-Maskable Interrupt
■ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port) DEVICE SUMMARY
DEVICE OTP
(Bytes) EPROM
(Bytes) EEPROM
ST62T55C 3884 - -
ST62T65C 3884 - 128
ST62E65C 3884 128
(See end of Datasheet for Ordering Information)
PDIP28
PS028
CDIP28W
SS0P28
2/86
Table of Cont ents
86
Document
Page
ST62T55C
ST62T65C/E65C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 Introduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.6 Data RAM/EEPROM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 PRO GRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4.2 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18
3.1 CL OCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.2 L ow Frequenc y Au xi liary Osc illator (LFA O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1 RESET In put . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.4 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.5 Application Note s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.6 MCU Initialization Sequen ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.1 Digital Watchdog Regist er (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.2 Application Note s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.1 Interrupt reque st . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.3 Interrupt Op tion Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4.4 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5.1 W AIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5.3 Exit from WAIT and STO P Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.1 Operat ing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.3 Timer 1 Alternate function Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.4 AR Timer Alternate function Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.5 SPI Alternate function Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2 T IMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.1 Timer Operat ing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.3 Application Note s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2.4 Timer Registe rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3 AUT O-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.2 Timer Operat ing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.4.1 Application Note s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.5.1 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.6 SPI TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.2 RECO MMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.6 T IMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.7 SPI CHARACTERIST ICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.8 ART IMER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.2 O RDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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Table of Cont ents
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ST62P55C
ST62P65C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
1 GENERAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.2.2 Listing Generat ion and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ST6255C
S T6265B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
1 GENERAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
1.3.2 Listing Generat ion and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5/86
ST62T55C ST62T65C/E65C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T55C, ST62T65C and ST62E65C devic-
es are low cos t m em bers of the S T6 2xx 8-bit HC-
MOS family of microcontrollers, which is targeted
at low to medium complexity applications. All
ST62xx dev ices are based on a building block ap-
proach: a common core is surrounded by a
number of on-chip peripherals.
The ST62E65C is the erasable EPROM version of
the ST62 T65C dev ice, which m ay be us ed to em -
ulate the ST62T55C and ST62T65C device, as
well as the respective ST6255C and ST6265C
ROM devices.
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
tionality selecting as ROM op tio ns th e options de-
fined in the programmable option byte of the OTP/
EPROM ver si o ns.
OTP devices offer all the advant ages of user pro-
grammability at low cost, which make them the
ideal choice in a wide range of appl ications where
frequent c ode chang es, mu ltiple code vers ions or
last minute programm ability are required.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program-
mable prescaler, an 8-bit Auto-Reload Timer,
EEPROM data capability (except ST62T55C), a
serial port communication interface, an 8-bit A/D
Converter with 13 analog inputs and a Digital
Watchdog timer, making them well suited for a
wide range of automotive, appliance and industrial
applications.
Figu re 1. Blo ck Diagram
j
TEST
NMI INTERRUPT
PROGRAM
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY OSCILLATOR RESET
DATA RO M
USER
SELECTABLE
DAT A RAM
PORT A
PORT B
TIMER
DIGITAL
8 BIT CORE
TEST/VPP
8-BIT
A /D CO NV ERTER PA0..PA7 / Ain
PB0..PB5 / 30 mA Sink
VDDVSS OSCin OSCout RESET
WATCHDOG
MEMORY
PB6 / ARTimin / 30 mA Sink
PORT C PC2 / Sin / Ain
PC3 / Sout / Ain
SPI (SERIA L
PERIPHERAL
INTERFACE)
AUTORELOAD
TIMER
PC4 / Sck / Ain
PB7 / ARTimout / 30 mA Sink
128 Bytes
3884 by tes
(ST62T55C, T65 C,
DATA EEPROM
128 Bytes
PC 0 / Ain
PC1 / Tim1 / Ain
(ST62T65C/E65C)
E65C)
6/86
ST62T55C ST62T65C/E65C
1.2 PIN DESCRIPTIONS
VDD and VSS. Power is supplied to the MCU via
these two pins. VDD is the po wer connection an d
VSS i s the ground connec tion.
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OS Cin pin is the input pin, the OSCout pin is
the output pin.
RESET. The active-low RESET pin is used to re-
start the microcontroller.
TEST/VPP. T he TEST mus t be held at VSS for nor-
mal operation. If TEST pin is connected to a
+12.5V le ve l du ring the res et phas e, t he E P ROM /
OTP programm ing Mo de is entered.
NMI. The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non
maskable interrupt to the MCU. The NMI input is
falling edge s ensitive. It i s provided with an on-chip
pullup resistor (if option has been enabled), and
Schmitt trigger ch aracteristics.
PA0-PA7. These 8 lines are organized as one I /O
port (A). Each line may be configured unde r soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs, ana-
log inputs for the A/D converter.
PB0-PB5. Thes e 6 lines are orga nized as one I /O
port (B). Each line may be configured unde r soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or pu sh-pull outputs.
PB0-PB5 can also sink 30mA for direct LED
driving.
PB6/ARTIMin, PB7/ARTIM out. These pins are ei-
ther Port B I/O bits or the Input and Ou tput pins of
the AR TIMER. To be used as timer input function
PB6 has to be programmed as input with or with-
out pull-up. A dedicated bit in the AR TIMER Mode
Control Register set s PB7 as t imer output function.
PB6-PB7 can also sink 30mA for direct LED driv-
ing.
PC0-PC4. Thes e 5 lines are organized as one I/O
port (C). Each line may be configu re d under soft-
ware control as input with or without internal pull-
up resistor, interrupt generating input with pull-up
resistor, analog input for the A/D converte r, open-
drain or push-pull output.
PC1 can also be used as Timer I/O bit while
PC2-PC4 can also be used as respectively Data
in, Data out and Clock I/O pins for the on-chip SPI
to carry the sync hronous se rial I/O signals.
Figure 2. ST6 2T55C , T65C , E65C Pin
Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
PB0
PB1
VPP/TEST
PB2
PB3
Ain / PA0
VDD
PB4
PB5
ARTIMin/PB6
PC0/Ain
PC1/TIM1/Ain
PC2/Sin/Ain
PC3/Sout/Ain
PC4/Sck/Ain
PA7/Ain
PA6/Ain
PA5/Ain
PA4/Ain
PA3/Ain
28
27
26
25
24
23
22
21
ARTIMout/PB7
VSS
Ain/PA1
Ain/PA2
NMI
RESET
OSCout
OSCin
7/86
ST62T55C ST62T65C/E65C
1.3 MEMORY MAP
1.3 .1 Introd ucti on
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three m emory spaces is
described in the follo wing paragraph s.
Briefly, Program space contains user program
code in OTP and user vectors; Data space con-
tains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for sub-
routine and interrupt service routine nesting.
Figure 3Mem ory Address in g Diagram
PROGRAM SPACE
PROGRAM
INTERRUPT &
RESET VECTORS ACCUMULATOR
DATA RAM
BANK SELECT
WINDOW SELECT
RAM
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
DATA READ-ONLY
WINDOW
RAM / EEPROM
BANKING AREA
000h
03Fh
040h
07Fh
080h
081h
082h
083h
084h
0C0h
0FFh
0-63
DATA SPACE
0000h
0FF0h
0FFFh
MEMORY MEMORY
DATA READ-ONLY
MEMORY
8/86
ST62T55C ST62T65C/E65C
MEMOR Y MA P (Cont’d)
1.3.2 Program Space
Program Space comprises the instructions to be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and the us er vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register).
1.3.2.1 Program Memo ry Protecti on
The P rogram M em ory i n OTP or EP ROM dev ices
can be protected against external readout of mem-
ory by selecting the READOUT PROTECTION op-
tion in the option byte.
In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Note: Once th e Readout Protec tion is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the OTP contents. Returned
parts with a protection s et c an therefore not be ac-
cepted.
Figure 4.ST 62T 55C/T65C/ E65C Pr og ram
Memory Map
0000h RESERVED*
USER
PROGRAM MEMORY
(OTP/EPROM)
3872 BYTES
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED*
RESERVED
INTERRUPT VECTORS
NMI VECTOR
USER RESET VECTOR
(*) Reserved areas should be filled with 0FFh
0080h
007Fh
9/86
ST62T55C ST62T65C/E65C
MEMOR Y MA P (Cont’d)
1.3.3 Data Space
Data Space accommodates all the data necessary
for processing the user program. This space com-
prises the RAM resource, the proc essor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in OTP/
EPROM.
1.3.3.1 Data ROM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the program code to be ex ecut ed, as well as
the constants and look-up tables required by the
application.
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through wh ich it is possible to acc ess the
read-only data stored in OTP/EPR OM .
1.3.3.2 Data RA M/EEPROM
In ST62T55C, ST62T65C and ST62E65C devic-
es, the data spa ce includes 60 bytes of RAM, the
accumulator (A), the indirect registers (X), (Y), the
short direct registers (V), (W), the I/O port regis-
ters, the peripheral data and control registe rs, the
interrupt option register and the Data ROM Win-
dow register (DRW register).
Additional RA M and EEPROM pages can also be
addressed using banks of 64 bytes located be-
tween addresse s 00h and 3Fh.
1.3.4 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
Table 1. Additional RAM/E EPRO M Banks
Table 2. ST62T55C, ST62T65C and ST62E65C
Data Memory Space
Device RAM EEPROM
ST62T55C 1 x 64 bytes -
ST62T65C/E65C 1 x 64 bytes 2 x 64 bytes
RAM and EEPROM 000h
03Fh
DATA ROM WINDOW AREA 040h
07Fh
X REGISTER 080h
Y REGISTER 081h
V REGISTER 082h
W REGISTER 083h
DATA RAM 60 BYTES 084h
0BFh
PORT A DATA REGISTER 0C0h
PORT B DATA REGISTER 0C1h
PORT C DATA REGIST E R 0C2h
RESERVED 0C3h
PORT A DIRECTION REGIST ER 0C4h
PORT B DIRECTION REGIST ER 0C5h
PORT C DIRECTION REGISTER 0C6h
RESERVED 0C7h
INTERRUPT OPTION REGIS TER 0C8h*
DATA ROM WIND O W RE G IST ER 0C9h*
RESERVED 0CAh
0CBh
PORT A OPTION REGISTER 0CCh
PORT B OPTION REGISTER 0CDh
PORT C OPTION REGISTER 0CEh
RESERVED 0CFh
A/ D DATA REGIST E R 0D0h
A/ D CONTROL REGI S T ER 0D1h
TI MER PRESCAL ER REGISTE R 0D2h
TI M ER COUN T ER R EGIST ER 0D3h
TI M ER ST ATUS CONT ROL REG IS T ER 0D4h
AR TIM E R M O DE CONT ROL RE G I STER 0D5h
AR TIMER STATUS/CONTROL REGISTER 1 0D6h
AR TIMER STATUS/CONTROL REGISTER 2 0D7h
WATCHDOG REGISTER 0D8h
AR TIMER RELOAD/CAPTURE REGISTER 0D9h
AR TIMER COMPARE REGISTER 0DAh
AR TIMER LOAD REGISTER 0DBh
OSCILLAT O R CONTRO L RE G I STER 0 DCh*
MISCELLANEOUS 0DDh
RESERVED 0DEh
0DFh
SPI DATA REGISTER 0E0h
SPI DIVIDE R REGISTER 0 E1 h
SPI MODE REGISTER 0E2h
RESERVED 0E3h
0E7h
DATA RAM/EEPROM REGISTER 0 E8 h*
RESERVED 0E9h
EEPROM CONTROL REGISTER 0EAh
RESERVED 0EBh
0FEh
ACCUMULATOR 0FFh
* WRITE ONLY REGISTER
10/86
ST62T55C ST62T65C/E65C
MEMOR Y MA P (Cont’d)
1.3.5 Data Windo w Reg ister (DWR)
The Data read-only memory window is located from
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat-
ed anywhere in program memory, between ad-
dress 0000h and 0FFFh (top memory address de-
pends on the specific device). All the program
memory can therefore be used to store either in-
structions or read-only data. Indeed, the window
can be moved i n steps of 64 byt es along the pro-
gram memory by writing the appropriate code in the
Data Window Register (DWR).
The DWR can be addressed like any RAM location
in t he Data Space, it is however a write-only regis-
ter and therefore cannot be accessed using single-
bit operations. This register is used to position th e
64-byte read-only data win dow (from address 40 h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte t o be read as dat a in progra m me mory is
obtained by concatenating the 6 least significant
bits of the register address given in the inst ruction
(as least significant bits) and the content of the
DWR register (as most s ignificant bit s), as illustrat-
ed in Figure 5 below. For instance, when address-
ing location 0040h of the Data Space, with 0 load-
ed in the DWR register, the physical location ad-
dressed in program memory is 00h. The DWR reg-
ister is not cleared on reset, therefore it must be
writ ten to prior to the fi rst access to the Data read-
only memory window area.
Data Wi ndow R eg ist er (DWR)
Address: 0C9h —Write Only
Bits 6, 7 = Not used .
Bit 5-0 = DWR5-DWR0: Data read-only memory
Window Register Bits. These are the Data read-
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
Caution: T his register is undefined on reset. Nei-
ther read nor single bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while exe-
cuting an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writ-
ing to the DWR during the interrupt service routine,
an ima ge of the regi ster mus t be saved in a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if an in-
terrupt occurs between the two instructions, the
DWR is not affe cted.
Figure 5Data read-only memory Window Memory Addressing
70
- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
DA TA ROM
WINDOW REGISTER
CONTENTS DATA SPAC E ADDRE SS
40h-7Fh
IN INSTRUCTION
PROGRAM SPACE ADDRE SS
765432 0
543210
543210
READ
1
67891011
01
VR01573C
12
1
0DATA SPAC E ADDRE SS
:
:
59h
000
01001
11
Example:
(DWR)
DWR=28h
11
0000000
1
ROM
ADDRESS:A19h 11
13
01
11/86
ST62T55C ST62T65C/E65C
MEMOR Y MA P (Cont’d)
1.3.6 Data RAM/EEPROM Bank Register
(DRBR)
Address: E8h —Write only
Bit 7-5 = These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2.
Bit 3-2 - Reserved. These bits are not used.
Bi t 1 - DRBR1. This bit, when set, selects
EEPROM Page 1, when avail able.
Bi t 0 - DRBR0. This bit, when set, selects
EEPROM Page 0, when avail able.
The selection of the bank is made by programming
the Data RAM Bank Switch register (DRBR regis-
ter) located at addres s E8 h of the Data Sp ace ac -
cording to Table 1. No more than one bank should
be set at a time.
The DRBR re gister can be addressed l ike a RAM
Data Space at the addre ss E8h; nevertheless it is
a write only register that cannot be accessed with
single-bit operations. This register is used to select
the desired 64-byte RAM/EEPROM bank of the
Data Space. The bank number has to be loaded in
the DRBR register and the in struction has to point
to the selected location as if it was in bank 0 (from
00h address to 3Fh address).
This register is not cleared during the MCU initiali-
zation, therefore it mu st b e written before the first
access to the Data Space bank region. Refer to
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occ urs.
Notes :
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the s ervice routine can-
not save and then restore its previous content. If it
is impossibl e to av oid the writing of th is register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs be tween the
two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing errors.
Care must also be taken not to change the
E²PROM page (when avail able) when the parallel
writing mode is set for the E²PRO M, as defined in
EECTL register.
Table 3Data RAM Bank Register Set-up
70
---
DRBR
4--
DRBR
1DRBR
0
DRBR ST62T55C ST62T65C/E65C
00 None None
01 Not Available EEPROM Page 0
02 Not Available EEPROM Page 1
08 Not Available Not Available
10h RAM Page 2 RAM Page 2
other Reserved Reserved
12/86
ST62T55C ST62T65C/E65C
MEMOR Y MA P (Cont’d)
1.3.7 EEPROM Descr iption
EEPROM memory is located in 64-byte pages in
data space. This memory may be used by the user
program for non-volatile data storage.
Data space from 00h to 3Fh is paged as described
in Table 4. EEPROM locations are accessed di-
rectly by addressing these paged sections of data
space.
The EEPROM does not requi re dedicated in struc-
tions for read or write access. Once selected via the
Data RAM Bank Register, the active EEPROM
page is controlled by the EEPROM Control Regis-
ter (EECT L), which is described below.
Bit E20FF of the EECTL register must be reset prior
to any write or read a ccess to the EEPROM. If no
bank has been selected, or if E2OFF is set, any ac-
cess is meaningless.
Programming must be enabled by setting the
E2ENA bit of the EECTL register.
The E2BUSY bit of the EECTL register is set when
the EEPROM is performing a programming cycle.
Any access to the EE PR OM when E 2BUS Y is set
is meaningless.
Provided E2OFF and E2BUSY are reset, an EEP-
ROM location is read just like any other data loca-
tion, also in te rms of access time.
Writing to the EE PR OM ma y be carried o ut in tw o
modes: Byte Mode (BMODE) and Parallel Mode
(PMODE). In BMODE, one byte is accessed at a
time, while in PMODE up to 8 bytes in the same
row are programmed simultaneously (with conse-
quent speed and power consumption advantages,
the latter being particularly important in battery
powered circuits).
Ge neral Notes:
Data should be written directly to the inten ded ad-
dress in EEPROM space. There is no buffer mem-
ory between data RAM and the EEPROM space.
When the EEPROM is busy (E2BUSY = “1”)
EECTL cannot be accessed in write mode, it is
only possible to read the status of E2BUSY. This
implies that as long as the EEPROM is busy, it is
not possible to change the st atus of the EEP ROM
Control Register. EECTL bits 4 and 5 are reserved
and must never be set.
Care is required when dealing with the EECTL reg-
ister, as some bits are w rite only. For this reason,
the EECTL c ontents m ust no t be altered while ex-
ecuting an interrupt service routine.
If it is impossible to avoid writing to this register
within an interrupt service routine, an image of the
register must be saved in a RAM location, and
each time the program writes to EECTL it must
also write to the image register. The image register
must be written to first so that, if an interrupt oc-
curs be twee n t he two in structions, the E E CT L wi ll
not be affected.
Table 4Row Ar rangement for P a rallel Wr itin g of EEPROM Loca t i ons
Note: The EEPR OM is disabled as soon as STOP instruction is executed in order to achieve the lowest
power-consumption.
Dataspace
addresses.
Banks 0 and 1.
Byte01234567
ROW7 38h-3Fh
ROW6 30h-37h
ROW5 28h-2Fh
ROW4 20h-27h
ROW3 18h-1Fh
ROW2 10h-17h
ROW1 08h-0Fh
ROW0 00h-07h
Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.
The number of available 64-byte banks (1 or 2) is device dependent.
13/86
ST62T55C ST62T65C/E65C
MEMOR Y MA P (Cont’d)
Additional Notes on Parallel Mode:
If the user wishes to perform parallel program-
ming, the first step should be to set the E2PAR2
bit. From this time on, the EEPROM will be ad-
dressed in write m ode , the ROW address and th e
data will be latched and it will be possible to
change them only at the end o f the programming
cycle or by resetting E2PAR2 without program-
ming the EEPROM. After the ROW address is
latched, the MCU can only “see” the selected
EEPROM row and any attempt to write or read
other rows w ill produc e error s.
The EEPROM should not be read while E2PAR2
is set.
As soon as the E2PAR2 bit is set, the 8 volatile
ROW latches are cleared. From this moment on,
the user can load data in all or in part of the ROW.
Setting E2PAR1 will modify the EEPROM regis-
ters corresponding to the ROW latches accessed
after E2PAR2. For example, if the software sets
E2PAR2 and accesses the EEPROM by wr iting to
addresses 18h, 1Ah and 1Bh, and then sets
E2 PAR 1 , t h es e t hr e e re gis ter s will b e mo dif ie d s i-
multaneously; the remaining bytes in the row will
be unaffected.
Note that E2PAR2 is internally reset at the end of
the programming cycle. This implies that the user
must set the E2PAR2 bit between two parallel pro-
gramming cycles. Note that if the user tries to set
E2PAR1 while E2PAR2 is not set, there will b e no
programming cycle and t he E2PAR1 bi t will be un-
affected. Consequently, the E2PAR1 bit cannot be
set if E2ENA is low. The E2PAR1 bit can be set by
the user, only if the E2ENA and E2PAR2 bits are
also set.
Notes: The EEPROM page shall not be change d
through the DRBR register when the E2PAR2 bit
is set.
EEPROM Control Register (EECTL)
Address: EAh —Read/Write
Reset status: 00h
Bit 7 = D7: Unused.
Bit 6 = E2OFF: Stand-by Enable Bit. WRITE ONLY.
If this bit is set the EEPROM is disabled (any access
will be meaningless) and the power consumption of
the EEPRO M is re d uc ed to its lowest va lue .
Bit 5-4 = D5-D4: Reserved. MUST be kept reset.
Bit 3 = E2PAR1: Parall el Start Bit. WRITE ON LY.
Once in Parallel Mode, as soon as the user software
sets the E2P AR1 bit, paral lel writing of the 8 adja-
cent registers will start. This bit is internally reset at
the end of the programming procedure. Note that
less than 8 bytes can be written if required, the un-
defined bytes being unaffected by the parallel pro-
gramming cycle; this is explained in greater detail in
the Additional Notes on Parallel Mode overleaf.
Bit 2 = E2PAR2: Parallel Mode En. Bit. WRITE
ONLY. This bit must be set by the user program in
order to perform parallel programming. If E2PA R2
is set and the parallel start bit (E2PAR1) is reset,
up to 8 adjacent bytes can be written simultane-
ously. These 8 adjacent bytes are considered as a
row, whose address lines A7, A6, A5, A4, A3 are
fixed while A2, A1 and A0 are the changing bits, as
illustrated in Figure 4. E2 PAR2 is automatically re-
set at the end of any parallel programm ing proce-
dure. It can be reset by the user software before
starting the programming procedure, thus leaving
the EEPROM registers unchanged.
Bit 1 = E2BUSY: EEPROM Busy Bit. READ ON-
LY. This bit is automatically set by the EEPROM
control logic when the EEPROM is in program-
ming mode. The user program should test it before
any EEPROM rea d or wri te o perat ion; any att emp t
to access the EEPROM while the busy bit is set
will be aborted and the writing procedure in
pro gr es s w ill b e c o m p let e d.
Bit 0 = E2ENA: EEPROM Ena bl e Bi t. WRITE ON-
LY. This bit enables programming of the EEPROM
cells. It must be set before any write to the EEP-
ROM register. Any attempt to write to the EEP-
ROM when E2E NA is low is mean ingless and will
not trigger a write cycle.
70
D7 E2O
FF D5 D4 E2PA
R1 E2PA
R2 E2BU
SY E2E
NA
14/86
ST62T55C ST62T65C/E65C
1.4 PROGRAM MING MODES
1.4.1 Option Bytes
The two Option Bytes allow configuration ca pabili-
ty to the MCUs. Opt ion byte’s co ntent is autom at i-
cally read, and the selected options enabled, when
the chip reset is activated.
It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING mode of the pro-
grammer.
The option bytes are located in a non-user map.
No address has to be specified.
EPROM Code Option Byte (LSB)
EPROM Code Option Byte (MSB)
D15-D13. Reserved. Must be cleared.
ADC SYNCHRO . When set, an A /D c onvers ion is
started upon WAIT instruction execution, in order
to reduce supply noise. When this bit is low, an A/
D conversion is started as soon a s the STA bit of
the A/D Converter Control Register is set.
D11-D10. Reser ve d , mu st be cleared.
NMI PULL. NM I Pull-Up. T h is b it mu st b e s e t h igh
to configure the NMI pin with a pull-up resistor.
When it is low , no pull-up is provided.
LVD. LVD RESET enable.When this bit is set, safe
RESET is performed by MCU when the supply
voltage is too low. When this bit is cleared, only
power-on reset or external RESET are active .
PROTECT. Readout Protection. This bit allows the
protection of the softw are conte nts aga inst piracy.
When the bit PROTECT is set high, readout of the
OTP contents is prevented by hardware.. When
this bit is low, the user prog ram can be read.
EXTCNTL. External STOP MODE control.. When
EXTCNTL is high, STOP mode is available with
watchdog active by setting NMI pin to one. When
EXTCNTL is low, STOP mode is not available with
the watchdog active.
PB2-3 PULL. When set this bit removes pull-up at
reset on PB2-PB3 pins. When cleared PB2-PB3
pins have an internal pull-up resistor at reset.
PB0-1 PULL. When set this bit removes pull-up at
reset on PB0-PB1 pins. When cleared PB0-PB1
pins have an internal pull-up resistor at reset.
WDACT. This bit controls the watchdog activation.
When it is high, hardware activation is selected.
The software activation is selected when WDA CT
is low .
DELAY. This bit enables the selection of the delay
internally generated after the internal reset (exter-
nal pin, LVD, or watchdog activated) is released.
When DELAY is low, the delay is 2048 cycles of
the oscillator, it is of 32768 cycles when DELAY is
high.
OSCIL. Oscillator selection. When this bit is low,
the oscil lator must be cont rolled by a quartz crys-
tal, a ceram ic resonator o r an ex ternal frequenc y.
When it is high, the oscillator must be controlled by
an RC network, with only the resistor having to be
externally provided.
OSGEN. Oscillator Safe Guard. This bit must be
set high to enable the Oscillator Safe Guard.
When this bit is low, the OSG is disabled.
The Option byt e is written during prog ra mming ei-
ther by using the PC menu (PC driven Mode) or
automati cally (stand-alone mod e).
70
PRO-
TECT EXTC-
NTL PB2-3
PULL PB0-1
PULL WDACT DE-
LAY OSCIL OSGEN
15 8
---ADC
SYNCHRO --
NMI
PULL LVD
15/86
ST62T55C ST62T65C/E65C
PROGRAMMING MODES (Cont’d)
1.4.2 EPROM Erasing
The EPROM of the windowed package of the
MCUs may be erased by exposure to Ultra Violet
light. The erasure characteristic of the MCUs is
such that erasure begins when the m emory is ex-
posed to li ght with a wave lengths shorter t han ap-
proximately 4000Å. It should be noted that sun-
lights and some types of fluorescent lamps have
wavelengths in the range 3000-4000Å.
It is thus recommended that the window of the
MCUs packages be covered by an opaque label to
prevent unintentional erasure problems when test-
ing the application in such an environment.
The recommended erasure procedure of the
MCUs EPROM is the exposure to short wave ul-
traviolet light which have a wave-length 2537A.
The integrated dose (i.e. U.V. intensity x exposure
time) for erasure should be a minimum of 15W-
sec/cm2. T he eras ure tim e with t his do sage is ap-
proximately 15 to 20 minutes using an ultraviolet
lamp with 12000µW/cm2 power rating. The
ST62 E65 C should be placed within 2.5 cm (1Inch)
of the lamp tubes during erasure.
16/86
ST62T55C ST62T65C/E65C
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communi ca ting with on -chip I/O, Mem ory and Pe-
ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip pe-
ripherals via the s erial data bus and indi rectly, f or
interrupt purposes, through the control registers.
2.2 CPU REGISTERS
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The a ccumula tor can be a ddressed in Dat a
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Indirec t Registers (X, Y). These t wo indi rect reg-
isters are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad-
dressed in the data space as RAM locations at ad-
dresses 80h (X) and 81h (Y). They can also be ac-
cessed with the direct, short direct, or bit direct ad-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect regi sters as any other reg-
ister of the data spac e.
Short Direct Re gisters (V, W). These two regis-
ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W ). They c an al so be acc essed us in g th e di-
rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
ters as any other register of the data space.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper-
and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
Figure 6. ST6 Core Block Diagram
PROGRAM
RESET
OPCODE FLAG
VALUES 2
CONTROLLER
FLAGS ALU
A-DATA B-DATA
ADDRESS/READ LINE
DATA SPACE
INTERRUPTS
DATA
RAM/EEPROM
DATA
ROM/EPROM
RESULTS TO DATA SPACE (WRITE LINE)
ROM/EPROM
DEDICATIONS
ACCUMULATOR
CONTROL
SIGNALS
OSCin OSCout
ADDRESS
DECODER 256
12 Pr ogram Co unter
and
6 LAYER STAC K
0,01 TO 8MHz
VR01811
17/86
ST62T55C ST62T65C/E65C
CPU REGISTERS (Cont’d)
However, if t he program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch re gister.
The PC value is incremented after reading the ad-
dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where th ey are added; the result is then
shifted back into the PC. The program counter can
be changed in the following ways:
- JP (Jump) instructionPC=Jump address
- CALL instructionPC= Call address
- Relative Branch Instruction.PC= PC +/- offset
- Interrupt PC=I nterrup t vector
- Reset P C= Reset vector
- RET & RETI instructionsPC= Pop (stack)
- Normal instructionPC= PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of o peration:
Normal mode, Interrupt mode and Non Maskabl e
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal ope ration, another pair is used dur-
ing Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZN-
MI).
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses t he Interrupt flags (resp. the NM I flags )
instead of the Normal flags. When the RETI in-
struction is executed, the previously used set of
flags is restored . It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main rou-
tine). The flags are not cleared during context
switching and thus retain their status.
The Carry flag is set when a carry or a borrow oc -
curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also partici-
pates in the ro tate left instruction.
The Zero flag is set if the result of t he last arithme-
tic or logical operation was equal to zero; other-
wise it is cleared.
Switching between the three sets of flags is per-
formed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is
automatic ally selected after the reset of the MCU,
the ST6 core uses at first the NMI flags.
Stack. The ST6 CPU includes a true LIFO hard-
ware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call (or inter-
rupt request) occurs, the contents of each level are
shifted into the next higher level, while the content
of the P C is shifted into the first level (the origi nal
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted bac k
into the PC and the value of ea ch level is popped
back into the previous level. Since the accumula-
tor, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subrou-
tine . Th e s tac k w ill r emain in its “deepest” posit io n
if more than 6 nested calls or interrupts are execut-
ed, and consequently the last return address will
be lo st. It will also re main in it s highe st posit ion if
the stack is empty and a RET or RETI is executed.
In this case the next instruction will be executed.
Figu re 7. ST6 CPU Pr ogram m in g M ode
l
SHORT
DIRECT
ADDRESSING
MODE
VREGISTER
WREGISTER
PROGRAM COUNTER
SIX LEVELS
STACK REGISTER
CZNORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
INDEX
REGISTER
VA000423
b7
b7
b7
b7
b7
b0
b0
b0
b0
b0
b0b11
ACCUMULATOR
Y REG. POINTER
X REG. POINTER
CZ
CZ
18/86
ST62T55C ST62T65C/E65C
3 CLOCK S, RESET , INTERRUP TS AND POWER SAVING MODES
3.1 CLOCK SYSTEM
The M C U f ea tu r e s a Main Os c illator w hic h c a n be
driven by an external clock, or used in conjunction
with an AT -cut para llel resonant crystal or a s uita-
ble cerami c resonat or, or with an e xternal resist or
(RNET). In addition, a Low Frequency Auxiliary Os-
cillator (LFAO) can be switched in for security rea-
sons, to reduce power consumption, or to offer the
benefits of a back-up clock syst em.
The Oscillator Safeguard (OSG) option filters
spikes from the oscillator li nes, provides access to
the LFAO to provide a backup oscillator in the
event of m ain osc illator failure and also automati-
cally limits the internal clock frequency (fINT) as a
function of VDD, in order to guarantee correct oper-
ation. These functions are illustrated in Figure 9,
Figure 10, Figure 11 and F igure 12.
A programmable divider on FINT is also provided in
order to adjust the internal clock of the MCU to the
best power consumption and performance trade-
off.
Figure 8 illu s trates vario us p os si b le o s c illator c on -
figurations using an external crystal or ceramic res-
onator, an external clock input, an external resistor
(RNET), or the lowest cost solution using only the
LFAO. CL1 an CL2 should have a capacitance in the
range 12 to 22 pF for an oscillator frequency in the
4-8 MHz range.
The internal MCU clock frequency (fINT) is divided
by 12 to drive the Timer, the A/D converter and the
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 11.
With an 8MHz oscillator frequency, the fastest ma-
chine cycle is therefore 1.625µs.
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment
the Program Counter). An instruction may requi re
two, four, or five machine cycles for execution.
3.1.1 Main Oscillator
The oscillator configuration may be specified by se-
lecting the appropriate option. When the CRYSTAL/
RESONATOR option is selected, it must be used with
a quartz crystal, a ceramic resonator or an external
signal provided on the OSCin pin. When the RC NET-
WORK opti on is selec ted, the syst em clock i s gen-
erated by an external resistor.
The main oscillator can be turned off (when the
OSG EN A BLED option is se lected ) by setti ng the
OSCOFF bit of the ADC Control Register. The
Low Frequenc y Auxiliary Oscillator is automatica l-
ly started.
Figu re 8. Os cill a tor C on f ig uration s
INTEGRATED CL OCK
CRYSTAL /R ESO NATO R option
OSG ENABLED option
OSCin OSCout
CL1n CL2
ST6xxx
CRYSTAL /R ESO NATO R CLOCK
CRYSTAL /R ESO NATO R option
OSCin OSCout
ST6xxx
EXT ERNAL CL OCK
CRYSTAL /R ESO NATO R option
NC
OSCin OSCout
ST6xxx
NC
OSCin OSCout
RNET
ST6xxx
RC NETWORK
RC NETWORK opti on
NC
19/86
ST62T55C ST62T65C/E65C
CLOCK SYSTEM (Cont’d)
Turning on the main oscillator is achieved by re-
setting the OSCOFF bit of the A/D Converter Con-
trol Register or by resetting the MCU. Restarting
the main oscillator implies a delay comprising the
oscillator start up delay period plus the duration of
th e soft wa re instru ction at fLFAO clock frequency.
3.1.2 Low Frequency Auxiliary Oscillator
(LFAO)
The Low Frequency Auxiliary Oscillator has three
main purposes. Firstly, it can be used to reduce
power consum ption in non timin g critical routines.
Secondly, it offers a fully integrated system clock,
without any external components. Lastly, it acts as
a safety oscillator in c ase of main oscillator failure.
This oscillator is available when the OSG ENA-
BLED option is selected. In this case, it automat i-
cally starts one of its periods after the first missing
edge from the main oscillator, whatever the reason
(main oscillator defective, no clock circuitry provid-
ed, main os c illator sw it ched off .. .).
User code, normal interrupts, WAIT and S TO P in-
structions, are processed as normal, at the re-
duced fLFAO frequency. The A/D converter accura-
cy is decreased, since the internal frequency is be-
low 1MHz.
At power on, the Low Frequenc y Auxiliary Osc ill a-
tor starts faster than the Main Oscillator. It there-
fore feeds the on-chip counter generating the POR
delay until the Main Oscillator runs.
The Low Frequency Auxiliary Oscillator is auto-
matically switched off as soon as the main oscilla-
tor s ta rt s.
ADCR
Address: 0D1h —Read/Write
Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:
ADC Control Register. These bits are reserved for
ADC Control.
Bi t 2 = OSCOFF. When low, t his bi t enables m ai n
oscillator to run. The main oscillator is switched off
when OSCOF F is high.
3.1.3 Oscillator Safe Guard
The Oscillator Safe Guard (OSG) affords drastical-
ly increased op erational in tegrity in ST 62xx devic-
es. The OSG circuit provides three basic func-
tions: it filters spikes from the oscillator lines which
would result in over frequency to the ST62 CPU; i t
gives access to the Low Frequency Auxiliary Os-
cillator (LFAO), used to ensure minimum process-
ing in case of main oscillator failure, to offer re-
duced power consumption or to provide a fixed fre-
quency low cost oscillator; finally, it automatically
limits the internal clo ck frequency as a f unction of
supply voltage, in order to ensure correct opera-
tion even if the power supply sho uld drop.
The O SG is enabled or disab led by choosin g the
relevant O SG option. It may be v iewed as a filter
whose cross-over freq uency is device dependent .
Spikes on the oscillator lines result in an effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over fre-
quency for a given power supply voltage. The
OSG filters out such spikes (as illustr ated in Figure
9). In all cases, when the OSG is active, the maxi-
mum internal clock frequency, fINT, is limited to
fOSG, w hich is sup ply voltage depend ent. This re-
lationship is illustrated in Figure 12.
When the OSG is enabled, the Low Frequency
Auxiliary Oscillator may be accessed. This oscilla-
tor starts operating after the first missing edge of
the main oscillator (see Figure 10).
Over-frequency, at a given power supply level, is
seen by the OS G as spikes; it therefore filters out
some cycles in order that the internal clock fre-
quency of the device is kept within the range the
particular device can stand (depending on VDD),
and below fOSG: the maximum authorised frequen-
cy with OSG enab led.
Note. The OSG should be used wherever possible
as it provid es ma ximu m safet y. Care must be tak-
en, however, as it can increase power consump-
tion and reduce the maximum operating frequency
to fOSG.
Warning: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and a maximum value and is not accu-
rate.
For prec ise tim ing mea suremen ts, it is not reco m-
mended t o use the OSG and it should not be ena-
bled in applications that use the SP I or the UART.
It should also be noted t hat power cons um ption in
Stop mode is higher when the OSG is enabled
(around 50µA at nominal conditions and room
temperature ).
70
ADCR
7ADCR
6ADCR
5ADCR
4ADCR
3OSC
OFF ADCR
1ADCR
0
20/86
ST62T55C ST62T65C/E65C
CLOCK SYSTEM (Cont’d)
Figu re 9. OSG Fi l te rin g P rin c i pl e
Figure 10. OSG Emergency Oscillator Principle
(1)
VR001932
(3)
(2)
(4)
(1)
(2)
(3)
(4)
Maximum Frequency for the device to work correctly
Actual Quartz Crystal Frequency at OSCin pin
Noise from OSCin
Resulting Internal Frequency
Main
VR001933
Internal
Emergency
Oscillator
Frequency
Oscillator
21/86
ST62T55C ST62T65C/E65C
CLOCK SYSTEM (Cont’d)
Oscillator Control Registers
Address: DCh —Write only
Reset State: 00h
Bit 7-4. Thes e bits are not used.
Bit 3. Reserved. Cleared at Reset. Must be kept
cleared.
Bit 2. Reserved. Must be kept low.
RS1-RS0. These bits select the division ratio of
the Oscillator Divider in order to generate the inter-
nal frequency. The following selctions are availa-
ble:
Note: Care is required when handling the OSCR
register as some bits are write only. For this rea-
son, it is not allowed to change the OSCR contents
while executing interrupt service routine, as the
service routine cannot save and then restore its
previous content. If it is impossible to avoid the
writing of this register in interrupt service routine,
an image of this reg ister must be saved in a RAM
location, and each time the program writes to
OSCR it must write also to the image register. The
image register must be written first, so if an inter-
rupt occurs between the two instructions the
OSCR is not affected.
70
----
OSCR
3-RS1RS0
RS1 RS0 Division Ratio
0
0
1
1
0
1
0
1
1
2
4
4
22/86
ST62T55C ST62T65C/E65C
CLOCK SYSTEM (Cont’d)
Figure 11. Clock Circuit Block Diagram
Figure 12. M axi m um Ope rating Fr equency (fMAX) versus Supply Voltage (VDD)
Notes:
1. In this area, operation is guaranteed at the
quartz crystal frequency.
2. When the OSG is disabled, operation in this
area is guaranteed at the crystal frequency. When
the OSG is enabled, operation in this area is guar-
anteed at a frequency of at least fOSG Min.
3. When the OSG is disabled, operation in this
area is guaranteed at the quartz crystal frequency.
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept a fOSG.
4. When the OSG is disabled, operation in this
area is not guaranteed
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept at fOSG.
MAIN
OSCILLATOR
OSG
LFAO
M
U
X
Core
: 13
: 12
: 1
TIMER 1
Watchdog
POR
fINT
Main Oscillator off
OSCILLATOR
DIVIDER
RS0,RS1
12.5 3.644.555.56
8
7
6
5
4
3
2
Maximum FREQUENCY (MHz)
SUPPL Y VOLTAG E (VDD)
FUNCTIONAL ITY IS NOT
3
43
2
1
fOSG
fOSG Mi n (at 85°C)
GUARANTEED
IN THIS AREA
VR01807J
fOSG Min (at 125°C)
23/86
ST62T55C ST62T65C/E65C
3.2 RESETS
The MCU can be reset in four ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
– by the digital Watchdog periph eral timing out.
– by Low Voltage Detection (LVD)
3.2.1 RESET Input
The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
the RESET pin are acceptable, prov ided VDD has
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as th e
RESET pin is held lo w.
If RESET activation occurs in the RUN or WAIT
modes, processing of the user program is s topped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors and the
mai n O s c illator is restar ted. Wh en th e le v el o n the
RESET pin then goes high, the initialization se-
quence is executed following expiry of the internal
delay period.
I f RESET pin activation occurs in the STOP mode,
the oscill ato r s tarts up a nd a ll Inputs and Out puts
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes h igh,
the initialization sequence is executed following
expiry of the internal delay period.
3.2.2 Power-on Res et
The function of the POR circuit consists in waking
up the MCU by detecting around 2V a dynamic
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured
in the Reset state: all I/O ports are configured as
inputs with pull-up resistors and no instruction is
executed. When the power supply voltage rises to
a sufficient level, the oscillator starts to operate,
whereupon an internal delay is initiated, in order to
allow the oscillator to fu lly stabil ize b efo re exec ut -
ing the first instruction. The initialization sequenc e
is executed immediately following the internal de-
lay.
To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi-
cient level for the chosen frequency (see recom-
mended operation) before the reset signal is re-
leased. In addition, supply rising must start from
0V.
As a consequence, the POR does not allow to su-
pervise static, slowly rising, or falling, or noisy
(pr es e nt in g o s c illation) VDD supp lies.
An external RC network connected to the RESET
pin, or the LVD reset can be used instead to get
the best performances.
Figure 13. Reset and Interru pt Processing
INT LATCH CLEARED
NMI MASK SE T
RESET
( IF PRESENT )
SELECT
NMI MODE FLAG S
IS RESET STILL
PRESENT?
YES
PUT FFEH
ON ADDRESS BUS
FROM RESET LOCATIONS
FFE/FFF
NO
FETCH INSTRUCTIO N
LOAD PC
VA000427
24/86
ST62T55C ST62T65C/E65C
RESETS (Cont’d)
3.2.3 Watchdog Reset
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will b e activ ated. This, am ongst oth-
er things, rese ts the watchdog counter.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built - in s tabilis a t io n d elay period .
3.2.4 LVD Reset
The on-chip Low Voltage Detector, selectable as
user option, features static Reset when supply
voltage is belo w a reference value. Thanks to this
feature, external reset circuit can be removed
while keeping the application safety. This SAFE
RESET is effective as well in Power-on phase as
in power supply drop with different reference val-
ues, allowing hysteresis effect. Reference value in
case of voltage drop has been set lower than the
reference value for power-on in order to avoid any
parasitic Reset when MCU start's running and
sinking current on the supply.
As long as the supply voltage is below the refer-
ence value, there is a internal and static RESET
comma nd. The M CU ca n start only when the s up-
ply voltage rises over the reference value. There-
fore, only two operating mode exist for the MCU:
RESET active below the voltage reference, and
running mode over the voltage reference as
shown on the Figu re 14 , that represents a power-
up, power-down sequence.
Note: When the RESE T state is controll ed by one
of the internal RESET sources (Low Voltage De-
tector, Watchdog, Power on Reset), the RESET
pin is tied to low logic level.
Figure 14. LVD Reset on Power-on and Power-down (Brown-out)
3.2.5 Application No tes
No external resistor is required between V DD an d
the Reset pin, thanks to the built-in pull-up device. Direct external connection of the pin RESET to
VDD must be avoided in order to ensure safe be-
haviour of the internal reset sources (AND.Wired
structure).
RESET
RESET
VR02106A
time
VUp
Vdn
VDD
25/86
ST62T55C ST62T65C/E65C
RESETS (Cont’d)
3. 2. 6 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, how-
ever, a pending interrupt is present, it will be serv-
iced.
Figure 15. Reset and Interru pt Processing
Figure 16. Reset Bl ock Diagra m
RESET
RESET
VECTOR
JP JP:2 BYTES/4 CYCLES
RETI RETI: 1 BYTE/2 CYCLES
INITIALIZATION
ROUTINE
VA00181
VDD
RESET
RPU
RESD1)
POWER
WATCHDOG RESET
CK
COUNTER
RESET
ST6
INTERNAL
RESET
fOSC
RESET
ON RESET
LVD RESET
VR02107A
AND. Wired
1) Resistiv e E S D prot ectio n. Val ue not gu arant eed.
26/86
ST62T55C ST62T65C/E65C
RESETS (Cont’d)
Table 5Register Reset Status
Register Address(es) Status Comment
Oscillator Control Register
EEPROM Control Register
Port Data Registers
Port Direction Register
Port Option Register
Interrupt Option Register
TIMER Status/Control
AR TIMER Mode Control Register
AR TIMER Status/Control 0 Register
AR TIMER Status/Control 1 Register
AR TIMER Compare Register
AR TIMER Load Register
Miscellaneous Register
SPI Registers
SPI DIV Register
SPI MOD Register
SPI DSR Register
0DCh
0EAh
0C0h to 0C2h
0C4h to 0C6h
0CCh to 0CEh
0C8h
0D4h
0D5h
0D6h
0D7h
0DAh
0DBh
0DDh
0E0h to 0E2h
0E1h
0E2h
0E0h
00h
00h
00h
00h
00h
00h
00h
00h
02h
00h
00h
00h
00h
00h
00h
00h
Undefined
EEPROM disabled (if available)
I/O are Input with pull-up
I/O are Input with pull-up
I/O are Input with pull-up
Interrupt disabled
TIMER disabled
AR TIMER stopped
SPI Output not connected to PC3
SPI disabled
SPI disabled
SPI disabled
SPI disabled
X, Y, V, W, Register
Accumulator
Data RAM
Data RAM EEPROM Page Register
Data ROM Window Register
EEPROM
A/D Result Register
AR TIMER Load Register
AR TIMER Reload/Capture Register
080H TO 083H
0FFh
084h to 0BFh
0E8h
0C9h
00h to 03Fh
0D0h
0DBh
0D9h
Undefined As written if programmed
TIMER Counter Register
TIMER Prescaler Register
Watchdog Counter Register
A/D Control Register
0D3h
0D2h
0D8h
0D1h
FFh
7Fh
FEh
40h
Max count loaded
A/D in Standby
27/86
ST62T55C ST62T65C/E65C
3.3 DIGITAL WATCHDOG
The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recovery from software upsets.
The Watchdog circuit generates a Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. In the event of a software mishap (usual-
ly caused by externally generated interference),
the user program will no l onger behave in i ts usual
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will
decrement do wn to 00h and reset the M CU. In or-
der to maximise the effectiveness of the Watchdog
function, user software must be written with this
concept in mind.
Watchdog behaviour is governed by two options,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (see Table 6).
In the SOFTWARE option, the W atchdog is d isa-
bled until bit C of the DWDR register has been set.
When the Watchdog is disabled, low power Stop
mode is available. Once activated, the Watchdog
cannot be disabled , except by resetting the MCU.
In the HARDWARE option, the Watchdog is per-
manently enabled. Since the oscillator will run con-
tinuously, low power mode is not available. The
STOP ins truction is inte r pr et e d a s a WAI T in s tru c -
tion, and the Watchdog cont inues to countdown.
However, when the EXTERNAL STOP MODE
CONTROL option has been selected low power
consum ption ma y be achieved in Stop Mode.
Execution of the STOP instruction is then gov-
erned by a secondary function associated with the
NMI pin. If a STOP instruction is encountered
when the NMI pin is low, it is interpreted as WAIT,
as described above. If, however, the STOP in-
struction is encountered when the NMI pin is high,
the Watchdog counter is frozen and the CPU en-
ters STOP mode.
When the MCU exits STOP mode (i.e. when an in-
terrupt is generated), the Watchdog resumes its
activity.
Table 6. Recomm en ded Option Choices
Functions Required Recommended Options
Stop Mode & Watchdog “EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”
Stop Mode “SOFTWARE WATCHDOG”
Watchdog “HARDWARE WATCHDOG”
28/86
ST62T55C ST62T65C/E65C
DIGITAL WATCHDOG (Cont’d)
The Watchdog is associated with a Data space
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.3.1 Digital Watchdog Register (DWDR).
This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the
timer downcounter bits, T0 to T5, and the SR bit
are all set to “1”, thus selecting the longest Watch-
dog timer period. This time period can be set to t he
user’s requirements by setting the appropriate val-
ue for bits T0 to T5 in the DWDR register. The SR
bit must be set to “1”, since it is this bit which gen-
erates the Reset signal when it changes to “0”;
clearing this bit woul d generate an i mmedia te Re-
set.
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the
DWDR register corresponds , in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bits are i nverted and shifted with respect to
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
bits and the physical implementation of the Watch-
dog timer downcounter is illustrated in F igure 17.
Only the 6 most significant bits may be used to de-
fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator
frequency of 8MHz, this is equivalent to ti mer peri-
ods ranging from 384µs to 24.576ms).
Figure 17. Watchdog Counter Control
WATCHDOG CONTROL REGIS TER
D0
D1
D3
D4
D5
D6
D7
WATCHDOG COUNTER
C
SR
T5
T4
T3
T2
T1
D2
T0
OSC ÷12
RESET
VR02068A
÷28
29/86
ST62T55C ST62T65C/E65C
DIGITAL WATCHDOG (Cont’d)
3.3.1 Digital Watchdo g Register (DWDR)
Address: 0D8h —Read/Write
Reset status: 1111 1110b
Bi t 0 = C: Watc hdog Control bit
If the hardware option is selected, this bit is forced
high and the user cannot change it (the Watchdog
is a lways active). When t he software option is se-
lected, th e Watchd og function is activated by set -
ting bit C to 1, and cannot then be disabled (sav e
by resetting the MCU).
When C is kept low the count er can be us ed as a
7-bit timer.
This bit is cleared to “0” on Reset.
Bi t 1 = SR: Software Reset bit
This bit triggers a Reset when cleared.
When C = “0” (Watchdog disabled) it is the MSB of
the 7-bit timer.
This bit is set to “1” on Reset.
Bits 2-7 = T5-T0: Downcounter bits
It should be noted that the register bits are re-
versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog
downcounter and bit-2 (T5) is the MSB .
These bits are set to “1” on Reset.
3.3.2 Application Notes
The Wat chdog plays an i mportant support ing role
in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog re-
lated options s hou ld be select ed o n t he basis of a
trade-off between application security and STOP
mode av ailabilit y.
When S T OP m ode is not requ ired, ha rd ware a cti-
vation without EXTERNAL STOP MODE CON-
TROL should be preferred, as it provides maxi-
mum security, especially during power-on.
When STOP mode is required, hardware activa-
tion and EXTERNAL STOP MODE CONTROL
should be chos en. NM I s houl d be high by default,
to allow STOP mode to be entered when the MCU
is idle .
The NMI pin can be c onnected to an I/O line (see
Figure 18) to allow its state to be controlled by soft-
ware. The I/O line can then be used to keep NMI
low while Watchdog protection is required, or to
avoid noise or key bounce. When no more
processing is required, the I/O li ne is rel eased and
the device placed in STOP mode for lowest power
consumption.
When software activation is selected and the
Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
bits are in reverse order).
The software activation option should be chosen
only when the Watchdog c ounter is to be used as
a timer. To ensure the Watchdog has not been un-
expectedly activated, the following instructions
should be executed within the first 27 instruction s:
jrr 0, WD, #+3
ldi WD, 0FDH
70
T0 T1 T2 T3 T4 T5 SR C
30/86
ST62T55C ST62T65C/E65C
DIGITAL WATCHDOG (Cont’d)
These instructions test the C bit and Reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
In all modes, a minimum of 28 instructions are ex-
ecuted after activation, before the Watchdog can
generate a Reset. Consequently, user software
should load the watchdog counter within the first
27 instructions following Watchdog activation
(software mode), or wi thin the first 27 instruc tions
executed following a Reset (hardware activation).
It should be noted that when the GEN bit is low (in-
terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.
Figure 18. A typical circuit making use of the
EXERNAL STOP MODE CONTROL feature
Figu re 19. D i gi ta l Wat chdo g B lo ck Diagram
NMI
SWITCH
I/O
VR02002
RSFF
8
DATA BUS VA00010
-2 -12
OSCILLATOR
RESET
WRITE
RESET
DB0
R
S
Q
DB1.7 SETLOAD
78
-2
SET
CLOCK
31/86
ST62T55C ST62T65C/E65C
3.4 INTERRUPTS
The CPU can manage four Maskable Interrupt
sources, in addition to a Non Maskable Interrupt
source (top priori ty interrupt). Each s ource i s asso-
ciated with a specific Interrupt Vector which con-
tains a Jump instruction to the associated interrupt
service routine. These vectors a re located i n Pro-
gram space (see Table 7).
When an interrupt source generates an interrupt
request, and interrupt processing is enabled, the
PC register is loaded with the address of the inter-
rupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt serv-
ice rou tine, thus servicing the interrupt.
Interrupt sources are linked to events either on ex-
ternal pins, or on chip periphe rals. Severa l events
can be ORed on the same interrupt source, and
relevant flags are available to determine which
event triggered the interrupt.
The Non Maskable Interrupt request has the high-
est priority and can interrupt any interrupt rou tine
at any time; the other four interrupts cannot inter-
rupt each other. If more than one interrupt request
is pending, these are proces sed by the proces sor
core according to their priority level: source #1 has
the higher priority while source #4 the lower. The
priority of each interrupt source is fixed.
Table 7. Interrupt Vector Map
3.4.1 Interrupt request
All interrupt sources but the Non Maskable Inter-
rupt source can be disabled by setting accordingly
the GEN bit of the Interrupt Option Register (IOR).
This GEN bit also defines if an interrupt source, in-
cluding the Non Maskable Interrupt source, can re-
start the MCU from STOP/WAIT modes.
Interrupt request fr om the Non M askable Interrupt
source #0 is lat ched by a flip flop which is automat-
ically reset by the core at the beginning of the non-
maskable interrupt service routine.
Interrupt request from source #1 can be config-
ured either as edge or level sensitive by setting ac-
cordingly the LES bit of the Interrupt Option Regis-
ter (IOR).
Interrupt request from sourc e #2 are always edge
sensitive. T he e dge polarity can be configured by
sett ing acco rdingl y the ESB bit of the Int erru pt Op-
tion Register (IOR).
Interrupt request from sources #3 & #4 are level
sensitive.
In edge sensitive mode, a latch is set when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started.
So, the occurrence of an interrupt can be stored,
until completion of the running interrupt routine be-
fore being proc esse d. If several interrupt reques ts
occurs before completion of the running interrupt
routine, only the first request is stored.
Storage of interrupt requests is not available in lev-
el sensitive mode. To be taken into account, the
low level m ust be present on the interrupt pin when
the MCU sa mples the line after instruction execu-
tion.
At the end of every instruction, th e MCU tests the
interrupt lines: if there is an interrupt request the
next instruction is not executed and the appropri-
ate interrupt service routine is executed instead.
Table 8. Interrupt Option Register Description
Interrupt Source Priority Vector Address
Interrupt source #0 1 (FFCh-FFDh)
Interrupt source #1 2 (FF6h-FF7h)
Interrupt source #2 3 (FF4h-FF5h)
Interrupt source #3 4 (FF2h-FF3h)
Interrupt source #4 5 (FF0h-FF1h) GEN SET Enable all interrupts
CLEARED Disable all interrupts
ESB SET Rising edge mode on inter-
rupt source #2
CLEARED Falling edge mode on inter-
rupt source #2
LES SET Level-sensitive mode on in-
terrupt source #1
CLEARED Falling edge mode on inter-
rupt source #1
OTHERS NOT USED
32/86
ST62T55C ST62T65C/E65C
INTERRUPTS (Cont’d)
3.4.2 Interrupt Procedure
The interrupt procedure is very similar to a call pro-
cedure, indeed the user can consider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context and the tim e at which i t occurred. A s a re-
sult, the user should save all Data space registers
which may be used within the interrupt routines.
There are separate sets of processor flags for nor-
mal, interrupt and non-maskable interrupt modes,
which are automatically switched and so do not
need to be saved.
The following list summarizes the interrupt proce-
dure:
MCU
– The interrupt is detected.
– The C and Z flags are replaced by the interrupt
fla gs (or by the NMI flags).
– The PC content s are stored in the first level of
th e stack.
– The normal interrupt lines are inhibited (NMI still
active).
– The first internal latch is cleared.
– The associated interrupt vector is loaded in the PC.
WARNING: In some circumstances, when a
maskable interrupt occurs while the ST6 core is in
NORMAL m ode and especially during the execu-
tion of an "ldi IOR, 00h" instruction (disabling all
maskable interrupts): if the interrupt arrives during
the first 3 cycles of the "ldi" instructio n (wh ich is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to
the interrupt pair CI and ZI.
User
– User selected registers are saved within the in-
terrupt service routine (normally on a software
stack).
– The source of the interrupt is found by polling the
interrupt flags (if more than one source is associ-
at ed with the same vector).
– The interrupt is serviced.
– Return from interrupt (RETI)
MCU
– Automatically the MCU switches back to the nor-
mal flag set (or the inte rrupt flag set) and pops
the previous PC value from the stack .
The interrupt rout ine usually begins by the identify-
ing the device which generated the interrupt re-
quest (by polling). The user should save the regis-
ters which are used within the int errupt routine in a
software stack. After the RETI instruction is exe-
cuted, the MCU returns to the main routine.
Figure 20. Interrupt Processing Flow Chart
INSTRUCTION
FETCH
INSTRUCTION
EXECUTE
INSTRUCTION
WAS
THE INSTRUCTION
A RETI ?
?
CLEAR
INTERRUPT MASK
SELECT
PROGRAM FLAGS
"POP"
THE STACKED PC
?CHECK IF THERE IS
AN INTERRUPT REQUEST
AND INTERRUPT MASK
SELECT
INTERNAL MODE FLAG
PUSH THE
PC INTO THE STACK
LOAD PC FROM
INTERRUPT VECTOR
(FFC/FFD)
SET
INTERRUPT MASK
NO
NO
YES IS TH E CORE
ALREADY IN
NORMAL MODE?
VA000014
YES
NO
YES
33/86
ST62T55C ST62T65C/E65C
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Regi ster (IOR )
The Interrupt Opt ion Register (IOR ) is used to en-
able/disable the individual interrupt sources and to
select the o perating mo de of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h —Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused.
Bi t 6 = LES: Level/Edge Selecti on bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 = ESB: Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enable d. W hen this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
Whe n the GEN bit is low, the NMI int errupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Interrupt sources available on these MCUs are
summarized in the Table 9 with associated mask
bit to enable/disable the interrupt request.
Table 9Interr upt Req uests and Mas k Bits
70
- LES ESB GEN - - - -
Peripheral Register Address
Register Mask bit Masked Interrupt Source Interrupt
vector
GENERAL IOR C8h GEN All Interrupts, excluding NMI
TIMER TSCR1 D4h ETI TMZ: TIMER Overflow Vector 4
A/D CONVERTER ADCR D1h EAI EOC: End of Conversion Vector 4
AR TIMER ARMC D5h OVIE
CPIE
EIE
OVF: AR TIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin Vector 3
SPI SPIMOD E2h SPIE SPRUN: End of Transmission Vector 2
Port PAn ORPA-DRPA C0h-C4h ORPAn-DRPAn PAn pin Vector 1
Port PBn ORPB-DRPB C1h-C5h ORPBn-DRPBn PBn pin Vector 1
Port PCn ORPC-DRPC C2h-C6h ORPCn-DRPCn PCn pin Vector 2
34/86
ST62T55C ST62T65C/E65C
INTERRUPTS (Cont’d)
Figu re 21 Int erru pt Blo ck Diag ram
Start
1
I
QCLK
CLR
FF
1
0
MUX
IOR REG . C8 H, bit 6
IOR REG. C8H, bit 5
FF
CLR
CLK Q
I2Start
TIMER1
CPIE
CPF
TMZ
ETI IN T # 4 (F F0 ,1 )
IN T # 3 (F F2 ,3 )
IN T # 2 (F F4 ,5 )
IN T # 1 (F F6 ,7 )
RESTAR T FROM
STOP/WAIT
AR TIMER
EF
EIE
OVF
OVIE
VA0426K
PBE
Bits
Bits
PORT B
PORT A PBE
PBE
DD
V
SIN GL E BI T ENAB L E
F ROM REGISTER PORT A,B,C
PORT C
SP IN T bi t
Start
0
I
QCLK
CLR
FF
Bit GEN (IOR Register)
NMI (FFC,D)
NMI
VDD
ADC EOC
EAI
SPIE bit
SPIDIV Register
SPIM O D Register
35/86
ST62T55C ST62T65C/E65C
3.5 POWER SAVING MODES
The WAIT and STOP modes have been imple-
mented in the ST62xx family of MCUs in order to
reduce the product’s electrical consumption during
idle periods. These two power saving modes are
described in the follo wing paragraph s.
3.5.1 WAIT Mode
The MCU goes into WAIT mode as soon as the
WAIT instruction is executed. The microcon troller
can be cons ide red as being in a “software frozen”
state where the core stops processing the pro-
gram instructions, the RAM contents and peripher-
al registers are preserved as long as the power
supply voltage is higher than the RAM retention
voltage. In this mode the peripherals are still ac-
tive.
WAIT mode can be used when the user wants to
reduce the MCU power consumption during idle
periods, while not losing track of time or the ca pa-
bility of monitoring ex ternal events. The ac tive os -
cillator is not stopped in order to provide a clock
signal to the peripherals. Timer counting may be
enabled as well as the Timer interrupt, before en-
teri ng the WAIT mode: this allows the WAIT mode
to be exited when a Timer interrupt occurs. The
same applies to other peripherals which use the
clock signal.
If the WAIT mode is exited due to a R eset (either
by activating the external pin or generated by the
Watchdog), the MCU enters a normal reset proce-
dure. If an interrupt is generated during WAIT
mode, the M CU’s behaviour depends on the stat e
of the processor core prior to the WAIT instr uction,
but also on the kind of interrupt request which is
genera ted. This is described in the following para-
graphs. The processor core does not generate a
delay following the occurrence of the interrupt, be-
cause the oscillator clock is still available and no
stabilisation period is necessary.
3.5.2 STOP Mode
If the Watchdog is disabled, STOP mode is availa-
ble. When in STOP mode, the MCU is placed in
the lowest power consumption mode. In this oper-
ating mode, the microcontroller can be considered
as being “frozen”, no instruction is executed, the
oscillator is stopped, the RAM contents and pe-
ripheral registers are preserved as long as the
power supply voltage is higher than the RAM re-
tention voltage, and th e ST62xx core waits for the
occurrence of an external interrupt request or a
Reset to exit the STOP state.
If the STOP state is exited due to a Reset (by acti-
vating the external pin) the MCU will enter a nor-
mal reset procedure. Behav iour in response to in-
terrupts depends on the state of the processor
core prior to issuing the STOP instruction, and
also on the kind of interrupt request that is gener-
ated.
This case will be described in the following para-
graphs. T he proces sor core generat es a de lay af-
ter occurrence of the i nterrupt reque st, in order to
wait for complete stabilisation of the oscillator, be-
fore executing the first instruction.
36/86
ST62T55C ST62T65C/E65C
POWER SAVING MODE (Cont’d)
3.5.3 Exit from WAIT and STOP Modes
The following paragraphs describe how the MCU
exits from WAIT and STOP modes, when an inter-
rupt occurs (not a Reset). It should be noted that
the restart sequence depends on the original state
of the MCU (normal, interrupt or non-maskable in-
terrupt mode) prior to entering WAIT or STOP
mode, as well as on the interrupt type.
Interrupts do not affect the oscillator selection.
3.5.3.1 Normal Mode
If the MCU was in the main routine when the WAIT
or STOP instruc tion was executed, exit from Sto p
or Wait mode will occur as soon as an interrupt oc-
curs; the related interrupt ro utine is exec uted and,
on completion, the instruction which follows the
STOP or WAIT instruction is then executed, pro-
viding no other interrupts are pending.
3.5.3.2 Non Maskable Interrupt Mode
If the STO P or WA IT inst ruction has been execut -
ed during exec ution of the n on-ma skab le interrupt
routine, the MCU exits from the Stop or Wait mode
as soon as an interrupt occurs: the instruction
which follows the STOP or WAI T instruction is ex-
ecuted, and the MCU remains in non-maskable in-
terrupt mode, even if another interrupt has been
generated.
3.5.3.3 Normal Interrupt Mode
If the MCU was in interrupt mode before the STOP
or WAIT instruction was executed, it exits from
STOP or WAIT mode as soon as an interrupt oc-
curs. Nevertheless, two cases must be consid-
ered:
– If the interrupt is a normal one, the interrupt rou-
tine in which the WAIT or STOP mode was en-
tered will be completed, starting with the
execution of the instruction which follows the
STOP or the WAIT instruction, and the MCU is
still in the in terrupt m ode. A t the end of t his rou-
tine pending interrupts will be serviced in accord-
ance with their priority.
– In the event of a non-maskable interrupt, the
non-maskable interrupt service routine is proc-
essed first , then the routine in which the WAIT or
STOP mode was entered will be completed by
executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal
inte rrupt mode.
Notes:
To achieve the lowest power consumption during
RUN or WAIT modes, the user program must take
care of:
– configuring unused I/Os as inputs without pull-up
(these should be externally tied to well defined
logic levels);
– placing all peripherals in their power down
modes before entering STOP mode;
When th e hardware act ivated Wat c hdog i s select-
ed, or when the software Watchdog is enabled, the
STOP instruction is disabled and a WAIT instruc-
tion will be executed in its place.
If all interrupt sources are disabled (GEN low), the
MCU can only be restarted by a Reset. Although
setting GEN low does not mask the NMI as an in-
terrupt, it will stop it genera ting a wake-up signal.
The WAIT and STOP instructions are not execut-
ed if an enabled interrupt request is pending.
37/86
ST62T55C ST62T65C/E65C
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
The MCU features Input/Output lines which may
be individually programmed as any of the f ollowing
input or output configurations:
– Input without pull-up or interrupt
– Input with pull-up and interrupt
– Input with pull-up, but without interrupt
– Anal og input
– Push-pul l output
– Open drain output
The lines are organised as byte wise Ports.
Each port is associated with 3 registers in Data
space. Each bit of these registers is associated
with a particular line (for instance, bits 0 of Port A
Data, Direction and Option registers are associat-
ed with the PA0 line of Port A).
The DATA registers (DRx), are used to read the
voltage level values of the lines which have bee n
configured a s inputs, or t o write the logic value of
the signal to be output on the lines configured as
outputs. The port data registers can be read to get
the effective l ogic levels of the pins, but they can
be also written by user software, in conjunction
with the related option registers, to select the dif-
ferent input mode options.
Single-bit operations on I/O registers are possible
but care is necessary because reading in input
mode is done from I/O pins while writing will direct-
ly affect the Port data register causing an unde-
sired change of the input configuration.
The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
set.
The Option registers (ORx) are used to select the
different port options available both in input and in
output mode.
All I/O registers can be read or written to just as
any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and
manipulation. During MCU initialization, all I/O reg-
isters are cleared and the input mode with pull-ups
and no interrupt generation is selected for all the
pins, thus avoiding pin conflicts.
Figure 22. I/O Port Block Diagram
VDD
RESET
SIN CO NTRO LS
SOUT
SHIFT
REGISTER
DATA
DATA
DIRECTION
REGISTER
REGISTER
OPTION
REGISTER
INPUT/OUTPUT
TO INTERRUPT
VDD
TO ADC VA00413
38/86
ST62T55C ST62T65C/E65C
I/O PO R T S (Cont’d)
4.1.1 Operating Mod es
Each pin may be individually programmed as input
or output with various configurations.
This is achieved by writing the relevant bit in the
Data (DR), Data Direction (DDR) an d Option reg-
isters (OR). Table 1 illustrates the various port
configurations which can be selected by user soft-
ware.
4.1.1.1 Input Options
Pull-up, High Impedance Option. All input lines
can be individually programmed with or without an
internal pull-up by programming the OR and DR
registers accordingly. If the pull-up option is not
selected, the input pin will be in the high-imped-
ance state.
4.1.1.2 Interru pt Op tion s
All input lines can be individually connected by
software to the interrupt system by programming
the OR and DR registers accordingly. The inter-
rupt trigger modes (falling edge, rising edge and
low level) can be configured by software as de-
scribed in the Interru pt Chapter for each port.
4.1.1.3 Analog Input Options
Som e pins can be co nfigured as analog inputs by
programm ing the OR and DR registers according-
ly. These analog inputs are connected to the on-
chip 8-bit Analog to Digital Con verter. ONLY ONE
pin shou ld be program med as a n analog i nput at
any time, since by selecting more than one input
simultaneously their pins will be effectively short-
ed.
Table 10. I/O Port Option Selection
Note: X = Do n’t car e
DDR OR DR Mode Option
0 0 0 Input With pull-up, no interrupt
0 0 1 Input No pull-up, no interrupt
0 1 0 Input With pull-up and with interrupt
0 1 1 Input Analog input (when available)
1 0 X Output Open-drain output (20mA sink when available)
1 1 X Output Push-pull output (20mA sink when available)
39/86
ST62T55C ST62T65C/E65C
I/O PO R T S (Cont’d)
4.1.2 Safe I/O State Switching Sequen ce
Switching the I/O ports from one state to another
should be done in a sequenc e wh ich ens ures t hat
no unwanted side effects can occur. The recom-
mended safe transitions are illustrated in Figure 2.
All other transitions are potentially risky and
should be avo ided when changing the I/O operat -
ing mode, as it i s most likely that undesirable side-
effects will be experienced, such as spurious inter-
rupt generation or two pins shorted together by the
analog multiplexer.
Single bit instructions (SET, RES, INC and DEC)
should be used with great caution on Ports Data
registers, since these instructions make an implicit
read and write back of the entire register. In port
input mode, however, the data register reads from
the input pins directly, and not f rom the data regis-
ter latches. Since data register information in input
mode is used to set the characteristics of t he input
pin (interrupt, pull-up , analog input), these may be
unintentionally reprogrammed depending on the
state of the input pins. As a general rule, it is better
to limit the use of single bit instructions on data
registers to when the whole (8-bit) port is in output
mode. In the case of inputs or of mixed inputs and
outputs, it is advisable to keep a copy of the data
register in RAM. Single bit instructions may then
be used on the RAM copy, after which the whole
copy register can be written to the port data regis-
ter:
SET bit, datacopy
LD a, datacopy
LD DRA, a
Warning : Care must also be taken to not use in-
structions that act on a whole port register (INC,
DEC, or read operations) when all 8 bits are not
available on the device. Unavailable bits must be
masked by software (AND instruction).
The WAIT and STOP instructions allow the
ST62xx to be used in situations where low power
consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in input
mode with well-defined logic levels.
The user must take care not to switch outputs with
heavy loads during the conversion of one of the
analog inputs in order to avoid any disturban ce to
the conversion.
Figure 23. Diagram showing Safe I/O State Transitions
Note *. xxx = DDR, OR, DR Bits respectively
Interrupt
pull-up
Output
Open Drain
Output
Push-pull
Input
pull-up (Reset
state)
Input
Analog
Output
Open Drain
Output
Push-pull
Input
010*
000
100
110
011
001
101
111
40/86
ST62T55C ST62T65C/E65C
I/ O PORT S (Cont’d)
Table 11I/O Port Option Selections
Note 1. Provided the correct configuration has been selected.
MODE AVAILABLE ON(1) SCHEMATIC
Input PA0-PA7
PB0-PB5, PB6-P B7
PC0-PC4
Input
with pull up
PA0-PA7
PB0-PB5, PB6-P B7
PC0-PC4
Input
with pull up
with interrupt
PA0-PA7
PB0-PB5, PB6-P B7
PC0-PC4
Analog Input PA0-PA7
PC0-PC4
Open drain output
5mA
Open drain output
30mA
PA0-PA7
PC0-PC4
PB0-PB5, PB6-P B7
Push-pull output
5mA
Push-pull output
30mA
PA0-PA7
PC0-PC4
PB0-PB5, PB6-P B7
Data in
Interrupt
Data in
Interrupt
Data in
Interrupt
Data out
ADC
Data out
41/86
ST62T55C ST62T65C/E65C
I/O PO R T S (Cont’d)
4.1.3 Tim er 1 Alternate func tion Option
When bit TOUT of register TSCR1 is low, pin PC1/
Timer 1 is configured through the port registers as
any standard pin of Port B. It is in addition connect-
ed to the Timer 1 input for Gated and E vent coun-
ter modes. When bit TOUT of register TSCR1 is
high, pin PC1/Timer 1 is forced as Timer 1 output,
independent ly of the port re gisters configurat ion.
4.1.4 AR Timer Alternate func tion Option
When bit PWMOE of register ARMC is low, pin AR-
TIMout/PB7 is configured as any standard pin of
port B through the port regi sters. When PWMOE is
high, ARTIMout/PB7 is the PWM output, independ-
ently of the port registers configuration.
ARTIMin/PB 6 is con nec ted to th e AR T imer inpu t.
It is configured through the port registers as any
standard pin of port B. To use ARTIMin/PB6 as AR
Timer input, it must be configured as input through
DDRB.
4.1.5 SPI Alternate function Option
PC2/PC4 are used as standard I/O as long as bit
SPCLK of the SPI Mode Register is kept low.
When PC2/Sin is configured as input, it is automat-
ically connected to the SPI shift register input, in-
dependent of the state at SPCLK.
PC3/SOUT is configured as SPI push-pull output
by setting bit 0 of the Miscellaneous register (ad-
dress DDh), regardless of the state of Port C reg-
isters. PC4/SCK is co nfigured as push-pull output
clock (master mode) by programming it as push-
pull output through DDRC register and by setting
bit SPCLK of the SPI Mode Register.
PC4/SCK is configured as input clock (slave mode)
by programming it as input through DDRC register
and by clearing bit SPCLK of the SPI Mode Regis-
ter. With this configuration, PC4 can simultaneous-
ly be used as an input.
42/86
ST62T55C ST62T65C/E65C
I/O PO R T S (Cont’d)
Figu re 24Peri pheral I nte rfac e Conf i gurat io n of SP I , Tim er 1 and AR Tim e r
MUX 1
0DR
PP/OD
OUT
IN
CLOCK IN
SPI
DR
DR
0
1
MUX
IN
OUT TIM ER 1
DR
MUX 1
0DR
OR AR TIMER
ARTIMout
ARTIMin
PWMOE
PP/OD
PC3/Sout
PC2/Sin
PC4/SCK
PC1/TIM1
ARTIMin
ARTIMout
VR0C1661
VDD
b0
REGISTER
MISC.
0
1CLOCK OUT
SPCLK
MOD REGISTER
MUX
OR
OR
DR
OR TOUT
43/86
ST62T55C ST62T65C/E65C
4.2 T IMER
The MCU features an on-chip Timer peripheral,
consisting of an 8-bit counter with a 7-bit program-
mable prescaler, giving a maximum count of 215.
The peripheral may be configured in three different
operating modes.
Figure 25 shows the Timer Block Diagram. The
external TIMER pin is available to the user. The
content of the 8-bit counter can be read/written in
the Timer/Counter register, TCR, while the state of
the 7-bit prescaler can be read in the PSC register.
The control logic device is managed in the TSCR
register as described in the following paragraphs.
The 8-bit counter is decremented by the output
(rising edge) coming from the 7-bit prescaler an d
can be loaded and read under program control.
When it decrements to zero then the TMZ (T imer
Zero ) b i t i n the TSC R is set to “1”. If the ETI (Ena-
ble Timer Interrupt) bit in the TSCR is also set to
“1”, an interrupt request is generated as described
in the Interrupt Chapter. The Timer interrupt can
be used to exit the MCU from WAIT mode.
The prescaler input can be the internal frequency
fINT divided by 12 or an external clock applied to
the TIMER pin. The prescaler decrements on the
rising edge. Dep ending on t he division factor pro-
grammed by PS2, PS1 and PS0 bits in the TSCR.
The clock input of the timer/counter register is mul-
tiplexed to different sources. F or division factor 1,
the clock input of the prescaler is also that of timer/
counter; fo r fa ctor 2, b it 0 of t he pres caler regi ster
is connected to the clock input of TCR. This bit
changes its state at half the frequency of the pres-
caler input clock. For factor 4, bit 1 of the PSC is
connected t o the c lock inp ut o f TCR, and s o forth.
The prescaler initialize bit, P SI, in the TSCR regis-
ter must be set to “1” to allow the prescaler (and
hence the counter) to start. If i t is cl eared to “0”, all
the prescaler bits are set to “1” and the counter is
inhibited from counting. The prescaler can be
loaded with any value between 0 and 7Fh, if bit
PSI is set to “1”. The prescaler tap is selected by
means of the PS2/PS1/PS0 bits in the control reg-
ister.
Figure 26 illustrates the Timer’s working principle.
Figu re 25. Ti m e r Bl oc k D i agram
DATABUS 8
8
88
8-BIT
COUNTER
6
5
4
3
2
1
0
PSC STATUS/CONTROL
REGISTER
b7 b6 b5 b4 b3 b2 b1 b0
TMZ ETI TOUT DOUT PSI PS2 PS1 PS0
SELECT
1 OF 7
3
LATCH
SYNCHRONIZATION
LOGIC
TIMER INTERRUPT
LINE
VA00009
:12
fOSC
44/86
ST62T55C ST62T65C/E65C
TIMER (Cont’d)
4.2.1 Timer Op erati ng Modes
There are three operating modes, which are se-
lected by the TOUT and DOUT bits (see TSCR
register). These three modes correspond to the
two clocks which can be connected to the 7-bit
prescaler (fINT ÷ 12 or TIMER pin signal), and to
the output mode.
4.2.1.1 Gated Mode
(TOUT = “0”, DOUT = “1”)
In this mode the prescaler is decremented by the
Timer c lock input (f INT ÷ 12), but ONLY when the
signal on the TIMER pin is held high (allowing
pulse width measurem ent). This mode is selected
by clearing the TOUT bit in the TSCR register to
“0” (i.e. as input) and setting the DOUT bit to “1”.
PC1 must be configured in input mode
4.2.1.2 Event Counter Mode
(TOUT = “0”, DOUT = “0”)
In this mode, the TIMER pin is the input clock of
the prescaler which is decremented on the rising
edge.
4.2.1.3 Output Mode
(TOUT = “1”, DOUT = data out)
The TIMER pin is connected to the DOUT latch,
hence the Timer presc aler is clocked by the pres-
caler clock input (fINT ÷ 12).
The user c an s elect the desired presc aler division
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. Th e TMZ bit can be tes ted u nder program
control to perform a timer function whenever it
goes high. The low-to-high TMZ bit transition is
used to latch the DOUT bi t of t he T SCR and trans-
fer it to t he TIMER pin. This operating mode allows
external signal generation on the TIMER pin.
Table 12. Timer Operating Modes
4.2.2 Timer Interrupt
When the counter register decrements to zero with
the ETI (Enab le Timer Interrupt) bit set to one, an
interrupt req uest is g enerated as described in the
Interrupt Chapter. When the counter decrements
to zero, the TMZ bit in the TSCR regis ter is set to
one.
Figure 26. Timer Working Principle
TOUT DOUT Timer Pin Timer Function
0 0 Input Event Counter
0 1 Input Gated Input
1 0 Output Output “0”
1 1 Output Output “1”
BIT0 BIT1 BIT2 BIT3 BIT6BIT5BIT4
CLOCK
7-BI T PRESCAL ER
8-1 MULTIPLEXER
8-BI T COU NT ER
BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
102
3456 7PS0
PS1
PS2
VA00186
45/86
ST62T55C ST62T65C/E65C
TIMER (Cont’d)
4.2.3 Application Notes
The user can select the presence of an on-chip
pull-up on the TIMER pin as o ption.
TMZ is set when t he counter r eaches zero; howev-
er, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, whi le the 7-bit prescaler is l oad-
ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.
If the Timer is programmed in output mode, the
DOUT bit is transferred to the TIMER pin when
TMZ is set to one (by software or due to counter
decrement). When TM Z is high, the latch is trans-
parent and DOUT is copied to the timer pin. When
TMZ goes low, DOUT is latched.
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.
4.2.4 Timer Registers
Timer Status Control Register (TSCR)
Address: 0D4h —Read/Write
Bi t 7 = TMZ: Ti mer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This bit must
be cleared by us er sof tw are before starting a new
count.
Bi t 6 = ETI: Enab le Timer Interrupt
When set, enables the timer interrupt request
(vector #4). I f E TI=0 the t imer interrupt is di sabled.
If ETI=1 and TMZ=1 an interrupt request is gener-
ated.
Bi t 5 = TOUT: Timers Output Control
When low, this bit selects the input mode for the
TIMER pin. When high the ou tput mode i s select-
ed.
Bit 4 = DOUT: Data Output
Data sent to the timer output when TMZ is set high
(output mode only). Input mode selection (input
mode only).
Bit 3 = PSI: Pre s c a ler Ini tializ e Bi t
Used to initialize the prescaler and inhibit its count-
ing. W hen PS I =“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
PSI=“0” both counter and prescaler are not run-
ning.
Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-
lect. These bits select the division ratio of the pres-
caler register.
Table 13P rescaler Division Factors
Ti m er Counter Register TCR
Address: 0D3h —Read/Write
Bit 7-0 = D7-D0: Counter Bits.
Prescaler Register PSC
Address: 0D2h —Read/Write
Bit 7 = D7: Always read as "0".
Bit 6-0 = D6-D0: Prescaler Bits.
70
TMZ ETI TOUT DOUT PSI PS2 PS1 PS0
PS2 PS1 PS0 Divided by
0 0 0 1
0 0 1 2
0 1 0 4
0118
10016
10132
11064
111128
70
D7 D6 D5 D4 D3 D2 D1 D0
70
D7 D6 D5 D4 D3 D2 D1 D0
46/86
ST62T55C ST62T65C/E65C
4.3 AUTO-RELOAD TIMER
The Auto-Reload Timer (AR Timer) on-chip pe-
ripheral consists of an 8-bit timer/counter with
compare an d capture/reload capabilities and of a
7-bit prescaler with a clock multiplexer, enabling
the clock input to be selected as fINT, fINT/3 or an
external clock source. A Mode Control Register,
ARMC, two Status Cont rol Regi sters, ARSC0 and
ARSC1, an output pin, ARTIMout, and an input
pin, ARTIMin, allow the Auto-Reload Timer to be
used in 4 modes:
– Auto-reload (PWM generation),
– Outp ut compare and reload on externa l event
(PLL),
– Input capture and output compare for time meas-
urement.
– Input capture and output compare for period
measurement.
The AR Timer can be used to wake the MCU from
WAIT mode either with an internal or with an exter-
nal clock. It also can be used to wake the MCU
from STOP mode, if used with an external clock
signal connected to the AR TIMin pin. A Load reg-
ister allows the program to read and write the
counter on the fly.
4.3.1 AR Tim er Description
The AR COUNTER is an 8-bit up-counter incre-
mented on the input clock’s rising edge. The coun-
ter is loaded from the ReLoad/Capture Register,
ARRC, for auto-reload or capture operations, as
well as for initialization. Direct access to the AR
counter is not possible; however, by reading or
writing the ARLR load register, it is possible to
read or write the counter’s conte nts on the fly.
The AR Timer’s input clock can be either the inter-
nal clock (from the Oscillato r Divider), the internal
clock divided by 3, or the clock signal connected to
the ARTIMin pin. Selection between these clock
sources is effected by suitably programming bits
CC0-CC1 of the ARSC1 register. The output of t he
AR Multiplexer feeds the 7-bit programmable AR
Prescaler, ARPSC, which selects one of the 8
available taps of the prescaler, as defined by
PSC0-PSC2 in the AR Mode Control Register.
Thus the division factor of the prescaler can be set
to 2n (where n = 0, 1,..7).
The clock input to the AR counter is enabled by the
TEN (Timer Enable) bit in the ARMC register.
When TEN is reset, the AR counter is stopped and
the prescaler and counter contents are frozen.
When TE N is set, the AR counter runs at the rate
of the selected clock source. The counter is
cleared on system reset.
The AR counter may also be initialized by writing
to the ARLR load register, which also causes an
immediate copy of the value to be placed in the AR
counter, regardless of wh ether the counter is run-
ning or not. Initialization of the counter, by either
method, will also clear the ARPSC register, where-
upon counting will start from a known value.
4.3.2 Timer Operating Modes
Four different operating modes are available for
the AR Timer:
Auto-reload Mode with PWM Generation. This
mode allows a Pulse Width Modulated signal to be
generated on the ARTIMout pin with minimum
Core processing overhead.
The free running 8-bit counter is fed by the pres-
caler’s output, and is incremented on every rising
edge of the clock signal.
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the Re-
load/Capture Register, ARCC, and ARTIMout is
set. When the counter reaches the value con-
tained in the c ompare regist er (ARCP), ARTIMout
is r eset.
On overflow, the OVF flag of the ARSC0 register i s
set and an overf low interrupt request is generated
if the overflow interrupt enable bit, OVIE, in the
Mode Control Register (ARMC), is set. The OVF
flag must be reset by the user software.
When the counter reaches the compare value, the
CPF flag of the ARSC 0 register is set and a com-
pare interrupt request is generated, if the Compare
Interrupt enable bit, CPIE, in the Mode Control
Register (ARMC), is set . The i nterrupt service rou-
tine may then adjust the PWM period by loading a
new value into ARCP. The CPF flag must be reset
by user software.
The PWM signal is generated on the ARTIMout
pin (refer to the B lo ck Diagram ). The fr equen cy of
this signal is controlled by the prescaler setting
and by the auto-reload value present in the Re-
load/Capture register, ARRC. The duty cycle of
the PWM signal is controlled by the Compare Reg-
ister, ARCP.
47/86
ST62T55C ST62T65C/E65C
AUTO-RELOAD TIMER (Cont’d)
Figure 27. AR Timer Block Diagram
DAT A BUS
8
8
8
COMPARE
8
RELOAD/CAPTURE
DATA BUS
AR TIMER
VR01660A
88
R
S
TCLD
OVIE
PWMOE
OVF
LOAD
ARTIMout
M
SYNCHRO
ARTIMin SL0-SL1
INT
f
PB6/
AR
REGISTER
EF
REGISTER
LOAD
AR
U
X
fINT /3 AR PR ESCA LE R
7-Bit
CC0-CC1
AR COUNTER
8-Bit
AR COMPARE
REGISTER
OVF
EIE
EF
INTERRUPT
CPF
CPIE
CPF
DRB7
DDRB7
PB7/
PS0-PS2
88
48/86
ST62T55C ST62T65C/E65C
AUTO-RELOAD TIMER (Cont’d)
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of PWM output signal. To obtain a signal on ARTI-
Mout, the contents of the ARCP register must be
greater than the contents of the ARRC register.
The maximum available resolution for the ARTI-
Mout duty cycle is:
Resolution = 1/[255-(ARRC)]
Where ARRC is the content of the Reload/Capture
register. The compare value loaded in the Com-
pare Register, ARCP, must be in the range from
(ARRC) to 255.
The ARTC counter is initialized by writing to the
ARRC register and by then setting the TCLD (Tim-
er Load) and the TEN (Timer Clock Enable) bits in
the Mode Control register, ARMC.
Enabling and sel ec tion of the clock sourc e is c on-
trolled by the CC0, CC1, SL0 and SL1 bits in the
Status Control Register, ARSC1. The prescaler di-
vision ratio is selected by the PS0, PS1 and PS2
bits in the ARSC1 register.
In Auto-reload Mode, any of the three available
clock sources can be selected: Internal Clock, In-
ternal Clock divided by 3 or the clock signal
present on the ARTIMin pin.
Figure 28. Auto-reload Timer PWM Function
COUNTER
COMPARE
VALUE
RELOAD
REGISTER
PWM OUTPUT
t
t
255
000
VR001852
49/86
ST62T55C ST62T65C/E65C
AUTO-RELOAD TIMER (Cont’d)
Capture Mode with PWM Generation. In this
mode, the AR counter operates as a free running
8-bit counter fed by the prescaler output. The
counter is incremented on every clock rising edge.
An 8-bit capture operation from the count er to the
ARRC regist er is performed o n every active edg e
on the ART IMin pin, whe n ena bled by E dge Con-
trol bits SL0, SL1 in the ARSC1 register. At the
same time, the External Flag, EF, in the ARSC0
register is set and an external interrupt request is
generated if the External Interrupt Enable bit, EIE,
in the ARMC register, is set . The E F flag must be
re set by user s o ftw a re .
Each ARTC overflow sets ARTIMout, while a
match between the counter and ARCP (Compare
Register) resets ARTIMout and sets the compare
flag, CPF. A compare interrupt request is generat-
ed if the related compare interrupt enable bit,
CPIE, is set. A PWM signal is generated on ARTI-
Mout. The CPF flag must be reset by user soft-
ware.
The frequency of the generated signal is deter-
mined by the prescaler setting. The duty cycle is
determined by the ARCP register.
Initialization and reading of the counter are ident i-
cal to the auto-reload mode (see previous descrip-
tion).
Enabling and selection of clock sources is control-
led by the CC0 and CC1 bits in the AR Status Con-
trol Register, ARSC 1.
The prescaler division ratio is selected by pro-
gramming the PS0, PS1 and PS2 bits in the
ARSC1 Register.
In Capture mode, the allowed clock sources are
the internal clock and t he internal clock divid ed by
3; the external ARTIMin input pin should not be
used as a clock source.
Capture Mode with Reset of counter and pres-
caler, and PWM Generation. This mode is identi-
cal to the previous o ne, with the difference that a
capture condition also resets the counter and the
prescaler, thus allowing eas y mea suremen t of the
time between two captures (for input period meas-
urement on the ARTIMin pin).
Load on External Input. The counter operates as
a free running 8-bit counter fed by the prescaler.
the count is incremented on every clock rising
edge.
Each counter overflow sets the ARTIMout pin. A
match between the counter and ARCP (Compare
Register) resets the ARTIMout pin and sets the
compare flag, CPF. A compare interrupt request is
generated if the related compare interrupt enable
bit, CPIE, is set. A PWM signal is generated on
ARTIMout. The CPF flag must be reset by user
software.
Initialization of the counter is as described in the
previous paragraph. In addition, if the external AR-
TIMin input is enabled, an active edge on the input
pin wi ll copy the contents of the ARRC r egister in to
the counter, whether the counter is running or not.
Notes:
The allowed AR Timer clock sources are the fol-
lowing:
The clock freque ncy should not be m odified while
the count er is counting, since the c ounter may be
set to an unpredictable value. For instance, the
multiplexer setting should not be modified while
the counter is counting.
Loading of the counter by any means (by auto-re-
load, through ARLR, ARRC or by the Core) resets
the prescaler at the same time.
Care should be taken when both the Capture inter-
rupt and the Overflow i nterrup t are used. Capt ure
and ov erflow are asynchron ous. If the capt ure oc -
curs when the Overflow Interrupt Flag, OVF, is
high (between counter overflow and the flag being
reset by software, in the interrupt routine), the Ex-
ternal Interrupt Flag, EF, may be cleared simul-
taneusly without the interrupt being taken into ac-
count.
The s olution consist s in resetting the OVF flag by
writing 06h in the ARSC0 register. The value of EF
is not affected by this operation. If an interrupt has
occ ured , it will b e pro ces sed w hen the MCU e xi ts
from the interrupt routine (the second interrupt is
latched).
AR Timer Mode Clock Sources
Auto-reload mode fINT, fINT/3, ARTIMin
Capture mode fINT, fINT/3
Capture/Reset mode fINT, fINT/3
External Load mode fINT, fINT/3
50/86
ST62T55C ST62T65C/E65C
AUTO-RELOAD TIMER (Cont’d)
4.3.3 AR Tim er Registers
AR Mode Control Register (ARMC)
Address: D5h —Read/Write
Reset status: 00h
The AR Mode Control Register ARMC is used to
program the different operating modes of the AR
Timer, to enable the clock and to initialize the
counter. It can be re ad and written to by the C ore
and it is cleared on system reset (the AR Timer is
disabled).
Bit 7 = TLCD: Timer Load Bit. Thi s bit, w hen set,
will cause the contents of ARRC register to be
loaded into the counter and the contents of the
prescaler register, ARPSC, are cleared in order to
initialize the timer before starting to count. This bit
is write -only and an y attempt to read it will yield a
log i ca l zero.
Bit 6 = TEN: Timer Clock Enable. This bit, when
set, allows the timer to count. When cleared, it will
stop the timer and freeze ARPSC and A RTSC.
Bit 5 = PWMOE: PWM Output Enable. This bit,
when set, enables the PWM output on the ARTI-
Mout pin. When reset, the PWM output is disabled.
Bit 4 = EIE: External Interrupt Enable. This bit,
when set, enables the external interrupt request.
When reset, the external interrupt request is
masked. If EIE is set and the related flag, EF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bit 3 = CPIE: Compare Interrupt Enable. This bit,
when set, enables the compare interrupt request.
If CPIE is reset, the compare interrupt request is
masked. If CPIE is set and the related f lag, CPF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bit 2 = OVIE: Overflow Interrupt. This bit, when
set, enables the overflow interrupt request. If OVIE
is reset, the compa re interrupt request is m ask ed.
If OVIE is set and the related flag, OVF in the
ARSC 0 regi ster is al so s et, an i nte rrupt request is
generated.
Bit 1-0 = ARMC1-ARMC0: Mode Co ntrol B its 1-0.
These are the operating mode control bi ts. The fol-
lowing bit co mbinations will select the vario us op-
erating modes:
AR Timer Status/Control Registers ARSC0 &
ARSC1. These registers contain the AR Timer sta-
tus information bits and also allow the program-
ming of clock sources, active edge and prescaler
mu lt ip lex e r s e ttin g.
ARSC0 register bits 0,1 and 2 contain the interrupt
flags of the AR Timer. These bits are read normal-
ly. Each o ne may be reset by software. Writing a
one does not affect the bit value.
AR Status Control Regi ster 0 (ARSC0)
Address: D6h —Read/Clear
Bits 7-3 = D7-D3: Unused
Bit 2 = EF: External Interrupt Flag. This bit is set by
any active edge on the external ARTIMin input pin.
The flag is cleared by writing a zero to the EF bit.
Bit 1 = CPF: Compare Interrupt Flag. This bit is set
if the contents of the count er and the ARCP regis-
ter are e qual. T he f lag is cleared by writing a zero
to the CPF bit.
Bit 0 = OVF: Overflow Interrupt Flag. This bit is set
by a transition of the counter from FFh to 00h
(overflow). The flag is cleared by writing a zero to
the OVF bit.
70
TCLD TEN PWMOE EIE CPIE OVIE ARMC1 ARMC0 ARMC1 ARMC0 Operating Mode
0 0 Auto-reload Mode
0 1 Capture Mode
10
Capture Mode with Reset
of ARTC and ARPSC
11
Load on External Edge
Mode
70
D7 D6 D5 D4 D3 EF CPF OVF
51/86
ST62T55C ST62T65C/E65C
AUTO-RELOAD TIMER (Cont’d)
AR Status Control Register 1(ARSC1)
Address: D7h —Read/Write
Bist 7-5 = PS2-PS0: Prescaler Division Selection
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio is listed in the
following table:
Table 14. Pre scaler Divisi on Ratio Selection
Bi t 4 = D4 : Reserved. Must be kept reset.
Bit 3-2 = SL1-SL0: Timer Input Edge Control Bits 1-
0. These bits control the edge function of the Timer
input pin for external synchronization. If bit SL0 is re-
set, edge detection is disabled; if set edge detection
is enabled. If bit SL1 is reset, the AR Timer input pin
is rising edge sensitive; if set, it is falling edge sen-
sitive.
Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
the clock sources is explained in the following Table
15:
Table 15. C lock So urce Selection.
AR Load Register ARLR. The ARLR load register
is used to read or write the ART C counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
AR Load Register (ARLR)
Address: DBh —Read/Write
Bit 7-0 = D7-D0: Load Register Data Bits. These
are the load register data bits.
AR Reload/Capture Register. The ARRC reload/
capture register is used to hold the auto-reload
value which i s aut om atically loa ded i nto the c oun-
ter when overflow occurs.
AR Reload/Capture (ARRC)
Address: D9h —Read/Write
Bit 7-0 = D7-D0 : Reload/Capture Data Bits. These
are the Reload/Capture register data bits.
AR Compare Reg ister. The CP compare register
is used to hold the compare value for the compare
function.
AR Compare Register (ARCP)
Address: DAh —Read/Write
Bit 7-0 = D7-D0: Compare Data Bits. These are
the Compare register data bit s.
70
PS2 PS1 PS0 D4 SL1 SL0 CC1 CC0
PS2 PS1 PS0 ARPSC Divis ion Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
16
32
64
128
SL1 SL0 Edge Detection
X 0 Disabled
0 1 Rising Edge
1 1 Falling Edge
CC1 CC0 Clock Source
00F
int
01F
int Divided by 3
1 0 ARTIMin Input Clock
11Reserved
70
D7 D6 D5 D4 D3 D2 D1 D0
70
D7 D6 D5 D4 D3 D2 D1 D0
70
D7 D6 D5 D4 D3 D2 D1 D0
52/86
ST62T55C ST62T65C/E65C
4.4 A/D CONVERTER (ADC)
The A/D converter periphe ral is an 8-bit analog to
digital converter with analog inputs as alternate I/O
functions (the number of which is device depend-
ent), offering 8-bit resolution with a typical conver-
sion time of 70us (at an oscillator clock frequenc y
of 8MHz).
The AD C converts the input voltage by a process
of successive approximations, using a clock fre-
quency derived from the oscillator with a division
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de-
creased.
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Op-
tio n and Data registers (refer to I/O ports descrip-
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin i s selecte d as an anal og in put s i-
multaneously, to avoid device malfunction.
The ADC uses two registers in t he data s pace: the
ADC data c onversion register, ADR, which stores
the conversion result, and the ADC control regis-
ter, ADCR, used to program the ADC functions.
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto-
matically clear s (rese ts to “0”) the End Of Conv er-
sion Bit (EOC). When a conversion is complete,
the EOC bit is automatically set to “1”, in order to
flag that conversion is complete and t hat the data
in the ADC d ata co nversion regi ster is valid. E ach
conversion has to be separately initiated by writing
to the ST A bit.
The STA bit is continuously scanned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com-
pleting the previous one. The start bit (STA) is a
wr it e onl y b it, any at te mpt to read it wi ll s how a log -
ical “0”.
The A/D converter features a maskable interrupt
associated with the end of conversion. This inter-
rupt is associated wit h interrupt vector #4 and oc-
curs when the E OC bit is set (i.e. when a conv er-
sion is c ompleted). T he interrupt is masked using
the EAI (interrupt mask ) bit in the control register.
The power consumption of the device can be re-
duced by turning off the ADC peripheral. This is
done by setting the PDS bit in the ADC control reg-
ister to “0”. If PDS=“1”, the A/D is powered and en-
abled for con version. T his bit must be set at least
one instruction before the beginning of the conver-
sion to allow stabilisation of the A/D converter.
This action is also needed before entering WAIT
mode, since the A/D comparator is not automati-
cally disabled in WAIT mode.
During Reset, any conversion in progress is
stopped, the control register is reset to 40h and the
ADC interrupt is masked (EAI=0).
Figure 29. ADC Block Diagram
4.4.1 Application Notes
The A /D c onvert er doe s not f eature a s ample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire con-
versio n cycl e . Vol ta ge va ri at i on should n o t exce e d
±1/2 LSB for th e opt imum co nversion ac curac y. A
low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
When selected as an analog channel, the input pin
is internally connected to a capacitor Cad of typi-
cally 12pF . For max imum ac curac y, this c apacitor
must be fully charge d at the beginning of conver-
sion. In the worst case, conversion starts one in-
struction (6.5 µs) after the channel has been se-
lected. In worst case conditions, the impedance,
ASI, of the analog voltage source is calculated us-
ing the following formula:
6.5µs = 9 x Cad x ASI
(capacitor charged to over 99.9%), i.e. 30 kΩ in-
cluding a 50% guardband. ASI can be higher if Cad
has been charged for a longer period by adding in-
structions before the start of conversion (adding
more than 26 CPU cycles is pointless).
CO NTROL REGIS T ER
CONVERTER
VA00418
RESULT REGISTER
RESET
INTERRUPT
CLOCK
AV
AVDD
Ain
8
CORE
CO NTROL SIGNA L S
SS
8
CORE
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ST62T55C ST62T65C/E65C
A/D CONVERT ER (Cont ’d)
Since the ADC is on the same chip as the micro-
processor, the user should not switch heavily load-
ed output signals during conversion, if high preci-
sion is required. Such switching will affect the sup-
ply voltages used as analog references.
The accuracy of the conversion depends on the
quality of the power supplies (VDD and VSS). Th e
user must take special care to ensure a well regu-
lated reference voltage is present on the VDD and
VSS pins (power supply voltage variations must be
less than 5V/ms). This implies, in particular, that a
suitable decoupling capacitor is used at the VDD
pin.
The converter resolution is given by::
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and
remain constant during conversion.
Conversion resolution can be improved if the pow-
er supply voltage (VDD) to the microcontroller is
lowered.
In order to optimise conversion resolution, the user
can configure the microcontroller in WAIT mode,
because this mode minimises noise disturbances
and power supply variations due to output switch-
ing. Nevertheless, the WAIT instruction should be
executed as soon as possible after the beginning
of the con version, because ex ecut ion of the WAIT
instruction may cause a small variation of the VDD
voltage. The negative effect of this variation is min-
imized at the beginning of the conversion when the
converter is less sensitive, rather than at the end
of conversion, when the less significant bits are
determined.
The best configuration, from an accuracy stand-
point, is WAIT mode with the Timer stopped. In-
deed, only the ADC peripheral and the oscillator
are then still working. The MCU must be woken up
from WAIT mode by the A DC interrupt at the end
of the conversion. It should be noted that waking
up the microcontroller could also be done using
the Timer int errupt, but in this case the Timer will
be working and the resulting noise could affect
conversion accura cy.
One extra fe ature is available in the A DC to get a
better accuracy. In f act, each ADC conversion has
to be followed by a WAIT instruction to minimize
the no ise during the conv ersion. Bu t the first con-
version step is performed before the execution of
the WAIT when most of clocks signals are still en-
abled . The key is to synchronize the ADC start
with the effective execution of the WAIT. This is
achieved by setting ADC SY NC option. This w ay,
ADC convers ion s tarts in effective WAI T for m axi-
mum accuracy.
Note: With this extra option, it is mand ato ry to ex-
ecute WAIT instruction just after ADC start instruc-
tion. Insertion of any extra instruction may cause
spurious interrupt request at ADC interrupt vector.
A/D Converter Cont rol Regist er (ADCR)
Address: 0D1h —Read/Write
Bit 7 = EAI: Enable A/D Interrupt. If t his bit i s set to
“1” the A/D interrupt is enabled, when EAI=0 the
interrupt is disabled.
Bit 6 = EOC: End of conversion. Read Only. This
read only bit indicates when a conversion has
been completed. This bit is au tomatically reset to
“0” when the STA bit is written. If the user is using
the interrupt option then this bit can be used as an
interrupt pending bit. Data in the data conversion
register are valid only when this bit is set to “1”.
Bit 5 = STA: Start of Conversion. Write Only. Wr it-
ing a “1” to this bit will start a conversion on the se-
lected channel and automatically reset to “0” the
EOC bit. If the bit is set again when a conversion is
in progress, the present conversion is stopped and
a new one will take place. This bit i s write only, any
attempt to read it will show a logical zero.
Bit 4 = PDS: Power Do wn Selection. This bit acti-
vates the A/D converter if set to “1”. Writing a “0” to
this bit will put the AD C in powe r down m ode (i dle
mode).
Bit 3-0 = D3-D0. Not used
A/D Converter Data Register (ADR)
Address: 0D0h —Read only
Bit 7-0 = D7-D0: 8 Bit A/D Conversion Result .
VDD VSS
–
256
----------------------------70
EAI EOC STA PDS D3 D2 D1 D0
70
D7 D6 D5 D4 D3 D2 D1 D0
54/86
ST62T55C ST62T65C/E65C
4.5 SERIAL PERIPHERAL INTERFACE (SPI)
The SPI peripheral is an optimized synchronous
serial interface with programmable transmission
mod es and mas ter/slave c apabilit ies suppo rting a
wide range of industry standard SPI specifications.
The SPI interface may also implement asynchro-
nous data tran sfer, in which case proces sor over-
head is limited to da ta transfer from or to the shi ft
register on an interrupt driven basis.
The SPI may be controlled by simple user soft-
ware to perform serial data exchange with low-
cost external memory, or with serially controlled
peripherals to drive displays, motors or relays.
The SPI’s shift register is simultaneously fed by
the Sin pin and f eeds the Sout pin, thus t ransm is-
sion and rec eption are ess entially the same proc-
ess. Suitable setting of the number of bits in the
data frame ca n allow f iltering of unwant ed l eadin g
data bits in the incoming data stream.
The SPI comprises an 8-bit Data/Shift Register,
DSR, a Divide register, DIV , a Mo de Control Reg-
ister MOD, and a Miscellaneous register, MISCR.
The SPI may be operated either in Master mode or
in Slave mode.
Master mode is def ined by the synchronous serial
clock bei ng supplied by t he MCU, by s uitably pro-
gramming the clock divider (DIV register). Slave
mode is defined by the serial clock be ing suppl ied
externally on the SCK pin by the external Master
device.
For maximum versatility the SPI may be pro-
grammed to sample data either on the rising or on
the falling edge of SCK, with or without phase shift
(clock Polarity and Phase selection).
The Sin, Sout and SCK signals are connected as
alternate I/O pin functions .
For serial input operation , Sin must be configured
as an input. For serial output operation, Sout is se-
lected as an output by programming Bit 0 of the
Miscellaneous Register: clearing this bit will set
the p in a s a standa rd I/O line, whi le set ting the bit
will select the Sout function.
An interrupt request may be associated with the
end of a transmission or reception cycle; this is de-
fined by programming the number of bits in the
data frame and by enabling the interrupt. This re-
quest is associated with interrupt vector #2, and
can be masked by programming the SPIE bit of
the MOD register. Since the SPI interrupt is
“ORed” with the port interrupt source, an interrupt
flag bit is available in the DIV register allowing dis-
crimination of the interrupt request.
Figure 30. S PI Block Diagram
SPI
SCK
FILTER
Sin Sout
CPU
CYCLE
CLOCK
CLOCK
DATA BUS
8
VR001693
SHIFT
REGISTER
FILTER
DIVIDER
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ST62T55C ST62T65C/E65C
SERIAL PERIPHERAL INTERFACE SPI (C on t’d)
4.5.1 SPI Registers
SPI Mode Cont rol Regist er (MOD)
Address: E2h —Read/Write
Reset status: 00h
The MOD register defines and controls the trans-
mission modes and charact eristics.
This register is read/write and all bits are clea re d
at reset. Setting SPSTRT = 1 and SPIN = 1 is not
allowed and must be avoided.
Bit 7 = SPRUN: SPI Run. T his bit i s the S PI activi ty
flag. This can be used in either transmit or receive
modes; it is automatically cleared by the SPI at the
end of a transmission or reception and generates
an interrupt request (providing that the SPIE Inter-
rupt Enable bit is set). The Core can stop transmis-
sion or reception at any time by resetting the
SPRUN bit; this will also generate an interrupt re-
quest (providi ng t hat the S P IE Int errupt enable bit
is set) . The SPRUN bit can be used as a start con-
dition parameter, in conjunction with the SPSTRT
bit, when an external signal is present on the Sin
pin. Note that a ri sing edge is then necessary to in-
itiate reception; this may require external data in-
version. Thi s bit c an be used t o pol l the end of re-
ception or transmission.
Bit 6 = SPIE: SPI Interrupt Enable. This bit i s the
SPI Interrupt Enable bit. If this bit is set the SPI in-
terrupt (vector #2) is enabled, when SPIE is reset,
the interrupt is disabled.
Bi t 5 = CP HA: Clock Phase S el ection. This bit se-
lects the clock phase of the clock sign al. If this bit
is cleared to zero the normal state is selected; in
this case Bit 7 of the data frame is present on Sout
pin as so on as the SP I Sh ift Reg ister is loaded. If
this bit is set to one the shifted state' is selected; in
this case Bit 7 of data frame is present on Sout pin
on the firs t f alling edge of Shift Register clock. The
polarity relation and the division ratio between
Shift Register and SPI base clock are also pro-
grammable; refer to DIV register and Timing Dia-
grams for more information.
Bi t 4 = SPCLK: Base Clock Selection
This bit selects the SPI base clock source. It is ei-
ther the core cycle clock (fINT/13) (Master mode)
or the signal provided at SCK pin by an external
device (slave mode). If SPCLK is low and the SCK
pin is configured as input, the slave mode is se-
lected. If SPCLK is high, the SCK pin is automatic-
cally co nfigured as pus h pull outpu t and the mas-
ter mode is selected. In this case, the phase and
polarity of the clock are controlled by CPOL and
CPHA.
Note: When the master mode is enabled, it is
mandatory to configure PC4 in i nput mode through
the i/o port registers.
Bit 3 = SPIN: Input Selection
This bit enables the transfer of the data input to the
Shift Register in receive mode. If this bit is cleared
the Shift Register input is 0. If this bit is set, the
Shift Register input corresponds to the input signal
present on the Sin pin.
Bit 2 = SPSTRT: Start Selection
This bit sele cts t he tr ansmi ssion or reception sta rt
mode. If SPSTRT is cle ared , the i ntern al sta rt con-
dition occurs as soon as the SPRUN bit is set. If
SPSTRT is set, the internal start signal is the logic
“AND” between the SPRUN bit and the external
signal present on the Sin pin; in this case transmis-
sion will start after the latest of both signals provid-
ing that the first signal is still present (note that this
implies a rising edge). After the transmission or re-
cetion has been start ed, it will c ontinue ev en if the
Sin signal is reset.
Bit 1 = EFILT: Enable Filters
This bit ena bles/disables the input no ise filters on
the Sin and SCK inputs. If it is cleared to zero the
filters are enabled, if set to one the filters are disa-
bled. These noise filters will el iminate any pulse on
Sin and SCK with a pulse width smaller than one
to two Core clock periods (depending on the oc-
currence of the signal edge with respect to the
Core clock edge). For example, if the ST6260B/
65B runs with an 8MHz crystal, Sin an d SCK will
be delayed by 125 to 250ns.
Bit 0 = CPOL: Clock Po lari ty
This bit controls the relation ship between t he dat a
on the Sin and Sout pins and SCK. The CP OL bit
selects the clock edge which captures data and al-
lows it to change s tate. It has t he greatest i mpact
on the first bit transmitted (the MSB) as it does (or
does not) allow a clock transition before the first
data capture edge.
Refer to the timing diagrams at the end of this sec-
tion for additional details. These show the relation-
ship between CPOL, CPHA and SCK, and i ndicate
the active clock edges and strobe times.
70
SPRUN SPIE CPHA SPCLK SPIN SPSTRT EFILT CPOL
56/86
ST62T55C ST62T65C/E65C
SERIAL PERIPHERAL INTERFACE SPI (C on t’d)
SPI DIV Regis te r ( DIV)
Address: E1h —Read/Write
Reset status: 00h
The SPIDIV register defines the transmission rate
and frame format and contains the interrupt flag.
Bits CD0-CD2, DIV3-DIV6 are read/write while
SPINT can be read and cleared only. Wri te access
is not allowed if SPRUN in the MOD register is set.
Bit 7 = SPINT: Interr upt Flag . If SPIE bit=1, SPI N T
is automatically set to one by the SPI at the end of
a transmission or reception and an interrupt re-
quest can be generated depen ding on the state of
the interrupt mask bit in the MOD control register.
This bit is write and read and must be cleared by
user software at the end of the interrupt service
routine.
Bit 6-3 = DIV6-DIV3: Burst Mode Bit Clock Period
Selection. Define the number of shift register bits
that are transmitted or received in a frame. The
available selections are listed in Table 17. The
normal maximum setting is 8 bits, since the shift
register is 8 bits wide. Note that by setting a great-
er numbe r of bits, in c on junct ion with the S PIN bit
in the MOD register, unwanted data bits m ay be f il-
tered from the data stream.
Bit 2-0 = CD2-CD0: Base/Bit Clock Rate Selec-
tion. Define the division ratio between the core
clock (fINT divided by 13) and the clock supplied to
the Shift Register in Master mode.
Table 16. B ase/Bit Clock Ratio Selection
Note: For example, when an 8MHz CPU clock is
used, asynchronous operation at 9600 Baud is
possible (8MHz/13/64). Other Baud rates are
available by proportionally selecting division fac-
tors depending on CPU clock frequency.
Data setup time on Sin is typically 250ns min, while
data hold time is typically 50ns min.
SPI Data/Shift Register (SPIDSR)
Address: E0h —Read/Write
Reset status: XXh
SPIDSR is read/write, however write access is not
allowed if the SPRUN b it of Mode Control regi ster
is set to on e.
Data is sampled into SPDSR on the SCK edge de-
termined by the CPOL and CPHA b its. The aff ect
of these setting is shown in the following diagrams.
The Shift Register transmits and receives the Most
Si g n ifica nt Bit fi r st .
Bit 7-0 = DSR7-DSR0: Data Bits. These are the
SPI shift register data bits.
Miscellaneous Register (MISCR)
Address: DDh —Write only
Reset status: xxxxxxxb
Bit 7-1 = D7-D1: Reserved.
Bit 0 = D0: Bit 0. This bit, when set, selects the
Sout pin as the SPI output line. When this bit is
cleared, Sout acts as a standard I/O line.
70
SPINT DOV6 DIV5 DIV4 DIV3 CD2 CD1 CD0
CD2-CD0 Divide Ratio (decimal)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 256
DIV6-DIV3 Number of bits sent
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved (not to be used)
1
2
3
4
5
6
7
8
9
10
11 Refer to the
12 description of the
13 DIV6-DIV3 bits in
14 the DIV Register
15
70
D7 D6 D5 D4 D3 D2 D1 D0
70
-------D0
57/86
ST62T55C ST62T65C/E65C
SERIAL PERIPHERAL INTERFACE SPI (C on t’d)
4.6 SP I Timing Diagra m s
Figure 31. CPOL = 0 Clock Polarity Normal, CPHA = 0 Phase Selection Normal
Figure 32. CP OL = 1 Clock Polarity Inverted, CPHA = 0 Phase Selec tion Normal
SPRUN
Sout
Sin
b7 b6 b5 b4 b3 b2 b1 b0
VR001694
SCK
Sampling
SPRUN
SCK
Sout
Sin
b7 b6 b5 b4 b3 b2 b1 b0
VR0A1694
Sampling
58/86
ST62T55C ST62T65C/E65C
SERIAL PERIPHERAL INTERFACE SPI (C on t’d)
Figure 33. CPOL = 0 Clock Polarity Normal, CPHA = 1 Phase Selection Shifted
Figure 34. CP OL = 1 Clock Polarity Inverted, CPHA = 1 Phase Selectio n Shifted
SPRUN
SCK
Sout b7 b6 b5 b4 b3 b2 b1 b0
VR0B1694
Sin
Sampling
SPRUN
SCK
Sout b7 b6 b5 b4 b3 b2 b1 b0
VR0C1694
Sin
Sampling
59/86
ST62T55C ST62T65C/E65C
5 SOFTW AR E
5.1 ST6 ARCHITECTURE
The ST6 software has been designed to fully use
the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short,
to provide byte efficient programming capability.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program
may branch to a selected address depending on
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET
or RES instr uction i s proc essed.
5. 2 ADDRESSING MODES
The ST6 core offers nine addressing modes,
which are described in the following paragraphs.
Three different address spaces are available: Pro-
gram space, Data space, and Stack space. Pro-
gram spac e c ontains t he instruc tions whi ch are t o
be executed, plus the data for immediate mode in-
structions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and Input/
Output registers, the RAM locations and Data
ROM locations (for storage of tables and con-
stants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines
and interrupts.
Immediate. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As the operand is a ROM byte, the imme-
diate addressing mode is used to access con-
stants which do not change during program execu-
tion (e.g., a constant used to initialize a loop coun-
ter).
Direct. In the direct addressing mode, the address
of the byte which is processed by the instruction is
stored in the location which follows the opcode. Di-
rect addressing allows the user to directly address
the 256 bytes in Data Space memory with a single
two-byte instruction.
Short Direct. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the op-
code. Short direct addressing is a subset of the di-
rect addressing mode. (Note that 80h and 81h are
also indirect registers).
Extended. In the extended add ressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) which use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is two-
byte long.
Program Counter Relative. The relative address-
ing mode is only used in conditional branch in-
structions. The instruction is used to perform a test
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
ative instruction . If the condition is not true , the in-
struction which follows the relative instruction is
executed. The relative addressing mode instruc-
tion is one-byte long. The opcode is obtained in
adding the three most significant bits which char-
acterize the kind of the test, one bit which deter-
mines whe ther the branch is a f orward (when it is
0) or backward (when it is 1) branch and the four
less significant bits which give the span of the
branch (0h to Fh) which must be added or sub-
tracted to t he address of t he rel ative inst ruction t o
obtain the address of the branch.
Bit Direct. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
dress of the byte in whi ch t he specified bit must be
set or cleared. Thus, any bit in the 256 locations of
Data space memory can be set or cleared.
Bit Test & Branch. The bit test and branch ad-
dressing mode is a combina tion of direct address-
ing and relative addressing. The bit test and
branch instruction is three-by te long. T he bi t iden-
tification and the tested condition are included in
the opcode byte. The address of the byte to be
tested follows imm ediately the opcode in the P ro-
gram space. The third byte is the jump displace-
ment, which is in the ran ge of -127 to +128. This
displacement can be determined using a label,
which is converted by the assembler.
Indirect. In the indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the in-
direct registers, X or Y (80h,81h). The indirect reg-
ister is selected by the bit 4 of the opcode. A regis-
ter indirect instruction is one byte long.
Inherent. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.
60/86
ST62T55C ST62T65C/E65C
5.3 INSTRUCTION SET
The ST6 c ore offers a set of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/call, and bit m anipu lation. T he f ollowing par-
agraphs describe the different types.
All the instructions belonging to a given type are
presented in individual tables.
Loa d & S tore. These instruc tions use one, two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained from data memory using
one of the addressing modes.
For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
immediat e data.
Table 18. Loa d & Store Instructions
Notes:
X,Y. Indirect Regist er Po i nters , V & W S hort D ir ect Regist ers
# . Immediate data (stored in ROM memory)
rr. Dat a space regi ster
∆. Affected
* . Not Affected
Instruction Addressing Mode Bytes Cycles Flags
ZC
LD A, X Short Direct 1 4 ∆ *
LD A, Y Short Direct 1 4 ∆ *
LD A, V Short Direct 1 4 ∆ *
LD A, W Short Direct 1 4 ∆ *
LD X, A Short Direct 1 4 ∆ *
LD Y, A Short Direct 1 4 ∆ *
LD V, A Short Direct 1 4 ∆ *
LD W, A Short Direct 1 4 ∆ *
LD A, rr Direct 2 4 ∆ *
LD rr, A Direct 2 4 ∆ *
LD A, (X) Indirect 1 4 ∆ *
LD A, (Y) Indirect 1 4 ∆ *
LD (X), A Indirect 1 4 ∆ *
LD (Y), A Indirect 1 4 ∆ *
LDI A, #N Immediate 2 4 ∆ *
LDI rr, #N Immediate 3 4 * *
61/86
ST62T55C ST62T65C/E65C
INSTRUCTION SET (Cont’d)
Arithmetic and Logic. These instructions are
used to perform the arithmetic calculations and
logic operations. In AND, ADD, CP, SUB instruc-
tions one operand i s al ways the accumulator whi le
the other can be either a data space memory con-
tent or an immediate value in relation with the ad-
dressing mode. In CLR, DEC, INC instructions the
operand can be any of the 256 data space ad-
dresses. In COM, RLC, SLA the operand i s always
the accumulator.
Table 19. A rithmetic & Logic Instructions
Notes:
X,Y.In direct Register Pointers, V & W Short Direct RegistersD. Affected
# . I m med iate data (s tore d i n ROM memory)* . No t A ffected
r r . Data space register
Instruction Addressing Mode Bytes Cycles Flags
ZC
ADD A, (X) Indirect 1 4 ∆∆
ADD A, (Y) Indirect 1 4 ∆∆
ADD A, rr Direct 2 4 ∆∆
ADDI A, #N Immediate 2 4 ∆∆
AND A, (X) Indirect 1 4 ∆∆
AND A, (Y) Indirect 1 4 ∆∆
AND A, rr Direct 2 4 ∆∆
ANDI A, #N Immediate 2 4 ∆∆
CLR A Short Direct 2 4 ∆∆
CLR r Direct 3 4 * *
COM A Inherent 1 4 ∆∆
CP A, (X) Indirect 1 4 ∆∆
CP A, (Y) Indirect 1 4 ∆∆
CP A, rr Direct 2 4 ∆∆
CPI A, #N Immediate 2 4 ∆∆
DEC X Short Direct 1 4 ∆*
DEC Y Short Direct 1 4 ∆*
DEC V Short Direct 1 4 ∆*
DEC W Short Direct 1 4 ∆*
DEC A Direct 2 4 ∆*
DEC rr Direct 2 4 ∆*
DEC (X) Indirect 1 4 ∆*
DEC (Y) Indirect 1 4 ∆*
INC X Short Direct 1 4 ∆*
INC Y Short Direct 1 4 ∆*
INC V Short Direct 1 4 ∆*
INC W Short Direct 1 4 ∆*
INC A Direct 2 4 ∆*
INC rr Direct 2 4 ∆*
INC (X) Indirect 1 4 ∆*
INC (Y) Indirect 1 4 ∆*
RLC A Inherent 1 4 ∆∆
SLA A Inherent 2 4 ∆∆
SUB A, (X) Indirect 1 4 ∆∆
SUB A, (Y) Indirect 1 4 ∆∆
SUB A, rr Direct 2 4 ∆∆
SUBI A, #N Immediate 2 4 ∆∆
62/86
ST62T55C ST62T65C/E65C
INSTRUCTION SET (Cont’d)
Conditional Branch. The branch instructions
achieve a branch in the program when the select-
ed condition is met.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Control Instructions. The control instructions
control the MCU operations during program exe-
cution.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutines call
inside the whole program space.
Table 20. C ond itional Branch Instructions
Notes:
b. 3-bit addre ss rr. Dat a spac e registe r
e. 5 bit s i gned di s pl acement i n the ran ge -15 t o +16<F128M > ∆ . Affected. The tested bit is shifted into carry.
ee. 8 bi t si gned di s pl acement i n th e range -126 to +129 * . Not A ff ected
Table 21. B it Manipulation Instructions
Notes:
b. 3-bit address; * . Not<M> Affected
rr. Dat a space regi ster;
Table 22. C ontro l Instructions
Notes:
1. Thi s i nstructi on i s deactivate d<N>and a WAIT is auto m at i call y ex ecut ed inst ead of a STOP if th e watc hdog f uncti on i s selected.
∆ . Affect ed
*. Not Affected
Table 23. J ump & Call Instruc tions
Notes:
abc. 12-bit address;
* . Not Affected
Instruction Branch If Bytes Cycles Flags
ZC
JRC e C = 1 1 2 * *
JRNC e C = 0 1 2 * *
JRZ e Z = 1 1 2 * *
JRNZ e Z = 0 1 2 * *
JRR b, rr, ee Bit = 0 3 5 * ∆
JRS b, rr, ee Bit = 1 3 5 * ∆
Instruction Addressing Mode Bytes Cycles Flags
ZC
SET b,rr Bit Direct 2 4 * *
RES b,rr Bit Direct 2 4 * *
Instruction Addressing Mode Bytes Cycles Flags
ZC
NOP Inherent 1 2 * *
RET Inherent 1 2 * *
RETI Inherent 1 2 ∆∆
STOP (1) Inherent 1 2 * *
WAIT Inherent 1 2 * *
Instruction Ad dres sing Mode Bytes Cycles Flags
ZC
CALL abc Extended 2 4 * *
JP abc Extended 2 4 * *
63/86
ST62T55C ST62T65C/E65C
Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW 0
0000 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111
LOW
HI HI
0
0000
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD 0
0000
e abc e b0,rr,ee e # e a,(x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
1
0001
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 LDI 1
0001
e abc e b0,rr,ee e x e a,nn
1pcr2ext1pcr3 bt1pcr1 sd1prc2imm
2
0010
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 CP 2
0010
e abc e b4,rr,ee e # e a,(x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
3
0011
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI 3
0011
e abc e b4,rr,ee e a,x e a,nn
1pcr2ext1pcr3 bt1pcr1 sd1prc2imm
4
0100
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 ADD 4
0100
e abc e b2,rr,ee e # e a,(x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
5
0101
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 ADDI 5
0101
e abc e b2,rr,ee e y e a,nn
1pcr2ext1pcr3 bt1pcr1 sd1prc2imm
6
0110
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 INC 6
0110
e abc e b6,rr,ee e # e (x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
7
0111
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 7
0111
e abc e b6,rr,ee e a,y e #
1pcr2ext1pcr3 bt1pcr1 sd1prc
8
1000
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD 8
1000
e abc e b1,rr,ee e # e (x),a
1pcr2ext1pcr3 bt1pcr 1prc1ind
9
1001
2 RNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 9
1001
e abc e b1,rr,ee e v e #
1pcr2ext1pcr3 bt1pcr1 sd1prc
A
1010
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND A
1010
e abc e b5,rr,ee e # e a,(x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
B
1011
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 ANDI B
1011
e abc e b5,rr,ee e a,v e a,nn
1pcr2ext1pcr3 bt1pcr1 sd1prc2imm
C
1100
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 SUB C
1100
e abc e b3,rr,ee e # e a,(x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
D
1101
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 SUBI D
1101
e abc e b3,rr,ee e w e a,nn
1pcr2ext1pcr3 bt1pcr1 sd1prc2imm
E
1110
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 DEC E
1110
e abc e b7,rr,ee e # e (x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
F
1111
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC F
1111
e abc e b7,rr,ee e a,w e #
1pcr2ext1pcr3 bt1pcr1 sd1prc
Abbreviations for Addressing Mode s: Leg end:
dir Direct # Indicates Illegal Instructions
sd S hort Di rect e 5 Bit Displacement
imm Immedi ate b 3 Bit Addres s
inh Inhe rent rr 1byte data space address
ext Extended nn 1 byte im m edi ate data
b.d Bit Direct abc 12 bit add ress
bt Bit Te st ee 8 bit Di sp l acement
pcr Program Counter Relative
ind Indirect
2JRC
e
1prc
Mnemonic
Addressi ng Mode
Bytes
Cycle
Operand
64/86
ST62T55C ST62T65C/E65C
Opcode Map Sum m ar y (Continued)
LOW 8
1000 9
1001 A
1010 B
1011 C
1100 D
1101 E
1110 F
1111
LOW
HI HI
0
0000
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD 0
0000
e abc e b0,rr e rr,nn e a,(y)
1pcr2ext1pcr2b.d1pcr3imm1prc1ind
1
0001
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD 1
0001
e abc e b0,rr e x e a,rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
2
0010
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP 2
0010
e abc e b4,rr e a e a,(y)
1pcr2ext1pcr2b.d1pcr 1prc1ind
3
0011
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 CP 3
0011
e abc e b4,rr e x,a e a,rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
4
0100
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC 4 ADD 4
0100
e abc e b2,rr e e a,(y)
1pcr2ext1pcr2b.d1pcr1inh1prc1ind
5
0101
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD 5
0101
e abc e b2,rr e y e a,rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
6
0110
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC 6
0110
e abc e b6,rr e e (y)
1pcr2ext1pcr2b.d1pcr1inh1prc1ind
7
0111
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 INC 7
0111
e abc e b6,rr e y,a e rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
8
1000
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD 8
1000
e abc e b1,rr e # e (y),a
1pcr2ext1pcr2b.d1pcr 1prc1ind
9
1001
2 RNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD 9
1001
e abc e b1,rr e v e rr,a
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
A
1010
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RCL 2 JRC 4 AND A
1010
e abc e b5,rr e a e a,(y)
1pcr2ext1pcr2b.d1pcr1inh1prc1ind
B
1011
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 AND B
1011
e abc e b5,rr e v,a e a,rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
C
1100
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RET 2 JRC 4 SUB C
1100
e abc e b3,rr e e a,(y)
1pcr2ext1pcr2b.d1pcr1inh1prc1ind
D
1101
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB D
1101
e abc e b3,rr e w e a,rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
E
1110
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC E
1110
e abc e b7,rr e e (y)
1pcr2ext1pcr2b.d1pcr1inh1prc1ind
F
1111
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 DEC F
1111
e abc e b7,rr e w,a e rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
Abbreviations for Addressing Mode s: Leg end:
dir Direct # Indicates Illegal Instructions
sd S hort Di rect e 5 Bit Displacement
imm Immedi ate b 3 Bit Addres s
inh Inhe rent rr 1byte data space address
ext Extended nn 1 byte im m edi ate data
b.d Bit Direct abc 12 bit add ress
bt Bit Te st ee 8 bit Di sp l acement
pcr Program Counter Relative
ind Indirect
2JRC
e
1prc
Mnemonic
Addressi ng Mode
Bytes
Cycle
Operand
65/86
ST62T55C ST62T65C/E65C
6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.
For proper operation it is recommended that VI
and VO be higher than VSS and lower than VDD.
Reliability is enhanced if unused inputs are con-
nected to an appropriate logic voltage level (VDD
or VSS).
Power Considerations.The average chip-junc-
tion temperature, Tj, in Celsius can be obtained
from:Tj= TA + PD x RthJA
Where:TA = Ambient Temperature.
RthJA =Package thermal resistance (junc-
tion-to ambient).
PD = Pint + Pport.
Pint =IDD x VDD (chip internal power).
Pport =Port power dissipation (determ ined
by the user).
Notes:
- Stresses abov e those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
func tional operat i on of the device at these conditions is not imp l i ed. Ex posu re to maxim um rating co nditions for ext ended per i ods may
affect device reliability.
- (1) Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection
current is kept within the specification.
Symbol Parameter Value Unit
VDD Supply Voltage -0.3 to 7.0 V
VIInput Voltage VSS - 0.3 to VDD + 0.3(1) V
VOOutput Voltage VSS - 0.3 to VDD + 0.3(1) V
IVDD Total Current into VDD (source) 80 mA
IVSS Total Current out of VSS (sink) 100 mA
Tj Junction Temperature 150 °C
TSTG Storage Temperature -60 to 150 °C
66/86
ST62T55C ST62T65C/E65C
6.2 RECOMMENDED OPERATING CONDITIONS
Notes:
1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the
A/D conve rsion. F or a -1mA i nj ecti on, a maxim um 10 KΩ is re comm ended.
2.An oscillator frequency above 1MHz is recommended for reliable A/D results
Figure 3 5. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)
The shaded area is outside the r ecomm ended ope rating ran ge; dev i c e func tionali ty is not guarante ed under these co nditions.
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
TAOperating Temperature 6 Suffix Version
1 Suffix Version
3 Suffix Version
-40
0
-40
85
70
125 °C
VDD
Operating Supply Voltage
(Except ST626xB ROM devices)
fOSC = 4MHz, 1 & 6 Suffix
fOSC = 4MHz, 3 Suffix
fosc= 8MHz , 1 & 6 Suffix
fosc= 8MHz , 3 Suffix
3.0
3.0
3.6
4.5
6.0
6.0
6.0
6.0 V
Operating Supply Voltage
(ST626xB ROM devices)
fOSC = 4MHz, 1 & 6 Suffix
fOSC = 4MHz, 3 Suffix
fosc= 8MHz , 1 & 6 Suffix
fosc= 8MHz , 3 Suffix
3.0
3.0
4.0
4.5
6.0
6.0
6.0
6.0 V
fOSC
Oscillator Frequency2)
(Except ST626xB ROM devices)
VDD = 3.0V, 1 & 6 Suffix
VDD = 3.0V , 3 Suffix
VDD = 3.6V , 1 & 6 Suffix
VDD = 3.6V , 3 Suffix
0
0
0
0
4.0
4.0
8.0
4.0 MHz
Oscillator Frequency2)
(ST626xB ROM devices)
VDD = 3.0V, 1 & 6 Suffix
VDD = 3.0V , 3 Suffix
VDD = 4.0V , 1 & 6 Suffix
VDD = 4.0V , 3 Suffix
0
0
0
0
4.0
4.0
8.0
4.0 MHz
IINJ+ Pin Injection Current (positive) VDD = 4.5 to 5.5V +5 mA
IINJ- Pin Injection Current (n egative) VDD = 4.5 to 5.5V -5 mA
8
7
6
5
4
3
2
1
2.5 3 44.5 55.5 6
SUPPLY VO LTAGE (VDD)
Maximum FREQUENCY (MHz)
FUNCTION ALITY IS NOT
GUARANTEED IN
THIS AREA
3 Suffix ve r sion
1 & 6 Suffix vers ion
3.6
3 Suffix vers ion
ST626xB ROM devices
All d evi ces except ST6 26xB ROM d evic es
1 & 6 Suffix
version
67/86
ST62T55C ST62T65C/E65C
6.3 DC ELECTRICAL CHARACTERISTICS
(TA = -40 to +125°C unless otherwise specified)
Notes:
(1) Hysteresis voltage between switching levels
(2) All peri pherals runn in g
(3) All peri pherals in stand-by
Symbol Parameter Te st Condi tion s Value Unit
Min. Typ. Max.
VIL Input Low Level Voltage
All Input pins VDD x 0.3 V
VIH Input High Level Voltage
All Input pins VDD x 0.7 V
VHys Hysteresis Voltage (1)
All Input pins VDD= 5V
VDD= 3V 0.2
0.2 V
Vup LVD Thres hold in power-on 4.1 4.3
Vdn L VD threshold in powerdown 3.5 3.8
VOL
Low Level Output Voltage
All Output pins VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = + 3mA 0.1
0.8 V
Low Level Output Voltage
30 mA Sink I/O pins VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = +7mA
VDD= 5.0V; IOL = +15mA
0.1
0.8
1.3
VOH High Level Output Voltage
All Output pins VDD= 5.0V; IOH = -10µA
VDD= 5.0V; IOH = -3.0mA 4.9
3.5 V
RPU Pull-up Resistance All Input pins 40 100 350 ΚΩ
RESET pin 150 350 900
IIL
IIH
Input Leakage Current
All Input pins but RESET VIN = VSS (No Pull-Up configured)
VIN = VDD 0.1 1.0 µA
Input Leakage Current
RESET pin VIN = VSS
VIN = VDD -8 -16 -30
10
IDD
Supply Current in RESET
Mode VRESET=VSS
fOSC=8MHz 7mA
Supply Current in
RUN Mode (2) VDD=5.0V fINT=8MHz 7 mA
Supply Current in WAIT
Mode (3) VDD=5.0V fINT=8MHz 2.5 mA
Supply Current in STOP
Mode, with LVD disabled(3) ILOAD=0mA
VDD=5.0V 20 µA
Supply Current in STOP
Mode, with LVD enabled(3) ILOAD=0mA
VDD=5.0V 500
Retentio n EPROM Data Retention TA = 55°C 10 years
68/86
ST62T55C ST62T65C/E65C
DC ELECTRICAL CHARACTERISTICS (Cont’d)
(TA = -40 to +85°C unless otherwise specified))
Note:
(*) All Peripherals in stand-by.
6.4 AC ELECTRICAL CHARACTERISTICS
(TA = -40 to +125°C unless otherwise specified)
Notes:
1. Period for which VDD has to be conne ct ed at 0V t o al l ow int ernal Rese t f uncti on at next power -up.
2 An oscillator frequency above 1MHz is recommended for reliable A/D results.
3. Me as ure perfo rm ed with OSCi n pin soldered on PCB , with an around 2p F equi valent capac i ta nce.
Symbol Parameter Te st Condi tion s Value Unit
Min. Typ. Max.
Vup LVD Thres hold in power-on Vdn +50 mV 4.1 4.3 V
Vdn L VD threshold in powerdown 3.6 3.8 V up -50 mV V
VOL
Low Level Output Voltage
All Output pins VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = + 5mA
VDD= 5.0V; IOL = + 10mAv
0.1
0.8
1.2 V
Low Level Output Voltage
30 mA Sink I/O pins
VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = +10mA
VDD= 5.0V; IOL = +20mA
VDD= 5.0V; IOL = +30mA
0.1
0.8
1.3
2.0
VOH High Level Output Voltage
All Output pins VDD= 5.0V; IOH = -10µA
VDD= 5.0V; IOH = -5.0mA 4.9
3.5 V
IDD Supply Current in STOP
Mode, with LVD disabled(*) ILOAD=0mA
VDD=5.0V 10 µA
Symbol Pa rameter Test Cond itions Value Unit
Min. Typ. Max.
tREC Supply Recovery Time (1) 100 ms
TWEE EEPROM Write Time TA = 25°C
TA = 85°C
TA = 125°C
5
10
20
10
20
30 ms
Endurance
(2) EEPROM WRITE/ERASE Cycle QA LOT Acceptance (25°C) 300 ,000 1 million cycles
Retention EEPROM Data Retention TA = 55°C 10 years
fLFAO Internal frequency with LF A O active 200 400 800 kHz
fOSG Internal Frequency with OSG
enabled2)
VDD = 3V
VDD = 3.6V
VDD = 4.5V
VDD = 6V
1
1
2
2fOSC MHz
fRC Internal frequency with RC oscilla-
tor and OSG disabled2) 3)
VDD=5.0V (Except 626xB ROM)
R=47kΩ
R=100kΩ
R=470kΩ
4
2.7
800
5
3.2
850
5.8
3.5
900
MHz
MHz
kHz
VDD=5.0V (626xB ROM)
R=10kΩ
R=27kΩ
R=67kΩ
R=100kΩ
6.3
4.7
2.8
2.2
8.2
5.9
3.6
2.8
9.8
7
4.3
3.4
MHz
MHz
MHz
MHz
CIN Input Capacitance All Inputs Pins 10 pF
COUT Output Capacitance All Outputs Pins 10 pF
69/86
ST62T55C ST62T65C/E65C
6.5 A/D CONVERTER CHARACTERISTICS
(TA = -40 to +125°C unless otherwise specified)
Notes:
1. Nois e at VDD, VSS <10mV
2. Wi th os cilla tor frequencies les s than 1M Hz, the A/D Convert er acc uracy is decr eased .
6.6 TIMER CHARACTERISTICS
(TA = -40 to +125°C unless otherwise specified)
6.7 SPI CHARACTERISTICS
(TA = -40 to +125°C unless otherwise specified)
6.8 ARTIMER ELECTRICAL CHARACTERISTICS
(TA = -40 to +125°C unless otherwise specified)
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
Res Resolution 8 Bit
ATOT Total Accuracy (1) (2) fOSC > 1.2MHz
fOSC > 32kHz ±2
±4LSB
tCConv ersion Time fOSC = 8MHz (TA < 85°C)
fOSC = 4 MHz 70
140 µs
ZIR Zero Input Reading Conversion result when
VIN = VSS 00 Hex
FSR Full Scale Reading Conversion result when
VIN = VDD FF Hex
ADIAnalog Input Current During
Conversion VDD= 4.5V 1.0 µA
ACIN Analog Input Capacitan ce 2 5 pF
Symb ol Paramete r Test Conditions Value Unit
Min. Typ. Max.
fIN Input Frequency on TIMER Pin MHz
tWPulse Width at TIMER Pin VDD = 3.0V
VDD >4.5V 1
125 µs
ns
fINT
4
----------
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
FCL Clock Frequency Applied on Scl 500 kHz
tSU Set-up Time Applied on Sin 250 ns
thHold Time Applied onSin 50 ns
Symbol Parameter Test Conditions Value Unit
Min Typ Max
fIN Input Frequency on ARTIMin Pin RUN and WAIT Modes MHz
STOP mode 2
70/86
ST62T55C ST62T65C/E65C
Figure 36. Vol versus Iol on all I/O port at Vdd=5V
Figure 37. Vol versus Iol on all I/O port at T=25°C
Fig ure 38. Vol versu s Iol for High si nk (30mA) I/Oport s at T=25°C
010203040
0
2
4
6
8
Iol (mA)
Vol (V)
T = -40°C
T = 2 5°C
T = 9 5°C
T = 125°C
This curves represents typical variations and is given for guidance only
0 10203040
0
2
4
6
8
Iol (mA)
Vol (V)
Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V
This curve s represents typical variations and is given for guidan ce only
0 10203040
0
1
2
3
4
5
Iol (mA)
Vo l (V)
Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V
This curves represents typical variations and is given for guidance only
71/86
ST62T55C ST62T65C/E65C
Figure 39. Vol versus Iol for High sink (30mA) I/O ports at Vdd=5V
Figure 40. Voh versus Ioh on all I/O port at 25°C
Figure 41. Voh versus Ioh on all I/O port at Vdd=5V
0 10203040
0
1
2
3
4
5
Iol (mA)
Vol (V)
T = -40°C
T = 25°C
T = 95°C
T = 125°C
This curves represents typical variations and is given for guidance only
0 10203040
-2
0
2
4
6
Ioh (mA)
Voh ( V)
Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V
This curve s represents typical variations and is given for guida nce only
0 10203040
-2
0
2
4
6
Ioh (mA)
Voh (V)
T = -40°C
T = 25°C
T = 95°C
T = 125°C
This curves represents typical variations and is given for guidance only
72/86
ST62T55C ST62T65C/E65C
Figu re 42 . Idd W AI T v ersus V DD at 8 Mhz for OTP devices
Figu re 43 . Idd S TOP versus V DD for OTP devices
Figu re 44 . Idd S TOP versus V DD for ROM devices
This curves represents typical variations and is given for guidance only
0
0.5
1
1.5
2
2.5
Vdd
Idd WAIT (mA)
3V 4V 5V 6V
T = -40°C
T = 2 5°C
T = 9 5°C
T = 125°C
This curves represents typical variations and is given for guidance only
-2
0
2
4
6
8
Vdd
Idd STOP (µA)
3V 4V 5V 6V
T = -40°C
T = 25°C
T = 95°C
T = 125°C
This curves represents typical variations and is given for guidance only
-0.5
0
0.5
1
1.5
2
Vdd
Idd STOP (µA)
3V 4V 5V 6V
T = -40°C
T = 25°C
T = 95°C
T = 125°C
73/86
ST62T55C ST62T65C/E65C
Figu re 45 . Idd W AI T v ersus V DD at 8Mhz for ROM devices
Figure 46. Idd RUN versus VDD at 8 Mhz for ROM and OTP devices
Figure 47. LVD thresholds versus temperature
This curves represent s typical variations and is given for guidance onl y
0
0.5
1
1.5
2
2.5
Vdd
Idd WA IT (mA)
3V 4V 5V 6V
T = -40°C
T = 25°C
T = 95°C
T = 125°C
This curves represents typical variations and is given for guidance only
0
2
4
6
8
Vdd
Id d RUN ( mA)
3V 4V 5V 6V
T = -40°C
T = 2 5°C
T = 9 5°C
T = 125°C
This curves represent s typical variations and is given for guidance only
3.7
3.8
3.9
4
4.1
4.2
Temp
Vthresh.
-40°C25°C95°C125°C
Vup
Vdn
74/86
ST62T55C ST62T65C/E65C
Figure 48. RC frequency versus VDD for ROM ST626xB on ly
Figure 49. RC frequency versus VDD (Except for ST626x B ROM devices)
This curves represents typical variations and is given for guidance only
3456
VDD (volts)]
1
10
MHz
Frequency
R=1OK
R=27K
R=67K
R=100K
This curves represents typical variations and is given for guidance only
33.544.555.56
0.1
1
10
MHz
VDD (volts)
Frequency
R=47K
R=100K
R=470K
75/86
ST62T55C ST62T65C/E65C
7 GE NERAL INFORMATI ON
7.1 PACKAG E MECHANICAL DATA
Figure 50. 28-Pin Plastic Dual In-Line Package, 600-mil Width
Figure 51. 28-Pin Plastic Small Outline Package, 300-mil Width
Dim. mm inches
Min Typ Max Min Typ Max
A6.35 0.250
A1 0.38 0.015
A2 3.18 4.95 0.125 0.195
B0.36 0.56 0.014 0.022
B1 0.76 1.78 0.030 0.070
C0.20 0.38 0.008 0.015
D35.05 39.75 1.380 1.565
D1 0.13 0.005
e2.54 0.100
eB 17.78 0.700
E15.24 15.88 0.600 0.625
E1 12.32 14.73 0.485 0.580
L2.92 5.08 0.115 0.200
Number of Pins
N28
E
E1
eB
C
L
AA2
A1
BB1 D
D1 e
Dim. mm inches
Min Typ Max Min Typ Max
A2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B0.33 0.51 0.013 0.020
C0.23 0.32 0.009 0.013
D17.70 18.10 0.697 0.713
E7.40 7.60 0.291 0.299
e1.27 0.050
H10.00 10.65 0.394 0.419
h0.25 0.75 0.010 0.030
α0°8°0°8°
L0.40 1.27 0.016 0.050
Number of Pins
N28
h x 45×
C
L
a
A
A1
e
B
D
HE
L
76/86
ST62T55C ST62T65C/E65C
PACKAGE MECHANICAL DATA (Cont’d)
Figure 5228-Cera m ic Dual In Line Package, 600-mi l Width
Figure 53. 28-Pin Plastic Shrink Small Outline Package
Dim. mm inches
Min Typ Max Min Typ Max
A4.17 0.164
A1 0.76 0.030
B0.36 0.46 0.56 0.014 0.018 0.022
B1 0.76 1.27 1.78 0.030 0.050 0.070
C0.20 0.25 0.38 0.008 0.010 0.015
D34.95 35.56 36.17 1.376 1.400 1.424
D1 33.02 1.300
E1 14.61 15.11 15.62 0.575 0.595 0.615
e2.54 0.100
G12.70 12.95 13.21 0.500 0.510 0.520
G1 12.70 12.95 13.21 0.500 0.510 0.520
G2 1.14 0.045
L2.92 5.08 0.115 0.200
S1.27 0.050
Ø8.89 0.350
Number of Pins
N28
CDIP28W
Dim. mm inches
Min Typ Max Min Typ Max
A2.00 0.079
A1 0.05 0.002
A2 1.65 1.75 1.85 0.065 0.069 0.073
b0.22 0.38 0.009 0.015
c0.09 0.25 0.004 0.010
D9.90 10.20 10.50 0.390 0.402 0.413
E7.40 7.80 8.20 0.291 0.307 0.323
E1 5.00 5.30 5.60 0.197 0.209 0.220
e0.65 0.026
θ0°4°8°0°4°8°
L0.55 0.75 0.95 0.022 0.030 0.037
Number of Pins
N28
E1 E
h
L
c
A
A1
A2
e
b
D
77/86
ST62T55C ST62T65C/E65C
7.2 ORDERING INFORMATION
Table 24OTP/EPROM VERSION ORDERING INFORMAT ION
Sales Type Program
Memory (Bytes) EEPROM (Byte s) T empe ratur e Rang e Pac kage
ST62E65CF1 3884 (EPROM) 128 0 to +70°CCDIP20
ST62T55CB6
ST62T55CB3
3884 (OTP) None
-40 to + 85°C
-40 to + 125°CPDIP28
ST62T55CM6
ST62T55CM3 -40 to + 85°C
-40 to + 125°CPSO28
ST62T55CN6
ST62T55CN3 -40 to + 85°C
-40 to + 125°CSSOP28
ST62T65CB6
ST62T65CB3
3884 (OTP) 128
-40 to + 85°C
-40 to + 125°CPDIP28
ST62T65CM6
ST62T65CM3 -40 to + 85°C
-40 to + 125°CPSO28
ST62T65CN6
ST62T65CN3 -40 to + 85°C
-40 to + 125°CSSOP28
78/86
ST62T55C ST62T65C/E65C
Notes:
July 2001 79/86
Rev. 2.9
ST62P55C
ST62P65C
8-BIT FAST RO M MCUs WITH A/D CONVERTER,
SAFE RESE T, AUTO-RELOAD TIMER, EEPROM AND SPI
■3.0 to 6.0V Supply Operating Range
■8 MHz Maximum Clock Frequency
■-40 to +125°C Operat ing Tempe rature Rang e
■Run, Wait and Stop Modes
■5 Interrupt Vectors
■Look-up Table capability in Program Memory
■Data Storage in Program Memory:
User selectable size
■Data RAM: 128 bytes
■Data EEPROM: 128 bytes (none o n ST62T55C )
■User Program mab le Options
■21 I/O pins, fully programmab le as:
–Input with pull-up resistor
–Input without pull-up resistor
–Input with interrupt generation
–Open-drain or push-pull output
–Analog Input
■8 I/O lines can sink up to 30mA to drive LEDs or
TRIACs directly
■8-bit Timer/Counter with 7-bit programmable
prescaler
■8-bit Auto-reload Timer wi th 7-bit programmable
prescaler (AR Timer)
■Digital Watchdog
■Oscillator Safe Guard
■Low Voltag e Detecto r fo r Safe Reset
■8-bit A/D Converter with 13 analog inputs
■8-b it Synchronous Pe ripheral Interface (SPI)
■On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■User configurable Power-on Reset
■One external Non-Maskable Interrupt
■ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
DEVICE ROM
(Bytes) EEPROM
ST62P55C 3884 -
ST62P65C 3884 128
(See end of Datasheet for Ordering Information)
PDIP28
PS028
SS0P28
80/86
ST62P55C ST62P65C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62P55C and ST62P65C are the Factory
Advanced Service Technique ROM (FASTROM)
versions of ST62T55C and ST62T65C OTP devic-
es.
They offer the same functionality as OTP devices,
selecting as FASTROM options the options de-
fined in t he program mab le option b yte of the OT P
version.
1.2 ORDERING INFORMATION
The following s ection deals with the procedure f or
transfer of customer codes to STMicroelectronics.
1.2.1 Tra nsfer of Customer Cod e
Customer code is made up of the ROM contents
and the list of the selected FASTROM options.
The ROM contents are to be sent on diskette, or
by electronic means, with the hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
The select ed options are c ommunicat ed to ST Mi-
croelectronics using the correctly filled OPTION
LIST appended. See page 84.
1.2.2 Listing Generation and Verification
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refers exactly to the ROM con-
tents and options which will be used to produce
the specified MCU. The listing is then returned to
the customer who must thoroughly check, com-
plete, sign and return it to STMicroelectronics. The
signed listing fo rms a part of t he contractual agree-
ment for the production of the specific customer
MCU.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Table 25. ROM Memory M ap ST62P55C/ P 65C
Table 26. FASTROM vers ion Ord ering Information
(*) Ad va nced informat io
Device Address Description
0000h-007Fh
0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Sales Type ROM EEPROM (Bytes) Temperature Range Package
ST62P55CB1/XXX
ST62P55CB6/XXX
ST62P55CB3/XXX (*)
3884 Bytes
None
0 to +70°C
-40 to + 85°C
-40 to + 125°CPDIP28
ST62P55CM1/XXX
ST62P55CM6/XXX
ST62P55CM3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°CPSO28
ST62P55CN1/XXX
ST62P55CN6/XXX
ST62P55CN3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°CSSOP28
ST62P65CB1/XXX
ST62P65CB6/XXX
ST62P65CB3/XXX (*)
128
0 to +70°C
-40 to + 85°C
-40 to + 125°CPDIP28
ST62P65CM1/XXX
ST62P65CM6/XXX
ST62P65CM3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°CPSO28
ST62P65CN1/XXX
ST62P65CN6/XXX
ST62P65CN3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°CSSOP28
July 2001 81/86
Rev. 2.9
ST6255C
ST6265B
8-BIT ROM MCUs WITH A/D CONVERTER,
SAFE RESE T, AUTO-RELOAD TIMER, EEPROM AND SPI
■3.0 to 6.0V Supply Operating Range
■8 MHz Maximum Clock Frequency
■-40 to +125°C Operat ing Tempe rature Rang e
■Run, Wait and Stop Modes
■5 Interrupt Vectors
■Look-up Table capability in Program Memory
■Data Storage in Program Memory:
User selectable size
■Data RAM: 128 bytes
■Data EEPROM: 128 bytes (none o n ST62T55C )
■User Program mab le Options
■21 I/O pins, fully programmab le as:
–Input with pull-up resistor
–Input without pull-up resistor
–Input with interrupt generation
–Open-drain or push-pull output
–Analog Input
■8 I/O lines can sink up to 30mA to drive LEDs or
TRIACs directly
■8-bit Timer/Counter with 7-bit programmable
prescaler
■8-bit Auto-reload Timer wi th 7-bit programmable
prescaler (AR Timer)
■Digital Watchdog
■8-bit A/D Converter with 13 analog inputs
■8-b it Synchronous Pe ripheral Interface (SPI)
■On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■User configurable Power-on Reset
■One external Non-Maskable Interrupt
■ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
DEVICE ROM
(Bytes) EEPROM LVD & OSG
ST6255C 3884 - Yes
ST6265B 3884 128 No
(See end of Datasheet for Ordering Information)
PDIP28
PS028
SS0P28
82/86
ST6255C ST6265B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST6255C and ST6265B are mask pro-
grammed ROM version of ST62T55C and
ST62T65C OTP devices .
They offer the same functionality as OTP devices,
selecting as ROM options the options defined in
the programmable option byte of the OTP version,
except the LVD & OSG options that are not availa-
ble on the ST6265B ROM device.
Figure 54. Programming Waveform
1.2 ROM READOUT PROTECTION
If the ROM READOUT PROTECTION option is
selected, a protection fuse can be blown to pre-
vent any access to the program memory conten t.
In case the user wants to blow this fuse, high volt-
age must be applied on the TEST pin .
Figu re 55. Pro gramm in g Circuit
Note: ZPD15 is used for overvoltage protection
0.5s min
TEST
15
14V typ
10
5
TEST
100mA
4mA typ
VR02001
max
150 µs typ
t
VR02003
TEST
5V
100nF
47mF
PROTECT
100nF
VDD
VSS
ZPD15
15V
14V
83/86
ST6255C ST6265B
1.3 ORDERING INFORMATION
The following s ection deals with the procedure f or
transfer of customer codes to STMicroelectronics.
1.3.1 Tra nsfer of Customer Cod e
Customer code is made up of the ROM contents
and the list of the selected mask options. The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file gener-
ated by the development tool. All unused bytes
mu st be set to FFh.
The selected mask options are communicated to
STMicroelectronics using the correctly filled OP-
TION LIST appended. Se e page 84.
1.3.2 Li st in g Generat i on a nd V eri f icati on
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This li sting refers exactl y to the mask which
will be used to produce the specified MCU. The
listing is then returned to the customer who must
thoroughly check, complete, sign and return it to
STMicroelectronics. The signed listing forms a
part of the contractual agreement for the creation
of the specific customer mask.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Table 27. ROM Memory M ap for ST6255 C/65B
Tab le 28. RO M Versi on Ord e ri ng I nform at io n
Device Address Description
0000h-007Fh
0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Sales Type ROM EEPROM (Bytes) Temperature Range Package
ST6255CB1/XXX
ST6255CB6/XXX
ST6255CB3/XXX
3884 Bytes
None
0 to +70°C
-40 to + 85°C
-40 to + 125°CPDIP28
ST6255CM1/XXX
ST6255CM6/XXX
ST6255CM3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°CPSO28
ST6255CN1/XXX
ST6255CN6/XXX
ST6255CN3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°CSSOP28
ST6265BB1/XXX
ST6265BB6/XXX
ST6265BB3/XXX
128
0 to +70°C
-40 to + 85°C
-40 to + 125°CPDIP28
ST6265BM1/XXX
ST6265BM6/XXX
ST6265BM3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°CPSO28
ST6265BN1/XXX
ST6265BN6/XXX
ST6265BN3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°CSSOP28
84/86
ST6255C ST6265B
ST6255C/65B/P55C/P65C MICROCONTROLLER OPTION LIST
Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phone: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references:
Device: [ ] ST6255C (4 KB) [ ] ST6265B (4 KB)
[ ] ST62P55C (4 KB) [ ] ST62P65C (4 KB)
Package: [ ] Dual in Line Plastic
[ ] Small Outline Plastic with conditioning
[ ] Shrink Small Outline Plastic with conditioning
Conditioning option: [ ] Standard (Tube) [ ] Tape & Reel
Temperature Range: [ ] 0°C to + 70°C [ ] - 40°C to + 85°C
[ ] - 40°C to + 125°C
Marking: [ ] Standard marking
[ ] Special marking (ROM only):
PDIP28 (10 char. max): _ _ _ _ _ _ _ _ _ _
PSO28 (8 char. max): _ _ _ _ _ _ _ _
SSOP28 (11 char. max): _ _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Oscillator Safeguard*: [ ] Enabled [ ] Disabled
Oscillator Selection: [ ] Quartz crystal / Ceramic resonator
[ ] RC network
Reset Delay [ ] 32768 cycle delay [ ] 2048 cycle delay
Watchdog Selection: [ ] Software Activation [ ] Hardware Activation
PB1:PB0 pull-up at RESET*: [ ] Enabled [ ] Disabled
PB3:PB2 pull-up at RESET*: [ ] Enabled [ ] Disabled
External STOP Mode Control: [ ] Enabled [ ] Disabled
Readout Prote ction: F ASTR OM:
[ ] Enabled [ ] Disabled
ROM: [ ] Enabled:
[ ] Fuse is blown by STMicroelectronics
[ ] Fuse can be blown by the customer
[ ] Disabled
Low Voltage Detector*: [ ] Enabled [ ] Disabled
NMI pull-up*: [ ] Enabled [ ] Disabled
ADC Synchro*: [ ] Enabled [ ] Disabled
*except on ST6265B
Comments:
Oscillator Frequency in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85/86
ST6255C ST6265B
2 SU MMAR Y OF CHANGES
Rev. Main Changes Date
2.9
Modification of “Additional Notes for EEPROM Parallel Mode” (p.13)
In section 4.2.4 on page 45: vector #4 instead of vector #3 in description of bit 6 (TSCR register).
Changed fRC values in section 6.4 on page 68
Changed Figure 48 on page 74.
Changed option list on page 84.
July 2001
86/86
ST6255C ST6265B
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No lic ense is gra nted
by i m pl i cati on or otherwise unde r any paten t or p atent ri ght s of S T M i croe l ectroni cs . Specific ations ment i oned in th i s pub licati on ar e subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical component s in l i f e support devices or sy st em s wit hout the expre ss writ t en approv al of STM i cro el ectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics - All Rights Reserved.
Pur ch ase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rig ht s t o use these components in an
I2C system i s granted provided t hat the system conforms to the I 2C Standard Specification as defined by Philips.
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