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LMH6723
,
LMH6724
SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
LMH6723/LMH6724 Single/Dual/Quad 370-MHz, 1-mA
Current Feedback Operational Amplifier
1 Features 3 Description
The LMH6723/LMH6724 provides a 260 MHz small
1• Large Signal Bandwidth and Slew Rate 100% signal bandwidth at a gain of +2 V/V and a 600 V/μs
Tested slew rate while consuming only 1 mA from ±5V
• 370 MHz Bandwidth (AV= 1, VOUT = 0.5 VPP)−3supplies.
dB BW The LMH6723/LMH6724 supports video applications
• 260 MHz (AV= +2 V/V, VOUT = 0.5 VPP)−3 dB BW with its 0.03% and 0.11° differential gain and phase
• 1 mA Supply Current for NTSC and PAL video signals, while also offering a
flat gain response of 0.1 dB to 100 MHz. Additionally,
• 110 mA Linear Output Current the LMH6723/LMH6724 can deliver 110 mA of linear
• 0.03%, 0.11° Differential Gain, Phase output current. This level of performance, as well as a
• 0.1 dB Gain Flatness to 100 MHz wide supply range of 4.5 to 12V, makes the
• Fast Slew Rate: 600 V/μsLMH6723/LMH6724 an ideal op amp for a variety of
portable applications. With small packages (SOIC
• Unity Gain Stable and SOT-23), low power requirement, and high
• Single Supply Range of 4.5 to 12V performance, the LMH6723/LMH6724 serves a wide
• Improved Replacement for CLC450, CLC452, variety of portable applications.
(LMH6723) The LMH6723/LMH6724 is manufactured in Texas
Instruments' VIP10 complimentary bipolar process.
2 Applications Device Information(1)
• Line Driver PART NUMBER PACKAGE BODY SIZE (NOM)
• Portable Video LMH6723 SOT-23 (5) 2.90 mm × 1.60 mm
• A/D Driver LMH6723 SOIC (8) 4.90 mm × 3.91 mm
• Portable DVD LMH6724 SOIC (8) 4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6723
,
LMH6724
SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
www.ti.com
Table of Contents
7.3 Evaluation Boards................................................... 13
1 Features.................................................................. 17.4 Feedback Resistor Selection .................................. 14
2 Applications ........................................................... 17.5 Active Filters............................................................ 16
3 Description............................................................. 17.6 Driving Capacitive Loads ........................................ 16
4 Revision History..................................................... 27.7 Inverting Input Parasitic Capacitance ..................... 17
5 Pin Configuration and Functions......................... 37.8 Layout Considerations ............................................ 18
6 Specifications......................................................... 47.9 Video Performance ................................................. 18
6.1 Absolute Maximum Ratings ...................................... 47.10 Single 5-V Supply Video....................................... 18
6.2 Handling Ratings....................................................... 48 Power Supply Recommendations...................... 19
6.3 Recommended Operating Conditions....................... 48.1 ESD Protection........................................................ 19
6.4 Thermal Information.................................................. 49 Device and Documentation Support.................. 20
6.5 ±5V Electrical Characteristics ................................... 59.1 Related Links .......................................................... 20
6.6 ±2.5V Electrical Characteristics ................................ 69.2 Trademarks............................................................. 20
6.7 Typical Performance Characteristics ........................ 89.3 Electrostatic Discharge Caution.............................. 20
7 Application and Implementation ........................ 13 9.4 Glossary.................................................................. 20
7.1 Application Information............................................ 13 10 Mechanical, Packaging, and Orderable
7.2 Typical Application.................................................. 13 Information........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (April 2013) to Revision I Page
• Changed data sheet structure and organization. Added, updated, or renamed the following sections: Device
Information Table, Application and Implementation; Power Supply Recommendations; Device and Documentation
Support; Mechanical, Packaging, and Ordering Information. Removed "LMH6725" from title and document. ..................... 1
• Deleted "Channel Matching" and "Crosstalk" plots. .............................................................................................................. 8
• Changed Figure 11 ................................................................................................................................................................ 9
• Changed Figure 12 ................................................................................................................................................................ 9
• Changed Figure 29............................................................................................................................................................... 11
• Changed Figure 30............................................................................................................................................................... 11
• Deleted sentence beginning "These evaluation boards..." .................................................................................................. 13
• Deleted sentence beginning, "Although the example..." ..................................................................................................... 17
• Deleted sentence beginning "The SOIC-14 has ..." ............................................................................................................ 19
Changes from Revision G (April 2013) to Revision H Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 19
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Product Folder Links: LMH6723 LMH6724
OUT B
1
2
3
4 5
6
7
8
OUT A
-IN A
+IN A
V-
V+
-IN B
+IN B
-+
+-
A
B
V+
1
2
3
45
6
7
8
N/C
-IN
+IN
V-
OUTPUT
N/C
+
-
N/C
OUT
V-
+IN
V+
-IN
+-
1
2
3
5
4
LMH6723
,
LMH6724
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SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
5 Pin Configuration and Functions
5-Pin SOT-23 (LMH6723) 8-Pin SOIC Package (LMH6723)
Package DBV Package D08A
(Top View) (Top View)
8-Pin SOIC Package (LMH6724)
Package D08A
(Top View)
Pin Functions
PIN
NUMBER I/O DESCRIPTION
NAME LMH6723 LMH6723 LMH6724
(DBV) (D08A) (D08A)
-IN 4 2 I Inverting Input
+IN 3 3 I Non-inverting Input
-IN A 2 I ChA Inverting Input
+IN A 3 I ChA Non-inverting Input
-IN B 6 I ChB Inverting Input
+IN B 5 I ChB Non-inverting Input
N/C 1,5,8 – –
OUT A 1 O ChA Output
OUT B 7 O ChB Output
OUTPUT 1 6 O Output
V - 2 4 4 I Negative Supply
V+ 5 7 8 I Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings(1)(2)(3)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC (V+- V-) ±6.75 V
IOUT 120(4) mA
Common Mode Input Voltage ±VCC V
Maximum Junction Temperature +150 °C
Soldering Information Infrared or Convection (20 sec) 235 °C
Wave Soldering (10 sec) 260 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(4) The maximum continuous output current (IOUT) is determined by device power dissipation limitations. See Power Supply
Recommendations for more details.
6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range −65 +150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2000
pins(1)(2)
V(ESD) Electrostatic discharge V
Machine Model (MM), per JEDEC specification JESD22-C101, all 200
pins(2)(3)
(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human Body Model, 1.5 kΩin series with 100 pF. Machine Model, 0ΩIn series with 200 pF.
(3) JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions(1)
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Operating Temperature Range −40 +85 °C
Nominal Supply Voltage 4.5 12 V
(1) The maximum continuous output current (IOUT) is determined by device power dissipation limitations. See Power Supply
Recommendations for more details.
6.4 Thermal Information SOT-23 SOIC
THERMAL METRIC(1) DBV D08A UNIT
5 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 230°C/W 166°C/W °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
6.5 ±5V Electrical Characteristics
Unless otherwise specified, AV= +2, RF= 1200Ω, RL= 100Ω.Boldface limits apply at temperature extremes.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY DOMAIN RESPONSE
SSBW −3 dB Bandwidth Small Signal VOUT = 0.5 VPP 260 MHz
LSBW −3dB Bandwidth Large Signal VOUT = 4.0 VPP 90 110 MHz
85 95
UGBW −3 dB Bandwidth Unity Gain VOUT = .2 VPP AV= 1 V/V 370 MHz
.1dB BW .1 dB Bandwidth VOUT = 0.5 VPP 100 MHz
DG Differential Gain RL= 150Ω, 4.43 MHz 0.03%
DP Differential Phase RL= 150Ω, 4.43 MHz 0.11 deg
TIME DOMAIN RESPONSE
TRS Rise and Fall Time 4V Step 2.5 ns
TSS Settling Time to 0.05% 2V Step 30 ns
SR Slew Rate 4V Step 500 600 V/μs
DISTORTION and NOISE RESPONSE
HD2 2nd Harmonic Distortion 2 VPP, 5 MHz −65 dBc
HD3 3rd Harmonic Distortion 2 VPP, 5 MHz −63 dBc
EQUIVALENT INPUT NOISE
VN Non-Inverting Voltage Noise >1 MHz 4.3 nV/√Hz
NICN Inverting Current Noise >1 MHz 6 pA/√Hz
ICN Non-Inverting Current Noise >1 MHz 6 pA/√Hz
STATIC, DC PERFORMANCE
VIO Input Offset Voltage ±3
1 mV
±3.7
IBN Input Bias Current Non-Inverting ±4
−2 µA
±5
IBI Input Bias Current Inverting ±4
0.4 µA
±5
PSRR Power Supply Rejection Ratio DC, 1V Step LMH6723 59 64
57 dB
LMH6724 59 64
55
CMRR Common Mode Rejection Ratio DC, 1V Step LMH6723 57 60
55 dB
LMH6724 57 60
53
ICC Supply Current (per amplifier) RL=∞1.2 mA
11.4
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ> TA. See Application and Implementation for information on temperature
derating of this device. Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as
noted.
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±5V Electrical Characteristics (continued)
Unless otherwise specified, AV= +2, RF= 1200Ω, RL= 100Ω.Boldface limits apply at temperature extremes.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MISCELLANEOUS PERFORMANCE
RIN+ Input Resistance Non-Inverting 100 kΩ
RIN−Input Resistance Inverting Ω
500
(Output Resistance of Input Buffer)
CIN Input Capacitance Non-Inverting 1.5 pF
ROUT Output Resistance Closed Loop 0.01 Ω
VOOutput Voltage Range RL=∞LMH6723 ±4 ±4.1
±3.9 V
LMH6724 ±4 ±4.1
±3.85
VOL Output Voltage Range, High RL= 100Ω3.6 3.7
3.5 V
Output Voltage Range, Low RL= 100Ω −3.25 −3.45
−3.1
CMVR Input Voltage Range Common Mode, CMRR > 50 dB ±4.0 V
IOOutput Current Sourcing, VOUT = 0 95 110
70 mA
Sinking, VOUT = 0 −80 110
−70
6.6 ±2.5V Electrical Characteristics
Unless otherwise specified, AV= +2, RF= 1200Ω, RL= 100Ω.Boldface limits apply at temperature extremes.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY DOMAIN RESPONSE
SSBW −3 dB Bandwidth Small Signal VOUT = 0.5 VPP 210 MHz
LSBW −3 dB Bandwidth Large Signal VOUT = 2.0 VPP 95 125 MHz
UGBW −3 dB Bandwidth Unity Gain VOUT = 0.5 VPP, AV= 1 V/V 290 MHz
.1dB BW .1 dB Bandwidth VOUT = 0.5 VPP 100 MHz
DG Differential Gain RL= 150Ω, 4.43 MHz .03%
DP Differential Phase RL= 150Ω, 4.43 MHz 0.1 deg
TIME DOMAIN RESPONSE
TRS Rise and Fall Time 2V Step 4 ns
SR Slew Rate 2V Step 275 400 V/μs
DISTORTION AND NOISE RESPONSE
HD2 2nd Harmonic Distortion 2 VPP, 5 MHz −67 dBc
HD3 3rd Harmonic Distortion 2 VPP, 5 MHz −67 dBc
EQUIVALENT INPUT NOISE
VN Non-Inverting Voltage >1 MHz 4.3 nV/√Hz
NICN Inverting Current >1MHz 6 pA/√Hz
ICN Non-Inverting Current >1MHz 6 pA/√Hz
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ> TA. See Application and Implementation for information on temperature
derating of this device. Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as
noted.
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±2.5V Electrical Characteristics (continued)
Unless otherwise specified, AV= +2, RF= 1200Ω, RL= 100Ω.Boldface limits apply at temperature extremes.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC, DC PERFORMANCE
VIO Input Offset Voltage ±3
−0.5 mV
±3.4
IBN Input Bias Current Non-Inverting ±4
−2.7 µA
±5
IBI Input Bias Current Inverting ±4
−0.7 µA
±5
PSRR Power Supply Rejection Ratio DC, 0.5V Step LMH6723 59 62
57 dB
LMH6724 58 62
55
CMRR Common Mode Rejection Ratio DC, 0.5V Step LMH6723 57 59
53 dB
LMH6724 55 59
52
ICC Supply Current (per amplifier) RL=∞1.1
0.9 mA
1.3
MISCELLANEOUS PERFORMANCE
RIN+ Input Resistance Non-Inverting 100 kΩ
RIN−Input Resistance Inverting Ω
500
(Output Resistance of Input Buffer)
CIN Input Capacitance Non-Inverting 1.5 pF
ROUT Output Resistance Closed Loop 0.02 Ω
VOOutput Voltage Range RL=∞±1.55 ±1.65 V
±1.4
VOL Output Voltage Range, High RL= 100ΩLMH6723 1.35 1.45
1.27 V
LMH6724 1.35 1.45
1.26
Output Voltage Range, Low RL= 100ΩLMH6723 −1.25 −1.38
−1.15 V
LMH6724 −1.25 −1.38
−1.15
CMVR Input Voltage Range Common Mode, CMRR > 50 dB ±1.45 V
IOOutput Current Sourcing 70 90
60 mA
Sinking −30 −60
−30
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110 100 1000
FREQUENCY (MHz)
-10
-8
-6
-4
-2
0
2
4
GAIN (dB)
VS = ±5V
VOUT = 2VPP
AV = +1, RF = 2000:
AV = 6, RF = 500:
AV = 2, RF = 1200:
AV = -1, RF = 1200:
110 100 1000
FREQUENCY (MHz)
-6
-5
-4
-3
-2
-1
0
1
GAIN (dB)
VS = ±6V
VS = ±5V
VS = ±3.3V
VS = ±2.5V
VOUT = 2VPP
AV = 2V/V
110 100 1000
FREQUENCY (MHz)
-10
-8
-6
-4
-2
0
2
4
GAIN (dB)
VOUT = 1VPP
VOUT = 2VPP
VOUT = 0.5VPP
VS = ±2.5V
RF = 2000:
AV = 1V/V
110 100 1000
FREQUENCY (MHz)
-10
-8
-6
-4
-2
0
2
4
GAIN (dB)
VOUT = 4VPP
VOUT = 1VPP
VOUT = 2VPP
VOUT = 0.5VPP
VS = ±5V
RF = 2000:
AV = 1V/V
110 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
GAIN (dB)
VOUT = 0.5VPP
VOUT = 2VPP
VOUT = 1VPP
VS = ±2.5V
AV = 2V/V
RF = 1200:
110 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
GAIN (dB)
VOUT = 0.5VPP
VOUT = 4VPP
VOUT = 2VPP
VOUT = 1VPP
VS = ±5V
AV = 2V/V
RF = 1200:
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,
LMH6724
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6.7 Typical Performance Characteristics
AV= 2, RF= 1200Ω, RL= 100Ω, unless otherwise specified.
Figure 1. Frequency Response vs. VOUT, AV= 2 Figure 2. Frequency Response vs. VOUT, AV= 2
Figure 3. Frequency Response vs. VOUT, AV= 1 Figure 4. Frequency Response vs. VOUT, AV= 1
Figure 6. Frequency Response vs. Supply Voltage
Figure 5. Large Signal Frequency Response
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Frequency (kHz)
| Z | (dB:)
Phase (degrees)
0.1 1 10 100 1000 10000 100000 1000000
40 -200
50 -160
60 -120
70 -80
80 -40
90 0
100 40
110 80
120 120
130 160
140 200
D001
Gain
Phase
Frequency (kHz)
| Z | (dB:)
Phase (Degrees)
0.1 1 10 100 1000 10000 100000
40 -180
50 -140
60 -100
70 -60
80 -20
90 20
100 60
110 100
120 140
130 180
D002
Gain
Phase
0.1 1 10 100 1000
FREQUENCY (MHz)
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
GAIN (dB)
RF = 800:
RF = 1200:
RF = 2000:
VS = ±2.5V
VOUT = 1VPP
0.1 1 10 100 1000
FREQUENCY (MHz)
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
GAIN (dB)
RF = 800:
RF = 1.2k:
RF = 2k:
VS = ±5V
VOUT = 1VPP
RL = 100:
1 2 3 4 5 6 7 8 9 10
0
500
1000
1500
2000
2500
RF (:)
GAIN (V/V)
1 2 3 4 5 6 7 8 9 10
0
200
400
600
800
1000
1200
1400
RF (:)
GAIN (-V/V)
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Typical Performance Characteristics (continued)
AV= 2, RF= 1200Ω, RL= 100Ω, unless otherwise specified.
Figure 7. Suggested RFvs. Gain Non-Inverting Figure 8. Suggested RFvs. Gain Inverting
Figure 9. Frequency Response vs. RFFigure 10. Frequency Response vs. RF
Figure 11. Open Loop Gain & Phase Figure 12. Open Loop Gain & Phase
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0.1 1 10 100 1000
FREQUENCY (MHz)
-10
-8
-6
-4
-2
0
2
GAIN (dB)
VS = ±2.5V
RL = 1k:||CL
VOUT = .8VPP
CL = 100pF, ROUT = 24:
CL = 47pF, ROUT = 30:
CL = 10pF, ROUT = 48:
0.1 1 10 100 1000
FREQUENCY (MHz)
-10
-8
-6
-4
-2
0
2
GAIN (dB)
VS = ±5V
RL = 1k:||CL
VOUT = .8VPP
CL = 100pF, ROUT = 24:
CL = 47pF, ROUT = 30:
CL = 10pF, ROUT = 48:
0 10 20 30 40 50
-80
-75
-70
-65
-60
-55
-50
-45
-40
DISTORTION (dBc)
FREQUENCY (MHz)
VS = ±2.5V
VOUT = 2VPP
HD2
HD3
0 10 20 30 40 50
-80
-75
-70
-65
-60
-55
-50
-45
-40
DISTORTION (dBc)
FREQUENCY (MHz)
VS = ±5V
VOUT = 2VPP
HD2
HD3
00.5 1 1.5 2 2.5 3
VOUT (VPP)
-75
-70
-65
-60
-55
-50
-45
-40
-35
DISTORTION (dBc)
VS = ±2.5V
f = 5MHz
HD3 HD2
01 2 3 4 5 6 7 8
VOUT (VPP)
-80
-75
-70
-65
-60
-55
-50
-45
-40
DISTORTION (dBc)
VS = ±5V
f = 5MHz
HD2
HD3
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Typical Performance Characteristics (continued)
AV= 2, RF= 1200Ω, RL= 100Ω, unless otherwise specified.
Figure 14. HD2 & HD3 vs. VOUT
Figure 13. HD2 & HD3 vs. VOUT
Figure 15. HD2 & HD3 vs. Frequency Figure 16. HD2 & HD3 vs. Frequency
Figure 17. Frequency Response vs. CLFigure 18. Frequency Response vs. CL
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0.001 0.01 0.1 1 100
FREQUENCY (MHz)
0.001
0.01
10
100
|Z|OUT (:)
10
0.1
1
VS = ±2.5V
VS = ±5V
0.001 0.1 100
FREQUENCY (MHz)
0
20
40
70
CMRR (dB)
10
1
0.01
60
30
10
50
VS = ±5V
VS = ±2.5V
0.001 0.1 100
FREQUENCY (MHz)
0
20
40
70
PSRR (dB)
10
1
0.01
60
30
10
50
PSRR+
PSRR-
VS = ±2.5V
80
0.001 0.1 100
FREQUENCY (MHz)
0
30
PSRR (dB)
10
1
0.01
60
50
20
10
40
70 PSRR+
PSRR-
VS = ±5V
110 100 1000
CAPACITIVE LOAD (pF)
0
10
20
30
40
50
60
SUGGESTED ROUT
VS = ±2.5V
LOAD = 1k:||CL
110 100 1000
CAPACITIVE LOAD (pF)
0
10
20
30
40
50
60
SUGGESTED ROUT
VS = ±5V
LOAD = 1k:||CL
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Typical Performance Characteristics (continued)
AV= 2, RF= 1200Ω, RL= 100Ω, unless otherwise specified.
Figure 19. Suggested ROUT vs. CLFigure 20. Suggested ROUT vs. CL
Figure 21. PSRR vs. Frequency Figure 22. PSRR vs. Frequency
Figure 24. CMRR vs. Frequency
Figure 23. Closed Loop Output Resistance
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Time (nS)
Vout (V)
0 5 10 15 20
-1.25
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
D001
Vs = r5V
Time (nS)
Vout (V)
0 5 10 15 20 25 30 35 40 45 50 55
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
D001
Vs = r5V
FREQUENCY (MHz)
10 100 1k
-3
-2
-1
0
1
GAIN (dB)
VS = ±2.5V
VOUT = 0.5 VPP
RF = 1.1 k:
110 100 1000
FREQUENCY (MHz)
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
CROSSTALK (dBc)
CHANNEL A
CHANNEL B
-0.75 -0.5 -0.25 0 0.25 0.5 0.75
OUTPUT OFFSET (V) 100 IRE = 0.714V
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
DIFFERENTIAL GAIN (%)
-0.01
0.01
0.03
0.05
0.07
0.09
0.11
DIFFERENTIAL PHASE (°)
PHASE
GAIN
VS = ±5V
f = 4.43MHz
RL = 150:
FREQUENCY (MHz)
10 100 1k
-3
-2
-1
0
1
GAIN (dB)
VS = ±5V
VOUT = 0.5 VPP
RF = 1.1 k:
LMH6723
,
LMH6724
SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
www.ti.com
Typical Performance Characteristics (continued)
AV= 2, RF= 1200Ω, RL= 100Ω, unless otherwise specified.
Figure 25. Differential Gain & Phase Figure 26. Channel Matching (LMH6724)
Figure 28. Crosstalk (LMH6724)
Figure 27. Channel Matching (LMH6724)
Figure 29. Output Small Signal Pulse Response Figure 30. Output Large Signal Pulse Response
12 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated
Product Folder Links: LMH6723 LMH6724
LMH6723
,
LMH6724
www.ti.com
SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
7 Application and Implementation
7.1 Application Information
The LMH6723/LMH6724 is a high speed current feedback amplifier manufactured on Texas Instruments' VIP10
(Vertically Integrated PNP) complimentary bipolar process. LMH6723/LMH6724 offers a unique combination of
high speed and low quiescent supply current making it suitable for a wide range of battery powered and portable
applications that require high performance. This amplifier can operate from 4.5V to 12V nominal supply voltages
and draws only 1 mA of quiescent supply current at 10V supplies (±5V typically). The LMH6723/LMH6724 has no
internal ground reference so single or split supply configurations are both equally useful.
7.2 Typical Application
7.3 Evaluation Boards
Texas Instruments provides the following evaluation boards as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the datasheet plots were measured with these boards.
DEVICE PACKAGE BOARD PART NUMBER
LMH6723MA SOIC-8 LMH730227
LMH6723MF SOT-23 LMH730216
LMH6724MA SOIC-8 LMH730036
Copyright © 2003–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMH6723 LMH6724
0.1 1 10 100 1000
FREQUENCY (MHz)
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
GAIN (dB)
RF = 800:
RF = 1200:
RF = 2000:
VS = ±2.5V
VOUT = 1VPP
LMH6723
,
LMH6724
SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
www.ti.com
7.4 Feedback Resistor Selection
One of the key benefits of a current feedback operational amplifier is the ability to maintain optimum frequency
response independent of gain by using appropriate values for the feedback resistor (RF). The Electrical
Characteristics and Typical Performance plots were generated with an RFof 1200Ω, a gain of +2V/V and ±5V or
±2.5V power supplies (unless otherwise specified). Generally, lowering RFfrom its recommended value will peak
the frequency response and extend the bandwidth; however, increasing the value of RFwill cause the frequency
response to roll off faster. Reducing the value of RFtoo far below it's recommended value will cause overshoot,
ringing, and eventually, oscillation.
Figure 31. Frequency Response vs. RF
Figure 31 shows the LMH6723/LMH6724's frequency response as RFis varied (RL= 100Ω, AV= +2). This plot
shows that an RFof 800Ωresults in peaking. An RFof 1200Ωgives near maximal bandwidth and gain flatness
with good stability. Since each application is slightly different, it is worth experimenting to find the optimal RFfor a
given circuit. In general, a value of RFthat produces ~0.1 dB of peaking is the best compromise between stability
and maximal bandwidth. Note that it is not possible to use a current feedback amplifier with the output shorted
directly to the inverting input. The buffer configuration of the LMH6723/LMH6724 requires a 2000-Ωfeedback
resistor for stable operation. For other gains see the charts Figure 32 and Figure 33. These charts provide a
good place to start when selecting the best feedback resistor value for a variety of gain settings.
14 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated
Product Folder Links: LMH6723 LMH6724
1 2 3 4 5 6 7 8 9 10
0
200
400
600
800
1000
1200
1400
RF (:)
GAIN (-V/V)
1 2 3 4 5 6 7 8 9 10
0
500
1000
1500
2000
2500
RF (:)
GAIN (V/V)
LMH6723
,
LMH6724
www.ti.com
SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
Feedback Resistor Selection (continued)
For more information see Application Note OA-13 which describes the relationship between RFand closed-loop
frequency response for current feedback operational amplifiers. The value for the inverting input impedance for
the LMH6723/LMH6724 is approximately 500 Ω. The LMH6723/LMH6724 is designed for optimum performance
at gains of +1 to +5V/V and −1 to −4V/V. Higher gain configurations are still useful; however, the bandwidth will
fall as gain is increased, much like a typical voltage feedback amplifier.
Figure 32. RF vs. Non-Inverting Gain
Figure 32 and Figure 33 show the value of RFversus gain. A higher RFis required at higher gains to keep RG
from decreasing too far below the input impedance of the inverting input. This limitation applies to both inverting
and non-inverting configurations. For the LMH6723/LMH6724 the input resistance of the inverting input is
approximately 500Ωand 100Ωis a practical lower limit for RG. The LMH6723/LMH6724 begins to operate in a
gain bandwidth limited fashion in the region where RFmust be increased for higher gains. Note that the amplifier
will operate with RGvalues well below 100 Ω; however, results will be substantially different than predicted from
ideal models. In particular, the voltage potential between the Inverting and Non-Inverting inputs cannot be
expected to remain small.
For inverting configurations the impedance seen by the source is RG|| RT. For most sources this limits the
maximum inverting gain since RFis determined by the desired gain as shown in Figure 33. The value of RGis
then RF/Gain. Thus for an inverting gain of −4 V/V the input impedance is equal to 100Ω. Using a termination
resistor, this can be brought down to match a 50-Ωor 75-Ωsource; however, a 150Ωsource cannot be matched
without a severe compromise in RF.
Figure 33. RFvs. Inverting Gain
Copyright © 2003–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMH6723 LMH6724
+
-
RIN
51:
RF
1.2k:
X1
-
+ROUT
51:
RG
1.2k:
CL
10pF RL
1k:
+
-
6.8PF
C2
100nF
RIN
75:
RG
1.2k:
RF
1.2k:
100nF
C3
6.8PF
C4
X1
-
+
ROUT
75:
C1
LMH6723
,
LMH6724
SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
www.ti.com
7.5 Active Filters
When using any current feedback operational amplifier as an active filter it is necessary to be careful using
reactive components in the feedback loop. Reducing the feedback impedance, especially at higher frequencies,
will almost certainly cause stability problems. Likewise capacitance on the inverting input should be avoided. See
Application Notes OA-07 and OA-26 for more information on Active Filter applications for Current Feedback Op
Amps.
When using the LMH6723/LMH6724 as a low-pass filter the value of RFcan be substantially reduced from the
value recommended in the RFvs. Gain charts. The benefit of reducing RFis increased gain at higher
frequencies, which improves attenuation in the stop band. Stability problems are avoided because in the stop
band additional device bandwidth is used to cancel the input signal rather than amplify it. The benefit of this
change depends on the particulars of the circuit design. With a high pass filter configuration reducing RFwill
likely result in device instability and is not recommended.
Figure 34. Typical Application with Suggested Supply Bypassing
Figure 35. Decoupling Capacitive Loads
7.6 Driving Capacitive Loads
Capacitive output loading applications will benefit from the use of a series output resistor as shown in Figure 35.
The charts "Suggested ROUT vs. Cap Load" give a recommended value for selecting a series output resistor for
mitigating capacitive loads. The values suggested in the charts are selected for .5 dB or less of peaking in the
frequency response. This gives a good compromise between settling time and bandwidth. For applications where
maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced
slightly from the recommended values.
There will be amplitude lost in the series resistor unless the gain is adjusted to compensate; this effect is most
noticeable with heavy loads (RL< 150Ω).
16 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated
Product Folder Links: LMH6723 LMH6724
(2)
(3)
(4)
(1)
OUTPUT
R6
1:
R5
1:
R4
1:
R8
3.5 k:
R2
3 k:
R1
750:
R3
50:
ein
R11
20:
+
-
-
+
+
-
C1
680 pF
-
+
R7
1:
R9
3.5 k:
R10
3.5 k:
+
-
RIN
51:
RF
1.2k:
X1
-
+ROUT
51:
RG
1.2k:
CL
10pF RL
1k:
LMH6723
,
LMH6724
www.ti.com
SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
Driving Capacitive Loads (continued)
An alternative approach is to place ROUT inside the feedback loop as shown in Figure 36. This will preserve gain
accuracy, but will still limit maximum output voltage swing.
Figure 36. Series Output Resistor Inside Feedback Loop
7.7 Inverting Input Parasitic Capacitance
Parasitic capacitance is any capacitance in a circuit that was not intentionally added. It is produced through
electrical interaction between conductors and can be reduced but never entirely eliminated. Most parasitic
capacitances that cause problems are related to board layout or lack of termination on transmission lines. See
Layout Considerations for hints on reducing problems due to parasitic capacitances on board traces.
Transmission lines should be terminated in their characteristic impedance at both ends.
High speed amplifiers are sensitive to capacitance between the inverting input and ground or power supplies.
This shows up as gain peaking at high frequency. The capacitor raises device gain at high frequencies by
making RGappear smaller. Capacitive output loading will exaggerate this effect.
One possible remedy for this effect is to slightly increase the value of the feedback (and gain set) resistor. This
will tend to offset the high frequency gain peaking while leaving other parameters relatively unchanged. If the
device has a capacitive load as well as inverting input capacitance, using a series output resistor as described in
Driving Capacitive Loads will help.
Figure 37. High Output Current Composite Amplifier
When higher currents are required than a single amplifier can provide, the circuit of Figure 37 can be used.
Careful attention to a few key components will optimize performance from this circuit. The first thing to note is
that the buffers need slightly higher value feedback resistors than if the amplifiers were individually configured.
As well, R11 and C1provide mid circuit frequency compensation to further improve stability. The composite
amplifier has approximately twice the phase delay of a single circuit. The larger values of R8, R9and R10, as well
as the high frequency attenuation provided by C1and R11, ensure that the circuit does not oscillate.
Copyright © 2003–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMH6723 LMH6724
110 100
6
7
8
9
10
11
12
13
14
GAIN (dB)
FREQUENCY (MHz)
GAIN
PHASE
VS = ±5V
VOUT = 2.5 VPP
RL = 5.6:
AV = 5 -180
-135
-90
-45
0
45
90
135
180
PHASE (°)
LMH6723
,
LMH6724
SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
www.ti.com
Inverting Input Parasitic Capacitance (continued)
Resistors R4, R5, R6, and R7are necessary to ensure even current distribution between the amplifiers. Since they
are inside the feedback loop they have no effect on the gain of the circuit. The circuit shown in Figure 37 has a
gain of 5. The frequency response of this circuit is shown in Figure 38.
Figure 38. Composite Amplifier Frequency Response
7.8 Layout Considerations
Whenever questions about layout arise, use the evaluation board as a guide. Evaluation boards are shipped with
sample requests.
To reduce parasitic capacitances ground and power planes should be removed near the input and output pins.
Components in the feedback loop should be placed as close to the device as possible. For long signal paths
controlled impedance lines should be used, along with impedance matching at both ends.
Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to
ground are applied in pairs. The larger electrolytic bypass capacitors can be located anywhere on the board;
however, the smaller ceramic capacitors should be placed as close to the device as possible.
7.9 Video Performance
The LMH6723/LMH6724 has been designed to provide good performance with both PAL and NTSC composite
video signals. The LMH6723/LMH6724 is specified for PAL signals. Typically, NTSC performance is marginally
better due to the lower frequency content of the signal. Performance degrades as the loading is increased;
therefore, best performance will be obtained with back terminated loads. The back termination reduces
reflections from the transmission line and effectively masks transmission line and other parasitic capacitances
from the amplifier output stage. Figure 34 shows a typical configuration for driving a 75Ωcable. The amplifier is
configured for a gain of 2 to make up for the 6dB of loss in ROUT.
7.10 Single 5-V Supply Video
With a 5V supply the LMH6723/LMH6724 is able to handle a composite NTSC video signal, provided that the
signal is AC coupled and level shifted so that the signal is centered around VCC/2.
7.10.1 Application Curves
See Figure 31 through Figure 33 and Figure 38.
18 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated
Product Folder Links: LMH6723 LMH6724
LMH6723
,
LMH6724
www.ti.com
SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
8 Power Supply Recommendations
Follow these steps to determine the maximum power dissipation for the LMH6723/LMH6724:
1. Calculate the quiescent (no-load) power: PAMP = ICC * (VS)
where VS= V+- V-
2. Calculate the RMS power dissipated in the output stage: PD(rms) = rms ((VS-VOUT)*IOUT) where VOUT and
IOUT are the voltage and current of the external load and Vsis the supply voltage.
3. Calculate the total RMS power: PT= PAMP +PD
The maximum power that the LMH6723/LMH6724 package can dissipate at a given temperature can be derived
with the following equation:
PMAX = (150º - TAMB)/ RθJA
where
• TAMB = Ambient temperature (°C)
• RθJA = Thermal resistance, from junction to ambient, for a given package (°C/W) (1)
For the SOIC-8 package RθJA is 166°C/W and for the SOT-23-5 it is 230°C/W.
8.1 ESD Protection
The LMH6723/LMH6724 is protected against electrostatic discharge (ESD) on all pins. The LMH6723 will survive
2000V Human Body Model or 200V Machine Model events.
Under closed loop operation the ESD diodes have no effect on circuit performance. There are occasions,
however, when the ESD diodes will be evident. If the LMH6723/LMH6724 is driven into a slewing condition the
ESD diodes will clamp large differential voltages until the feedback loop restores closed loop operation. Also, if
the device is powered down and a large input signal is applied, the ESD diodes will conduct.
Copyright © 2003–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMH6723 LMH6724
LMH6723
,
LMH6724
SNOSA83I –AUGUST 2003–REVISED AUGUST 2014
www.ti.com
9 Device and Documentation Support
9.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
LMH6723 Click here Click here Click here Click here Click here
LMH6724 Click here Click here Click here Click here Click here
9.2 Trademarks
All trademarks are the property of their respective owners.
9.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
9.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated
Product Folder Links: LMH6723 LMH6724
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6723 MWC ACTIVE WAFERSALE YS 0 1 TBD Call TI Call TI -40 to 85
LMH6723MA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMH67
23MA
LMH6723MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMH67
23MA
LMH6723MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMH67
23MA
LMH6723MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 AB1A
LMH6723MFX NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 AB1A
LMH6723MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 AB1A
LMH6724MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMH67
24MA
LMH6724MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMH67
24MA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6723MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6723MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6723MFX SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6723MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6724MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6723MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6723MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMH6723MFX SOT-23 DBV 5 3000 210.0 185.0 35.0
LMH6723MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMH6724MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/E 09/2019
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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