Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch TDA8443A When the synchronization pulse is over, the current source is switched off and the voltage at pin 24 will rise to its higher level. Because of the time constant at pin 24, the restoration will take some microseconds. The voltage at pin 24 is also sensed internally and at the time it is between 0.456VP and 0.544VP, a time pulse is generated and used for the clamping action. Input clamps The R, G, B respectively (R-Y), Y and (B-Y) video signals are AC-coupled to the IC where they are clamped on the black level. The timing information for this clamping action is derived from the associated synchronization signal SYNC, which could also consist of the composite video information signal CVBS. The syncsignal is AC-coupled to the IC where it is clamped on top-sync level, information obtained from this action is used to generate the clamp pulses. 2. Using a sandcastle pulse (external clamping) If an associated sandcastle pulse is available, it can also be used as a clamping pulse. In this event the sandcastle pulse should be connected to pin 24, the top of the clamping pulse should be between 0.544VP and 0.456VP. The timing of the internal clamping pulse will be equal to the timing of the higher part of the sandcastle pulse. If the sync signal is also connected, the current sink will also become active during the synchronization pulses. This means that the sandcastle pulse should be connected to pin 24 via a 1 k dropping resistor. In this event only the sandcastle pulse at pin 24 will be influenced during sync pulses, but the sandcastle pulse at the sandcastle source will be unchanged. The clamp pulses can be generated in two ways: 1. Using the sync information (internal clamping) The sync information is clamped on top-sync and the information obtained from this action is used to switch an internal current source at pin 24. Pin 24 should be connected to VP via a 4.7 k resistor, and a 1 nF capacitor to ground. During video scan the voltage at pin 24 will be HIGH (equals positive supply voltage). During the synchronization pulses the voltage at pin 24 will drop to zero because of the current sink (2.5 mA). handbook, halfpage VP V1 = 0.544 V P V2 = 0.456 VP 9.4 k V1 1.8 k V2 clamp pulse signal 9.4 k pin 24 ON when current sync = 2.5 mA OFF when current sync = 0 mA MEA623 Tolerance on V1 and V2 is given by R/R and VP/VP. The diffusion process gives R/R (max) = 1.5%. Fig.7 Clamping circuit. 1995 Mar 07 15 Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch TDA8443A outputs handbook, full pagewidth SDA SCL S0 S1 VP S2 (B Y) outputs Y (R Y) GND SYNC CLAMP 4.7 k 1 nF 13 14 15 16 17 18 19 20 21 22 23 24 5 4 3 2 1 TDA8443A 12 11 47 nF (B Y) 10 47 nF Y 9 7 4.7 F 47 nF (R Y) 8 ON SYNC1 6 22 nF internal voltage 47 nF 47 nF B G 7 channel 1 (colour decoder) 9 8 R 11 10 13 12 4.7 F 47 nF FS 15 14 16 17 SYNC2 Fig.6 Application diagram (example). 1995 Mar 07 14 SEL 19 18 20 channel 2 (peritelevision connector) VP MLD007 Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch TDA8443A APPLICATION INFORMATION Table 10 Channel input/output information INPUT 1 INPUT 2 Y = 0.34 V U = -1.33 V V = -1.05 V - S = 0.3 V - Y = 0.34 V U = -1.33 V B = 0.75 V V = -1.05 V - Y = 0.68 V B = 0.75 V V = -2.10 V 1995 Mar 07 2 1 1 1 1 1 1 1 2 1 0 0 1 1 0 0 2 1 0 1 0 1 0 1 2 1 1 0 0 1 1 0 S = 0.6 V Y = 0.34 V - U = -1.33 V V = -1.05 V S = 0.6 V Y = 0.34 V Y = 0.34 V U = -1.33 V U = -1.33 V V = -1.05 V V = -1.05 V S = 0.6 V Y = 0.68 V - S = 0.3 V - V = -2.10 V U = -2.66 V S = 0.3 V V = -1.05 V U = -2.66 V G = 0.75 V Y = 0.34 V U = -1.33 V D3 S = 0.6 V S = 0.3 V - D4 S = 0.6 V R = 0.75 V S = 0.3 V V = -1.05 V D5 Y = 0.68 V Y = 0.34 V U = -1.33 V V = -1.05 V G = 0.75 V S = 0.3 V - MODE S = 0.6 V S = 0.3 V V = -1.05 V U = -1.33 V R = 0.75 V Y = 0.34 V U = -1.33 V OUTPUT Y = 0.34 V U = -2.66 V V = -2.10 V S = 0.6 V Y = 0.34 V Y = 0.68 V U = -1.33 V U = -2.66 V V = -1.05 V V = -2.10 V S = 0.3 V S = 0.6 V 13 Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch TDA8443A handbook, full pagewidth fast switching input signal switching delay 90 % output signal (YUV) 50 % 10 % MLD006 switching time Fig.5 Fast switching signal diagram. 1995 Mar 07 12 Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch TDA8443A TIMING CHARACTERISTICS I2C-bus load conditions: 4 k pull-up resistor to +5 V; 200 pF capacitor to GND; all values are referenced to VIH = 3 V and VIL = 1.5 V; see Fig.4. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. tBUF time bus must be free before start 4.7 - s tSU;STA set-up time for start condition 4.7 - s tHD;STA hold time for start condition 4.0 - s tLOW SCL and SDA LOW time 4.7 - s tHIGH SCL HIGH time 4.0 - s tr SCL and SDA rise time - 1.0 s tf SCL and SDA fall time - 0.3 s tSU;DAT data set-up time (write) 250 - ns 1.0 - s - 2 s acknowledge hold time 0 - s set-up time for stop condition 4.7 - s tHD;DAT data hold time (write) tSU;ACK acknowledge set-up time note 1 tHD;ACK tSU;STO Note 1. Timing tHD;DAT deviates from the I2C-bus specification. After reset has been activated, a delay of 50 s must occur before transmission may be resumed. handbook, full pagewidth SDA (WRITE) t BUF t HD; DAT tf t SU; ACK tr t HD; ACK t LOW SCL t SU; STA t LOW t HIGH t HD; STA t SU; DAT Fig.4 I2C-bus timing diagram. 1995 Mar 07 11 t SU; STO MLD005 Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch SYMBOL TDA8443A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Select input VIH HIGH level input voltage 3 - VIL LOW level input voltage -0.3 IIH HIGH level input current - IIL LOW level input current VIH VIL VP V - 0.4 V 0 10 A -50 -10 0 A HIGH level input voltage 3 - VP V LOW level input voltage -0.3 - 1.5 V IIH HIGH level input current - - 10 A IIL LOW level input current - - 10 A ON input Notes 1. Crosstalk is defined as the unwanted data transfer from an output, driven at nominal level, to other inputs and outputs on the IC and is expressed as a ratio in dBs. Vo ( p - p) 2. Signal-to-noise ratio = 20log ----------------------- ( B = 5 MHz ) V no ( rms ) V RR ( supply ) 3. Supply voltage ripple rejection = 20log ----------------------------------------V RR ( at the output ) 1995 Mar 07 10 Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch SYMBOL Gdiff(p-p) PARAMETER differential gain at nominal output signals (peak-to-peak value) TDA8443A CONDITIONS MIN. TYP. MAX. UNIT R-Y = 1.05 V (p-p) - - 10 % B-Y = 1.33 V (p-p) - - 10 % Y = 0.34 V (p-p) - - 10 % S/N signal-to-noise ratio nominal input; B = 5 MHz; note 2 50 - - dB SVRR supply voltage ripple rejection note 3 30 - - dB VO DC output levels during clamping - 5.3 - V Synchronization channels Gdiff gain difference (programmed value) B bandwidth - - 10 % -3 dB - 50 - MHz +3 dB; gain x 1 - 20 - MHz 3 dB; gain x 2 - 13 - MHz Vi(p-p) input amplitude of sync signal for correct operation of clamp pulse generator (peak-to-peak value) 0.2 - 2.5 V |Z23-22| output impedance (pin 23) - 20 30 Vo(p-p) maximum undistorted output amplitude (pin 23) (peak-to-peak value) 2.5 - - V VO DC output level on top of sync pulse 1.5 1.9 2.4 V V I2C-bus inputs for SDA, SCL VIH HIGH level input voltage 3 - VP VIL LOW level input voltage -0.3 - 1.5 V IIH HIGH level input current - - 10 A IIL LOW level input current - - 10 A - - 0.4 V I2C-bus output for SDA (open collector) VOL LOW level output voltage IOL = 3 mA Address selection inputs for S0, S1, S2 VIH HIGH level input voltage 3 - VP V VIL LOW level input voltage -0.3 - 0.4 V IIH HIGH level input current - 0 10 A IIL LOW level input current -50 -10 0 A Fast switching input VIH HIGH level input voltage 1 - 3 V VIL LOW level input voltage -0.3 - 0.4 V IIH HIGH level input current - 0 500 A IIL LOW level input current -100 - - A tsw switching time see Fig.5 - 10 - ns td switching delay see Fig.5 - 20 - ns 1995 Mar 07 9 Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch TDA8443A LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VP supply voltage (pin 18) - 14 V VI(SDA) input voltage (pin 13) -0.3 14 V VI(SCL) input voltage (pin 14) -0.3 14 V Vn input voltage any other pin -0.3 VP + 0.3 V IO(max) maximum output current - 20 mA Tamb operating ambient temperature 0 +70 C Tstg IC storage temperature range -55 +125 C Tj maximum junction temperature - +125 C CHARACTERISTICS VP = 12 V; Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VP supply voltage (pin 18) 10.8 12.0 13.2 V IP supply current - 65 90 mA - 0 10 % between Y output and the (R-Y) and (B-Y) channel outputs - 0 10 % between any other two channels - 0 5 % RGB/YUV channels Gabs absolute gain difference (programmed value) Grel relative gain difference II input current - 0.5 1.0 A |Z19-22| output impedance (pin 19) - 7 30 |Z20-22| output impedance (pin 20) - 7 30 |Z21-22| output impedance (pin 21) - 7 30 B bandwidth -3 dB; mode 0 or 2 - 25 - MHz +3 dB; mode 0 or 2 - 12 - MHz 3 dB; mode 1 - 10 - MHz tdiff mutual time difference at output all inputs of one source connected together - - 25 ns Vo(p-p) maximum output amplitude of YUV signals (peak-to-peak value) gain x 1 2.1 - - V gain x 2 4.2 - - V crosstalk note 1; fi = 5 MHz; between inputs of same source - - -30 dB note 1; between same source - - -40 dB fi = 10 MHz 50 - - dB ct off 1995 Mar 07 isolation (OFF state) 8 Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch Table 5 D2 TDA8443A Priority/fast switching bit D2 FAST SWITCHING (PIN 3) X(1) 0 1 Table 6 MODE 0 to 2, depending on D7, D6 0.4 V 2 Note Output state control bits D1 D0 PIN 9 FUNCTION 0 X(1) X(1) OFF 1 0 L OFF 1 0 H ON 1 1 X(1) ON Note 1. X = don't care. 1. X = don't care. Power-on reset If the circuit is switched on in the I2C-bus mode, all bits of D0 to D7 are set to zero. Table 7 Non-I2C-bus mode (S2 = S1 = S0 = L) CONTROL GAIN SETTINGS PIN 1 MODE SWITCHED BY FS (PIN 3) A1 A4, A3, A2 B1, B3 B2 1 1 1 2 1 1 1 1 -1 0.45 1 1 -1 0.45 2 or 0 2 1 1 1 H 2 or 0 2 2 1 1 H L 2 or 1 2 1 -1 0.45 H H 2 or 0 2 1 -1 0.45 PIN 13 PIN 14 L L L 2 or 0 1 L L H 2 or 0 1 L H L 2 or 1 L H H 2 or 0 H L L H L H H Table 8 Fast switching input (pin 3) FS 0.4 V Table 9 MODE SELECTED ON mode 2 7 FUNCTION L OFF; no output signal; high impedance OFF-state H function is determined in Table 7 1 to 3 V mode 0 or mode 1 as set by control 1995 Mar 07 ON input (pin 9) Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch Table 2 TDA8443A Address selection ADDRESS SELECT PINS(1)(2) ADDRESS SELECT BITS S2 (PIN 17) S1 (PIN 16) S0 (PIN 15) MA2 MA1 MA0 L L L (3) (3) (3) L L H 0 0 1 L H L 0 1 0 L H H 0 1 1 H L L 1 0 0 H L H 1 0 1 H H L 1 1 0 H H H 1 1 1 Notes 1. L = LOW level input voltage. 2. H = HIGH level input voltage. 3. = non-I2C-bus operation. Table 3 Mode control bits D7 and D6 MODE D7 D6 0 0 0 Channel 2 selected, no matrix 1 0 1 Channel 2 selected, matrix active 2 1 0 Channel 1 selected - 1 1 not allowed Table 4 FUNCTION Gain setting (see also Table 9) D5 D4 D3 A1 A2, A3, A4 B1, B3 B2 0 0 0 1 1 -1 0.45 0 0 1 1 1 1 1 0 1 0 0 1 1 - - 1 -1 0.45 not allowed 1 1 0 0 2 2 -1 0.45 1 0 1 2 1 1 1 1 1 0 2 2 1 1 1 1 1 2 1 -1 0.45 Matrix equations The relationship between output and input signals of the matrix is as follows: Y = 0.3R + 0.59G + 0.11B R-Y = 0.7R - 0.59G - 0.11B B-Y = -0.3R - 0.59G + 0.89B 1995 Mar 07 6 Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch TDA8443A FUNCTIONAL DESCRIPTION I2C-bus mode The circuit contains two sets of inputs (see Fig.1). Both channels can receive RGB or YUV signals. Each set of inputs has its own synchronization input, which internally generates a pulse to clamp the inputs. The internal clamping pulse can also be controlled by a signal (e.g. a sandcastle pulse) applied to pin 24. The pulse will occur during the time that the signal at pin 24 is between 5.5 and 6.5 V. If both a sync signal and a pin 24 signal are used the signal should be applied to pin 24 via a 1 k resistor. The protocol for the devices in I2C-bus mode is shown in Fig.3. Table 1 BIT RGB signals of Channel 2 can be matrixed to YUV signals. The outputs can be set in a high impedance OFF state, which allows the use of seven devices in parallel (I2C-bus mode). The circuit can be controlled by an I2C-bus compatible microcontroller or directly by DC voltages. The fast switching input can be operated via pin 16 of the peritelevision connector. handbook, full pagewidth STA 1 1 0 1 MA2 MA1 MA0 0 Protocol bit description ACK DESCRIPTION STA start condition MA2 to MA0 address selection bits; see Table 2 ACK acknowledge bit D7 channel selection bit; see Table 3 D6 matrix selection bit; see Table 3 D5 to D3 gain control bits; see Table 4 D2 fast switching priority bit; see Table 5 D1 and D0 output state control bits; see Table 6 STO stop condition D7 D6 D5 D4 D3 D2 D1 D0 ACK STO MSA003 See Table 1. Fig.3 I2C-bus protocol. 1995 Mar 07 5 Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch TDA8443A PINNING SYMBOL PIN DESCRIPTION SEL 1 select input (non-I2C-bus mode only) SYNC2 2 synchronization input for Channel 2 FS 3 fast switching input R/(R-Y)IN 4 R or (R-Y) signal input G/Y IN 5 G or Y signal input B/(B-Y)IN 6 B or (B-Y) signal input VINT 7 internal voltage supply SYNC1 8 synchronization input for Channel 1 ON 9 ON input R/-(R-Y)IN 10 R or -(R-Y) signal input G/Y IN 11 G or Y signal input B/-(B-Y)IN 12 B or -(B-Y) signal input SDA 13 serial data input/output; I2C-bus SCL 14 serial clock input; I2C-bus S0 15 address selection input 0 S1 16 address selection input 1 S2 17 address selection input 2 VP 18 supply voltage B/-(B-Y)OUT 19 B or -(B-Y) signal output G/Y OUT 20 G or Y signal output R/-(R-Y)OUT 21 R or -(R-Y) signal output GND 22 ground SYNC 23 synchronization output CLAMP 24 clamping pulse generator input/output 1995 Mar 07 handbook, halfpage SEL 1 24 CLAMP SYNC2 2 23 SYNC FS 3 22 GND R/ (R Y) IN 4 21 R/ (R Y) OUT G/Y IN 5 20 G/Y OUT B/ (B Y) IN 6 V INT 7 18 V P SYNC1 8 17 S2 ON 9 16 S1 R/ (R Y) IN 10 15 S0 19 B/ (B Y) OUT TDA8443A G/Y IN 11 14 SCL B/ (B Y) IN 12 13 SDA MLD004 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch TDA8443A BLOCK DIAGRAM outputs handbook, full pagewidth SDA SCL S0 13 14 15 S1 S2 16 VP 17 18 I 2C-BUS INTERFACE/ DECODER TDA8443A B/ (B Y) input G/Y input 19 R/ (R Y) SYNC input GND output 20 A4 21 A3 A2 22 clamp pulse generator 23 24 A1 FAST SWITCHING B3 B2 B1 MATRIX RGB/YUV CLAMP PULSE GENERATOR 9 8 CLAMP CLAMP CLAMP 12 11 10 ON B/ (B Y) input input SYNC1 G/Y input R/ (R Y) input CLAMP 7 CLAMP 6 CLAMP 5 internal B/ (B Y) voltage input G/Y input 4 R/ (R Y) input channel 1 SYNC2 channel 2 Fig.1 Block diagram. 1995 Mar 07 2 3 3 fast switching 1 SEL MLD003 Philips Semiconductors Product specification I2C-bus controlled YUV/RGB switch TDA8443A FEATURES * Two RGB/YUV selectable clamped inputs with associated synchronization * RGB/YUV matrix * 3-state switching with an OFF-state * Selectable gain * I2C-bus or non-I2C-bus mode * Address selection for 7 devices * Fast switching. GENERAL DESCRIPTION The TDA8443A is a general purpose two-channel switch for YUV or RGB signals. One channel provides matrixing from RGB to YUV, which can be bypassed. The IC is controlled via I2C-bus by seven different addresses or can be used in a non-I2C-bus mode. In the non-I2C-bus mode, control of the circuit is achieved by DC voltages. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VP supply voltage (pin 18) 10.8 12.0 13.2 V IP supply current - 65 90 mA RGB/YUV channels Z19-22 output impedance (pin 19) - 7 30 Z20-22 output impedance (pin 20) - 7 30 Z21-22 output impedance (pin 21) - 7 30 B bandwidth - 25 - MHz VO(p-p) Tamb -3 dB; mode 0 or 2 maximum output amplitude of YUV signals (peak-to-peak value) +3 dB; mode 0 or 2 - 12 - MHz 3 dB; mode 1 - 10 - MHz gain x 1 2.1 - - V gain x 2 4.2 - - V 0 - +70 C operating ambient temperature ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8443A DIP24 1995 Mar 07 DESCRIPTION plastic dual in-line package; 24 leads (600 mil) 2 VERSION SOT101-1