November 2010
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SV00 • Rev. 1.0.3
NC7SV00 — TinyLogic
®
ULP-A 2-Input NAND Gate
NC7SV00
TinyLogic® ULP-A 2-Input NAND Gate
Features
0.9V to 3.6V VCC Supply Operation
3.6V Over-Voltage Tolerant I/Os at VCC from
0.9V to 3.6V
Extremely High Speed tPD
- 1.0ns: Typical for 2.7V to 3.6V VCC
- 1.2ns: Typical for 2.3V to 2.7V VCC
- 2.0ns: Typical for 1.65V to 1.95V VCC
- 3.2ns: Typical for 1.4V to 1.6V VCC
- 6.0ns: Typical for 1.1V to 1.3V VCC
- 13.0ns: Typical for 0.9V VCC
Power-Off High-Impedance Inputs and Outputs
High Static Drive (IOH/IOL)
- ±24mA at 3.00V VCC
- ±18mA at 2.30V VCC
- ±6mA at 1.65V VCC
- ±4mA at 1.4V VCC
- ±2mA at 1.1V VCC
- ±0.1mA at 0.9V VCC
Uses Proprietary Quiet Series™ Noise/EMI
Reduction Circuitry
Ultra-Small MicroPak™ Packages
Ultra-Low Dynamic Power
Description
The NC7SV00 is a single two-input NAND gate from
Fairchild's Ultra-Low Power (ULP-A) Series of
TinyLogic®. ULP-A is ideal for applications that require
extreme high speed, high drive, and low power. This
product is designed for a wide low-voltage operating
range (0.9V to 3.6V VCC) and applications that require
more drive and speed than the TinyLogic® ULP series,
but still offer best-in-class, low-power operation.
The NC7SV00 is uniquely designed for optimized power
and speed and is fabricated with an advanced CMOS
technology to achieve high-speed operation while
maintaining low CMOS power dissipation.
Ordering Information
Part Number Top Mark Package Packing Method
NC7SV00P5X V00 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3000 Units on Tape & Reel
NC7SV00L6X F5 6-Lead MicroPak™, 1.00mm Wide 5000 Units on Tape & Reel
NC7SV00FHX F5 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch 5000 Units on Tape & Reel
TinyLogic® is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak™ and Quiet Series™ are trademarks of Fairchild Semiconductor Corporation.
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SV00 • Rev. 1.0.3 2
NC7SV00 — TinyLogic
®
ULP-A 2-Input NAND Gate
Battery Life
Figure 1. Battery Life vs. VCC Supply Voltage
Notes:
1. TinyLogic® ULP and ULP-A with up to 50% less power consumption can extend battery life significantly.
Battery Life = (Vbattery•Ibattery•.9)/(Pdevice)/24hrs/day
where, Pdevice = (ICC • VCC) + (CPD + CL) • VCC2 • f.
2. Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and derated 90% and device frequency at
10MHz, with CL=15pF load.
Connection Diagram
IEEE/IEC
A
B
&Y
Figure 2. Logic Symbol
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SV00 • Rev. 1.0.3 3
NC7SV00 — TinyLogic
®
ULP-A 2-Input NAND Gate
Pin Configurations
AV
CC
15
B
2
GND Y
3 4
1
A
2
B
3
6
5
4
GND
V
CC
NC
Y
Figure 3. SC70 (Top View) Figure 4. MicroPak™ (Top Through View)
Pin Definitions
Pin # SC70 Pin # MicroPak™ Name Description
1 1 A Input
2 2 B Input
3 3 GND Ground
4 4 Y Output
5 NC No Connect
5 6 VCC Supply Voltage
Function Table
Inputs Output
A B Y
L L H
L H H
H L H
H H L
H=HIGH Logic Level
L=LOW Logic Level
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SV00 • Rev. 1.0.3 4
NC7SV00 — TinyLogic
®
ULP-A 2-Input NAND Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage -0.5 4.6 V
VIN DC Input Voltage -0.5 4.6 V
VOUT DC Output Voltage HIGH or LOW State(3) -0.5 VCC + 0.5 V
VCC=0V -0.5 4.6
IIK DC Input Diode Current VIN < 0V -50 mA
IOK DC Output Diode Current VOUT < 0V -50 mA
VOUT > VCC +50
IOH/IOL DC Output Source/Sink Current ±50 mA
ICC or IGND DC VCC or Ground Current per Supply Pin ±50 mA
TSTG Storage Temperature Range -65 +150 °C
TJ Junction Temperature Under Bias +150 °C
TL Junction Lead Temperature, Soldering 10 Seconds +260 °C
PD Power Dissipation at +85°C SC70-5 150
mW MicroPak™-6 130
MicroPak2™-6 120
ESD Human Body Model, JEDEC:JESD22-A114 4000 V
Charge Device Model, JEDEC:JESD22-C101 2000
Note:
3. IO absolute maximum rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Conditions Min. Max. Unit
VCC Supply Voltage 0.9 3.6 V
VIN Input Voltage 0 3.6 V
VOUT Output Voltage VCC=0V 0 3.6
V
HIGH or LOW State 0 VCC
IOH/IOL Output Current in IOH/IOL
VCC=3.0V to 3.6V ±24.0
mA
VCC=2.3V to 3.6V ±18.0
VCC=1.65V to 1.95V ±6.0
VCC=1.4V to 1.6V ±4.0
VCC=1.1V to 1.3V ±2.0
VCC=0.9V ±0.1
TA Operating Temperature, Free Air -40 +85 °C
Δt/ΔV Minimum Input Edge Rate VIN=0.8V to 2.0, VCC=3.0V 10 ns/V
θJA Thermal Resistance SC70-5 425
°C/W MicroPak™-6 500
MicroPak2™-6 560
Note:
4. Unused inputs must be held HIGH or LOW. They may not float.
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SV00 • Rev. 1.0.3 5
NC7SV00 — TinyLogic
®
ULP-A 2-Input NAND Gate
DC Electrical Characteristics
Symbol Parameter VCC Conditions TA=25°C TA=-40 to 85°C Units
Min. Max. Min. Max.
VIH HIGH Level I nput
Voltage
0.90
.65 x VCC .65 x VCC
V
1.10 ≤ VCC ≤ 1.30 .65 x VCC .65 x VCC
1.40 ≤ VCC ≤ 1.60 .65 x VCC .65 x VCC
1.65 ≤ VCC ≤ 1.95 .65 x VCC .65 x VCC
2.30 ≤ VCC ≤ 2.70 1.6 1.6
2.70 ≤ VCC ≤ 3.60 2.0 2.0
VIL LOW Level I nput
Voltage
0.90
.35 x VCC .35 x VCC
V
1.10 ≤ VCC ≤ 1.30 .35 x VCC .35 x VCC
1.40 ≤ VCC ≤ 1.60 .35 x VCC .35 x VCC
1.65 ≤ VCC ≤ 1.95 .35 x VCC .35 x VCC
2.30 ≤ VCC ≤ 2.70 0.7 0.7
2.70 ≤ VCC ≤ 3.60 0.8 0.8
VOH HIGH Level Output
Voltage
0.90
IOH=-100µA
VCC-0.1 VCC-0.1
V
1.10 ≤ VCC ≤ 1.30 VCC-0.1 VCC-0.1
1.40 ≤ VCC ≤ 1.60 VCC-0.2 VCC-0.2
1.65 ≤ VCC ≤ 1.95 VCC-0.2 VCC-0.2
2.30 ≤ VCC ≤ 2.70 VCC-0.2 VCC-0.2
2.70 ≤ VCC ≤ 3.60 VCC-0.2 VCC-0.2
1.10 ≤ VCC ≤ 1.30 IOH=-2mA .75 x VCC .75 x VCC
1.40 ≤ VCC ≤ 1.60 IOH=-4mA .75 x VCC .75 x VCC
1.65 ≤ VCC ≤ 1.95 IOH=-6mA 1.25 1.25
2.30 ≤ VCC ≤ 2.70 2.00 2.00
2.30 ≤ VCC ≤ 2.70 IOH=-12mA 1.8 1.8
2.70≤ VCC ≤ 3.60 2.2 2.2
2.30 ≤ VCC ≤ 2.70 IOH=-18mA 1.7 1.7
2.70 ≤ VCC ≤ 3.60 2.4 2.4
2.70 ≤ VCC ≤ 3.60 IOH=-24mA 2.2 2.2
Continued on foll owing page…
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SV00 • Rev. 1.0.3 6
NC7SV00 — TinyLogic
®
ULP-A 2-Input NAND Gate
DC Electrical Characteristics (Continued)
Symbol Parameter VCC Conditions TA=25°C TA=-40 to 85°C Units
Min. Max. Min. Max.
VOL LOW Level
Output Vol t age
0.90
IOL=100µA
0.1 0.1
V
1.10 ≤ VCC ≤ 1.30 0.1 0.1
1.40 ≤ VCC ≤ 1.60 0.2 0.2
1.65 ≤ VCC ≤ 1.95 0.2 0.2
2.30 ≤ VCC ≤ 2.70 0.2 0.2
2.70 ≤ VCC ≤ 3.60 0.2 0.2
1.10 ≤ VCC ≤ 1.30 IOL=2mA 0.25 x VCC 0.25 x VCC
1.40 ≤ VCC ≤ 1.60 IOL=4mA 0.25 x VCC 0.25 x VCC
1.65 ≤ VCC ≤ 1.95 IOL=6mA 0.3 0.3
2.30 ≤ VCC ≤ 2.70 IOL=12mA 0.4 0.4
2.70 ≤ VCC ≤ 3.60 0.4 0.4
2.30≤ VCC ≤ 2.70 IOL=18mA 0.6 0.6
2.70 ≤ VCC ≤ 3.60 0.4 0.4
2.70 ≤ VCC ≤ 3.60 IOL=24mA 0.55 0.55
IIN Input Leakage
Current 0.90 to 3.60 0 ≤ VIN ≤ 3.60 ±0.1 ±0.5 µA
IOFF Power Off
Leakage
Current 0 0 ≤ (VIN, vO) ≤ 3.60 0.5 0.5 µA
ICC Quiescent
Supply Current 0.90 to 3.60 VIN=VCC, or GND 0.9 0.9 µA
VCC ≤ VIN ≤ 3.6V ±0.9
AC Electrical Characteristics
Symbol Parameter VCC Conditions
TA=25°C TA=-40 to 85°C Units Figure
Min. Typ. Max. Min. Max.
tPHL, tPLH Propagation
Delay
0.90 CL=15pF, RL=1MΩ 13
ns Figure 5
Figure 6
1.10 ≤ VCC ≤ 1. 30 CL=15pF, RL=2kΩ 3.0 6.0 9.9 1.0 14.6
1.40 ≤ VCC ≤ 1. 60 1.0 3.2 6.0 1.0 7.2
1.65 ≤ VCC ≤ 1. 95
CL=30pF, RL=500Ω
1.0 2.0 4.5 1.0 5.3
2.30 ≤ VCC ≤ 2. 70 0.8 1.2 2.6 0.7 3.7
2.70 ≤ VCC ≤ 3. 60 0.7 1.0 2.3 0.6 3.0
CIN Input
Capacitance 0 2 pF
CPD Power
Dissipation
Capacitance 0.90 to 3.60 VIN=0V or VCC,
f=10MHz 8 pF
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SV00 • Rev. 1.0.3 7
NC7SV00 — TinyLogic
®
ULP-A 2-Input NAND Gate
AC Loadings and Waveforms
Figure 5. AC Test Circuit
Figure 6. AC Waveforms
Symbol VCC
3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V 1.5V ± 0.1V 1.2V ± 0.1V 0.9V
Vmi 1.5V VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
Vmo 1.5V VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SV00 • Rev. 1.0.3 8
NC7SV00 — TinyLogic
®
ULP-A 2-Input NAND Gate
Physical Dimensions
Figure 7. 5-Lead, SC70, EIAJ SC-88a, 1.25mm Wide
Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner
without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specificat i on
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf.
Package Designator Tape Section Cavity Number Cavity Status Cover Type Status
P5X Leader (Start End) 125 (Typical) Empty Sealed
Carrier 3000 Filled Sealed
Trailer (Hub End) 75 (Typical) Empty Sealed
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SV00 • Rev. 1.0.3 9
NC7SV00 — TinyLogic
®
ULP-A 2-Input NAND Gate
Physical Dimensions
2. DIMENSIONS ARE IN MILLIMETERS
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
4. FILENAME AND REVISION: MAC06AREV4
Notes:
3. DRAWING CONFORMS TO ASME Y14.5M-1994
TOP VIEW
RECOMMENED
LAND PATTERN
BOTTOM VIEW
1.45
1.00
A
B0.05 C
0.05 C
2X
2X
0.55MAX
0.05 C
(0.49)
(1)
(0.75)
(0.52)
(0.30)
6X
1X
6X
PIN 1
DETAIL A
0.075 X 45
CHAMFER
0.25
0.15
0.35
0.25
0.40
0.30
0.5
(0.05)
1.0
5X
DETAIL A
PIN 1 TERMINAL
0.40
0.30
0.45
0.35
0.10
0.00
0.10 CBA
0.05 C
C0.05 C
0.05
0.00
5X
5X
6X (0.13)
4X
6X
PIN 1 IDENTIFIER
(0.254)
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
5
OTHER LINE IN THE M ARK CODE LAYOUT.
Figure 8. 6-Lead, MicroPak™, 1.0mm Wide
Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner
without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specificat i on
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator Tape Section Cavity Number Cavity Status Cover Type Status
L6X Leader (Start End) 125 (Typical) Empty Sealed
Carrier 5000 Filled Sealed
Trailer (Hub End) 75 (Typical) Empty Sealed
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SV00 • Rev. 1.0.3 10
NC7SV00 — TinyLogic
®
ULP-A 2-Input NAND Gate
Physical Dimensions
1.00
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
0.05 CA
B
0.55MAX
0.05 C
C
0.35
0.09
0.19
123
0.35
0.25
5X
6X
DETAIL A
0.60
(0.08)
4X
(0.05) 6X
0.40
0.30
0.075X45°
CHAMFER
5X 0.40
0.35
1X 0.45
6X 0.19
TOP VIEW
BOTTOM VIEW
0.66
0.10 CBA
.05 C
0.89
PIN 1
0.05 C
2X
2X 1.00
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
E. DRAWING FILENAME AND REVISION: MGF06AREV3
0.52
0.73
0.57
0.20 6X
1X
5X
RECOMMENDED LAND PATTERN
FOR SPA CE CONST RAINED PCB
DETAIL A
PIN 1 LEAD SCALE: 2X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL A PPL IC ATIO N
DESIGN.
0.90
MIN 250uM
654
0.35
(0.08) 4X
SIDE VIEW
Figure 9. 6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch
Pack age drawings are provi ded as a servic e to customers considering Fairc h i l d components. Drawi ngs may change in any manner
without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emic onductor representative to v er ify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specificat i on
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator Tape Section Cavity Number Cavity Status Cover Type Status
FHX Leader (Start End) 125 (Typical) Empty Sealed
Carrier 5000 Filled Sealed
Trailer (Hub End) 75 (Typical) Empty Sealed
© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7SV00 • Rev. 1.0.3 11
NC7SV00 — TinyLogic
®
ULP-A 2-Input NAND Gate
