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February 11, 2000 (Version 1.8) 6-101
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000E Electrical Specifications
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions.
All specifications subject to change without notice.
XC4000E DC Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Symbol Description Value Units
VCC Supply voltage relative to GND -0.5 to +7.0 V
VIN Input voltage relative to GND (Note 1) -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output (Note 1) -0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) -65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 °C
TJJunction Temperature Ceramic packages +150 °C
Plastic packages +125 °C
Note 1: Maximum DC excursion above Vcc or below Ground must be limited to either 0.5 V or 10 mA, whichever is easier to
achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to VCC + 2.0 V, provided this over or
undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods
of time may affect device reliability.
Symbol Description Min Max Units
VCC Supply voltage relative to GND, TJ = -0 °C to +85°C Commercial 4.75 5.25 V
Supply voltage relative to GND, TJ = -40°C to +100°C Industrial 4.5 5.5 V
Supply voltage relative to GND, TC = -55°C to +125°C Military 4.5 5.5 V
VIH High-Level Input Voltage TTL inputs 2.0 VCC V
CMOS inputs 70% 100% VCC
VIL Low-Level Input Voltage TTL inputs 0 0.8 V
CMOS inputs 0 20% VCC
TIN Input signal transition time 250 ns
Notes: At junction temperatures above those listed above, all delay parameters increase by 0.35% per °C.
Input and output measurement thresholds for TTL are 1.5 V and for CMOS are 2.5 V.
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6-102 February 11, 2000 (Version 1.8)
DC Characteristics Over Operating Conditions
Symbol Description Min Max Units
VOH High-level output voltage @ IOH = -4.0mA, VCC min TTL outputs 2.4 V
High-level output voltage @ IOH = -1.0mA, VCC min CMOS outputs VCC-0.5 V
VOL Low-level output voltage @ IOL = 12.0mA, VCC min
(Note 1) TTL outputs 0.4 V
CMOS outputs 0.4 V
ICCO Quiescent FPGA supply current (Note 2) Commercial 3.0 mA
Industrial 6.0 mA
Military 6.0 mA
ILInput or output leakage current -10 +10 µA
CIN Input capacitance (sample tested) PQFP and MQFP
packages 10 pF
Other packages 16 pF
IRIN* Pad pull-up (when selected) @ VIN = 0V (sample tested) -0.02 -0.25 mA
IRLL* Horizontal Longline pull-up (when selected) @ logic Low 0.2 2.5 mA
Notes: With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins.
With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
configured with a Development system Tie option.
*Characterized Only.
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February 11, 2000 (Version 1.8) 6-103
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000E Switching Characteristics
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from the
static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature).
Global Buffer Switching Characteristic Guidelines
Speed Grade -4 -3 -2 -1 Units
Description Symbol Device Max Max Max Max
From pad through
Primary buffer,
to any clock K
TPG XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
7.0
7.0
7.5
8.0
11.0
11.5
12.0
12.5
4.7
4.7
5.3
6.1
6.3
6.8
7.0
7.2
4.0
4.3
5.2
5.2
5.4
5.8
6.4
6.9
3.5
3.8
4.6
4.6
4.8
5.2
6.0
–
ns
ns
ns
ns
ns
ns
ns
ns
From pad through
Secondary buffer,
to any clock K
TSG XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
7.5
7.5
8.0
8.5
11.5
12.0
12.5
13.0
5.2
5.2
5.8
6.6
6.8
7.3
7.5
7.7
4.4
4.7
5.6
5.6
5.8
6.2
6.7
7.2
4.0
4.3
5.1
5.1
5.3
5.7
6.5
–
ns
ns
ns
ns
ns
ns
ns
ns
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6-104 February 11, 2000 (Version 1.8)
Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions.
Speed Grade -4 -3 -2 -1 Units
Description Symbol Device Max Max Max Max
TBUF driving a Horizontal Longline (LL):
I going High or Low to LL going High or
Low, while T is Low.
Buffer is constantly active.
(Note1)
TIO1 XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
4.2
5.0
5.9
6.3
6.4
7.2
8.2
9.1
3.4
4.0
4.7
5.0
5.1
5.7
7.3
7.3
2.9
3.4
4.0
4.3
4.4
4.9
5.6
–
ns
ns
ns
ns
ns
ns
ns
ns
I going Low to LL going from resistive
pull-up High to active Low.
TBUF configured as open-drain.
(Note1)
TIO2 XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.0
6.0
7.8
8.1
10.5
11.0
12.0
12.0
4.2
5.3
6.4
6.8
6.9
7.7
8.7
9.6
3.6
4.5
5.4
5.8
5.9
6.5
8.7
9.6
3.1
3.8
4.6
4.9
5.0
5.5
7.4
–
ns
ns
ns
ns
ns
ns
ns
ns
T going Low to LL going from resistive
pull-up or floating High to active Low.
TBUFconfiguredasopen-drain oractive
buffer with I = Low.
(Note1)
TON XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.5
7.0
7.5
8.0
8.5
8.7
11.0
11.0
4.6
6.0
6.7
7.1
7.3
7.5
8.4
8.4
3.9
5.7
5.7
6.0
6.2
7.0
7.1
7.1
3.5
4.7
4.9
5.2
5.4
6.2
6.3
–
ns
ns
ns
ns
ns
ns
ns
ns
T going High to TBUF going inactive,
not driving LL TOFF All devices 1.8 1.5 1.3 1.1 ns
T going High to LL going from Low to
High, pulled up by a single resistor.
(Note 1)
TPUS XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
20.0
23.0
25.0
27.0
29.0
32.0
35.0
42.0
14.0
16.0
18.0
20.0
22.0
26.0
32.5
39.1
14.0
16.0
18.0
20.0
22.0
26.0
32.5
39.1
12.0
14.0
16.0
16.0
18.0
21.0
26.0
–
ns
ns
ns
ns
ns
ns
ns
ns
T going High to LL going from Low to
High, pulled up by two resistors.
(Note1)
TPUF XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
9.0
10.0
11.5
12.5
13.5
15.0
16.0
18.0
7.0
8.0
9.0
10.0
11.0
13.0
14.8
16.5
6.0
6.8
7.7
8.5
9.4
11.7
14.8
16.5
5.4
5.8
6.5
7.5
8.0
9.4
10.5
–
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.
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February 11, 2000 (Version 1.8) 6-105
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions.
Speed Grade -4 -3 -2 -1 Units
Description Symbol Device Max Max Max Max
Full length, both pull-ups,
inputs from IOB I-pins TWAF XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
9.2
9.5
12.0
12.5
15.0
16.0
17.0
18.0
5.0
6.0
7.0
8.0
9.0
11.0
13.9
16.9
5.0
6.0
7.0
8.0
9.0
11.0
13.9
16.9
4.3
5.1
6.0
6.5
7.5
8.6
10.1
–
ns
ns
ns
ns
ns
ns
ns
ns
Full length, both pull-ups,
inputs from internal logic TWAFL XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
12.0
12.5
14.0
16.0
18.0
19.0
20.0
21.0
7.0
8.0
9.0
10.0
11.0
13.0
15.5
18.9
7.0
8.0
9.0
10.0
11.0
13.0
15.5
18.9
5.5
6.4
7.0
7.5
8.5
10.0
11.8
–
ns
ns
ns
ns
ns
ns
ns
ns
Half length, one pull-up,
inputs from IOB I-pins TWAO XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
10.5
10.5
13.5
14.0
16.0
17.0
18.0
19.0
6.0
7.0
8.0
9.0
10.0
12.0
15.0
17.6
6.0
7.0
8.0
9.0
10.0
12.0
15.0
17.6
5.1
6.0
6.5
7.0
7.5
10.0
11.8
–
ns
ns
ns
ns
ns
ns
ns
ns
Half length, one pull-up,
inputs from internal logic TWAOL XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
12.0
12.5
14.0
16.0
18.0
19.0
20.0
21.0
8.0
9.0
10.0
11.0
12.0
14.0
16.8
19.6
8.0
9.0
10.0
11.0
12.0
14.0
16.8
19.6
6.0
7.0
7.6
8.4
9.2
10.8
12.6
–
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: These delays are specified from the decoder input to the decoder output.
Note 2: Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but
increases delays. Use the static timing analyzer to determine delays if fewer pullups are used.
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6-106 February 11, 2000 (Version 1.8)
XC4000E CLB Characteristics Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted
CLB Switching Characteristics Guidelines
Speed Grade -4 -3 -2 -1 Units
Description Symbol Min Max Min Max Min Max Min Max
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H to X/Y outputs
C inputs via SR through H to X/Y outputs
C inputs via H to X/Y outputs
C inputs via DIN through H to X/Y outputs
TILO
TIHO
THH0O
THH1O
THH2O
2.7
4.7
4.1
3.7
4.5
2.0
4.3
3.3
3.6
3.6
1.6
2.7
2.4
2.2
2.6
1.3
2.2
1.9
1.6
1.9
ns
ns
ns
ns
ns
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to COUT
CIN through function generators to
X/Y outputs
CIN to COUT, bypass function generators
TOPCY
TASCY
TINCY
TSUM
TBYP
3.2
5.5
1.7
3.8
1.0
2.6
4.4
1.7
3.3
0.7
2.1
3.7
1.4
2.6
0.6
1.7
2.5
1.2
1.8
0.5
ns
ns
ns
ns
ns
Sequential Delays
Clock K to outputs Q TCKO 3.7 2.8 2.8 1.9 ns
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
CIN input via F/G and H
TICK
TIHCK
THH0CK
THH1CK
THH2CK
TDICK
TECCK
TRCK
TCCK
TCHCK
4.0
6.1
4.5
5.0
4.8
3.0
4.0
4.2
2.5
4.2
3.0
4.6
3.6
4.1
3.8
2.4
3.0
4.0
2.1
3.5
2.4
3.9
3.5
3.3
3.7
2.0
2.6
4.0
1.8
2.8
2.4
2.1
2.5
1.0
2.0
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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February 11, 2000 (Version 1.8) 6-107
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000E CLB Characteristics Guidelines (Continued)
Speed Grade -4 -3 -2 -1 Units
Description Symbol Min Max Min Max Min Max Min Max
Hold Time after Clock K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via SR, going Low (inactive)
TCKI
TCKIH
TCKHH0
TCKHH1
TCKHH2
TCKDI
TCKEC
TCKR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
Clock
Clock High time
Clock Low time TCH
TCL
4.5
4.5 4.0
4.0 4.0
4.0 3.0
3.0 ns
ns
Set/Reset Direct
Width (High)
Delay from C inputs via S/R,
going High to Q
TRPW
TRIO
5.5 6.5 4.0 4.0 4.0 4.0 3.0 3.0 ns
ns
Master Set/Reset (Note 1)
Width (High or Low)
Delay from Global Set/Reset net to Q
Global Set/Reset inactive to first
active clock K edge
TMRW
TMRQ
TMRK
13.0 23.0 11.5 18.7 11.5 17.4 10.0 15.0 ns
ns
Toggle Frequency(Note 2) FTOG 111 125 125 166 MHz
Note 1: Timing is based on the XC4005E. For other devices see the static timing analyzer.
Note 2: Export Control Max. flip-flop toggle rate.
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6-108 February 11, 2000 (Version 1.8)
CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested.
Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more
precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation net list. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature). Values apply to all XC4000E devices unless otherwise noted.
Single Port RAM Speed Grade -4 -3 -2 -1 Units
Size Symbol Min Max Min Max Min Max Min Max
Write Operation
Address write cycle time (clock K period) 16x2
32x1 TWCS
TWCTS
15.0
15.0 14.4
14.4 11.6
11.6 8.0
8.0 ns
ns
Clock K pulse width (active edge) 16x2
32x1 TWPS
TWPTS
7.5
7.5 1ms
1ms 7.2
7.2 1ms
1ms 5.8
5.8 1ms
1ms 4.0
4.0 ns
ns
Address setup time before clock K 16x2
32x1 TASS
TASTS
2.8
2.8 2.4
2.4 2.0
2.0 1.5
1.5 ns
ns
Address hold time after clock K 16x2
32x1 TAHS
TAHTS
0
00
00
00
0ns
ns
DIN setup time before clock K 16x2
32x1 TDSS
TDSTS
3.5
2.5 3.2
1.9 2.7
1.7 1.5
1.5 ns
ns
DIN hold time after clock K 16x2
32x1 TDHS
TDHTS
0
00
00
00
0ns
ns
WE setup time before clock K 16x2
32x1 TWSS
TWSTS
2.2
2.2 2.0
2.0 1.6
1.6 1.5
1.5 ns
ns
WE hold time after clock K 16x2
32x1 TWHS
TWHTS
0
00
00
00
0ns
ns
Data valid after clock K 16x2
32x1 TWOS
TWOTS
10.3
11.6 8.8
10.3 7.9
9.3 6.5
7.0 ns
ns
Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
Note 2: Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Dual-Port RAM Speed Grade -4 -3 -2 -1 Units
Size Symbol Min Max Min Max Min Max Min Max
Write Operation
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
TWCDS
TWPDS
TASDS
TAHDS
TDSDS
TDHDS
TWSDS
TWHDS
TWODS
15.0
7.5
2.8
0
2.2
0
2.2
0.3
1 ms
10.0
14.4
7.2
2.5
0
2.5
0
1.8
0
1 ms
7.8
11.6
5.8
2.1
0
1.6
0
1.6
0
1ms
7.0
8.0
4.0
1.5
0
1.5
0
1.5
06.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: Applicable Read timing specifications are identical to Level-Sensitive Read timing
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February 11, 2000 (Version 1.8) 6-109
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
CLB RAM Synchronous (Edge-Triggered) Write Timing Waveforms
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT OLD NEW
TDSS TDHS
TASS TAHS
TWSS
TWPS
TWHS
TWOS
TILO
TILO
WCLK (K)
WE
ADDRESS
DATA IN
TDSDS TDHDS
TASDS TAHDS
TWSDS
TWPDS
TWHDS
X6474
DATA OUT OLD NEW
TWODS
TILO
TILO
Single Port Dual Port
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6-110 February 11, 2000 (Version 1.8)
CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000E devices unless otherwise noted.
Speed Grade -4 -3 -2 -1 Units
Description Size Symbol Min Max Min Max Min Max Min Max
Write Operation
Address write cycle time 16x2
32x1 TWC
TWCT
8.0
8.0 8.0
8.0 8.0
8.0 8.0
8.0 ns
ns
Write Enable pulse width (High) 16x2
32x1 TWP
TWPT
4.0
4.0 4.0
4.0 4.0
4.0 4.0
4.0 ns
ns
Address setup time before WE 16x2
32x1 TAS
TAST
2.0
2.0 2.0
2.0 2.0
2.0 2.0
2.0 ns
ns
Address hold time after end of WE 16x2
32x1 TAH
TAHT
2.5
2.0 2.0
2.0 2.0
2.0 2.0
2.0 ns
ns
DIN setup time before end of WE 16x2
32x1 TDS
TDST
4.0
5.0 2.2
2.2 0.8
0.8 0.8
0.8 ns
ns
DIN hold time after end of WE 16x2
32x1 TDH
TDHT
2.0
2.0 2.0
2.0 2.0
2.0 2.0
2.0 ns
ns
Read Operation
Address read cycle time 16x2
32x1 TRC
TRCT
4.5
6.5 3.1
5.5 2.6
3.8 2.6
3.8 ns
ns
Data valid after address change
(no Write Enable) 16x2
32x1 TILO
TIHO
2.7
4.7 1.8
3.2 1.6
2.7 1.6
2.7 ns
ns
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K 16x2
32x1 TICK
TIHCK
4.0
6.1 3.0
4.6 2.4
3.9 2.4
3.9 ns
ns
Read During Write
Datavalid after WEgoes active(DIN
stable before WE) 16x2
32x1 TWO
TWOT
10.0
12.0 6.0
7.3 4.9
5.6 4.9
5.6 ns
ns
Data valid after DIN
(DIN changes during WE) 16x2
32x1 TDO
TDOT
9.0
11.0 6.6
7.6 5.8
6.2 5.8
6.2 ns
ns
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K 16x2
32x1 TWCK
TWCKT
8.0
9.6 6.0
6.8 5.1
5.8 5.1
5.8 ns
ns
Data setup time before clock K 16x2
32x1 TDCK
TDCKT
7.0
8.0 5.2
6.2 4.4
5.3 4.4
5.3 ns
ns
Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
R
February 11, 2000 (Version 1.8) 6-111
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
CLB Level-Sensitive RAM Timing Waveforms
WC
T
ILO
T
CKO
T
DO
T
DH
T
WO
T
CKO
T
WCK
T
DCK
T
ICK
TCH
T
WO
T
WP
T
VALID
VALID
(OLD)
VALID
(OLD)
VALID
(PREVIOUS)
VALID
(NEW)
VALID
(NEW)
VALID
ADDRESS
X,Y OUTPUTS
CLOCK
XQ, YQ OUTPUTS
WRITE ENABLE
X, Y OUTPUTS
X, Y OUTPUTS
XQ, YQ OUTPUTS
WRITE ENABLE
DATA IN
CLOCK
DATA IN
(stable during WE)
DATA IN
(changing during WE)
READ WITHOUT WRITE
READ, CLOCKING DATA INTO FLIP-FLOP
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
READ DURING WRITE
WRITE ENABLE
DATA IN
WRITE AS
TWP
T
DS
TDH
T
REQUIRED
AH
T
WP
T
OLD NEW
VALID VALID
X2640
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-112 February 11, 2000 (Version 1.8)
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted.
Speed Grade -4 -3 -2 -1 Units
Description Symbol Device
Global Clock to Output
(fast) using OFF TICKOF
(Max)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
12.5
14.0
14.5
15.0
16.0
16.5
17.0
17.0
10.2
10.7
10.7
10.8
10.9
11.0
11.0
12.6
8.7
9.1
9.1
9.2
9.3
9.4
10.2
10.8
5.8
6.2
6.4
6.6
6.8
7.2
7.4
–
ns
ns
ns
ns
ns
ns
ns
ns
Global Clock to Output
(slew-limited) using OFF TICKO
(Max)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
16.5
18.0
18.5
19.0
20.0
20.5
21.0
21.0
14.0
14.7
14.7
14.8
14.9
15.0
15.1
15.3
11.5
12.0
12.0
12.1
12.2
12.8
12.8
13.0
7.8
8.2
8.4
8.6
8.8
9.2
9.4
–
ns
ns
ns
ns
ns
ns
ns
ns
Input Setup Time, using IFF
(no delay) TPSUF
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
2.5
2.0
1.9
1.4
1.0
0.5
0
0
2.3
1.2
1.0
0.6
0.2
0
0
0
2.3
1.2
1.0
0.6
0.2
0
0
0
1.5
0.8
0.6
0.2
0
0
0
–
ns
ns
ns
ns
ns
ns
ns
ns
Input Hold Time, using IFF
(no delay) TPHF
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
4.0
4.6
5.0
6.0
6.0
7.0
7.5
8.0
4.0
4.5
4.7
5.1
5.5
6.5
6.7
7.0
4.0
4.5
4.7
5.1
5.5
5.5
5.7
5.9
1.5
2.0
2.0
2.5
2.5
3.0
3.5
–
ns
ns
ns
ns
ns
ns
ns
ns
Input Setup Time, using IFF
(with delay) TPSU
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
8.5
8.5
8.5
8.5
8.5
8.5
9.5
9.5
7.0
7.0
7.0
7.0
7.0
7.0
7.0
7.6
6.0
6.0
6.0
6.0
6.0
6.0
6.8
6.8
5.0
5.0
5.0
5.0
5.0
5.0
5.0
–
ns
ns
ns
ns
ns
ns
ns
ns
Input Hold Time, using IFF
(with delay) TPH
(Min)
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
ns
ns
ns
ns
ns
ns
ns
ns
OFF = Output Flip-Flop, IFF = Input Flip-Flop or Latch
OFF
Global Clock-to-Output Delay
.
.
.
.
.
X3202
T
PG
OFF
Global Clock-to-Output Delay
.
.
.
.
.
X3202
T
PG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
T
PG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
T
PG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
T
PG
IFF
D
X3201
Input
Set - Up
&
Hold
Time
T
PG
R
February 11, 2000 (Version 1.8) 6-113
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000E IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted.
Speed Grade -4 -3 -2 -1 Units
Description Symbol Device Min Max Min Max Min Max Min Max
Propagation Delays (TTL Inputs)
Pad to I1, I2
Pad to I1, I2 via transparent
latch, no delay
with delay
TPID
TPLI
TPDLI
All devices
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
3.0
4.8
10.4
10.8
10.8
10.8
11.0
11.4
13.8
13.8
2.5
3.6
9.3
9.6
10.2
10.6
10.8
11.2
12.4
13.7
2.0
3.6
6.9
7.4
8.1
8.2
8.3
9.8
11.5
12.4
1.4
2.8
6.4
6.5
6.9
7.0
7.3
8.4
9.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delays (CMOS Inputs)
Pad to I1, I2
Pad to I1, I2 via transparent
latch, no delay
with delay
TPIDC
TPLIC
TPDLIC
All devices
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.5
8.8
16.5
16.5
16.8
17.3
17.5
18.0
20.8
20.8
4.1
6.8
12.4
13.2
13.4
13.8
14.0
14.4
15.6
15.6
3.7
6.2
11.0
11.9
12.1
12.4
12.6
13.0
14.0
14.0
1.9
3.3
6.9
7.0
7.4
7.4
7.8
9.0
9.5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delays
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2
(latch enable, active Low)
TIKRI
TIKLI
All devices
All devices
5.6
6.2
2.8
4.0
2.8
3.9
2.7
3.2
ns
ns
Hold Times (Note 1)
Pad to Clock (IK), no delay
with delay
Clock Enable (EC) to Clock (IK),
no delay
with delay
TIKPI
TIKPID
TIKEC
TIKECD
All devices
All devices
All devices
All devices
0
0
1.5
0
0
0
1.5
0
0
0
0.9
0
0
0
0
0
ns
ns
ns
ns
Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the
clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-114 February 11, 2000 (Version 1.8)
XC4000E IOB Input Switching Characteristic Guidelines (Continued)
Speed Grade -4 -3 -2 -1 Units
Description Symbol Device Min Max Min Max Min Max Min Max
Setup Times (TTL Inputs)
Pad to Clock (IK), no delay
with delay TPICK
TPICKD
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
4.0
10.9
10.9
10.9
11.1
11.3
11.8
14.0
14.0
2.6
8.2
8.7
9.2
9.6
9.8
10.2
11.4
11.4
2.0
6.0
6.1
6.2
6.3
6.4
7.9
9.4
10.0
1.5
4.8
5.1
5.8
5.8
6.0
7.6
8.2
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup Time (CMOS Inputs)
Pad to Clock (IK), no delay
with delay TPICKC
TPICKDC
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
6.0
12.0
12.0
12.3
12.8
13.0
13.5
16.0
16.0
3.3
8.8
9.7
9.9
10.3
10.5
10.9
12.1
12.1
2.4
6.9
8.0
8.1
8.2
8.3
10.0
12.1
12.1
2.4
5.3
5.6
6.3
6.3
6.5
7.9
8.1
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
(TTL or CMOS)
Clock Enable (EC) to Clock
(IK), no delay
with delay TECIK
TECIKD
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
3.5
10.4
10.4
10.4
10.4
10.7
11.1
14.0
14.0
2.5
8.1
8.5
9.1
9.5
9.7
10.1
11.3
11.3
2.1
4.3
5.6
6.7
6.9
7.1
9.0
10.6
11.0
1.5
4.3
5.0
6.0
6.0
6.5
8.0
9.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
Global Set/Reset (Note 3)
Delay from GSR net
through Q to I1, I2
GSR width
GSR inactive to first active
Clock (IK) edge
TRRI
TMRW
TMRI
13.0
12.0
11.5
7.8
11.5
6.8
10.0
6.8 ns
ns
Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Note 3: Timing is based on the XC4005E. For other devices see the XACT timing calculator.
R
February 11, 2000 (Version 1.8) 6-115
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000E IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
Speed Grade -4 -3 -2 -1 Units
Description Symbol Min Max Min Max Min Max Min Max
Propagation Delays (TTL Output Levels)
Clock (OK) to Pad, fast
slew-rate limited
Output (O) to Pad, fast
slew-rate limited
3-state to Pad hi-Z
(slew-rate independent)
3-state to Pad active
and valid, fast
slew-rate limited
TOKPOF
TOKPOS
TOPF
TOPS
TTSHZ
TTSONF
TTSONS
7.5
11.5
8.0
12.0
5.0
9.7
13.7
6.5
9.5
5.5
8.5
4.2
8.1
11.1
4.5
7.0
4.8
7.3
3.8
7.3
9.8
3.0
5.0
3.2
5.2
3.0
6.8
8.8
ns
ns
ns
ns
ns
ns
ns
Propagation Delays (CMOS Output Levels)
Clock (OK) to Pad, fast
slew-rate limited
Output (O) to Pad, fast
slew-rate limited
3-state to Pad hi-Z
(slew-rate independent)
3-state to Pad active
and valid, fast
slew-rate limited
TOKPOFC
TOKPOSC
TOPFC
TOPSC
TTSHZC
TTSONFC
TTSONSC
9.5
13.5
10.0
14.0
5.2
9.1
13.1
7.8
11.6
9.7
13.4
4.3
7.6
11.4
7.0
10.4
8.7
12.1
3.9
6.8
10.2
4.0
7.0
4.0
6.0
3.9
6.8
8.8
ns
ns
ns
ns
ns
ns
ns
Note 1: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-116 February 11, 2000 (Version 1.8)
IOB Output Switching Characteristics Guidelines (Continued)
Speed Grade -4 -3 -2 -1 Units
Description Symbol Min Max Min Max Min Max Min Max
Setup and Hold
Output (O) to clock (OK)
setup time
Output (O) to clock (OK)
hold time
Clock Enable (EC) to
clock (OK) setup
Clock Enable (EC) to
clock (OK) hold
TOOK
TOKO
TECOK
TOKEC
5.0
0
4.8
1.2
4.6
0
3.5
1.2
3.8
0
2.7
0.5
2.3
0
2.0
0
ns
ns
ns
ns
Clock
Clock High
Clock Low TCH
TCL
4.5
4.5 4.0
4.0 4.0
4.0 3.0
3.0 ns
ns
Global Set/Reset (Note 3)
Delay from GSR net to Pad
GSR width
GSR inactive to first active
clock (OK) edge
TRPO
TMRW
TMRO
13.0 15.0 11.5 11.8 11.5 8.7 7.0 ns
ns
Note 1: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Note 3: Timing is based on the XC4005E. For other devices see the XACT timing calculator.
R
February 11, 2000 (Version 1.8) 6-117
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more
up-to-date information, use the values provided by the XACT timing calculator and used in the simulator. These values can
be printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Revision Control
Speed Grade -4 -3 -2 -1 Units
Description Symbol Min Max Min Max Min Max Min Max
Setup Times
Input (TDI) to clock (TCK)
Input (TMS) to clock (TCK) TTDITCK
TTMSTCK
30.0
15.0 30.0
15.0 30.0
15.0 20.0
10.0 ns
ns
Hold Times
Input (TDI) to clock (TCK)
Input (TMS) to clock (TCK) TTCKTDI
TTCKTMS
0
00
00
00
0ns
ns
Propagation Delay
Clock (TCK) to Pad (TDO) TTCKPO 30.0 30.0 30.0 20.0 ns
Clock
Clock (TCK) High
Clock (TCK) Low TTCKH
TTCKL
5.0
5.0 5.0
5.0 5.0
5.0 4.0
4.0 ns
ns
Frequency FMAX 15.0 15.0 15.0 25.0 MHz
Note 1: Input setup and hold times and clock-to-pad times are specified with respect to external signal pins.
Note 2: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Note 3: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Version Nature of Changes
3/30/98 (1.5) As submitted for the 1999 data book
1/29/99 (1.5) Updated Switching Characteristics Tables
5/14/99 (1.6) Replaced Electrical Specification and pinout pages for E, EX, and XL families with separate updates
and added URL link on placeholder page for electrical specifications/pinouts for WebLINX users
8/27/99 (1.7) Included missing IOB Propagation Delay page (6-113)
2/11/00 (1.8) Altered IOB heads (Acrobat PDF file problem), corrected Dual-port Write Mins for -4 speed grade.