74F573
Octal transparent latch (3-State)
74F574
Octal transparent latch (3-State)
Product specification
IC15 Data Handbook
1989 Oct 16
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
74F573 Octal Transparent Latch (3-State)
74F574 Octal D Flip-Flop (3-State)
2
1989 Oct 16 853-0083 97897
FEATURES
•74F573 is broadside pinout version of 74F373
•74F574 is broadside pinout version of 74F374
•Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
•Useful as an Input or Output port for Microprocessors
•3-State Outputs for Bus interfacing
•Common Output Enable
•74F563 and 74F564 are inverting version of 74F573 and 74F574
respectively
•3-State Outputs glitch free during power-up and power-down
•These are High-Speed replacements for N8TS805 and N8TS806
DESCRIPTION
The 74F573 is an octal transparent latch coupled to eight 3-State
output buf fers. The two sections of the device are controlled
independently by Enable (E) and Output Enable (OE) control gates.
The 74F573 is functionally identical to the 74F373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
Enable (E) input is High. The latch remains transparent to the data
input while E is High and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independent to the latch operation. When OE is Low, the latched or
transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
The 74F574 is functionally identical to the 74F374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocesors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE) control gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independently of the latch operation. When OE is Low, the latched
or transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
TYPE TYPICAL
PROPAGATION DELAY
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F573 5.0ns 35mA
TYPE TYPICAL fMAX TYPICAL SUPPLY
CURRENT
(TOTAL)
74F574 180MHz 50mA
ORDERING INFORMATION
DESCRIPTION COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°CPKG DWG #
20-Pin Plastic DIP N74F573N, N74F574N SOT146-1
20-Pin Plastic SOL N74F573D, N74F574D SOT163-1
20-Pin Plastic SSOP N74F573DB SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74F (U.L.)
HIGH/LOW LOAD VALUE
HIGH/LOW
D0 - D7 Data inputs 1.0/1.0 20µA/0.6mA
E (74F573) Latch Enable input (active falling edge) 1.0/1.0 20µA/0.6mA
OE Output Enable input (active Low) 1.0/1.0 20µA/0.6mA
CP (74F574) Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
Q0 - Q7 3-State outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
1989 Oct 16 3
PIN CONFIGURATION – 74F573
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
OE
GND
VCC
E
SF01073
Q0
D0
D1 Q1
D2 Q2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
Q7
D7
PIN CONFIGURATION – 74F574
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
OE
GND
VCC
CP
SF01074
Q0
D0
D1 Q1
D2 Q2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
Q7
D7
LOGIC SYMBOL – 74F573
345678
141516171819
1
11 E
OE
Q0
D0 D1
Q1
D2
Q2 Q3
D3
Q4
D4
Q5
D5
9
2
1213
Q6
D6
Q7
D7
SF01075
VCC=Pin 20
GND=Pin 10
LOGIC SYMBOL – 74F574
345678
141516171819
1
11 CP
OE
Q0
D0 D1
Q1
D2
Q2 Q3
D3
Q4
D4
Q5
D5
9
2
1213
Q6
D6
Q7
D7
SF01076
VCC=Pin 20
GND=Pin 10
LOGIC SYMBOL (IEEE/IEC) – 74F573
2D 1
SF01077
1
11
2
3
4
5
6
7
8
9
EN1
EN2
19
18
17
16
15
14
13
12
LOGIC SYMBOL (IEEE/IEC) – 74F574
2D 1
SF01078
1
11 EN1
C2
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
1989 Oct 16 4
LOGIC DIAGRAM – 74F573
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
E
OE
23456789
1213141516171819
1
11
E
D
Q E
D
QEQ
D
E
D
Q E
D
Q E
D
Q E
D
Q E
D
Q
VCC=Pin 20
GND=Pin 10
SF01079
FUNCTION TABLE – 74F573
INPUTS INTERNAL OUTPUTS
OPERATING MODES
OE E Dn REGISTER Q0 – Q7
OPERATING
MODES
L
LH
HL
HL
HL
HLoad and read register
L
L↓
↓l
hL
HL
HLatch and read register
L L X NC NC Hold
H
HL
HX
Dn NC
Dn Z
ZDisable outputs
H = High voltage level
h = High voltage level one setup time prior to the High-to-Low E transition
L = Low voltage level
l = Low voltage level one setup time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “of f” state
↓= High-to-Low E transition
LOGIC DIAGRAM – 74F574
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CP
OE
23456789
1213141516171819
1
11
CP
D
Q CP
D
Q CP Q
D
CP
D
Q CP
D
Q CP
D
Q CP
D
Q CP
D
Q
VCC=Pin 20
GND=Pin 10
SF01080
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
1989 Oct 16 5
FUNCTION TABLE – 74F574
INPUTS INTERNAL OUTPUTS
OPERATING MODES
OE CP Dn REGISTER Q0 – Q7
OPERATING
MODES
L
L↑
↑l
hL
HL
HLoad and read register
L↑X NC NC Hold
H↑Dn Dn Z Disable outputs
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “of f” state
↑= Low-to-High clock transition
↑= Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL PARAMETER RATING UNIT
VCC Supply voltage –0.5 to +7.0 V
VIN Input voltage –0.5 to +7.0 V
IIN Input current –30 to +5.0 mA
VOUT Voltage applied to output in High output state –0.5 to +VCC V
IOUT Current applied to output in Low output state 48 mA
Tamb Operating free-air temperature range 0 to +70 °C
Tstg Storage temperature –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5.0 5.5 V
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
IIK Input clamp current –18 mA
IOH High-level output current –3 mA
IOL Low-level output current 24 mA
Tamb Operating free-air temperature range 0 70 °C
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
1989 Oct 16 6
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
NO TAG
LIMITS
SYMBOL PARAMETER TEST CONDITIONS
NO
TAG
MIN TYP
NO TAG MAX UNIT
VO
High level out
p
ut voltage
V
CC
= MIN
,
V
IL
= MAX
,
±10%VCC 2.4 V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
VCC
MIN,
VIL
MAX,
VIH = MIN, IOH = MAX ±5%VCC 2.7 3.4 V
VO
Low level out
p
ut voltage
V
CC
= MIN
,
V
IL
= MAX
,
±10%VCC 0.35 0.50 V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
VCC
MIN,
VIL
MAX,
VIH = MIN, IOL = MAX ±5%VCC 0.35 0.50 V
VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V
IIInput current at
maximum input voltage VCC = MAX, VI = 7.0V 100 µA
IIH High-level input current VCC = MAX, VI = 2.7V 20 µA
IIL Low-level input current VCC = MAX, VI = 0.5V –0.6 mA
IOZH Off-state output current,
High-level voltage applied VCC = MAX, VO = 2.7V 50 µA
IOZL Off-state output current,
Low-level voltage applied VCC = MAX, VO = 0.5V –50 µA
IOS Short-circuit output currentNO TAG VCC = MAX –60 –150 mA
ICCH 30 40 mA
ICCL 74F573 VCC = MAX 35 50 mA
ICC
Supply
current
ICCZ 40 60 mA
I
CC curren
t
(total) ICCH 45 65 mA
()
ICCL 74F574 VCC = MAX 50 70 mA
ICCZ 55 85 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
1989 Oct 16 7
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST
CONDITIONS Tamb= +25°C
VCC = +5V
CL = 50pF, RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5V ± 10%
CL = 50pF, RL = 500ΩUNIT
MIN TYP MAX MIN MAX
tPLH
tPHL Propagation delay
Dn to Qn Waveform
NO TAG 3.0
1.0 5.5
3.5 8.0
6.0 2.5
1.0 9.0
7.0 ns
tPLH
tPHL Propagation delay
E to Qn Waveform
NO TAG 4.5
3.0 8.5
5.0 11.5
7.0 4.0
2.5 12.5
8.0 ns
tPZH
tPZL Output Enable time
to High or Low level 74F573 Waveform
NO TAG
Waveform
NO TAG
2.5
2.5 5.5
5.5 9.5
8.0 2.0
2.0 10.5
8.5 ns
tPHZ
tPLZ Output Disable time
from High or Low level
Waveform
NO TAG
Waveform
NO TAG
1.0
1.0 3.0
2.5 6.0
5.5 1.0
1.0 6.5
5.5 ns
fMAX Maximum Clock frequency Waveform
NO TAG 160 180 150 MHz
tPLH
tPHL Propagation delay
CP to Qn Waveform
NO TAG 3.5
3.5 5.0
5.0 7.5
7.5 3.0
3.0 8.0
8.0 ns
tPZH
tPZL Output Enable time
to High or Low level 74F574 Waveform
NO TAG
Waveform
NO TAG
2.5
3.0 4.5
5.0 7.5
8.0 2.0
3.0 7.5
8.5 ns
tPHZ
tPLZ Output Disable time
from High or Low level
Waveform
NO TAG
Waveform
NO TAG
1.0
1.0 3.0
2.5 5.5
5.5 1.0
1.0 6.0
6.0 ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL PARAMETER TEST
CONDITIONS
Tamb= +25°C
VCC = +5V
CL = 50pF, RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500ΩUNIT
MIN TYP MAX MIN MAX
ts(H)
ts(L) Setup time,
Dn to E W aveform 4 0.0
1.5 0.0
2.0 ns
th(H)
th(L) Hold time,
Dn to E 74F573 W aveform 4 2.5
4.0 2.5
4.0 ns
tw(H) E pulse width,
High W aveform NO TAG 3.0 3.5 ns
ts(H)
ts(L) Setup time,
Dn to CP W aveform NO TAG 2.5
2.5 3.0
3.0 ns
th(H)
th(L) Hold time,
Dn to CP 74F574 W aveform NO TAG 0
00
0ns
tw(H)
tw(L) CP Pulse width,
High or Low W aveform NO TAG 3.0
3.5 3.0
4.0 ns
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
1989 Oct 16 8
AC WAVEFORMS
For all waveforms, VM = 1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
tW(H)
E, CP
QnVMVM
VMVMVM
1/fMAX
tW(L) tPLH
tPHL
SF01081
W aveform 1. Propagation Delay, Clock and Enable Inputs
to Output, Enable, Clock Pulse Widths,
and Maximum Clock Frequency
VM
VM
VM
tPHL
Dn
VM
tPLH
SF01082
Qn
W aveform 2. Propagation Delay for Data to Outputs
th(H)ts(H)
CP
SF00191
VMVM
VM
VM
VMVM
th(L)ts(L)
Dn
W aveform 3. Data Setup and Hold Times
E
Dn VMVMVMVM
VMVM
ts(L)ts(H) th(L)th(H)
SF00992
W aveform 4. Data Setup and Hold Times
VM
VM
VM
tPHZ
tPZH VOH -0.3V
0V
OE
Qn
SF00343
W aveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
VM
VM
VM
tPLZ
tPZL
VOL +0.3V
Qn
OE
SF00344
W aveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
1989 Oct 16 9
TEST CIRCUIT AND WAVEFORM
tw90%
VM
10%
90%
VM10%
90%
VM10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf )
INPUT PULSE REQUIREMENTS
rep. rate twtTLH tTHL
1MHz 500ns 2.5ns 2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN VOUT
Test Circuit for 3-State Outputs
DEFINITIONS:
RL= Load resistor;
see AC electrical characteristics for value.
CL= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT= Termination resistance should be equal to ZOUT of
pulse generators.
tTHL (tf )
tTLH (tr )
tTLH (tr )AMP (V)
amplitude
3.0V 1.5V
VM
RL
7.0V
SF00777
TEST SWITCH
tPLZ closed
tPZL closed
All other open
SWITCH POSITION
Philips Semiconductors Product specification
74F573, 74F574Latch/flip-flop
1989 Oct 16 10
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
Philips Semiconductors Product specification
74F573, 74F574Latch/flip-flop
1989 Oct 16 11
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
Philips Semiconductors Product specification
74F573, 74F574Latch/flip-flop
1989 Oct 16 12
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
Philips Semiconductors Product specification
74F573, 74F574Latch/flip-flop
1989 Oct 16 13
NOTES
Philips Semiconductors Product specification
74F573, 74F574Latch/flip-flop
yyyy mmm dd 14
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05141
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
