TL/F/6401
54LS169/DM54LS169A/DM74LS169A
Synchronous 4-Bit Up/Down Binary Counter
June 1989
54LS169/DM54LS169A/DM74LS169A
Synchronous 4-Bit Up/Down Binary Counter
General Description
This synchronous presettable counter features an internal
carry look-ahead for cascading in high-speed counting ap-
plications. Synchronous operation is provided by having all
flip-flops clocked simultaneously, so that the outputs all
change at the same time when so instructed by the count-
enable inputs and internal gating. This mode of operation
helps eliminate the output counting spikes that are normally
associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four master-slave flip-flops
on the rising edge of the clock waveform.
This counter is fully programmable; that is, the outputs may
each be preset either high or low. The load input circuitry
allows loading with the carry-enable output of cascaded
counters. As loading is synchronous, setting up a low level
at the load input disables the counter and causes the out-
puts to agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional gating.
Both count-enable inputs (P and T) must be low to count.
The direction of the count is determined by the level of the
up/down input. When the input is high, the counter counts
up; when low, it counts down. Input T is fed forward to en-
able the carry outputs. The carry output thus enabled will
produce a low-level output pulse with a duration approxi-
mately equal to the high portion of the QAoutput when
counting up, and approximately equal to the low portion of
the QAoutput when counting down. This low-level overflow
carry pulse can be used to enable successively cascaded
stages. Transitions at the enable P or T inputs are allowed
regardless of the level of the clock input. All inputs are diode
clamped to minimize transmission-line effects, thereby sim-
plifying system design.
This counter features a fully independent clock circuit.
Changes at control inputs (enable P, enable T, load, up/
down), which modify the operating mode, have no effect
until clocking occurs. The function of the counter (whether
enabled, disabled, loading, or counting) will be dictated
solely by the conditions meeting the stable setup and hold
times.
Features
YFully synchronous operation for counting and
programming.
YInternal look-ahead for fast counting.
YCarry output for n-bit cascading.
YFully independent clock circuit
YAlternate Military/Aerospace device (54LS169) is
available. Contact a National Semiconductor Sales
Office/Distributor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/64011
Order Number 54LS169DMQB, 54LS169FMQB, 54LS169LMQB,
DM54LS169AJ, DM54LS169AW, DM74LS169AM or DM74LS169AN
See NS Package Number E20A, J16A, M16A, N16E or W16A
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range
DM54LS and 54LS b55§Ctoa
125§C
DM74LS 0§Ctoa
70§C
Storage Temperature Range b65§Ctoa
150§C
Note:
The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol Parameter DM54LS169A DM74LS169A Units
Min Nom Max Min Nom Max
VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
VIL Low Level Input Voltage 0.7 0.8 V
IOH High Level Output Current b0.4 b0.4 mA
IOL Low Level Output Current 4 8 mA
fCLK Clock Frequency (Note 1) 0 25 0 25 MHz
Clock Frequency (Note 2) 0 20 0 20 MHz
tWClock Pulse Width (Note 3) 25 25 ns
tSU Setup Time Data 20 20
(Note 3) Enable 20 20
T or P ns
Load 25 25
U/D 30 30
tHHold Time (Note 3) 0 0 ns
TAFree Air Operating Temperature b55 125 0 70 §C
Note 1: CLe15 pF, RLe2kX,T
Ae25§C and VCC e5V.
Note 2: CLe50 pF, RLe2kX,T
Ae25§C and VCC e5V.
Note 3: TAe25§C and VCC e5V.
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
(Note 4)
VIInput Clamp Voltage VCC eMin, IIeb
18 mA b1.5 V
VOH High Level Output VCC eMin, IOH eMax DM54 2.5 3.4 V
Voltage VIL eMax, VIH eMin DM74 2.7 3.4
VOL Low Level Output VCC eMin, IOL eMax DM54 0.25 0.4
Voltage VIL eMax, VIH eMin DM74 0.35 0.5 V
IOL e4 mA, VCC eMin DM74 0.25 0.4
IIInput Current @Max VCC eMax Enable T 0.2 mA
Input Voltage VIe7V Others 0.1
IIH High Level Input VCC eMax Enable T 40 mA
Current VIe2.7V Others 20
IIL Low Level Input VCC eMax Enable T b0.8 mA
Current VIe0.4V Others b0.4
IOS Short Circuit VCC eMax DM54 b20 b100 mA
Output Current (Note 5) DM74 b20 b100
ICC Supply Current VCC eMax (Note 6) 20 34 mA
Note 4: All typicals are at VCC e5V and TAe25§C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 6: ICC is measured after a momentary 4.5V, then ground, is applied to the CLOCK with all other inputs grounded and all the outputs open.
2
Switching Characteristics at VCC e5V and TAe25§C (See Section 1 for Test Waveforms and Output Load)
From (Input)
RLe2kX
Symbol Parameter To (Output) CLe15 pF CLe50 pF Units
Min Max Min Max
fMAX Maximum Clock 25 20 MHz
Frequency
tPLH Propagation Delay Time Clock to 35 39 ns
Low to High Level Output Ripple Carry
tPHL Propagation Delay Time Clock to 35 44 ns
High to Low Level Output Ripple Carry
tPLH Propagation Delay Time Clock to 20 24 ns
Low to High Level Output Any Q
tPHL Propagation Delay Time Clock to 23 32 ns
High to Low Level Output Any Q
tPLH Propagation Delay Time Enable T to 18 24 ns
Low to High Level Output Ripple Carry
tPHL Propagation Delay Time Enable T to 18 28 ns
High to Low Level Output Ripple Carry
tPLH Propagation Delay Time Up/Down to 25 30 ns
Low to High Level Output Ripple Carry (Note 1)
tPHL Propagation Delay Time Up/Down to 29 38 ns
High to Low Level Output Ripple Carry (Note 1)
Note 1: The propagation delay from UP/DOWN to RIPPLE CARRY must be measured with the counter at either a minimum or a maximum count. As the logic level
of the up/down input is changed, the ripple carry output will follow. If the count is minimum, the ripple carry output transition will be in phase. If the count is
maximum, the ripple carry output will be out of phase.
3
Logic Diagram
LS169A Binary Counter
TL/F/64012
4
Timing Diagram
LS169A Binary Counters
Typical Load, Count, and Inhibit Sequences
TL/F/64013
5
Physical Dimensions inches (millimeters)
Ceramic Leadless Chip Carrier Package (E)
Order Number 54LS169LMQB
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 54LS169DMQB or DM54LS169AJ
NS Package Number J16A
6
Physical Dimensions inches (millimeters) (Continued)
16-Lead Small Outline Molded Package (M)
Order Number DM74LS169AM
NS Package Number M16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS169AN
NS Package Number N16E
7
54LS169/DM54LS169A/DM74LS169A
Synchronous 4-Bit Up/Down Binary Counter
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 54LS169FMQB or DM54LS169AW
NS Package Number W16A
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