2007-2015 Microchip Technology Inc. DS40001341F-page 1
PIC16(L)F722/3/4/6/7
Devices Included In This Data Sheet:
PIC16F722/3/4/6/7 Devices:
PIC16LF722/3/4/6/7 Devices:
High-Performance RISC CPU:
• Only 35 Instru ctions to Lear n:
- All single-cycle instructions except branches
• Ope rati ng Sp eed :
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Up to 8K x 14 Words of Flash Program Memory
• Up to 368 Bytes of Data Memory (RAM)
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
• Processor Read Access to Program Memory
• Pinou t Compatibl e to other 28/40-pin PI C16CXXX
and PIC16FXXX Microcontrollers
S pecial Microcontroller Features:
• Precision Internal Oscillator:
- 16 MHz or 500 kHz operation
- Factory calibrated to ±1%, typical
- Softwa re tu nable
- Software selectable ÷1, ÷2, ÷4 or ÷8 divider
• 1.8V-5.5V Operation – PIC16F722/3/4/6/7
• 1.8V-3.6V Operation – PIC16LF722/3/4/6/7
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR):
- Selectable between two trip points
- Disable in Sleep option
• Programmable Code Protection
• In-C ircuit Serial Programm ingTM (ICSPTM) via Two
Pins
• Multiplexed Master Clear with Pull-up/Input Pin
• Indus tri al and Extended Temperatu r e Range
• High-Endurance Flash Cell:
- 1,000 write Flash endurance (typical)
- F lash r etention: > 40 years
• Power-Saving Sleep mode
Extreme Low-Power M anagement
PIC16LF722/3/4/6/7 with XLP:
• Sleep Mode: 20 nA
• Watchdog Ti mer: 500 nA
• Timer1 Oscillator: 600 nA @ 32 kHz
Analog Features:
• A/D Converter:
- 8-bit resolution and up to 14 channels
- Conversion available during Sleep
- Select ab le 1.0 24/2 . 04 8/4 .096 V voltage
reference
• On-ch ip 3 .2V Regulator (PIC1 6F 72 2/3 /4 /6/ 7
devices only)
Peripheral Highl ights:
• Up to 35 I/O Pins and One Input-only Pin:
- High-current source/sink for direct LED drive
- Interrupt-on-pin change
- Individually programmable weak pull-ups
• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler
• Enhanced Timer1:
- Dedicated low-power 32 kHz oscillator
- 16-bit timer/counter with prescaler
- External Gate Input mode with Toggle and
Single Shot modes
- Interrupt-on-gate completion
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two Capture, Compare, PWM (CCP) Modules:
- 1 6-bit Capture, max. resolution 12.5 ns
- 16-bit Compare, max. resolution 200 ns
- 10-bit PWM, max. frequency 20 kHz
• Addressable Universal Synchronous
Asynchronous Receiver Transmitter (AUSART)
• Synchronous Serial Port (SSP):
- SPI (Master/Slave)
-I
2C (Slave) with Address Mask
•mTouch
® Sensing Oscill ator Module:
- Up to 16 input channels
• PIC16F722 • PIC16F726
• PIC16F723 • PIC16F727
•PIC16F724
• PIC16LF722 • PIC16LF726
• PIC16LF723 • PIC16LF727
• PIC16LF724
28/40/44-Pin Flash Microcontrollers with XLP Technology
PIC16(L)F722/3/4/6/7
DS40001341F-page 2 2007-2015 Mic rochip Tec hnology Inc.
PIC16(L)F72X Family Types
Device
Data Sheet Index
Program Memory
Flash (words)
Data SRAM
(bytes)
High-Endurance Flash
Memory (bytes)
I/O’s(2)
8-bit ADC (ch)
CapSense (ch)
Timers
(8/16-bit)
AUSART
SSP (I2C/SPI)
CCP
Debug(1)
XLP
PIC16(L)F707 (1) 8192 363 036 14 32 4/2 1 1 2 I Y
PIC16(L)F720 (2) 2048 128 128 18 12 —2/1 1 1 1 I Y
PIC16(L)F721 (2) 4096 256 128 18 12 —2/1 1 1 1 I Y
PIC16(L)F722 (4) 2048 128 0 25 11 8 2/1 1 1 2 I Y
PIC16(L)F722A (3) 2048 128 025 11 82/1 1 1 2 I Y
PIC16(L)F723 (4) 4096 192 0 25 11 8 2/1 1 1 2 I Y
PIC16(L)F723A (3) 4096 192 025 11 82/1 1 1 2 I Y
PIC16(L)F724 (4) 4096 192 0 36 14 16 2/1 1 1 2 I Y
PIC16(L)F726 (4) 8192 368 0 25 11 8 2/1 1 1 2 I Y
PIC16(L)F727 (4) 8192 368 0 36 14 16 2/1 1 1 2 I Y
Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.
2: One pin is input-only.
Dat a Shee t Index: (Unshaded devices are described in this document.)
1: DS41418 PIC16(L)F707 Data Sheet, 40/44-Pin Flash, 8-bit Microcontrollers
2: DS41430 PIC16(L)F720/721 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers
3: DS41417 PIC16(L)F722A/723A Data Sheet, 28-Pin Flash, 8-bit Microcontrollers
4: DS41341 PIC16(L)F72X Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers
2007-2015 Microchip Technology Inc. DS40001341F-page 3
PIC16(L)F722/3/4/6/7
Pin Diagrams – 28-PIN PDIP/SOIC/SSOP/QFN/UQFN (PIC16F722/723/726/PIC16LF722/723/726)
PIC16F722/723/726/
PIC16LF722/723/726
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
VCAP(3)/SS(2)/AN0/RA0
AN1/RA1
AN2/RA2
VREF/AN3/RA3
T0CKI/CPS6/RA4
VCAP(3)/SS(2)/CPS7/AN4/RA5
RB6/ICSPCLK
RB5/AN13/CPS5/T1G
RB4/AN11/CPS4
RB3/AN9/CPS3/CCP2(1)
RB2/AN8/CPS2
RB1/AN10/CPS1
RB0/AN12/CPS0/INT
VDD
VSS
11
12
13
14 15
16
17
18
19
20
28
27
26
25
24
23
22
21
VSS
CLKIN/OSC1/RA7
VCAP(3)/CLKOUT/OSC2/RA6
T1CKI/T1OSO/RC0
CCP2(1)/T1OSI/RC1
CCP1/RC2
SCL/SCK/RC3
RC5/SDO
RC4/SDI/SDA
RC7/RX/DT
RC6/TX/CK
RB7/ICSPDAT
2
3
6
1
18
19
20
21
15
716
17
T1CKI/T1OSO/RC0
5
4
RB7/ICSPDAT
RB6/ICSPCLK
RB5/AN13/CPS5/T1G
RB4/AN11/CPS4
RB3/AN9/CPS3/CCP2(1)
RB2/AN8/CPS2
RB1/AN10/CPS1
RB0/AN12/CPS0/INT
VDD
VSS
RC7/RX/DT
CK/TX/RC6
SDO/RC5
SDA/SDI/RC4
RE3/MCLR/VPP
RA0/AN0/SS(2)/VCAP(3)
RA1/AN1
AN2/RA2
VREF/AN3/RA3
T0CKI/CPS6/RA4
VCAP(3)/SS(2)/CPS7/AN4/RA5
VSS
CLKIN/OSC1/RA7
VCAP(3)/CLKOUT/OSC2/RA6
CCP2(1)/T1OSI/RC1
CCP1/RC2
SCL/SCK/RC3
9
10
13
8
14
12
11
27
26
23
28
22
24
25
PIC16F722/723/726/
PIC16LF722/723/726
Note 1:CCP2 pin location may be selected as RB3 or RC1.
2: SS pin location may be selected as RA5 or RA0.
3: PIC16F722/723/726 devices only.
PDIP, SOIC, SSOP
QFN, UQFN
PIC16(L)F722/3/4/6/7
DS40001341F-page 4 2007-2015 Mic rochip Tec hnology Inc.
TABLE 1: 28-PIN PDIP/SOIC/SSOP/QFN/UQFN SUMMARY (PIC16F722/723/726/PIC16LF722/723/
726)
I/O
28-Pin
PDIP,
SOIC,
SSOP
28-Pin
QFN,
UQFN A/D Cap Sensor Timers CCP AUSART SSP Interrupt Pull-Up Basic
RA0 227 AN0 — — — — SS(3) — — VCAP(4)
RA1 3 28 AN1 — — — — — — — —
RA2 4 1 AN2 — — — — — — — —
RA3 5 2 AN3/VREF ——————— —
RA4 6 3 — CPS6 T0CKI — — — — — —
RA5 7 4 AN4 CPS7 — — — SS(3) —— VCAP(4)
RA6 10 7 — — — — — — — — OSC2/CLKOUT/VCAP(4)
RA7 9 6 — — — — — — — — OSC1/CLKIN
RB0 21 18 AN12 CPS0 — — — — IOC/INT Y —
RB1 22 19 AN10 CPS1 — — — — IOC Y —
RB2 23 20 AN8 CPS2 — — — — IOC Y —
RB3 24 21 AN9 CPS3 — CCP2(2) — — IOC Y —
RB4 25 22 AN11 CPS4 — — — — IOC Y —
RB5 26 23 AN13 CPS5 T1G — — — IOC Y —
RB6 27 24 — — — — — — IOC YICSPCLK/ICDCLK
RB7 28 25 — — — — — — IOC Y ICSPDAT/ICDDAT
RC0 11 8 — — T1OSO/T1CKI — — — — — —
RC1 12 9 — — T1OSI CCP2(2) ———— —
RC2 13 10 — — — CCP1 — — — — —
RC3 14 11 — — — — — SCK/SCL — — —
RC4 15 12 — — — — SDI/SDA — — —
RC5 16 13 — — — — — SDO — — —
RC6 17 14 — — — — TX/CK — — — —
RC7 18 15 — — — — RX/DT — — — —
RE3 126 — — — — — — — Y(1) MCLR/VPP
—2017 — — — — — — — — VDD
—8,19 5,16 — — — — — — — — VSS
Note 1: Pull-up enabled only with external MCLR Configuration.
2: RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.
3: RA5 is the default pin location for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register.
4: PIC16F724/727/PIC16LF724/727 devices only.
Note: The PIC 16F722/3 /4/6/7 devi ces have an internal low dropou t volta ge regulato r . An exte rnal cap acitor mu st
be connected to one of the available VCAP pins to stabilize the regulator. For more information, see
Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16L F722/3 /4/6/7 dev ices d o not h ave t he
voltage regulator and therefore no external capacitor is required.
2007-2015 Microchip Technology Inc. DS40001341F-page 5
PIC16(L)F722/3/4/6/7
Pin Diagrams – 40-PIN PDIP (PIC16F724/727/PIC16LF724/727)
PIC16F724/727/
PIC16LF724/727
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
VCAP(3)/SS(2)/AN0/RA0
AN1/RA1
AN2/RA2
VREF/AN3/RA3
T0CKI/CPS6/RA4
VCAP(3)/SS(2)/CPS7/AN4/RA5
AN5/RE0
AN6/RE1
AN7/RE2
RB6/ICSPCLK
RB5/AN13/CPS5/T1G
RB4/AN11/CPS4
RB3/AN9/CPS3/CCP2(1)
RB2/AN8/CPS2
RB1/AN10/CPS1
RB0/AN12/CPS0/INT
VDD
VSS
RD2/CPS10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
VSS
CLKIN/OSC1/RA7
VCAP(3)/CLKOUT/OSC2/RA6
T1CKI/T1OSO/RC0
CCP2(1)/T1OSI/RC1
CCP1/RC2
SCL/SCK/RC3
CPS8/RD0
CPS9/RD1
RC5/SDO
RC4/SDI/SDA
RD3/CPS11
RD4/CPS12
RC7/RX/DT
RC6/TX/CK
RD7/CPS15
RD6/CPS14
RD5/CPS13
RB7/ICSPDAT
Note 1:CCP2 pin location may be selected as RB3 or RC1.
2: SS pin location may be selected as RA5 or RA0.
3: PIC16F724/727 devices only.
PIC16(L)F722/3/4/6/7
DS40001341F-page 6 2007-2015 Mic rochip Tec hnology Inc.
Pin Diagrams – 44-PIN TQFP (PIC16F724/727/PIC16LF724/727)
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
VREF/AN3/RA3
AN2/RA2
AN1/RA1
VCAP(3)/SS(2)/AN0/RA0
VPP/MCLR/RE3
NC
ICSPDAT/RB7
ICSPCLK/RB6
T1G/CPS5/AN13/RB5
CPS4/AN11/RB4
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/CPS11
RD2/CPS10
RD1/CPS9
RD0/CPS8
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2(1)
NC
NC
RC0/T1OSO/T1CKI
RA6/OSC2/CLKOUT/VCAP(3)
RA7/OSC1/CLKIN
VSS
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/CPS7/SS(2)/VCAP(3)
RA4/CPS6/T0CKI
DT/RX/RC7
CPS12/RD4
CPS13/RD5
CPS14/RD6
VSS
VDD
INT/CPS0/AN12/RB0
CPS1/AN10/RB1
CPS2/AN8/RB2
CCP2(1)/CPS3/AN9/RB3
CPS15/RD7 5
4PIC16F724/727/
PIC16LF724/727
Note 1:CCP2 pin location may be selected as RB3 or RC1.
2: SS pin location may be selected as RA5 or RA0.
3: PIC16F724/727 devices only.
2007-2015 Microchip Technology Inc. DS40001341F-page 7
PIC16(L)F722/3/4/6/7
Pin Diagrams – 44-PIN QFN (PIC16F724/727/PIC16LF724/727)
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
VREF/AN3/RA3
AN2/RA2
AN1/RA1
VCAP(3)/SS(2)/AN0/RA0
VPP/MCLR/RE3
CCP2(1)/CPS3/AN9/RB3
ICSPDAT/RB7
ICSPCLK/RB6
T1G/CPS5/AN13/RB5
CPS4/AN11/RB4
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/CPS11
RD2/CPS10
RD1/CPS9
RD0/CPS8
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T1CKI
RA6/OSC2/CLKOUT/VCAP(3)
RA7/OSC1/CLKIN
VSS
VSS
NC
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/CPS7/SS(2)/VCAP(3)
RA4/CPS6/T0CKI
DT/RX/RC7
CPS12/RD4
CPS13/RD5
CPS14/RD6
CPS15/RD7
VSS
VDD
VDD
INT/CPS0/AN12/RB0
CPS1/AN10/RB1
CPS2/AN8/RB2
PIC16F724/727/
PIC16LF724/727
Note 1:CCP2 pin location may be selected as RB3 or RC1.
2: SS pin location may be selected as RA5 or RA0.
3: PIC16F724/727 devices only.
PIC16(L)F722/3/4/6/7
DS40001341F-page 8 2007-2015 Mic rochip Tec hnology Inc.
TABLE 2: 40/44-PIN PDIP/TQFP/QFN SUMMARY (PIC16F724/727/PIC16LF724/727)
I/O 40-Pin
PDIP 44-Pin
TQFP 44-Pin
QFN A/D Cap
Sensor Timers CCP AUSART SSP Interrupt Pull-Up Basic
RA0 219 19 AN0 — — — — SS(3) — — VCAP(4)
RA1 3 20 20 AN1 — — — — — — — —
RA2 421 21 AN2 — — — — — — — —
RA3 5 22 22 AN3/VREF ——— — — —— —
RA4 623 23 —CPS6 T0CKI — — — — — —
RA5 7 24 24 AN4 CPS7 — — — SS(3) —— VCAP(4)
RA6 14 31 33 — — — — — — — — OSC2/CLKOUT/VCAP(4)
RA7133032 — — — — — — — — OSC1/CLKIN
RB0 33 8 9 AN12 CPS0 — — — — IOC/INT Y —
RB1 34 9 10 AN10 CPS1 — — — — IOC Y —
RB2 35 10 11 AN8 CPS2 — — — — IOC Y —
RB3 36 11 12 AN9 CPS3 — CCP2(2) — — IOC Y —
RB4 37 14 14 AN11 CPS4 — — — — IOC Y —
RB5381515AN13CPS5T1G— — — IOC Y —
RB6 39 16 16 — — — — — — IOC YICSPCLK/ICDCLK
RB7 40 17 17 — — — — — — IOC Y ICSPDAT/ICDDAT
RC0 15 32 34 — — T1OSO/
T1CKI — — — — — —
RC1 16 35 35 — — T1OSI CCP2(2) ———— —
RC2 17 36 36 — — — CCP1 — — — — —
RC3 18 37 37 — — — — — SCK/SCL — — —
RC4 23 42 42 — — — — SDI/SDA — — —
RC5 24 43 43 — — — — SDO — — —
RC6 25 44 44 — — — — TX/CK — — — —
RC7 26 1 1 — — — — RX/DT — — — —
RD0 19 38 38 —CPS8 — — — — — — —
RD1 20 39 39 — CPS9 — — — — — — —
RD2 21 40 40 —CPS10 — — — — — — —
RD3 22 41 41 — CPS11 — — — — — — —
RD4 27 2 2 — CPS12 — — — — — — —
RD5 28 3 3 — CPS13 — — — — — — —
RD6 29 4 4 — CPS14 — — — — — — —
RD7 30 5 5 — CPS15 — — — — — — —
RE0 825 25 AN5 — — — — — — — —
RE1 9 26 26 AN6 — — — — — — — —
RE2 10 27 27 AN7 — — — — — — — —
RE3 1 18 18 — — — — — — — Y(1) MCLR/VPP
—11,32 7,28 7,8,28 — — — — — — — — VDD
— 12,13 6,29 6,30,31 — — — — — — — — VSS
Note 1: Pull-up enabled only with external MCLR configur ati o n.
2: RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.
3: RA5 is the default pin location for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register.
4: PIC16F 72 2/3 /4/6 / 7 devices onl y.
Note: The PIC 16F722/3 /4/6/7 devi ces have an internal low dropou t volta ge regulato r . An exte rnal cap acitor mu st
be connected to one of the available VCAP pins to stabilize the regulator. For more information, see
Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16L F722/3 /4/6/7 dev ices d o not h ave t he
voltage regulator and therefore no external capacitor is required.
2007-2015 Microchip Technology Inc. DS40001341F-page 9
PIC16(L)F722/3/4/6/7
Table of Contents
Device Overview ................................................................................................................................................................................. 11
Memory Organization ...................................................................................... .................................................................................... 17
Resets ................................................................................................................................................................................................. 30
Interrupts ............................................................................................................................................................................................. 40
Low Dropout (LDO) Voltage Regulator ................................................................................ ............................................................... 49
I/O Ports ............ ........ ................. ......... ................ ......... ................. ........ ................. ............................................................................. 50
Oscillator Module ................................................................................................................................................................................ 85
Device Configuration ........................................................................................................................................................................... 91
Analog-to-Digital Converter (ADC) Module .................................................... ..................................................................................... 94
Fixed Voltage Reference ......... .. .... ....... .. .. .... .. .... ....... .. .. .... .. .. ....... .... .. .. .... .. ....... .... .. .. .... .. .. .... ........................................................... 104
Timer0 Module ................................. ................................................................................................................................................. 105
Timer1 Module with Gate Control ..................................................................................................................................................... 108
Timer2 Module ................................. ................................................................................................................................................. 120
Capacitive Sensing Module .................... .. .... .. .... ....... .... .. .... .. ......... .. .... .. .... .. ......... .. .... .. .... ............................................................... 122
Capture/Compare/PWM (CCP) Module ............................................................................. ............................................................... 128
Addressable Universal Synchronous Async h ronous Receiv er Transmitter (AUS ART ) .................................................................... 138
SSP Module Overview ...................................................................................................................................................................... 159
Program Memo ry Read . ................... .......................................... ..................... .................................................................................. 181
Power-Down Mode (Sleep) ............................................................................................................................................................... 184
In-Circuit Serial Programming™ (ICSP™) ........................................................................................................................................ 186
Instruction Set Summary ................................................................................................................................................................... 187
Development Support ...................... .................................................................................... ............................................................. 196
Electrical Specifications .................................................................................................................................................................... 200
DC and AC Characteristics Graphs and Charts ................................................................................................................................ 228
Packagi n g Information . ........ ................. ................. ................ ................. ................. ........ ................................................................. 263
Appendix A: Data Sheet Revision History .................................................................. .... ........... ........................................................ 277
Appendix B: Migrating From Other PIC® Devices .............................................................................. ... ........................................... 277
The Micro chip Website .................. ................. ................. ................. ................. ................ ............................................................... 278
Customer Change Notification Service ............. ................. ................. ...... ................. ........ ............ ................................................... 278
Customer Support ............................................................................................................................................................................. 278
Product Identification System ........................................................................................................................................................... 279
PIC16(L)F722/3/4/6/7
DS40001341F-page 10 2007-2015 Microchip Technology Inc.
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2007-2015 Microchip Technology Inc. DS40001341F-page 11
PIC16(L)F722/3/4/6/7
1.0 DEVICE OVERVIEW
The PIC16(L)F722/3/4/6/7 devices are covered by this
data sheet. They are available in 28/40/44-pin pack-
ages. Figure 1-1 shows a block diagram of the
PIC16F722/723/726/PIC16LF722/723/726 devices
and Figure 1-2 shows a block diagram of the
PIC16F724/727/PIC16LF724/727 devices. Table 1-1
shows the pinout descriptions.
PIC16(L)F722/3/4/6/7
DS40001341F-page 12 2007-2015 Microchip Technology Inc.
FIGURE 1-1: PIC16F722/723/726/PIC16LF722/723/726 BLOCK DIAGRAM
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start- up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD
PORTA
RA4
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
8
8
Brown-out
Reset
AUSART
Timer0 Timer1 Timer2
RA3
RA1
RA0
8
3
Analog-To-Dig ital Conve rte r
RA6
RA7
RB6
RB7
VSS
T0CKI T1G T1CKI
VREF Synchronous
SDA SCL SSSDO
Serial Port
SDI/ SCK/
TX/CK RX/DT
Internal
Oscillator
Block
Configuration 13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
RAM Addr
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start- up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
MCLR VDD
RC1
8
8
Brown-out
Reset
AUSART
Timer0 Timer1 Timer2
8
3
VSS
T0CKI T1CKI
Synchronous
SDA SCL SSSDO
Serial Port
SDI/ SCK/
Internal
Oscillator
Block
Configuration 13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
RAM Addr
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Power-up
Timer
Oscillator
Start- up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode and
Control
Timing
Generation
MCLR VDD
PORTB
PORTC
RA5
8
8
Brown-out
Reset
Timer0 Timer1 Timer2
RA2
8
3
RB0
RB1
RB2
RB3
RB4
RB5
VSS
T0CKI T1CKI
Synchronous
SDA SCL SSSDO
Serial Port
SDI/ SCK/
Internal
Oscillator
Block
Configuration
CCP2
CCP2
Timer1
32 kHz
Oscillator
PORTE RE3
CCP1
CCP1
T1OSI
T1OSO
AN9
AN0 AN1 AN2 AN3 AN4 AN8 AN10 AN11 AN12 AN13
LDO(1)
Regulator
Flash
Program
Memory
Note 1: PIC16F722/723/726 only.
RAM
Capacitive Sensi n g Modul e
CPS6
CPS0 CPS1 CPS2 CPS3 CPS4 CPS5 CPS7
2007-2015 Microchip Technology Inc. DS40001341F-page 13
PIC16(L)F722/3/4/6/7
FIGURE 1-2: PIC16F724/727/PIC16LF724/727 BLOCK DIAGRAM
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
PORTA
PORTB
PORTC
PORTD
PORTE
RA4
RA5
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RE0
RE1
RE2
8
8
AUSART
Timer0 Timer1 Timer2
RA3
RA1
RA0
8
3
RA6
RA7
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RB0
RB1
RB2
RB3
RB4
RB5
RB7
AN6
AN0 AN1 AN2 AN3 AN4 AN5 AN7
Synchronous
SDA SCL SSSDO
Serial Port
SDI/ SCK/
TX/CK RX/DT
Internal
Oscillator
Block
Configuration 13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
RAM Addr
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
PORTB
PORTC
PORTD
PORTE
RC1
8
8
AUSART
Timer0 Timer1 Timer2
8
3
Synchronous
SDA SCL SSSDO
Serial Port
SDI/ SCK/
Internal
Oscillator
Block
Configuration 13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
RAM Addr
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
Instruction
Decode and
Control
Timing
Generation
PORTB
PORTC
PORTD
PORTE
RC1
8
8
AUSART
Timer0 Timer1 Timer2
8
3
Analog-To-Digital Converter
RB6
Synchronous
SDA SCL SSSDO
Serial Port
SDI/ SCK/
Internal
Oscillator
Block
Configuration
RE3
CCP2
CCP2
CCP1
CCP1
VREF
RA2
AN9AN8 AN10 AN11 AN12 AN13
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VDD
Brown-out
Reset
VSS
T0CKI T1G T1CKI
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VDD
Brown-out
Reset
VSS
T0CKI T1CKI
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VDD
Brown-out
Reset
VSS
T0CKI T1CKI
Timer1
32 kHz
Oscillator
T1OSI
T1OSO
LDO(1)
Regulator
Note 1: PIC16F724/727 only.
Capacitive Sensing Module
CPS6CPS0 CPS1 CPS2 CPS3 CPS4 CPS7 CPS8 CPS9 CPS10 CPS11 CPS12 CPS13 CPS14 CPS15CPS5
Flash
Program
Memory RAM
PIC16(L)F722/3/4/6/7
DS40001341F-page 14 2007-2015 Microchip Technology Inc.
TABLE 1-1: PIC16(L)F722/3/4/6/7 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
RA0/AN0/SS/VCAP RA0 TTL CMO S General purpose I/O.
AN0 AN — A /D Channel 0 input.
SS ST — S lave Select input.
VCAP Power Power Filter capacitor for V oltage Regulator (PIC16F72X only).
RA1/AN1 RA1 TTL CMOS General purpose I/O.
AN1 AN — A /D Channel 1 input.
RA2/AN2 RA2 TTL CMOS General purpose I/O.
AN2 AN — A /D Channel 2 input.
RA3/AN3/VREF RA3 TTL CMOS Gener al purpose I/O.
AN3 AN — A /D Channel 3 input.
VREF AN — A/D Voltage Reference input.
RA4/CPS6/T0CKI RA4 TTL CMO S Gener al purpose I/O.
CPS6 AN — Capacitive sensing input 6.
T0CKI ST — Timer0 clock input.
RA5/AN4/CPS7/SS/VCAP RA5 T TL CMOS General purpose I/O.
AN4 AN — A /D Channel 4 input.
CPS7 AN — Capacitive sensing input 7.
SS ST — Slave Select input.
VCAP Power Power Filter capacitor for V oltage Regulator (PIC16F72X only).
RA6/OSC2/CLKOUT/VCAP RA6 TTL CMO S Gener al purpose I/O.
OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKOUT — CMOS FOSC/4 output.
VCAP Power Power Filter capacitor for V oltage Regulator (PIC16F72X only).
RA7/OSC1/CLKIN RA7 TTL CMO S Gener al purpose I/O.
OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).
CLKIN CMOS — External clock input (EC mode).
CLKIN ST — RC oscillator connection (RC mode).
RB0/AN12/CPS0/INT RB0 TTL CMOS General purpose I/O. Individually controlled inter-
rupt-on-change. Individually enabled pull-up.
AN12 AN — A/D Channel 12 input.
CPS0 AN — Capacitive sensing input 0.
INT ST — External interrupt.
RB1/AN10/CPS1 RB1 TTL CMOS General purpose I/O. Individually controlled inter-
rupt-on-change. Individually enabled pull-up.
AN10 AN — A/D Channel 10 input.
CPS1 AN — Capacitive sensing input 1.
RB2/AN8/CPS2 RB2 TTL CMOS General purpose I/O. Individually controlled inter-
rupt-on-change. Individually enabled pull-up.
AN8 AN — A /D Channel 8 input.
CPS2 AN — Capacitive sensing input 2.
RB3/AN9/CPS3/CCP2 RB3 TTL CMOS General purpose I/O. Individually controlled inter-
rupt-on-change. Individually enabled pull-up.
AN9 AN — A /D Channel 9 input.
CPS3 AN — Capacitive sensing input 3.
CCP2 ST CMOS Capture/Compare/PWM2.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTA L = Crystal levels
2007-2015 Microchip Technology Inc. DS40001341F-page 15
PIC16(L)F722/3/4/6/7
RB4/AN11/CPS4 RB4 TTL CMOS General purpose I/O. Individually controlled inter-
rupt-on-change. Individually enabled pull-up.
AN11 AN — A/D Channel 11 input.
CPS4 AN — Capacitive sensing input 4.
RB5/AN13/CPS5/T1G RB5 TTL CMOS General purpose I/O. Individually controlled inter-
rupt-on-change. Individually enabled pull-up.
AN13 AN — A/D Channel 13 input.
CPS5 AN — Capacitive sensing input 5.
T1G ST — Timer1 Gate input.
RB6/ICSPCLK/ICDCLK RB6 TTL CMOS General purpose I/O. Individually controlled inter-
rupt-on-change. Individually enabled pull-up.
ICSPCLK S T — Serial Programming Clock.
ICDCLK ST — In-Circuit Debug Clock.
RB7/ICSPDAT/ICDDAT RB7 TTL CMOS General purpose I/O. Individually controlled inter-
rupt-on-change. Individually enabled pull-up.
ICSPDAT ST CMOS ICSP™ Data I/O.
ICDDAT ST — In-Circuit Data I/O.
RC0/T1OSO/T1CKI RC0 ST CMOS General purpose I/O.
T1OSO XTAL XTAL Timer1 oscillator co nnection.
T1CKI ST — Timer1 clock input.
RC1/T1OSI/CCP2 RC1 ST CMOS General purpose I/O.
T1OSI X TAL XTAL Timer1 oscillator co nnection.
CCP2 ST CMOS Capture/Compare/PWM2.
RC2/CCP1 RC2 ST CMOS General purpose I/O.
CCP1 ST CMOS Capture/Compare/PWM1.
RC3/SCK/SCL RC3 ST CMOS General purpose I/O.
SCK ST CM O S SPI clock.
SCL I2CODI
2C clock.
RC4/SDI/SDA RC4 ST CMOS General purpose I/O.
SDI ST — SPI data input.
SDA I2CODI
2C data input/output.
RC5/SDO RC5 ST CMOS General purpose I/O .
SDO — CMOS SPI data output.
RC6/TX/CK RC6 ST CMOS General purpose I/O .
TX — CMOS USART async hronous tr ansmit.
CK ST CMOS USART synchronous clock.
RC7/RX/DT RC7 ST CMOS Gener al purpose I/O.
RX ST — USART async hronous input.
DT ST CMO S U SART synch ronous data.
RD0/CPS8 RD0 ST CMOS Gener al purpose I/O.
CPS8 AN — Capacitive sensing input 8.
RD1/CPS9 RD1 ST CMOS Gener al purpose I/O.
CPS9 AN — Capacitive sensing input 9.
RD2/CPS10 RD2 ST CMOS Gener al purpose I/O.
CPS10 AN — Capacitive sensing input 10.
TABLE 1-1: PIC16(L)F722/3/4/6/7 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTA L = Crys tal levels
PIC16(L)F722/3/4/6/7
DS40001341F-page 16 2007-2015 Microchip Technology Inc.
RD3/CPS11 RD3 ST CMOS Gener al purpose I/O.
CPS11 AN — Capacitive sensing input 11.
RD4/CPS12 RD4 ST CMOS General purpose I/O.
CPS12 AN — Capacitive sensing input 12.
RD5/CPS13 RD5 ST CMOS General purpose I/O.
CPS13 AN — Capacitive sensing input 13.
RD6/CPS14 RD6 ST CMOS General purpose I/O.
CPS14 AN — Capacitive sensing input 14.
RD7/CPS15 RD7 ST CMOS General purpose I/O.
CPS15 AN — Capacitive sensing input 15.
RE0/AN5 RE0 ST CMOS General purpose I/O.
AN5 AN — A /D Channel 5 input.
RE1/AN6 RE1 ST CMOS General purpose I/O.
AN6 AN — A /D Channel 6 input.
RE2/AN7 RE2 ST CMOS General purpose I/O.
AN7 AN — A /D Channel 7 input.
RE3/MCLR/VPP RE3 TTL — General purpose input.
MCLR ST — Master Clear with internal pull-up.
VPP HV — Program ming voltage.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.
Note: The PIC 16F722/3 /4/6/7 devi ces have an internal low dropou t volta ge regulato r . An exte rnal cap acitor mu st
be connected to one of the available VCAP pins to stabilize the regulator. For more information, see
Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16L F722/3 /4/6/7 dev ices d o not h ave t he
voltage regulator and therefore no external capacitor is required.
TA BL E 1-1: PI C16( L) F722/ 3/4/6/7 PINOUT DESCRIPTION (C ONTI NUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTA L = Crystal levels
2007-2015 Microchip Technology Inc. DS40001341F-page 17
PIC16(L)F722/3/4/6/7
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC16(L)F722/3/4/6/7 has a 13-bit program
counter capable of addressing a 2K x 14 program
memory space for the PIC16F722/LF722
(0000h-07FFh), a 4K x 14 program memory space for
the PIC16F723/LF723 and PIC16F724/LF724
(0000h-0FFFh) and an 8K x 14 program memory space
for the PIC16F726/LF726 and PIC16F727/LF727
(0000h-1FFFh). Accessing a location above the
memory boundaries for the PIC16F722/LF722 will
cause a wrap-around within the first 2K x 14 program
memory space. Accessing a location above the
memory boundaries for the PIC16F723/LF723 and
PIC16F 724 / LF 724 w i ll cause a wra p- aro und w ith in t he
first 4K x 14 program memory space. The Reset vector
is at 0000h and the interrupt vector is at 000 4h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F722/LF722
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F723/LF723 AND
PIC16F724/LF724
PC<12:0>
13
0000h
0004h
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
0005h
On-chip
Program
Memory Page 0 07FFh
Wraps to Page 0
Wraps to Page 0
Wraps to Page 0
0800h
0FFFh
1000h
17FFh
1800h
1FFFh
PC<12:0>
13
0000h
0004h
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
0005h
On-chip
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
Wraps to Page 0
Wraps to Page 1
1000h
17FFh
1800h
1FFFh
PIC16(L)F722/3/4/6/7
DS40001341F-page 18 2007-2015 Microchip Technology Inc.
FIGURE 2-3: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F726/LF726 AND
PIC16F727/LF727
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPRs)
and the Special Function Registers (SFRs). Bits RP0
and RP1 are bank select bits.
RP1 RP0
00Bank 0 is selected
01Bank 1 is selected
10Bank 2 is selected
11Bank 3 is selected
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.
2.2.1 GENERAL PUR POSE REGISTER
FILE
The register file is organized as 128 x 8 bits in the
PIC16F722/LF722, 192 x 8 bits in the PIC16F723/LF723
and PIC16F724/LF724, and 368 x 8 bits in the
PIC16F726/LF726 and PIC16F727/LF727. Each
register is accessed either directly or indirectly through
the File Select Register (FSR), (Refer to Section 2.5
“Indirect Addressing,