LM48821, LM48821TLEVAL
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SNAS354A –JUNE 2007–REVISED MAY 2013
LM48821 Direct Coupled, Ultra Low Noise, 52mW
Differential Input Stereo Headphone Amplifier with I2C Volume Control
Check for Samples: LM48821,LM48821TLEVAL
1FEATURES DESCRIPTION
With its directly-coupled output technology, the
2• Ground Referenced Outputs LM48821 is a variable gain audio power amplifier
• Differential Inputs capable of delivering 52mWRMS per channel into a
• I2C Volume and Mode Controls 16Ωsingle-ended load with less than 1% THD+N
from a 3V power supply. The I2C volume control has
• Available in Space-Saving DSBGA Package a range of –76dB to 18dB.
• Ultra Low Current Shutdown Mode The LM48821's Tru-GND technology utilizes
• Advanced Output Transient Suppression advanced charge pump technology to generate the
Circuitry Eliminates Noises During Turn-On LM48821’s negative supply voltage. This eliminates
and Turn-Off Transitions the need for output-coupling capacitors typically used
• 2.0V to 4.0V Operation (PVDD and SVDD)with single-ended loads.
• 1.8 to 4.0V Operation (I2CVDD)Boomer audio power amplifiers were designed
• No Output Coupling Capacitors, Snubber specifically to provide high quality output power with a
Networks, Bootstrap Capacitors, or Gain- minimal amount of external components. The
Setting Resistors Required LM48821 does not require output coupling capacitors
or bootstrap capacitors, and therefore, is ideally
suited for mobile phone and other low voltage
APPLICATIONS applications where minimal power consumption is a
• Notebook PCs primary requirement.
• Desktop PCs The LM48821 incorporates selectable low-power
• Mobile Phones consumption shutdown and channel select modes.
• PDAs The LM48821 contains advanced output transient
• Portable Electronic Devices suppression circuitry that eliminates noises which
would otherwise occur during turn-on and turn-off
• MP3 Players transitions.
KEY SPECIFICATIONS
• Improved PSRR at 217Hz: 82dB (typ)
• Stereo Output Power at VDD = 3V, RL = 16Ω,
THD+N = 1%: 52mW (typ)
• Mono Output Power at VDD = 3V, RL = 16Ω,
THD+N = 1%: 93mW (typ)
• Shutdown current: 0.1μA (typ)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
4
3
2
1
IN A- IN B- I2CVDD PVDD
CCP+
SDAIN B+IN A+
SGND VOBSCL PGND
CCP-
VSS
VOASVDD
A D
C
B
IN A-
IN A+
IN B+
IN B-
SCL
SDA
I2CVDD
-
+
+
-
VOB
Bias
Control
Charge
Pump
Digital
Control
System
I2C Digitally
Controlled
Analog Volume
Control
Interface
0.47 PF
0.47 PF
0.47 PF
0.47 PFSGND
PGND
CCP+
CCP- VSS
4.7 PF 4.7 PF
VDD
VOA
4.7 PF0.1 PF
SVDD
PVDD
0.1 PF
LM48821, LM48821TLEVAL
SNAS354A –JUNE 2007–REVISED MAY 2013
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Typical Application
Figure 1. Typical Audio Amplifier Application Circuit
Connection Diagram
Figure 2. DSBGA - Top View
See YZR0016 Package
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PIN DESCRIPTIONS
Pin Designator Pin Name Pin Function
A1 SVDD Signal power supply input
A2 SGND Signal ground
A3 IN A+ Left non-inverting input
A4 IN A- Left inverting input
B1 VOA Left output
B2 VOB Right output
B3 IN B+ Right non-inverting input
B4 IN B- Right inverting input
C1 VSS DC to DC converter output
C2 SCL I2C serial clock input
C3 SDA I2C serial data input
C4 I2CVDD I2C supply voltage input
D1 CCP- DC to DC converter flying capacitor inverting input
D2 PGND Power ground
D3 CCP+ DC to DC converter flying capacitor non-inverting input
D4 PVDD DC to DC converter power supply input
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)(3)
Supply Voltage 4.5V
Storage Temperature −65°C to +150°C
Input Voltage −0.3V to VDD +0.3V
Power Dissipation (4) Internally Limited
ESD Susceptibility (5) 2000V
ESD Susceptibility (6) 200V
Junction Temperature 150°C
Thermal Resistance
θJA (typ) - (DSBGA) (4) 105°C/W
(1) All voltages are measured with respect to the GND pin unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not specify performance limits. Electrical Characteristics state DC and AC electrical specifications
under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings.
Specifications are for parameters where no limit is given, however, the typical value is a good indication of device performance.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM48821, see power derating currents for more information.
(5) Human body model, 100pF discharged through a 1.5kΩresistor.
(6) Machine Model, 220pF - 240pF discharged through all pins.
Operating Ratings
Temperature Range
TMIN ≤TA≤TMAX −40°C ≤TA≤+85°C
Supply Voltage
PVDD and SVDD 2.0V ≤VDD ≤4.0V
I2CVDD 1.8V ≤I2CVDD ≤4.0V
Audio Amplifier Electrical Characteristics VDD = 3V (1)
The following specifications apply for VDD = 3V, RL= 16Ω, AV= 0dB, unless otherwise specified. Limits apply for TA= 25°C.
LM48821 Units
Symbol Parameter Conditions Typical (2) Limits (Limits)
(3) (4)
VIN = 0V, inputs terminated, 3.0 4.5 mA (max)
both channels enabled
IDD Quiescent Power Supply Current VIN = 0V, inputs terminated, 2.0 3.0 mA
one channel enabled
ISD Shutdown Current Right and Left Enable bits set to 0 0.1 1.2 µA (max)
VOS Output Offset Voltage RL= 32Ω0.5 2.5 mV (max)
[B0:B4] = 00000 –76 dB
AVVolume Control Range [B0:B4] = 11111 +18 dB
ΔAVChannel-to-Channel Gain Match ±0.015 dB
AV-MUTE Mute Gain –76 dB
5 kΩ(min)
Gain = 18dB 9 15 kΩ(max)
RIN Input Resistance Gain = –76dB 81 kΩ
(1) All voltages are measured with respect to the GND pin unless otherwise specified.
(2) Typicals are measured at +25°C and represent the parametric norm.
(3) Limits are specified to AOQL (Average Outgoing Quality Level).
(4) Data sheet min and /max specification limits are specified by design, test, or statistical analysis.
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Audio Amplifier Electrical Characteristics VDD = 3V (1) (continued)
The following specifications apply for VDD = 3V, RL= 16Ω, AV= 0dB, unless otherwise specified. Limits apply for TA= 25°C.
LM48821 Units
Symbol Parameter Conditions Typical (2) Limits (Limits)
(3) (4)
THD+N = 1% (max); fIN = 1kHz, 52 43 mW (min)
RL= 16Ω, per channel
THD+N = 1% (max); fIN = 1kHz, 53 45 mW (min)
RL= 32Ω, per channel
POUT Output Power THD+N = 1% (max); fIN = 1kHz, 93 80 mW (min)
RL= 16Ω, single channel driven
THD+N = 1% (max); fIN = 1kHz, 79 mW
RL= 32Ω, single channel driven
POUT = 50mW, f = 1kHz 0.022 %
RL= 16Ω, single channel
Total Harmonic Distortion +
THD+N Noise POUT = 50mW, f = 1kHz 0.011 %
RL= 32Ω, single channel
VRIPPLE = 200mVP-P, input referred
f = 217Hz 82 65 dB (min)
PSRR Power Supply Rejection Ratio f = 1kHz 80 dB
f = 20kHz 55 dB
VRIPPLE = 200mVp-p, Input referred
CMRR Common Mode Rejection Ratio 65 dB
f = 2kHz
RL= 32Ω, POUT = 20mW,
SNR Signal-to-Noise-Ratio 100 dB
f = 1kHz, BW = 20Hz to 22kHz
TWU Charge Pump Wake-Up Time 400 μs
RL= 16Ω, POUT = 1.6mW,
XTALK Crosstalk 82 dB
f = 1kHz, A-weighted filter
ZOUT Output Impedance Right and Left Enable bits set to 0 41 kΩ
Control Interface Electrical Characteristics (1)
The following specifications apply for 1.8V ≤I2CVDD ≤4.0V, unless otherwise specified. Limits apply for TA= 25°C. See
Figure 56.LM48821 Units
Symbol Parameter Conditions (Limits)
Typical (2) Limits (3) (4)
t1SCL period 2.5 μs (min)
t2SDA Setup Time 100 ns (min)
t3SDA Stable Time 0 ns (min)
t4Start Condition Time 100 ns (min)
t5Stop Condition Time 100 ns (min)
VIH Logic High Input Threshold 0.7 x I2CVDD V (min)
VIL Logic Low Input Threshold 0.3 x I2CVDD V (max)
(1) All voltages are measured with respect to the GND pin unless otherwise specified.
(2) Typicals are measured at +25°C and represent the parametric norm.
(3) Limits are specified to AOQL (Average Outgoing Quality Level).
(4) Data sheet min and /max specification limits are specified by design, test, or statistical analysis.
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0.001
1
0.01
0.1
THD+N (%)
20 20k100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k100 200 1k 2k 10k
FREQUENCY (Hz)
LM48821, LM48821TLEVAL
SNAS354A –JUNE 2007–REVISED MAY 2013
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Typical Performance Characteristics
THD+N vs Frequency THD+N vs Frequency
VDD = 2V, PO= 6mW, VDD = 2V, PO= 10mW,
RL= 16Ω, Stereo RL= 32Ω, Stereo
Figure 3. Figure 4.
THD+N vs Frequency THD+N vs Frequency
VDD = 2V, PO= 16mW, VDD = 2V, PO= 16mW,
RL= 16Ω, Mono Left RL= 16Ω, Mono Right
Figure 5. Figure 6.
THD+N vs Frequency THD+N vs Frequency
VDD = 2V, PO= 18mW, VDD = 2V, PO= 18mW,
RL= 32Ω, Mono Left RL= 32Ω, Mono Right
Figure 7. Figure 8.
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0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k100 200 1k 2k 10k
FREQUENCY (Hz)
LM48821, LM48821TLEVAL
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SNAS354A –JUNE 2007–REVISED MAY 2013
Typical Performance Characteristics (continued)
THD+N vs Frequency THD+N vs Frequency
VDD = 3V, PO= 35mW, VDD = 4V, PO= 50mW,
RL= 16Ω, Stereo RL= 16Ω, Stereo
Figure 9. Figure 10.
THD+N vs Frequency THD+N vs Frequency
VDD = 3V, PO= 70mW, VDD = 3V, PO= 70mW,
RL= 16Ω, Mono Left RL= 16Ω, Mono Right
Figure 11. Figure 12.
THD+N vs Frequency THD+N vs Frequency
VDD = 4V, PO= 160mW, VDD = 4V, PO= 160mW,
RL= 16Ω, Mono Left RL= 16Ω, Mono Right
Figure 13. Figure 14.
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0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k100 200 1k 2k 10k
FREQUENCY (Hz)
0.001
1
0.01
0.1
THD+N (%)
20 20k
100 200 1k 2k 10k
FREQUENCY (Hz)
LM48821, LM48821TLEVAL
SNAS354A –JUNE 2007–REVISED MAY 2013
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Typical Performance Characteristics (continued)
THD+N vs Frequency THD+N vs Frequency
VDD = 3V, PO= 40mW, VDD = 3V, PO= 60mW,
RL= 32Ω, Stereo RL= 32Ω, Mono Left
Figure 15. Figure 16.
THD+N vs Frequency THD+N vs Frequency
VDD = 3V, PO= 60mW, VDD = 4V, PO= 90mW,
RL= 32Ω, Mono Right RL= 32Ω, Stereo
Figure 17. Figure 18.
THD+N vs Frequency THD+N vs Frequency
VDD = 4V, PO= 120mW, VDD = 4V, PO= 120mW,
RL= 32Ω, Mono Left RL= 32Ω, Mono Right
Figure 19. Figure 20.
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0.01 1
OUTPUT POWER (mW)
0.001
0.01
0.1
1
THD + N (%)
0.005
0.05
0.5
0.1 10 100 500
0.01 1
OUTPUT POWER (mW)
0.001
0.01
0.1
1
THD + N (%)
0.005
0.05
0.5
0.1 10 100 500
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SNAS354A –JUNE 2007–REVISED MAY 2013
Typical Performance Characteristics (continued)
THD+N vs Output Power THD+N vs Output Power
VDD = 2V, RL= 16Ω, VDD = 2V, RL= 16Ω,
f = 1kHz, Mono Left f = 1kHz, Mono Right
Figure 21. Figure 22.
THD+N vs Output Power THD+N vs Output Power
VDD = 2V, RL= 16Ω, VDD = 3V, RL= 16Ω,
f = 1kHz, Stereo f = 1kHz, Mono Left
Figure 23. Figure 24.
THD+N vs Output Power THD+N vs Output Power
VDD = 3V, RL= 16Ω, VDD = 3V, RL= 16Ω,
f = 1kHz, Mono Right f = 1kHz, Stereo
Figure 25. Figure 26.
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0.01 1
OUTPUT POWER (mW)
0.001
0.01
0.1
1
THD + N (%)
0.005
0.05
0.5
0.1 10 100 500
0.01 1
OUTPUT POWER (mW)
0.001
0.01
0.1
1
THD + N (%)
0.005
0.05
0.5
0.1 10 100 500
LM48821, LM48821TLEVAL
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Typical Performance Characteristics (continued)
THD+N vs Output Power THD+N vs Output Power
VDD = 4V, RL= 16Ω, VDD = 4V, RL= 16Ω,
f = 1kHz, Mono Left f = 1kHz, Mono Right
Figure 27. Figure 28.
THD+N vs Output Power THD+N vs Output Power
VDD = 4V, RL= 16Ω, VDD = 2V, RL= 32Ω,
f = 1kHz, Stereo f = 1kHz, Mono Left
Figure 29. Figure 30.
THD+N vs Output Power THD+N vs Output Power
VDD = 2V, RL= 32Ω, VDD = 2V, RL= 32Ω,
f = 1kHz, Mono Right f = 1kHz, Stereo
Figure 31. Figure 32.
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0.01 1
OUTPUT POWER (mW)
0.001
0.01
0.1
1
THD + N (%)
0.005
0.05
0.5
0.1 10 100 500
0.01 1
OUTPUT POWER (mW)
0.001
0.01
0.1
1
THD + N (%)
0.005
0.05
0.5
0.1 10 100 500
LM48821, LM48821TLEVAL
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SNAS354A –JUNE 2007–REVISED MAY 2013
Typical Performance Characteristics (continued)
THD+N vs Output Power THD+N vs Output Power
VDD = 3V, RL= 32Ω, VDD = 3V, RL= 32Ω,
f = 1kHz, Mono Left f = 1kHz, Mono Right
Figure 33. Figure 34.
THD+N vs Output Power THD+N vs Output Power
VDD = 3V, RL= 32Ω, VDD = 4V, RL= 32Ω,
f = 1kHz, Stereo f = 1kHz, Mono Left
Figure 35. Figure 36.
THD+N vs Output Power THD+N vs Output Power
VDD = 4V, RL= 32Ω, VDD = 4V, RL= 32Ω,
f = 1kHz, Mono Right f = 1kHz, Stereo
Figure 37. Figure 38.
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+0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 200 1k 2k 10k
PSRR (dB)
FREQUENCY (Hz)
+0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 200 1k 2k 10k
PSRR (dB)
FREQUENCY (Hz)
+0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 200 1k 2k 10k
PSRR (dB)
FREQUENCY (Hz)
+0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 200 1k 2k 10k
PSRR (dB)
FREQUENCY (Hz)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
CMRR (dB)
20 20k100 200 1k 2k 10k
FREQUENCY (Hz)
+0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 200 1k 2k 10k
PSRR (dB)
FREQUENCY (Hz)
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Typical Performance Characteristics (continued)
CMRR vs Frequency PSRR vs Frequency
VDD = 3V, RL= 16ΩVDD = 2V, RL= 16Ω
Figure 39. Figure 40.
PSRR vs Frequency PSRR vs Frequency
VDD = 2V, RL= 32ΩVDD = 3V, RL= 16Ω
Figure 41. Figure 42.
PSRR vs Frequency PSRR vs Frequency
VDD = 3V, RL= 32ΩVDD = 4V, RL= 16Ω
Figure 43. Figure 44.
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0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35
MONOPHONIC OUTPUT POWER (W)
AMPLLIFIER DISSIPATION (W)
THD=1% THD=10%
VDD=4V
VDD=3V
VDD=2V
0
50
100
150
200
250
300
1.5 2 2.5 3 3.5 4 4.5
POWER SUPPLY VOLTAGE (V)
MONO OUTPUT POWER (W)
THD=1%
THD=10%
0
50
100
150
200
250
300
1.5 2 2.5 3 3.5 4 4.5
POWER SUPPLY VOLTAGE (V)
STEREO OUTPUT POWER (W)
THD=1%
THD=10%
0
50
100
150
200
250
300
1.5 2 2.5 3 3.5 4 4.5
POWER SUPPLY VOLTAGE (V)
MONO OUTPUT POWER (W)
THD=1%
THD=10%
+0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 200 1k 2k 10k
PSRR (dB)
FREQUENCY (Hz)
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Typical Performance Characteristics (continued)
PSRR vs Frequency Output Power vs Voltage Supply
VDD = 4V, RL= 32ΩRL= 16Ω, Mono
Figure 45. Figure 46.
Output Power vs Voltage Supply Output Power vs Voltage Supply
RL= 32Ω, Mono RL= 16Ω, Stereo
Figure 47. Figure 48.
Output Power vs Voltage Supply Output Power vs Power Dissipation
RL= 32Ω, Stereo VDD = 2V, 3V, 4V, RL= 16Ω, Mono
Figure 49. Figure 50.
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0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5
POWER SUPPLY VOLTAGE (V)
POWER SUPPLY CURRENT (mA)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5
POWER SUPPLY VOLTAGE (V)
POWER SUPPLY CURRENT (mA)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35
TOTAL STEREO OUTPUT POWER (W)
AMPLLIFIER DISSIPATION (W)
THD=10%
THD=1%
VDD=4V
VDD=3V
VDD=2V
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35
MONOPHONIC OUTPUT POWER (W)
AMPLLIFIER DISSIPATION (W)
VDD=2V
VDD=4V
VDD=3V
THD=10%
THD=1%
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35
TOTAL STEREO OUTPUT POWER (W)
AMPLLIFIER DISSIPATION (W)
THD=10%
THD=1% VDD=4V
VDD=3V
VDD=2V
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Typical Performance Characteristics (continued)
Output Power vs Power Dissipation Output Power vs Power Dissipation
VDD = 2V, 3V, 4V, RL= 32Ω, Mono VDD = 2V, 3V, 4V, RL= 16Ω, Stereo
Figure 51. Figure 52.
Output Power vs Power Dissipation Supply Current vs Supply Voltage
VDD = 2V, 3V, 4V, RL= 32Ω, Stereo Mono
Figure 53. Figure 54.
Supply Current vs Supply Voltage
Stereo
Figure 55.
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APPLICATION INFORMATION
Figure 56. I2C Timing Diagram
Figure 57. I2C Bus Format
Table 1. Chip Address
D7 D6 D5 D4 D3 D2 D1 D0
Chip Address 1 1 1 0 1 1 0 0
Table 2. Control Registers
D7 D6 D5 D4 D3 D2 D1 D0
LF RT
Volume Control VD4 VD3 VD2 VD1 VD0 MUTE ENABLE ENABLE
I2C VOLUME CONTROL
The LM48821 can be configured in 32 different gain steps by forcing I2C volume control bits to a desired gain
according to Table 3.
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Table 3. Volume Control
VD4 VD3 VD2 VD1 VD0 Gain (dB)
0 0 0 0 0 –76
0 0 0 0 1 –62
0 0 0 1 0 –52
0 0 0 1 1 –44
0 0 1 0 0 –38
0 0 1 0 1 –34
0 0 1 1 0 –30
0 0 1 1 1 –27
0 1 0 0 0 –24
0 1 0 0 1 –21
0 1 0 1 0 –18
0 1 0 1 1 –16
0 1 1 0 0 –14
0 1 1 0 1 –12
0 1 1 1 0 –10
01111–8
10000–6
10001–4
10010–2
100110
101002
101014
101106
101118
1100010
1100112
1101013
1101114
1110015
1110116
1111017
1111118
I2C COMPATIBLE INTERFACE
The LM48821 uses a serial data bus that conforms to the I2C protocol. Controlling the chip’s functions is
accomplished with two wires: serial clock (SCL) and serial data (SDA). The clock line is uni-directional. The data
line is bi-directional (open-collector). The maximum clock frequency specified by the I2C standard is 400kHz. In
this discussion, the master is the controlling microcontroller and the slave is the LM48821.
The bus format for the I2C interface is shown in Figure 57. The bus format diagram is broken up into six major
sections: The Start Signal, the I2C Address, an Acknowledge bit, the I2C data, second Acknowledge bit, and the
Stop Signal.
The start signal is generated by lowering the data signal while the clock signal is high. The start signal will alert
all devices attached to the I2C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is high.
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After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM48821 has received the address correctly, then it
holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse,
then the master should abort the rest of the data transfer to the LM48821. The 8 bits of data are sent next, most
significant bit first. Each data bit should be valid while the clock level is stable high.
After the data byte is sent, the master must check for another acknowledge to see if the LM48821 received the
data.
If the master has more data bytes to send to the LM48821, then the master can repeat the previous two steps
until all data bytes have been sent.
The stop signal ends the transfer. To signal stop , the data signal goes high while the clock signal is high. The
data line should be held high when not in use.
The LM48821's I2C address is shown in Table 1. The I2C data register and its control bit names are shown in
Table 2. The data values for the volume control are shown in Table 3.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM48821’s I2C interface is powered up through the I2CVDD pin. The LM48821’s I2C interface operates at a
voltage level set by the I2CVDD pin. This voltage can be independent from the main power supply pin (VDD). This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 3.3V voltage regulator typically use a 10μF in parallel with a 0.1μF filter
capacitors to stabilize the regulator’s output, reduce noise on the regulated supply lines, and improve the
regulator’s transient response. However, their presence does not eliminate the need for a local 1.0μF tantalum
bypass capacitance connected between the LM48821’s supply pins and ground. Keep the length of leads and
traces that connect capacitors between the LM48821’s power supply pins and ground as short as possible.
ELIMINATING THE OUTPUT COUPLING CAPACITOR
The LM48821 features a low noise inverting charge pump that generates an internal negative supply voltage.
This allows the LM48821 to reference its amplifier outputs to ground instead of a half-supply voltage, like
traditional capacitivel-coupled headphone amplifiers. Because there is no DC bias voltage associated with either
stereo output, the large DC blocking capacitors (typically 220μF) are not necessary. The coupling capacitors are
replaced by two, small ceramic charge pump capacitors, saving board space and cost.
Eliminating the output coupling capacitors also improves low frequency response. In traditional headphone
amplifiers, the headphone impedance and the output capacitor form a high pass filter that not only blocks the DC
component of the output, but also attenuates low frequencies, impacting the bass response. Because the
LM48821 does not require the output coupling capacitors, the low frequency response of the device is not
degraded.
In addition to eliminating the output coupling capacitors, the ground referenced output nearly doubles the output
voltage swing and available dynamic range of the LM48821 when compared to a traditional capacitively-coupled
output headphone amplifier operating from the same supply voltage.
OUTPUT TRANSIENT ELIMINATED
The LM48821 contains advanced circuitry that virtually eliminates output transients (’clicks' and 'pops’). This
circuitry attenuates output transients when the supply voltage is first applied or when the part resumes operation
after using the shutdown mode.
POWER DISSIPATION
Power dissipation is a major concern when using any power amplifier and must be thoroughly understood to
ensure a successful design. Equation 1 states the maximum power dissipation point for a single-ended amplifier
operating at a given supply voltage and driving a specified output load.
PDMAX = (2VDD)2/ (2π2RL) (1)
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Since the LM48821 has two power amplifiers in one package, the maximum internal power dissipation point is
twice that of the number which results from Equation 1. Even with large internal power dissipation, the LM48821
does not require heat sinking over a large range of ambient temperatures. The maximum power dissipation point
obtained must not be greater than the power dissipation that results from Equation 2:
PDMAX = (TJMAX - TA) / (θJA) (2)
For the DSBGA package, θJA = 105°C/W. TJMAX = 150°C for the LM48821. Depending on the ambient
temperature, TA, of the system surroundings, Equation 2 can be used to find the maximum internal power
dissipation supported by the IC packaging. If the result of Equation 1 is greater than that of Equation 2, then
either the supply voltage must be decreased, the load impedance increased or TAreduced. Power dissipation is
a function of output power and thus, if typical operation is not around the maximum power dissipation point, the
ambient temperature may be increased accordingly.
SELECTING EXTERNAL COMPONENTS
Optimizing the LM48821’s performance requires properly selecting external components. Though the LM48821
operates well when using external components with wide tolerances, best performance is achieved by optimizing
component values.
Charge Pump Capacitor Selection
Use low ESR (equivalent series resistance) (<100mΩ) ceramic capacitors with an X7R dielectric for best
performance. Low ESR capacitors keep the charge pump output impedance to a minimum, extending the
headroom on the negative supply. Higher ESR capacitors result in reduced output power from the audio
amplifiers.
Charge pump load regulation and output impedance are affected by the value of the flying capacitor (connected
between the CCP-and CCP+ pins). A larger valued C1(up to 4.7μF) improves load regulation and minimizes charge
pump output resistance. Beyond 4.7μF, the switchon-resistance dominates the output impedance.
The output ripple is affected by the value and ESR of the output capacitor (connected between the VSS and
PGND pins). Larger capacitors reduce output ripple on the negative power supply. Lower ESR capacitors
minimize the output ripple and reduce the output impedance of the charge pump.
The LM48821 charge pump design is optimized for 4.7μF, low ESR, ceramic, flying, and output capacitors.
Power Supply Bypass Capacitor
For good THD+N and low noise performance and to ensure correct power-on behavior at the maximum allowed
power supply voltage, a local 4.7μF power supply bypass capacitor should be connected as physically closed as
possible to the PVDD pin.
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value input coupling capacitors (the 0.47μF capacitors in
Figure 1). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In
many cases, however, the speakers used in portable systems, whether internal or external, have little ability to
reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little
improvement by using high value input and output capacitors.
Besides affecting system cost and size, the input coupling capacitor value has an effect on the LM48821’s click
and pop performance. The magnitude of the pop is directly proportional to the input capacitor’s size. Thus, pops
can be minimized by selecting an input capacitor value that is no higher than necessary to meet the desired -3dB
frequency.
The LM48821's nominal input resistance at full volume is 10kΩand a minimum of 5kΩ. This input resistance and
the input coupling capacitor value produce a -3dB high pass filter cutoff frequency that is found using Equation 3.
f-3dB = 1/2πRiCi(3)
REVISION HISTORY
Rev Date Description
1.0 06/06/07 Initial release.
A 05/02/2013 Changed layout of National Data Sheet to TI format.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM48821TL/NOPB ACTIVE DSBGA YZR 16 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 G16
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM48821TL/NOPB DSBGA YZR 16 250 178.0 8.4 2.08 2.08 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM48821TL/NOPB DSBGA YZR 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 2
MECHANICAL DATA
YZR0016xxx
www.ti.com
TLA16XXX (Rev C)
0.600±0.075 D
E
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
4215051/A 12/12
D: Max =
E: Max =
1.99 mm, Min =
1.99 mm, Min =
1.93 mm
1.93 mm
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