DSPIC33FJ64GS610-I/PT - Microchip Technology

dsPIC33FJ32GS406/606/608/610 and

dsPIC33FJ64GS406/606/608/610

The dsPIC33FJ32GS406/606/608/610 and

dsPIC33FJ64GS406/606/608/610 family devices that

you have received conform functionally to the current

Device Data Sheet (DS70591C), except for the

anomalies described in this d ocument.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errat a described in this document will be addressed

in future revisions of the dsPIC33FJ32GS406/606/608/

610 and dsPIC33FJ64GS406/606/608/610 sil icon.

Data Sheet clarifications and corrections start on page 9,

following the discussion of silicon issue s.

The silicon revision level can be identified using the

current version of MPLAB® IDE and Microchip’s

programmers, debuggers and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 3 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 3 programmer/

debugger or PICkit 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Sel ect Tool).

4. Perform a “Connect” operation to the device

(Debugger>Connect). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window .

The DEVREV values for the various

dsPIC33FJ32GS406/606/608/610 and

dsPIC33FJ64GS406/606/608/610 silicon revisions are

shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A1).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID(1) Revision ID for Silicon Revision(2)

A0 A1

dsPIC33FJ32GS406 0x4000

0x3000 0x3001

dsPIC33FJ32GS606 0x4002

dsPIC33FJ32GS608 0x4004

dsPIC33FJ32GS610 0x4006

dsPIC33FJ64GS406 0x4001

dsPIC33FJ64GS606 0x4003

dsPIC33FJ64GS608 0x4005

dsPIC33FJ64GS610 0x4007

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration

memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.

2: Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for detailed information on

Device and Revision IDs for your specific device.

dsPIC33FJ32GS406/606/608/610 and

dsPIC33FJ64GS406/606/608/610

Family Silicon Errata and Data Sheet Clarification

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

TABLE 2: SILICON ISSUE SUMMARY

Module Feature Item

Number Issue Summary Affected Revisions(1)

A0 A1

ECAN WAKIF bit 1. The WAKIF bit in the CiINTF register cannot be

cleared by software instruction after the device is

interrupted from Sleep due to activity on the CAN

bus.

Reserved — 2. — — —

SPI ASS1 Pin 3. The ASS1 pin function does not work. X X

JTAG Boun dary Scan 4. The boundary scan cells for the RD3 and RD13 pins

are swapped. XX

PWM Secondary

Master Time

Base

Synchronization

5. The external time base synchronization output pin,

SYNCO2, does not work. XX

Interrupts Exit from Doze

Mode on

Interrupt

6. An interrupt w it h a priority level lo we r th an the CPU

priority level will trigger the dsPIC® DSC device to

exit the Doze mode, but an interrupt request will not

be generated.

ADC Current

Consumption in

Sleep Mode

7. If the ADC module is in an enabled state when the

device enters Sleep mode, the power-down current

(IPD) of the device may exceed the device data

sheet specifications.

PWM External Period

Reset Mode

(XPRES)

8. When using the External Period Reset mode, PWM

period will get reset immediately if the Reset signal

is active at the end of the PWM ON time.

PWM PWM Module

Enable 9. A glitch may be observed on the PWM pins when

the PWM module is enabled after assignment of pin

ownership to the PWM module.

ECAN Error Interrupt

Flag 10. The ERRIF status bit does not get set when a CAN

error condition occurs. XX

SPI Framed Master

Mode 11. When the SPI module is configured in Framed Mas-

ter mode and the Frame Sync Pulse Edge Select bit

(FRMDLY) is set to ‘1’, transmitting a word and then

buffering another word in the SPIxBUF register

before the transmission has completed, results in an

incomplete transmission of the first data word.

I2CSlave Mode 12. When operating the I2C™ module in Slave mode,

intermittent address and data receive errors may be

detected.

PWM SWAP 13. When the PWM SW AP feature is enabled, the user-

defined dead time is ignored during the Fault or

current-li mi t co nd i tion.

PWM External Period

Reset Mode

(XPRES)

14. When using the External Period Reset in True Inde-

pendent Output mode, the external reset signal only

resets the PWMxH signal.

CPU div.sd

Instruction 15. When using the div.sd instruction, the overflo w bit

is not getting set when an overflow occurs. XX

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

CPU Interrupt

Disable 16. When a previo us DISI instruction is active (i.e., the

DISICNT register is non-zero), and the value of the

DISICNT register is updated manually , the DISICNT

UART TX Interrupt 17. A transmit (TX) Interrupt may oc cur before the data

transmission is complete. XX

PWM Edge-Aligned

Complimentary

Mode

18. When operating in Edge-Aligned Complimentary

mode, the dead time could become 0. XX

PWM —19. In Master time base mode, writing to the period

module will cause the updat e of the other timing

parameter to take ef fect one PWM cycle after the

period update is effective.

TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)

Module Feature Item

Number Issue Summary Affected Revisions(1)

A0 A1

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

Silicon Errata Issues

1. Module: ECAN

The WAKIF bit in the CiINTF register cannot be

cleared by software instruction after the device is

interrupted from Sleep due to acti vity on the CAN

bus.

When the device wakes up from Sleep due to CAN

bus activity, the ECAN module is placed in

operational mode. The ECAN event interrupt

occurs due to the WAKIF flag. Trying to clear the

flag in the Interrupt Service Routine (ISR) may not

be sufficient. The WAKIF bit being set will not

cause repetitive Interrupt Service Routine

execution.

Work around

Although the WAKIF bit does not clear, the de vice

Sleep and ECAN Wake function continue to work

as expected. If the ECAN event is enabled, the

CPU will enter the Interrupt Service Routine due to

the WAKIF flag getting set. The application can

maintain a secondary flag, which tracks the dev ice

Sleep and Wake events.

Affected Silicon Revisions

2. Module: Reserved

The issue in the previous version of the document

has been removed.

3. Module: SPI

The ASS1 pin is provided as an alternative pin for

the slave select function of the SPI1 module.

However, the alternate slave select function

(ASS1) on this pin does not work. All other

functions multiplexed on the same pin work as

expected.

Work around

Use the SS1 pin for the slave select func ti on .

Affected Silicon Revisions

4. Module: JTAG

The boundary scan cells for the RD3 and RD13

pins are swapped. When running the boundary

scan test, an input to the RD3 pin excites the RD13

pin, and vice versa.

This erratum does not affect any other functionality

on the RD3 and RD13 pins.

Work aro und

None.

Affected Silicon Revisions

5. Module: PWM

The SYNCO2 pin can be used to transmit

synchronization pulses to generate an identical

PWM time base on another device. Ho wever, the

SYNCO2 function does not work as expected. As

a result of this erratum, the secondary master time

base cannot be used for synchronizing a slave

device.

All other functions multiplexed on the same pin

work as expected.

Work aro und

A spare PWMxL/PWMxH pin can be used as the

synchronization source output instead of the

SYNCO2 pin using the following procedure:

1. Configure the spare PWMxL/PWMxH pin to

operate on the same time base, period, and

phase as the synchronizing (or reference) PWM

channel.

2. Set up the duty cycle for the spare PWMxL/

PWMxH pin to the desired pulse width for the

synchronization signal (typically 100 ns at the

highest PWM resolution).

3. Connect the spare PWMxL/PWMxH pin to the

synchronization input of the slave PWM

generator.

Affected Silicon Revisions

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. The shaded

column in the “Affected Silicon Revisions”

table included in each issue indicates that

the issue applies to the most current

revision of silicon (A1).

A0 A1

X X

A0 A1

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

6. Module: Interrupts

When the dsPIC® DSC device is operating in Doze

mode, any interrupt should trigger the device to

exit Doze mode and generate an interrupt request

(IRQ) regardless of the interrupt priority level.

However, if the interrupt priority level is lower than

the CPU priority level, the interrupt request will not

be generated. As a result, the CPU will not detect

that it has exited Doze mode.

Work around

Any interrupt that is expected to wake the CPU

from Doze mode must be configured for an

interrupt priority level higher than the CPU priority

level. This work around can be implemented in

software right before the device enters Doze mode

and reverted to the desired priority level after it

wakes up from Doze mode.

Affected Silicon Revisions

7. Module: ADC

If the ADC module is in an enabled state when the

device enters Sleep mode as a result of executing

a PWRSAV #0 instruction, the devi ce power-do wn

current (IPD) may exceed the specifications listed

in the device da ta sheet. This may ha ppen even if

the ADC module is disabled by clearing the ADON

bit prior to entering Sleep mode.

Work around

In order to remain within the IPD specifications

listed in the device data sheet, the user software

must completely disable the ADC module by

setting the ADC Module Disable bit in the

corresponding Peripheral Modul e Disable register

(PMDx), prior to executing a PWRSAV #0

instruction.

Affected Silicon Revisions

8. Module: PWM

The External Period Reset mode is used to reset

the PWM period when the se lected reset si gnal is

asserted during the OFF time of the PWM. If the

reset signal remains active during and after the

PWM ON time, the reset signal must be ignored.

However , the reset signal is not ignored at the end

of the PWM ON time. Therefore, the PWM period

will be reset immediately after the end of the PWM

ON time.

Work arou nd

Ensure that the External Period Reset signal is

asserted during the PWM OFF time and

deasserted before the end of the PWM ON time.

Affected Silicon Revisions

A0 A1

X X

A0 A1

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

9. Module: PWM

The PENH and PENL bi ts in the IOCONx register

are used to assign ownership of the pins to either

the PWM module or the GPIO module. The correct

procedure to configure the PWM module is to

assign pin ownership to the PWM module and then

enabling it using the PTEN bit in the PTCON

If the PWM module is enabled using the above

sequence, then a glitch may be observed on the

PWM pins before actual switching of the PWM

outputs begins. This gli tch may cause momentary

turn ON of power MOSFETs that are driven by the

PWM pins and may cause damage to the

application hardware.

Work around

Follow the given sequence to avoid any glitches

from appearing on the PWM outputs at the time of

enabling.

1. Configure the respective PWM pins to digital

inputs using the TRISx regi sters. This step will

put the PWM pins in a high-impedance state.

The PWM outputs must be maint ained in a saf e

state by using pull-up or pull-down resistors.

2. Assign pin ownership to the GPIO module by

configuring the PENH bit (IOCONx<15>) = 0

and the PENL bit (IOCONx<14>) = 0.

3. Specify the PWM override state to the desired

safe state for the PWM pins using the

OVRDAT<1:0> bit-field in the IOCONx register .

4. Override the PWM outputs by setting the

OVRENH bit (IOCONx<9>) = 1 and the

OVRENL bit (IOCONx<8>) = 1.

5. Enable the PWM module by setting the PTEN

bit (PTCON<15>) = 1.

6. Remove the PWM Overrides by making the OVR-

ENH bit (IOCONx<9>) = 0 and the OVRENL bit

(IOCONx<8>) = 0.

7. Assign pin ownership to the PWM module by

setting the PENH bit (IOCONx<15>) = 1 and

the PENL bit (IOCONx<14>) = 1.

The code in Example 1 il lustrates the use of this work

around.

EXAMPLE 1: CONFIGURE PWM MODULE TO PREVENT GLITCHES ON PWM1H AND PWM1L

PINS AT THE TIME OF ENABLING

Affected Silicon Revisions

TRISAbits.TRISA4 = 1; // Configure PWM1H/RA4 as digital input

// Ensure output is in safe state using pull-up or

// pull-down resistors

TRISAbits.TRISA3 = 1; // Configure PWM1L/RA3 as digital input

// Ensure output is in safe state using pull-up or

// pull-down resistors

IOCON1bits.PENH = 0; // Assign pin ownership of PWM1H/RA4 to GPIO module

IOCON1bits.PENL = 0; // Assign pin ownership of PWM1L/RA3 to GPIO module

IOCON1bits.OVRDAT = 0; // Configure override state of the PWM outputs to

// desired safe state.

IOCON1bits.OVRENH = 1; // Override PWM1H output

IOCON1bits.OVRENL = 1; // Override PWM1L output

PTCONbits.PTEN = 1; // Enable PWM module

IOCON1bits.OVRENH = 0; // Remove override for PWM1H output

IOCON1bits.OVRENL = 0; // Remove override for PWM1L output

IOCON1bits.PENH = 1; // Assign pin ownership of PWM1H/RA4 to PWM module

IOCON1bits.PENL = 1; // Assign pin ownership of PWM1L/RA3 to PWM module

A0 A1

X X

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

10. Module: ECAN

The ERRIF status flag (CiINTF<5>) does not get

set when a CAN error condition occurs. However,

the correspon ding CiIF in terrupt fl ag will get se t on

a CAN error condition, and an interrupt will be

correctly generated if enabled.

Work around

Do not inspect the state of the ERRIF bit to

determine if a CAN error interrupt has occurred.

Instead, inspect the individual error condition

status flags TXBO, TXBP, RXBP, TXWAR,

RXWA R and EWARN (CiINTF<13:8>).

Affected Silicon Revisions

11. Module: SPI

When the SPI module is configured in Framed

Master mode and the Frame Sync Pulse Edge

Select bit (FRMDLY) is set to ‘1’, transmitting a

word and then buffering another word in the

SPIxBUF register before the transmission has

completed, results in an incomplete transmission

of the first data word. Only the first 15 bits from the

first data word are transmitted, followed by the

sync pulse and the complete second word.

Work around

Between the two back-to-back SPI operations,

add a delay to ensure that the first word is fully

transmitted before the second word is written to

the SPIxBUF register, as shown in Example 2.

EXAMPLE 2:

Affected Silicon Revisions

12. Module: I2C

When operati ng the I2C™ module in Slave mode,

intermittent address and data receive errors may

be detected.

For example, any one of the 8 bits received in the

transaction may be received incorrectly. As a

result of this erroneous reception, the slave device

may send an incorrect Acknowledge/Not-

Acknowledge, or the data may be received

incorrectly.

On devices that exhibit this issue, the rate of

erroneous receptions may be up to 0.05% of all

address and data transactions.

Work arou nd

1. Implement Bit-Banged I2C

Software controlled (bit-banged) I2C slave

communication can be implemented. This

workaround ensures that all receive errors will be

eliminated from the I2C communication.

2. Implement Redundant Transmissions

The I2C Master device can be programmed to

transmit the same address/data packet multiple

times. After receiving all redundant transmissions,

the slave can compare the data received and

detect and correct receive errors by performing a

majority detect on all bits of the transmission.

3. Master Address Resend for Address Errors, and

Checksums or Parity Bit s for Dat a Errors

Configure the I2C master device to resend address

bytes upon reception of an invalid NACK. With this

workaround, the I2C slave device that incorrectly

sent a NACK will be provided additional

opportunities to receive the correct address. Using

multiple resends can reduce the occurrence of

incorrect address receptions by the slave.

Checksums and parity bits can be used for

detecting and/or correcting data receive errors on

the I2C slave device.

Affected Silicon Revisions

A0 A1

X X

A0 A1

X X

SPI1BUF = 0x0001;

while (SPI1STATbits.SPITBF);

asm("REPEAT #50");.

asm("NOP");

// The number of NOPs depends on the SPI

// clock prescalers

SPI1BUF = 0x0002;

A0 A1

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

13. Module: PWM

The PWM SWAP bit allows the user-assigned

application to connect the PWMxH signal to the

PWMxL pin, and the PWMxL signal to the PWMxH

pin. When the SWAP bit is set and Current-Limit

mode or Fault mode is enabled, the user-defined

dead time is ignored during the Fault condition and

the PWM pins default to their defined state as

specified by the FLTDAT and CLDAT bits in the

IOCONx register .

Work around

None.

Affected Silicon Revisions

14. Module: PWM

When using the External Period Reset in True

Independent Output mode, the external reset

signal should reset the timebases of the PWMxH

and PWMxL signals. However, the external period

reset signal does not affect the PWMxL signal.

This issue is not exhibited in Complementary,

Redundant or Push-pull PWM modes.

Work around

The PWMxH channel of a spare PWM generator

can be configured identically to that of the PWMxL

channel mentioned abo ve. The same current-limit

signal should be selected for this spare PWM

generator.

Affected Silicon Revisions

15. Module: CPU

When using the Signed 32-by-16-bit Division

instruction, div.sd, the overflow bit does not

always get set when an overflow occurs.

Work around

Test for and handle overflow con ditions outside of

the div.sd instruction.

Affected Silicon Revisions

16. Module: CPU

When a previous DISI instruction is active (i.e.,

the DISICNT register is non-zero), and the value of

the DISICNT register is updated manually, the

DISICNT register freezes and disables interrupts

permanently.

Work aro und

Avoid updating the DISICNT register manually.

Instead, use the DISI #n instruction with the

required value for 'n'.

Affected Silicon Revisions

17. Module: UART

When using UTXISEL = 01 (Interrupt when last

character is shifted out of the Transmit Shift

out through the Transmit Shift Register, the

Transmit (TX) Interrupt may occur before the final

bit is shifted out.

Work aro und

If it is critical that the interrupt processing occur

only when all transmit operations are complete.

Hold off the interrupt routine processing by adding

a loop at the beginning of the routine that polls the

Transmit Shift Register Empty bit (TRMT) before

processing the rest of the interrupt.

Affected Silicon Revisions

18. Module: PWM

When operating in Edge-Aligned Complimentary

mode, if the duty cycle (PDCx) becomes less than

the alternate dead time (ALTDTRx), the dead time

on the PWMs will become 0.

Work aro und

Ensure that the duty cycle (PDCx) always meets

the following condition: PDCx > (ALTDTRx - 1).

Affected Silicon Revisions

A0 A1

X X

A0 A1

X X

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

19. Module: PWM

The High Speed PWM module can operate with

variable period, duty cycle, dead-time and phase

values. The master period and other timing

parameters can be updated in the same PWM

cycle. With immediate updates disabled, the new

values should take effect at the start of the next

PWM cycle.

As a result of this erratum, the updated master

period takes effect on the next PWM cycle, while

the update of the additional timing parameter is

delayed by one PWM cycle. The parameters

affected by this erratum are as follows:

Master Period Registers: Update effective on the

next PWM cycle:

1. PTPER : if PWMCONx<MTBS> = 0

2. STPER : if PWMCONx<MTBS> = 1

Additional PWM Timing parameters: Update

effective one PWM cycle after master period

update:

1. Duty cycle: PDCx, SDCx, and MDC registers

2. Phase: PHASEx or SPHASEx registers

3. Dead-time: DTRx and ALTDTRx registers and

dead-time compensation signals

4. Clearing of current-limit and fault conditions, and

application of external period reset signal

Work around

If the application requires the master period and

other parameters to be updated at the same time,

enable both immediate updates:

• PTCON<EIPU> = 1 to enable immediate period

updates

• PWMCONx<IUE> = 1 to enable immediate

updates of additional parameters listed above

Enabling immediate up dates will allow updates to

the master period and the other parameter to take

effect immediately after writing to the respective

registers.

Affected Silicon Revisions

A0 A1

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

Data Sheet Clarifications

The following typographic corrections and clarifications

are to be noted for the latest version of the device data

sheet (DS70591C):

1. Module: DC Characteristics: I/O Pin Input

Specifications

The maximum value for parameter DI19 (VIL

specifications for SDAx and SCLx pins) was stated

incorrectly in Table 31-9 of the current device data

sheet. Also, parameters DI28 and DI29 (VIH

specifications for SDAx and SCLx pins) were not

stated. The correct values are shown in bold type in

Table 3.

TABLE 3: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Note: Corrections are shown in bold. Where

possible, the original bold text formatting

has been removed for clarity.

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherw i se stated)

Operatin g te mperature -40°C ≤ TA≤ +85°C for Industrial

-40°C ≤ TA≤+125°C for Extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

VIL Input Low Voltage

DI18 SDAx, SCLx VSS — 0.3 VDD V SMBus disabled

DI19 SDAx, SCLx VSS —0.8 V SMBus enabled

VIH Input High Vol tage

DI28 SDAx, SCLx 0.7 VDD — 5.5 V SMBus disabled

DI29 SDAx, SCLx 2.1 — 5.5 V SMBus enabled

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

APPENDIX A: REVISION HISTORY

Rev A Document (10/2009)

Initial release of this document; issued for revision A0.

Includes silicon issues 1 (ECAN), 2 (SPI), 3 (SPI)

4(JTAG), 5 (PWM) and 6 (Interrupts).

Rev B Document (6/2010)

Removed silicon issue 2 (SPI) and marked its location

as reserved.

Updated the work around in silicon issue 5 (PWM).

Added silicon issues 7 ( ADC), 8 (PWM) and 9 (PWM)

and data sheet clarification 1 (DC Characteristics: I/O

Pin Input Specifications).

Rev C Document (11/2010)

Updated the Device IDs in Table 1 for the following

devices:

• dsPIC33FJ32GS606

• dsPIC33FJ32GS608

• dsPIC33FJ32GS610

• dsPIC33FJ64GS406

• dsPIC33FJ64GS606

• dsPIC33FJ64GS608

Added silicon issue 10 (ECAN).

Rev D Document (3/2011)

Added silicon issue 11 (SPI).

Rev E Document (4/2011)

Added silicon issue 12 (I2C).

Rev F Document (6/2011)

Updated current silicon revision to A1 throughout the

document.

Updated silicon issue 8 (PWM).

Removed the word s High-S pe ed from the title of issue 9

(PWM).

Added silicon issues 13 and 14 (PWM), and silicon

issue 15 (CPU).

Rev G Document (11/2011)

Added silicon issues 16 (CPU), 17 (UART), and 18

(PWM).

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

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All other trademarks mentioned herein are property of their

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Printed on recycled paper.

ISBN: 978-1-61341-764-5

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts

allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:200 9 certif ication for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and

analog product s. In addition, Microchip ’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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08/02/11