IRF3305PBF - INFINEON TECHNOLOGIES AG

07/23/10

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HEXFET® Power MOSFET

VDSS = 55V

RDS(on) = 8.0mΩ

ID = 75A

Description

Designed to support Linear Gate Drive

Applications

175°C Operating Temperature

Low Thermal Resistance Junction - Case

Rugged Process Technology and Design

Fully Avalanche Rated

Lead-Free

Features

TO-220AB

IRF3305PbF

Absolute Maximum Ratings

Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

ID @ TC = 100°C Continuous Drain Current, VGS @ 10V A

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)

IDM Pulsed Drain Current

PD @TC = 25°C Power Dissipation W

Linear Derating Factor W/°C

VGS Gate-to-Source Voltage V

EAS (Thermally limited) Single Pulse Avalanche Energy

EAS (Tested ) Single Pulse Avalanche Energy Tested Value

IAR Avalanche Current

c

EAR Repetitive Avalanche Energy

TJ Operating Junction and

TSTG Storage Temperature Range °C

Soldering Temperature, for 10 seconds

Mounting Torque, 6-32 or M3 screw

Thermal Resistance

Parameter Typ. Max. Units

RθJC Junction-to-Case

––– 0.45

RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W

RθJA Junction-to-Ambient

––– 62

-55 to + 175

300 (1.6mm from case )

10 lbf

in (1.1N

330

2.2

± 20

Max.

140

560

860

470

See Fig.12a, 12b, 15, 16

This HEXFET Power MOSFET utilizes a rugged

planar process technology and device design,

which greatly improves the Safe Operating Area

(SOA) of the device. These features, coupled

with 175°C junction operating temperature and

"low thermal resistance of 0.45C/W"

PD - 95758A

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 Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Limited by TJmax, starting TJ = 25°C, L = 0.17mH

RG = 25Ω, IAS = 75A, VGS =10V. Part not

recommended for use above this value.

 Pulse width ≤ 1.0ms; duty cycle ≤ 2%.

 Coss eff. is a fixed capacitance that gives the

same charging time as Coss while VDS is rising

from 0 to 80% VDSS .

Notes:

 Coss eff. is a fixed capacitance that gives the same charging time

as Coss while VDS is rising from 0 to 80% VDSS .

 Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive

avalanche performance.

 This value determined from sample failure population. 100%

tested to this value in production.

 Rθ is measured at TJ of approximately 90°C.

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V

∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.055 ––– V/°C

RDS(on) Static Drain-to-Source On-Resistance ––– ––– 8.0 mΩ

VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V

gfs Forward Transconductance 41 ––– ––– S

IDSS Drain-to-Source Leakage Current ––– ––– 25 µA

––– ––– 250

IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA

Gate-to-Source Reverse Leakage ––– ––– -200

QgTotal Gate Charge ––– 100 150

Qgs Gate-to-Source Charge ––– 21 ––– nC

Qgd Gate-to-Drain ("Miller") Charge ––– 45 –––

td(on) Turn-On Delay Time ––– 16 –––

trRise Time ––– 88 –––

td(off) Turn-Off Delay Time ––– 43 ––– ns

tfFall Time ––– 34 –––

LDInternal Drain Inductance ––– 4.5 ––– Between lead,

nH 6mm (0.25in.)

LSInternal Source Inductance ––– 7.5 ––– from package

and center of die contact

Ciss Input Capacitance ––– 3650 –––

Coss Output Capacitance ––– 1230 –––

Crss Reverse Transfer Capacitance ––– 450 ––– pF

Coss Output Capacitance ––– 4720 –––

Coss Output Capacitance ––– 930 –––

Coss eff. Effective Output Capacitance ––– 1490 –––

Source-Drain Ratin

s and Characteristics

Parameter Min. Typ. Max. Units

ISContinuous Source Current ––– ––– 75

(Body Diode) A

ISM Pulsed Source Current ––– ––– 560

(Body Diode)

c

VSD Diode Forward Volta

e––––––1.3V

trr Reverse Recover

Time –––5786ns

Qrr Reverse Recover

Char

e ––– 130 190 nC

ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

VDS = 25V, ID = 75A

ID = 75A

VDS = 44V

Conditions

VGS = 10V

VGS = 0V

VDS = 25V

ƒ = 1.0MHz

VGS = 20V

VGS = -20V

MOSFET symbol

showing the

integral reverse

p-n junction diode.

TJ = 25°C, IS = 75A, VGS = 0V

TJ = 25°C, IF = 75A, VDD = 28V

di/dt = 100A/µs

Conditions

VGS = 0V, ID = 250µA

Reference to 25°C, ID = 1mA

VGS = 10V, ID = 75A

VDS = VGS, ID = 250µA

VDS = 55V, VGS = 0V

VDS = 55V, VGS = 0V, TJ = 125°C

VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz

VGS = 0V, VDS = 44V, ƒ = 1.0MHz

VGS = 0V, VDS = 0V to 44V

VGS = 10V

VDD = 28V

ID = 75A

RG = 2.6 Ω

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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

Vs. Drain Current

0 20 40 60 80 100 120 140

ID, Drain-to-Source Current (A)

Gfs, Forward Transconductance (S)

TJ = 25°C

TJ = 175°C

VDS = 10V

380µs PULSE WIDTH

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

≤ 60µs PULSE WIDTH

Tj = 25°C

4.5V

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

≤ 60µs PULSE WIDTH

Tj = 175°C

4.5V

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

2.0 3.0 4.0 5.0 6.0 7.0 8.0

VGS, Gate-to-Source Voltage (V)

0.1

1.0

10.0

100.0

1000.0

ID, Drain-to-Source Current

(Α)

VDS = 25V

≤ 60µs PULSE WIDTH

TJ = 25°C

TJ = 175°C

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Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

110 100

VDS, Drain-to-Source Voltage (V)

1000

2000

3000

4000

5000

6000

7000

C, Capacitance (pF)

Coss

Crss

Ciss

VGS = 0V, f = 1 MHZ

Ciss = Cgs + Cgd, Cds SHORTED

Crss = Cgd

Coss = Cds + Cgd

0 40 80 120 160

QG Total Gate Charge (nC)

VGS, Gate-to-Source Voltage (V)

VDS= 44V

VDS= 28V

ID= 75A

0.0 0.4 0.8 1.2 1.6 2.0 2.4

VSD, Source-to-Drain Voltage (V)

0.1

1.0

10.0

100.0

1000.0

ISD, Reverse Drain Current (A)

TJ = 25°C

TJ = 175°C

VGS = 0V

1 10 100 1000

VDS , Drain-toSource Voltage (V)

0.1

100

1000

10000

ID, Drain-to-Source Current (A)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA

LIMITED BY R DS(on)

100µsec

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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current Vs.

Case Temperature

Fig 10. Normalized On-Resistance

Vs. Temperature

25 50 75 100 125 150 175

TC , Case Temperature (°C)

100

120

140

ID , Drain Current (A)

LIMITED BY PACKAGE

-60 -40 -20 020 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

2.5

RDS(on) , Drain-to-Source On Resistance

(Normalized)

ID = 75A

VGS = 10V

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

0.0001

0.001

0.01

0.1

Thermal Response ( Z

thJC )

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

Ri (°C/W) τi (sec)

0.1758 0.00045

0.228 0.004565

0.0457 0.01858

τJ

τ1

τ2

τ2τ3

τ3

R1R2

R2R3

τC

Ci i/Ri

Ci= τi/Ri

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Charge

10 V

Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

Fig 14. Threshold Voltage Vs. Temperature

0.01

Ω

D.U.T

VDS

-V

DRIVER

15V

20V

VGS

25 50 75 100 125 150 175

Starting TJ, Junction Temperature (°C)

400

800

1200

1600

2000

EAS, Single Pulse Avalanche Energy (mJ)

I D

TOP 18A

26A

BOTTOM 75A

-75 -50 -25 025 50 75 100 125 150 175

TJ , Temperature ( °C )

1.0

1.5

2.0

2.5

3.0

3.5

4.0

VGS(th) Gate threshold Voltage (V)

ID = 5.0A

ID = 1.0A

ID = 250µA

VCC

DUT

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Fig 15. Typical Avalanche Current Vs.Pulsewidth

Fig 16. Maximum Avalanche Energy

Vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of Tjmax. This is validated for

every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is

not exceeded.

3. Equation below based on circuit and waveforms shown in

Figures 12a, 12b.

4. PD (ave) = Average power dissipation per single

avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. Iav = Allowable avalanche current.

7. ∆T = Allowable rise in junction temperature, not to exceed

Tjmax (assumed as 25°C in Figure 15, 16).

tav = Average time in avalanche.

D = Duty cycle in avalanche = tav ·f

ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Iav = 2DT/ [1.3·BV·Zth]

EAS (AR) = PD (ave)·tav

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

100

1000

10000

Avalanche Current (A)

0.05

Duty Cycle = Single Pulse

0.10

Allowed avalanche Current vs

avalanche pulsewidth, tav

assuming ∆Tj = 25°C due to

avalanche losses. Note: In no

case should Tj be allowed to

exceed Tjmax

0.01

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

100

200

300

400

500

EAR , Avalanche Energy (mJ)

TOP Single Pulse

BOTTOM 1% Duty Cycle

ID = 75A

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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

VGS=10V

VDD

ISD

Driver Gate Drive

D.U.T. ISD Waveform

D.U.T. VDS Waveform

Inductor Curent

D = P. W .

Period

* VGS = 5V for Logic Level Devices







RGVDD

• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



VDS

90%

10%

VGS

d(on)

d(off)

VDS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

VGS

D.U.T.

10V

VDD

Fig 18a. Switching Time Test Circuit

Fig 18b. Switching Time Waveforms

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Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 07/2010

Notes:

1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/

2. For the most current drawing please refer to IR website at http://www.irf.com/package/

TO-220AB package is not recommended for Surface Mount Application

TO-220AB Part Marking Information

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

INTERNATIONAL PART NUMBER

RECT IFIE R

LOT CODE

AS S E MB L Y

LOGO

YEAR 0 = 2000

DAT E CODE

WEEK 19

LINE C

LOT CODE 1789

EXAMPLE : T HIS IS AN IRF 1010

Note: "P" in assembly line position

i ndi cates "L ead - F ree"

IN THE ASSEMBLY LINE "C"

ASS EMBL ED ON WW 19, 2000