64K x 16 Static RAM
CY62127BV
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05155 Rev. ** Revised September 6, 2001
27BV
Features
• 2.7V–3.6V opera tion
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
—54 mW (max.) (15 mA)
• Low standby power (70 ns, LL version)
—54 µW (max.) (15 µA)
• Automatic power-down when deselected
—Power down either with CE or BHE and BLE HIGH
•Independent control of Upper and Lower Bytes
•Available in 44-pin TSOP II (forward) and fBGA
Functional Description
The CY62127BV is a high-performance CMOS Static RAM
organ iz ed as 65,5 36 w ords by 16 bi ts. This dev ic e ha s an au-
tomatic power-down feature that significantly reduces power
consumption by 99% when deselected. The device enters
power-d own mode when CE is HIGH or when CE is LOW and
both BLE and BHE are HIGH.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW , the n data from memo ry will appea r on I/O 9 to I/O16. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY6 2127BV i s av ailabl e in st anda rd 44-pi n TSOP Type II
(forward pinout) and fBGA packages.
Logic Block Diagram Pin Configurations
64K x 16
RAM Array I/O1–I/O8
ROW DECODER
A10
A9
A7
A6
A3
A0
COLUMN DECODER
A
5
A
8
A
13
A
14
A
15
1024 X 1024
SENS E AMP S
DATA IN DRIVERS
OE
A2
A1
I/O9–I/O16
CE
WE
BLE
BHE
A
4
A11
A12
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
TSOP II (Forward)
12
13
41
44
43
42
16
15 29
30
VCC
A15
A14
A13
A12
NC
A4
A3
OE
VSS
A5
I/O16
A2
CE
I/O3
I/O1
I/O2
BHE
NC
A1
A0
18
17
20
19
I/O4
27
28
25
26
22
21 23
24 NC
VSS
I/O7
I/O5
I/O6
I/O8
A6
A7
BLE
VCC
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
A8
A9
A10
A11
CY62127BV
Document #: 38-05155 Rev. ** Page 2 of 11
Maximum Ratings
(Above w hi ch the useful life may be impaired. For user g uid e-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1] ................................–0.5 V to VCC + 0.5V
Current into Outputs (LOW) ........................................20 mA
Static Discharge Voltage.......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Notes:
1. VIL (min.) = –2.0V for pul se duration s of less than 20 ns.
2. TA is the “Instant On” case temperature.
Pin Configurati ons (continued)
fBGA
Selection Guide 62127BV-55 62127BV-70 Units
Maxi mu m Access Time 55 70 ns
Maximum Operat ing Curre nt 20 15 mA
Maximum CMOS Stand by Current 15 15 µA
WE
VCC
A11
A10
NC
A6
A0
A3CE
I/O11
I/O9
I/O10
A4
A5
I/O12
I/O14
I/O13
I/O15
I/O16
VSS
A9
A8
OE
VSS
A7
I/O1
BHE
NC
NC
A2
A1
BLE
VCC
I/O3
I/O2
I/O4
I/O5
I/O6I/O7
I/O8
A15
A14
A13
A12
NC
NC
NC NC
62127BV–3
3
26
5
41
D
E
B
A
C
F
G
H
Operating Range
Range Ambient
Temperature[2] VCC
Industrial –40°C to +85°C2.7V–3.6V
CY62127BV
Document #: 38-05155 Rev. ** Page 3 of 11
Electrical Characteristics Ov er the Op erating Range
62127BV–55, 70
Parameter Description Test Conditions Min. Typ.[3] Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.2 V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 V
VIH Input HIGH Voltage 2.0 VCC+
0.3 V
VIL Input LOW Voltage[1] –0.3 0.4 V
IIX Input Load Current GND ≤ VI ≤ VCC –1+1 µA
IOZ Out put Leakage Current GND ≤ VI ≤ VCC,
Output Di sabled –1+1 µA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
55 ns 20 mA
70 ns 15 mA
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE ≥ VIH
VIN ≥ VIH or
VIN ≤ VIL, f = fMAX
2mA
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE ≥ VCC – 0.3V,
VIN ≥ VCC – 0.3V,
or VIN ≤ 0.3V, f=0
0.5 15 µA
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.3V 9pF
COUT Output Capacitance 9pF
AC Test Loads and Wavefor ms
Notes:
3. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal
conditions (T A = 25°C, VCC=3.0V). Parameters are guaranteed by design and characterization, and not 100% tested.
4. Tested initially and after any design or process changes that may affect these parameters.
62127BV-4
90%
10%
VCC
GND
90%
10%
ALL INPUT PULSES
3.0V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
3.0V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
R1 1076ΩΩ
R2
1262ΩR2
581Ω
Equivalent to: THÉVENIN
EQUIVALENT 1.62V
R1 1076
1262Ω
Rise Time:
1 V/ns Fall Time
1 V/ns
CY62127BV
Document #: 38-05155 Rev. ** Page 4 of 11
Switching Characteristics[5] Over the Operating Range
62127BV–55 62127BV–70
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LOW to Low Z[7] 5 5 ns
tHZOE OE HIGH to Hi gh Z[6, 7] 20 25 ns
tLZCE CE LOW to Low Z[7] 10 10 ns
tHZCE CE HIGH to High Z[6, 7] 20 25 ns
tPU CE LOW to Power-Up 0 0ns
tPD CE HIGH to Power-Down 55 70 ns
tDBE Byte Enable to Data Valid 55 70 ns
tLZBE Byte Enable to LOW Z[7] 5 5 ns
tHZBE Byte Disable to HIGH Z[6, 7] 20 25 ns
WRITE CYCLE[8]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 45 60 ns
tAW Address Set-Up to Write End 45 60 ns
tHA Address Hold from Write End 0 0ns
tSA Address Set-Up to Write Start 0 0ns
tPWE WE Pulse Width 40 50 ns
tSD Data Set-Up to Writ e End 25 30 ns
tHD Data Hold from Write End 0 0ns
tLZWE WE HIGH to Low Z[7] 5 5 ns
tHZWE WE LOW to High Z[6, 7] 25 25 ns
tBW Byte Enable to End of Write 45 60 ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V , input pulse levels of 0 to 3.0V , and output loading of the specified
IOL/IOH and 30 pF load capacitance .
6. tHZOE, tHZCE, tHZWE, and tHZBE are spec ified w ith a l oad c apaci tance of 5 pF a s in par t (b) of A C Test Loads. T ransi tion i s measure d ±500 mV from stead y-state volt age.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZWE is less than tLZWE, and tHZBE is less than tLZBE, for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW . CE and WE must be LOW to initiate a write, and the transition of any of these
signal s can t erminat e the write. The input data set-up and h old t iming s hould be referenc ed to the lead ing e dge of the sig nal t hat t erminates the w rite. R efer t o trut h table for
further con ditions from BHE and BLE.
CY62127BV
Document #: 38-05155 Rev. ** Page 5 of 11
Data Retention Characteristics (Over the Operating Range for “L” and “LL” version only)
Parameter Description Conditions[9] Min. Typ Max. Unit
VDR VCC for Data Retention 2.0 3.6 V
ICCDR Data Retention Current VCC = VDR = 2.0V,
CE > VCC-0.3V,
VIN > VCC - 0.3V or,
VIN < 0.3V.
0.5 15 µA
tCDR[4] Chip Deselect to Data Retention Time 0 ns
tROperation Recovery Time tRC ns
Data Retention Waveform
Switching Waveforms
Read Cycle No.1[10, 11]
Notes:
9. No input may exceed VCC + 0.3V.
10. Device is continuously selected. O E, CE, BHE, BLE = VIL.
11. WE is HIGH f or read cycle .
62127BV–5
3.0V3.0V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
PREVIO U S D AT A VA LID DATA VALI D
tRC
tAA
tOHA
62127BV-6
ADDRESS
DATA OUT
CY62127BV
Document #: 38-05155 Rev. ** Page 6 of 11
Read Cycle No. 2 (OE Controlled)[11, 12, 13]
Write Cycle No. 1 (CE Controlled)[13, 14]
Notes:
12. Address v a lid prior to or coincident with CE trans ition L OW .
13. Data I/O is high impedance if OE = VIH or BHE and BLE = VIH.
14. If CE, BHE, or BLE go HIGH simulta neously wi th WE going HIGH, the ou tput r emains i n a high -impeda nce s tate.
Switching Waveforms (continued)
62127BV-7
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
V
OE
DATA OUT
CC
SUPPLY
CURRENT
BHE, BLE
ICC
ISB
HIGH
IMPEDANCE
ADDRESS
tLZBEtDBE tHZBE
CE
62127BV-8
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
CE
ADDRESS
WE
DATA I/O
BHE, BL E
tBW
CY62127BV
Document #: 38-05155 Rev. ** Page 7 of 11
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
Write Cycle No.3 (WE Controlled, OE LOW)[13, 14]
Note:
15. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms (continued)
62127BV-9
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATA
IN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 15
BHE, BLE tBW
62127BV-10
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATAI/O NO TE 15
BHE, BLE tBW
CY62127BV
Document #: 38-05155 Rev. ** Page 8 of 11
Truth Table
CE OE WE BLE BHE I/O1–I/O8I/O9–I/O16 Mode Power
H X X X X High Z High Z Power Down Standby (ISB)
L L H L L Da ta Out Data Out Read All Bits Active (ICC)
L L H L H Data Out High Z Read Lower Bits Only Active (ICC)
L L H H L High Z Data Out Read Upper Bits Only Active (ICC)
L X L L L Data In Data In Write All Bits Active (ICC)
L X L L H Data In High Z Write Lower Bits Only Active (ICC)
L X L H L High Z Data In Write Upper Bits Only Active (ICC)
L H H L L High Z High Z Selected, Outputs Disabled Active (ICC)
L X X H H High Z High Z Power Down Standby (ISB)
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
55 CY62127BVLL-55ZI Z44 44-Lead TSOP II Industrial
CY62127BVLL-55BAI BA48A 48-Ball Fine Pitch Ball Grid Array (fBGA)
70 CY62127BVLL-70ZI Z44 44-Lead TSOP II
CY62127BVLL-70BAI BA48A 48-Ball Fine Pitch Ball Grid Array (fBGA)
CY62127BV
Document #: 38-05155 Rev. ** Page 9 of 11
Package Diagrams
48-Ball (7.00 mm x 7.00 mm) FBGA BA48A
51-85096-*D
CY62127BV
Document #: 38-05155 Rev. ** Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cy press Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
44-Pin TSOP II Z44
51-85087-A
CY62127BV
Document #: 38-05155 Rev. ** Page 11 of 11
Document Title: CY62127BV 64K x 16 Static RAM
Document Number: 38-05155
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 109899 01/10/02 SZV Change from Spec number: 38-01018 to 38-05155
