UA741CN - TEXAS INSTRUMENTS

1. General description

The PCA9703 is a low power 18 V tolerant SPI General Purpose In put (GPI) shif t r egister

designed to monitor the status of switch inputs. It generates an interrupt when one or

more of the switch inputs change state but allows selected inputs to not generate

interrupts using the interrupt masking feature. The input level is recognized as a HIGH

when it is greater th an 0.8 ×VDD and as a LOW when it is less than 0.55 ×VDD (minimum

LOW threshold of 2.5 V at 5 V node). The PCA9703 can monitor up to 16 switch inputs.

The falling edge of the CS pin samples the inpu t port status and clears the interrupt. When

CS is LOW, the rising e dge of the SCL K loads the shift register and shif ts the value out of

the shift register . The serial input is sampled on the falling edge of SCLK. The contents of

the shift register are loaded into the interrupt mask register of the device on the rising

edge of CS.

Each of the input ports has a 18 V breakdown ESD protection circuit, which dumps the

ESD/overvoltage current to ground. When used with a series resistor (minimum 100 kΩ),

the input can connect to a 12 V battery and support double battery, reverse battery, 27 V

jump sta rt and 40 V load dump conditions in automotive applications. Higher volt ages can

be tolerated on the inputs depending on the series resistor used to limit the input current.

The INT_EN pin is used to both enable the GPI pins and to enable the INT output pin to

minimize battery drain in cyclically supplied pull-up or pull-down applications. The SDIN

pull-down prevents floating nodes when the device is used in daisy-chain applications.

With both the high breakdown voltage and high ESD, this device is useful for both

automotive (AEC-Q100 compliance available) and mobile applications.

2. Features and benefits

16 general purpose input ports

18 V tolerant input ports with 100 kΩ external series resistor

Input LOW threshold 0.55 ×VDD with minimum of 2.5 V at VDD =4.5V

Input hystere sis 0. 04 ×VDD with minimum of 180 mV at VDD =4.5V

Open-drain interrupt output

Interrupt enable pin (INT_EN) disables GPI pins and interrupt output

Interrupt-masking feature allows no interrupt generation from selected inputs

VDD range: 4.5 V to 5.5 V

IDD is very low 2.5 μA maximum

SPI serial interface with speeds up to 5 MHz

SPI supports daisy-chain connection for large switch numbers

AEC-Q100 compliance available

PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

Rev. 2 — 14 June 2012 Product data sheet

Product data sheet Rev. 2 — 14 June 2012 2 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

ESD protection exceeds 5 kV HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Operating temperature range: −40 °C to +125 °C

Offered in TSSOP24 and HWQFN24 packages

3. Applications

Automotive

Body control modules

Electronic control units (for example, for body controller)

Switch monitoring

SBC wake pin extension

Industrial equipment

Cellular telephones

Emergency lighting

4. Ordering information

[1] PCA9703PW/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP.

Tabl e 1. Ordering information

Type number Topside

mark Package

Name Description Version

PCA9703HF 9703 HWQFN24 plastic thermal enhanced very very thin quad flat package;

no leads; 24 terminals; body 4 ×4×0.75 mm SOT994-1

PCA9703PW PCA9703PW TSSOP24 plastic thin shrink small outline package; 24 leads;

body width 4.4 mm SOT355-1

PCA9703PW/Q900[1] PCA9703PW TSSOP24 plastic thin shrink small outline package; 24 leads;

body width 4.4 mm SOT355-1

Product data sheet Rev. 2 — 14 June 2012 3 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

5. Block diagram

6. Pinning information

6.1 Pinning

Fig 1. Block diagram of PCA9703

SCLK

SDIN

SDOUT

INT

002aae021

SHIFT REGISTER

DFF0

IN0

DFF1

IN1

DFF15

IN15

PCA9703

INT_EN

INPUT

STATUS

20 μA

INPUT

MASK REGISTER

Fig 2. Pin configuration for HWQFN24 Fig 3. Pin configuration for TSSOP24

002aae024

PCA9703HF

Transparent top view

IN11

IN4

IN5

IN12

IN3 IN13

IN2 IN14

IN1 IN15

IN0 CS

IN6

IN7

IN8

IN9

IN10

INT_EN

INT

SDOUT

SDIN

SCLK

terminal 1

index area

613

514

4 15

3 16

2 17

118

PCA9703PW

PCA9703PW/Q900

SDOUT V

INT SDIN

INT_EN SCLK

IN0 CS

IN1 IN15

IN2 IN14

IN3 IN13

IN4 IN12

IN5 IN11

IN6 IN10

IN7 IN9

IN8

002aae023

Product data sheet Rev. 2 — 14 June 2012 4 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

6.2 Pin description

[1] HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

PCB in the thermal pad region.

Table 2. Pin description

Symbol Pin Type Description

TSSOP24 HWQFN24

SDOUT 1 22 output 3-state serial data output; normally

high-impedance

INT 2 23 output open-drain interrupt output (active LOW)

INT_EN 3 24 input GPI pin enable and interrupt output en able

1 = GPI pin and interrupt output are enabled

0 = GPI pin and interrupt output are disabled and

interrupt output is high-impedance

IN0 4 1 input input port 0

IN1 5 2 input input port 1

IN2 6 3 input input port 2

IN3 7 4 input input port 3

IN4 8 5 input input port 4

IN5 9 6 input input port 5

IN6 10 7 input input port 6

IN7 11 8 input input port 7

VSS 12 9[1] ground ground supply

IN8 13 10 input input port 8

IN9 14 11 input input port 9

IN10 15 12 i nput input port 10

IN11 16 13 input input port 11

IN12 17 14 input in put port 12

IN13 18 15 input in put port 13

IN14 19 16 input in put port 14

IN15 20 17 input in put port 15

CS 21 18 input chi p se le ct (acti ve LOW)

SCLK 22 19 input serial input clock

SDIN 23 20 input serial data input (20 μA pull-down)

VDD 24 21 supply supply voltage

Product data sheet Rev. 2 — 14 June 2012 5 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

7. Functional description

PCA9703 is a 16-bit General Purpose Input (GPI) with an open-drain interrupt output

designed to monitor switch status. By putting an external 100 kΩ series resistor at the

input port, the device allows the input to tolerate momentary double 12 V battery, reverse

battery, 27 V jump start or 40 V load dump conditions. The interrupt output is asserted

when an input port status changes, the input is not masked and the interrupt output is

enabled. The open-drain interrupt output is enabled when INT_EN is HIGH a nd disabled

when INT_EN is LOW. The INT_EN also enables the GPI pins when it is HIGH. In

cyclically supplied pull-up or pull-d own applications, the GPI pull-ups or pull-downs should

be active before the INT_EN is taken HIGH and the INT output should only be sampled

after transient conditions have settled. Additionally, interrupts can be disabled in software

by using the interrupt mask feature. The input port status is accessed via the 4-wire SPI

interface.

Upon power-up, the power-up reset cell clears all the registers, resulting in all zeros in

both the input status register and the interrupt mask register. Since a zero in the interrupt

mask register masks the interrupt from that pin, there will not be any interrupts generated.

After power-up it is necessary to access the PCA9703 through the SPI pins in order to

activate the interrup t for any GPI pin s. When th e PCA97 03 is read over the SPI wires, the

input conditions are clo cked into the input sta tus register on the CS falling edge. Since the

inputs and the input status register now match, no interrupt is generated and any

pre-existing interrupt is cleared. The input status register data is parallel loaded into the

shift register on the first rising edge of the SCLK. The serial input data is captured on the

opposite clock ed ge so th at th er e is a 1⁄2 clock cycle hold time. The set-up time is

diminished by the propagation time so the SCLK falling edge to rising edge must be long

enough to provide sufficient set-up time. Successive clock cycles on the SCLK pin clock

the data out of the PCA9703 and new data from the SDIN into the shift register. There is

no limit to the number of clock cycles that can be applied with the CS LOW, however

sufficient clock cycles should be used to both shift out all of the GPI data and shift in the

new interrupt mask data to the correct position with the MSB first before the CS rising

edge.

For cyclic switch bias applications the switch bias should be applied first, then after the

input voltage is settled the general purpose inputs are switched on by taking the INT_EN

HIGH. This also enables the interr upt output, which will only indicate an interrupt if the GPI

data does not match the input status register on a bit that is enabled by the interrupt mask

active and the INT_EN should re main active and the SPI pins are used to update the input

status register and read the data out. They are also used to store the new interrupt mask

on the rising edge of CS. After the SPI transaction is complete the INT_EN is taken LOW

to turn the inputs off and disable the INT output. Then the GPI pull-ups or pull-downs can

be turned off. The GPI pins are specifically designed so that any ESD/overstress current

flows to ground, not VDD. They are also specifically designed so that if the input voltage

returns to the same value a fter pull-up or pu ll-down bias cycling as before th e input pull-up

or pull-down bias cycling, before the input is enabled it will be detected as the same state.

If the Input Status register is read when INT_EN is LOW, the input state at the INT_EN

transition will be output irregardless of the actual input levels since the GPI pins are turned

off.

Product data sheet Rev. 2 — 14 June 2012 6 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

If the VDD falls below the 4.5 V minimum specified supply voltage, the input threshold will

move down since they are a function of the VDD voltage . The inp ut status register a nd the

interrupt mask register retain their values to below VDD = 2.0 V and power-down can only

be used to generate a power-up reset if the VDD falls below 0.2 V before returning to the

operating range.

Multiple PCA9703 devices can be serially connected for monitoring a large number of

switches by connecting the SDOUT of one device to the SDIN of the next device. SCLK

and CS must be common among all devices and interrupt outputs may be tied together.

No external logic is necessary because all the devices’ interrupt outputs are open-drain

that function as ‘wired-AND’ and can simply be connected together to a single pull-up

resistor.

7.1 SPI bus operation

The PCA9703 interfaces with th e controller via the 4-wire SPI bus that is comprised of the

following signals: chip select (CS), serial clock (SCLK), serial data in (SDIN), and serial

data out (SDOUT). To access the device, the controller asserts CS LOW, then sends

SCLK and SDIN. When reading is complete and the interrupt mask data is in place, the

controller de-asserts CS. See Figure 4 for register access timing.

7.1.1 CS - chip select

The CS pin is the device chip select and is an active LOW input. The falling edge of CS

captures the input port status in the inpu t status register . If the interrupt output is asserted,

the falling edge of CS will clear the interrupt. When CS is LOW , the SPI interface is active.

When CS transitions HIGH the interrupt mask is stored and when CS is HIGH, the SPI

interface is disabled.

7.1.2 SCLK - serial clock input

SCLK is the serial clock input to the d evice. It should be L OW and remain LOW during the

falling and rising edge of CS. When CS is LOW, the first rising edge of SCLK parallel

loads the shift register from the input status register. The subseq ue n t risin g ed ge s on

SCLK serially shifts data out from the shift register. The falling edge of SCLK samples the

data on SDIN.

7.1.3 SDIN - serial data input

SDIN is the serial data input port. The data is sampled into the shift register on the falling

edge of SCLK. SDIN is only active when CS is LOW. This input has a 20 μA pull-down

current source to prevent the SDIN node from floating when CS is HIGH.

7.1.4 SDOUT - serial data output

SDOUT is the serial data output signal. SDOUT is h igh-imp edance when CS is HIGH and

switches to low-impedance after CS goes LOW. Whe n CS is LOW, after the first rising

edge of SCLK the most significant bit in the shif t register is presented on SDOUT.

Subsequent rising edges of SCLK shift the remaining data from the shift register onto

SDOUT.

Product data sheet Rev. 2 — 14 June 2012 7 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

7.1.5 Register access timing

Figure 4 shows the waveforms of the device operation. Initially CS is HIGH and SCLK is

LOW. On the falling edge of CS, input port status, DATA[n:0] is captured into the input

status register, and subsequently the first rising edge of SCLK parallel loads the shif t

7.1.6 Software reset operation

Software reset will be activated by writing all zeroes into the shif t register. This is identical

to having an interrupt mask value of 0X00. Such an operation will reset the device, clear

the input status register to zero and set the interrupt output to HIGH (no interrupt).

7.2 Interrupt output

INT is the open-drain interrupt output and is active LOW. A pull-up resistor of

approximately 10 kΩ is recommended.

A user-defined interrupt mask bit pattern is shifted into the shift register via SDIN. The

value of bits in the mask pattern will determine which input pins will cause an interrupt.

Any bit that is = 0 will disable the input pin corresponding to that bit position from

generating an interrupt. Interrupts will be enabled for bits having value = 1. The mask bit

pattern is not automatically aligned with the desired input pins. It is the responsibility of the

programmer to sh if t the corr ect number of (mask) bit s to the cor rect positions into the shif t

DATA[15:0] is data on the input pins, IN[15:0].

Shaded areas indicate active but invalid data.

Fig 4. Register access timing

SCLK

SDIN

SDOUT high-impedance

MSB in

MSB out

002aae286

MSB − 1 in

MSB − 1 out

LSB in

LSB out

input status

shift

DATA[15:0]

sample

SDIN

interrupt mask

Product data sheet Rev. 2 — 14 June 2012 8 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

CS rising edge. Misaligned mask pattern will result in unexpected activation of the

interrupt signal.

The interrupt output is asserted when the input status is changed, and the interrupt mask

bit correspo nding to the input pin that caused the change is unmasked (bit value = 1), and

is cleared on the falling edge of CS or when the input port st atus matche s the inp ut st atus

pull-up.

Table 3 illustrates the state of the interrupt output versus the state of the input port and

input status register. The interrupt output is asserted when the input port and input status

[1] Input status register is the value or content of the D flip-flops.

[2] Logic states shown for INT pin assumes 10 kΩ pull-up resistor.

7.3 Interrupt enable

INT_EN is the interrupt output enable inpu t a nd the gener al pu rp ose input en able inp ut. It

is an active HIGH input. When the INT_EN pin is LOW the GPI pins are turned of f and the

input state is saved to minimize power loss when the input pull-ups or pull-downs are

cycled and the INT output is disabled. The cycled pull-ups or pull-downs should be active

sufficiently long before the INT_EN is taken active that the GPI pin voltage is completely

settled to prevent false or transient interrupt signals.

7.4 General Purpose Inputs

The General Purpose Input s (GPI) are designed to behave like a typical input in the 0 V to

5.5 V range, but are also desig ned to have low leakage cur rents at elevated volt ages. The

input structure allows for elevated voltages to be applied through a series resistor. The

series resistor is required when the input voltage is above 5.5 V. The series resistor is

required for two reasons: first, to prevent damage to the input avalanche diode, and

second, to prev en t th e ES D prote c t ion circu i try from creating an excessive current flow.

The ESD protection circuitry includes a latch-back style device, which provides excellent

ESD protection during assembly or typical 5.5 V applications. The series resistor limits the

current flowing into the part and provides additional ESD protection. The limited current

prevents the ESD latch-back device from latching back to a low voltage, which would

cause excessive current flow and damage the part when the input voltage is ab ove 5.5 V.

Table 3. Interrupt output function truth table

H = HIGH; L = LOW; X = don’t care

INT_EN Input port status Input status register[1] INT output [2]

Mask bit = 1

(unmasked) Mask bit = 0

(masked)

HL L H H

HL H L H

HH L L H

HH H H H

LX X H H

Product data sheet Rev. 2 — 14 June 2012 9 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

The minimum required series resistance for applications with input voltages above 5.5 V

is 100 kΩ. Fo r ap plic at ion s re qu irin g an ap plied vo ltage abo ve 27 V, Equation 1 is

recommended to determine the series resistor. Failure to include the appropriate input

series resistor may result in product failure and will void the warranty.

(1)

The series resistor sho uld be pl ace physically as clos e as possible to the con nected input

to reduce the effective node capacitance. The input response time is effected by the RC

time constant of the series resistor and the input node capacitance.

7.4.1 VIL, VIH and switching points

A minimum LOW threshold of 2.5 V is guaranteed for the logical switching points for the

inputs. See Figure 5 for details.

The VIL is specified as a maximum of 0.55 ×VDD and is 2.5 V at 4.5 V VDD. This means

that if the user applies 2.5 V or less to the input (with VDD = 4.5 V), or as the voltage

passes this threshold, they will always see a LOW.

The VIH is specified as a minimum of 0.8 ×VDD. This means that if the user applies 3.6 V

or more to the input (with VDD = 4.5 V), or as the voltage passes this threshold, they will

always see a HIGH.

Hysteresis minimum is specified as 180 mV at VDD = 4.5 V. This means there will always

be at least 180 mV of difference between the LOW threshold and HIGH threshold to help

prevent oscillations and handle higher noise.

Rsvoltage applied 17 V–

------------------------------------------------------------

Fig 5. Logic level thresholds

002aae101

hysteresis

minimum = 0.04V

0 V

0.55V

0.8V

HIGH

LOW

possible ground shift

Product data sheet Rev. 2 — 14 June 2012 10 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

8. Application design-in information

8.1 General application

8.2 Automotive application

Supports:

•12 V battery (8 V to 16 V)

•Double battery (16 V to 32 V)

•Reverse battery (−8 V to −16 V)

•Jump start (27 V for 60 seconds)

•Load dump (40 V)

Fig 6. Typical application

SCLK

SDIN

SDOUT

002aae026

IN0

IN1

IN15

PCA9703

INT_EN

INT

CONTROLLER

PROCESSOR

10 kΩ

4.5 V to 5.5 V

1.5 kΩ

100 kΩ

relay

18 V

100 kΩ

18 V

10 kΩ

5 V

500 kΩ

180 V

50 kΩ

IN2

open

Product data sheet Rev. 2 — 14 June 2012 11 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

8.2.1 SBC wake port extension with cyclic biasing

System Basis Chips (SBC) offer many functions needed for in-vehicle networking

solutions. Some of the features built into SBC are:

•Transceivers (HS-CAN, LIN 2.0)

•Scalable voltage regulators

•Watchdog timers; wake-up function

•Fail-safe function

For more information on SBC, refer to

www.nxp.com/products/interface_and_connectivity/system_basis_chips/.

8.2.1.1 UJA106x with PCA9703, standby

•PCA9703 fits to SBC UJA106x and UJA107xA family

•PCA9703 can be powered by V1 of SBC

•Extends the SBC with 16 additional wake inputs

•μC can be set to stop-mode during standby to save ECU standby current. SBC with

GPI periodically monitors the wake inputs

–Cyclic bias via V3

–Very low system current consumption even with clamped switches

–Interrupt enable control via V2

Fig 7. UJA106x with PCA9703 with su pplied μC (standby)

SDIN

SDOUT

SCLK

002aae027

IN0

PCA9703

VSS

VDD

INT_EN

INT

IN1

IN15

alternate

PVR100AD-B5V0

UJA106x

WAKE

V1 GND

VCC

μC

CSN

MOSI

MISO

SCLK

GND

Product data sheet Rev. 2 — 14 June 2012 12 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

8.2.1.2 UJA106x with PCA9703, sleep

•Very low quiescent system current (50 μA) due to disabled μC and cyclically biasing

of switches

•Wake-up upon change of switches or upon bus traffic (CAN and LIN)

•PCA970x supplied out of cyclically biased tra nsistor regulator

Fig 8. UJA106x with PCA9703 with un supplied μC (sleep)

SDIN

SDOUT

SCLK

002aae028

IN0

PCA9703

INT_EN

IN1

IN15

alternate

PVR100AD-B5V0 V3

UJA106x

WAKE

V1 GND

μC

CSN

MOSI

MISO

SCLK

GND

INT

alternate

PMEM4010ND

RSTN

alternate

PDTC144TU

Product data sheet Rev. 2 — 14 June 2012 13 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

8.2.1.3 UJA107xA with PCA9703, standby and sleep

•UJA107xA SBC provides WBIAS pin for cyclic biasing of the inputs

•Compatible with UJA107xA based ASSPs

Fig 9. UJA107xA with PCA9703 with supplied μC (standby)

Fig 10. UJA107xA with PCA9703 with supplied μC (sleep)

SDIN

SDOUT

SCLK

002aae029

IN0

PCA9703

VSS

VDD

INT_EN

INT

IN1

IN15

BAT

UJA107xA

WAKE2

V1 GND

VCC

μC

CSN

MOSI

MISO

SCLK

GND

WBIAS

RSTN

1 kΩ 1 kΩ 1 kΩ

100 kΩ

10 kΩ

47 kΩ

47 kΩ WAKE1

alternate PDTA114E

alternate

PDTA144E

SDIN

SDOUT

SCLK

002aae972

IN0

PCA9703

VSS

VDD

INT_EN

INT

IN1

IN15

BAT

UJA107xA

WAKE2

V1 GND

VCC

μC

CSN

MOSI

MISO

SCLK

GND

WBIAS

RSTN

1 kΩ 1 kΩ 1 kΩ

100 kΩ

10 kΩ

47 kΩ

47 kΩ WAKE1

330 Ω

470 nF

10 kΩ

47 kΩ

alternate

PVR100AD-B5V0

alternate PDTA114E

alternate PDTA144E

alternate

PDTC144T

Product data sheet Rev. 2 — 14 June 2012 14 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

8.2.2 Application examples including switches to battery

9. Limiting values

[1] With GPI external series resistors, the inputs support double battery, reverse battery and load dump conditions. During double battery or

load dump the input pin will drain slightly higher leakage current until the input drops to 18 V. For more detail of leakage current

specification, please refer to Table 5 “Static characteristics”. See Section 7.4 for series resistor requirements.

Fig 11 . Clamp 15 (ignition) detectio n Fig 12. Swit ch e s to ba tte ry an d ground with

cyclic biasing

002aae030

IN0

PCA9703

IN1

IN15

switch bias

clamp 15

002aae031

IN0

PCA9703

IN1

IN15

switch bias

BAT BAT

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Tamb =

−

Cto+125

C, unless otherwise specified.

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +6.0 V

IIinput current IN[15:0] pi ns with series resistor and

VI>5.5V [1] - 350 μA

VIinput voltage GPI pins IN[15:0]; no series resistor [1] −0.5 +6 V

SPI pins −0.5 +6 V

Tstg storage temperature −65 +150 °C

Tj(max) maximum junction temperature operating - 125 °C

Product data sheet Rev. 2 — 14 June 2012 15 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

10. Static characteristics

[1] VDD must be lowered to 0.2 V for at least 5 μs in order to reset device.

[2] Minimum VIL is 2.5 V at VDD =4.5V.

[3] Minimum Vhys is 180 mV at VDD =4.5V.

[4] For GPI pin voltages > 5.5 V, see Section 7.4.

Table 5. Static characteristics

VDD = 4.5 V to 5.5 V; VSS =0V; T

amb =

−

C to +125

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supply

VDD supply voltage 4.5 5.0 5.5 V

IDD supply current VDD =5.5V; input=5Vor18V;

INT_EN = VDD

-1.02.5μA

VPOR power-on reset voltage [1] -1.82.2V

General Purpose Inputs (IN0 to IN15)

VIL LOW-level input voltage [2] - - 0.55VDD V

VIH HIGH-level input voltage 0.8VDD -- V

Vhys hysteres is voltage [3] 0.04VDD -- V

IIinput current GPI recommended maximum current;

VI> 5.5 V; with series resistor Rs

[4] - - 100 μA

IIH HIGH-level input current each input; VI=V

DD −1-+1μA

ILI input leakage current VI= 17 V; 100 kΩ series resistor −1-+1μA

Ciinput capacitance VI=V

SS or VDD -2.05.0pF

Interrupt output (INT)

IOL LOW - l e ve l ou tp u t current VDD =4.5V; V

OL =0.4V 6 - - mA

IOH HIGH-level output current VOH =V

DD −1-+1μA

Cooutput capacitance - 2 5 pF

SPI and control (SDOUT, SDIN, SCLK, CS, INT_EN)

VIL LOW-level input voltage - - 0.3VDD V

VIH HIGH-level input voltage 0.7VDD -5.5V

IIH HIGH-level input current SDIN; VI=V

DD = 5.5 V - 20 40 μA

IOL LOW - l e ve l ou tp u t current SDOUT; VOL =0.4V; V

DD =4.5V 5 - - mA

IOH HIGH-level output current SDOUT; VOH =V

DD −0.5 V; VDD =4.5V −5−11 - mA

Ciinput capacitance VI=V

SS or VDD -25pF

Cooutput capacitance SDOUT; CS =V

DD -46pF

Product data sheet Rev. 2 — 14 June 2012 16 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

11. Dynamic characteristics

Table 6. Dynamic characteristics

VDD = 4.5 V to 5.5 V; VSS =0V; T

amb =

−

C to +125

C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

fmax maximum input clock frequency - - 5 MHz

trrise time SDOUT; 10 % to 90 % at 5 V - 35 60 ns

tffall time SDOUT; 90 % to 10 % at 5 V - 25 50 ns

tWH pulse width HIGH SCLK 50 - - ns

tWL pulse width LOW SCLK 50 - - ns

tSPILEAD SPI enable lead time CS falling edge to SCLK rising edge 50 - - ns

tSPILAG SPI enable lag time SCLK falling edge to CS rising edge 50 - - ns

tsu(SDIN) SDIN set-up time SDIN to SCLK falling edge 20 - - ns

th(SDIN) SDIN hold time from SCLK falling edge 30 - - ns

ten(SDOUT) SDOUT enable time from CS LOW to

SDOUT low-impedance; Figure 16 --55ns

tdis(SDOUT) SDOUT disable time from rising edge of CS to SDOUT

high-impedance; Figure 16 --85ns

tv(SDOUT) SDOUT valid time from rising edge of SCLK; Figure 17 --55ns

tsu(SCLK) SCLK set-up time SCLK falling to CS falling 50 - - ns

th(SCLK) SCLK hold time SCLK rising after CS rising 50 - - ns

tPOR power-on reset pulse time time before CS is active

after VDD >V

POR

- - 250 ns

trel(int) interrupt release time after CS go ing LOW; Figure 18 - - 500 ns

tv(INT) valid time on pin INT after INn changes or INT_EN

goes HIGH - 200 800 ns

Fig 13. Timing diagram

SCLK

SDIN

SDOUT

INT

tSPILAG

tWL

tWH

high-impedance

tSPILEAD

MSB in

MSB out

002aac428

tsu(SDIN) th(SDIN)

ten(SDOUT) tv(SDOUT) tdis(SDOUT)

trel(int)

50 % 50 %

tsu(SCLK) th(SCLK)

Product data sheet Rev. 2 — 14 June 2012 17 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

Fig 14. AC waveform for tPOR timing

Fig 15. AC waveform for INT timing

SCLK

SDOUT MSB out

002aad158

tPOR

VPOR 2.5 V

0 V

VDD

MSB − 1

INn

INT_EN

002aaf294

trel(int)

STATE 0 STATE 1 STATE 0

INT

tv(INT) tv(INT)

trel(int)

Product data sheet Rev. 2 — 14 June 2012 18 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

12. Test information

RL= load resistance.

CL= load capacitance includes jig and probe capacitance.

RT= termination resistance should be equal to the output impedance Zo of the pu lse

generators.

Fig 16. Test circ uitry for enable/disable times, SDOUT (ten(SDOUT) and tdis(SDOUT))

Fig 17. Test circuitry for switching times, SDOUT (tv(SDOUT))

Fig 18. Test circuitry for switchi ng time s , IN T

PULSE

GENERATOR

50 pF

10 kΩ

002aac580

VDD

DUT

VDD

open

10 kΩ

PULSE

GENERATOR

50 pF

002aac581

VDD

DUT

PULSE

GENERATOR

50 pF

10 kΩ

002aac582

VDD

DUT

VDD

Product data sheet Rev. 2 — 14 June 2012 19 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

13. Package outline

Fig 19. Package outline SOT355-1 (TSSOP24)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 7.9

7.7 4.5

4.3 0.65 6.6

6.2 0.4

0.3 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT355-1 MO-153 99-12-27

03-02-19

0.25 0.5

0.2

112

24 13

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

max.

1.1

Product data sheet Rev. 2 — 14 June 2012 20 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

Fig 20. Package outline SOT994-1 (HWQFN24)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT994-1 - - -

MO-220

- - -

SOT994-1

07-02-07

07-03-03

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

UNIT A(1)

max

mm 0.8 0.05

0.00 0.30

0.18 4.1

3.9 2.25

1.95 4.1

3.9 2.25

1.95 2.5 2.5 0.1

DIMENSIONS (mm are the original dimensions)

HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.75 mm

0 2.5 5 mm

scale

b c

0.2

D(1) DhE(1) Ehe

0.5

e1e2L

0.5

0.3

v w

0.05

0.1

B A

terminal 1

index area E

detail X

A1c

1/2 e

AC B

∅ vMC∅ wM

terminal 1

index area

613

127

24 19

Product data sheet Rev. 2 — 14 June 2012 21 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often p referred when through-h ole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 2 — 14 June 2012 22 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

14.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 21) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accord ance with

Table 7 and 8

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 21.

Table 7. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow tempe ratu re (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 8. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow tempe ratu re (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 2 — 14 June 2012 23 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

15. Abbreviations

MSL: Moisture Sensitivity Level

Fig 21. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 9. Abbreviations

Acronym Description

ASSP Application Specific St andard Product

CAN Controller Area Network

CDM Charged-Device Model

DUT Device Under Test

ECU Electronic Control Unit

ESD ElectroStatic Discharge

GPI General Purpose Input

HBM Human Body Model

HS-CAN High-Speed Controller Area Network

LIN Local Interconnect Network

MSB Most Significant Bit

PCB Printed-Circuit Board

PPAP Production Part Approval Process

RC Resistor-Capacitor network

SBC System Basis Chip

SPI Serial Peripheral Interface

μC microcontroller

Product data sheet Rev. 2 — 14 June 2012 24 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

16. Revision history

Table 10. Revision history

Document ID Re lease date Data sheet status Change notice Supersedes

PCA9703 v.2 20120614 Product data sheet - PCA9703 v.1

Modifications: •Section 1 “General description”, fourth paragraph, first sentence changed from “pull-up cycled

applications” to “cyclically supplied pull-up or pull-down applications”

•Section 2 “Features and benefits”, 13th bullet item: deleted phrase “350 V MM per AEC-Q100”

•Section 7 “Functional description”:

–first paragraph, sixth sentence re-written

–third paragraph, third sentence changed from “the pull-up should remain active” to “the pull-up

or pull-down source should remain active”

–third paragraph, sixth sentence changed from “pull-ups can be turned off” to “pull-ups and

pull-downs can be turned off”

–third paragraph, eighth sentence re-written

–third paragraph: added new ninth sentence

•Section 7.3 “Interrupt enable”:

–second sentence re-written

–third sentence: changed from “pull-up should be active” to “pu ll-ups or pull-downs should be

active”

•Section 8.2. 1 “ SBC wake port extension with cyclic biasing”,

–second paragraph: URL is updated

–type number “UJA107x” is replaced with “UJA107xA” (including sub-sections that follow)

PCA9703 v.1 20100223 Product data sheet - -

Product data sheet Rev. 2 — 14 June 2012 25 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short dat a sheet is an extract from a full data sh eet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict wit h the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

17.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applicati ons or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the applica tion or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Not hing in this document may be interpret ed or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyri ghts, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objecti ve specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 14 June 2012 26 of 27

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automo tive use. It i s neither qua lified nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever cust omer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specificat ions.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

17.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PCA9703

18 V tolerant SPI 16-bit GPI with maskable INT

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 June 2012

Document identifier: PCA970 3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

7.1 SPI bus operation. . . . . . . . . . . . . . . . . . . . . . . 6

7.1.1 CS - chip select . . . . . . . . . . . . . . . . . . . . . . . . 6

7.1.2 SCLK - serial clock input . . . . . . . . . . . . . . . . . 6

7.1.3 SDIN - serial data input. . . . . . . . . . . . . . . . . . . 6

7.1.4 SDOUT - serial data output . . . . . . . . . . . . . . . 6

7.1.5 Register access timing . . . . . . . . . . . . . . . . . . . 7

7.1.6 Software reset operation. . . . . . . . . . . . . . . . . . 7

7.2 Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . . 7

7.3 Interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . 8

7.4 General Purpose Inputs . . . . . . . . . . . . . . . . . . 8

7.4.1 VIL, VIH and switching points. . . . . . . . . . . . . . . 9

8 Application design-in inform ation . . . . . . . . . 10

8.1 General application. . . . . . . . . . . . . . . . . . . . . 10

8.2 Automotive application . . . . . . . . . . . . . . . . . . 10

8.2.1 SBC wake port extension with cyclic biasing . 11

8.2.1.1 UJA106x with PCA9703, standby. . . . . . . . . . 11

8.2.1.2 UJA106x with PCA9703, sleep. . . . . . . . . . . . 12

8.2.1.3 UJA107xA with PCA9703, standby and sleep 13

8.2.2 Application examples including switches to

battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 15

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 16

12 Test information. . . . . . . . . . . . . . . . . . . . . . . . 18

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19

14 Soldering of SMD packages . . . . . . . . . . . . . . 21

14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 21

14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 21

14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 21

14.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 22

15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24

17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25

17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 26

18 Contact information . . . . . . . . . . . . . . . . . . . . 26

19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27