Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3 1Publication Order Number:
MC14512B/D
MC14512B
8-Channel Data Selector
The MC14512B is an 8–channel data selector constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. This data selector finds primary
application in signal multiplexing functions. It may also be used for
data routing, digital signal switching, signal gating, and number
sequence generation.
•Diode Protection on All Inputs
•Single Supply Operation
•3–State Output (Logic “1”, Logic “0”, High Impedance)
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range –0.5 to +18.0 V
Vin, Vout Input or Output V oltage Range
(DC or Transient) –0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current
(DC or Transient) per Pin ±10 mA
PDPower Dissipation,
per Package (Note NO TAG) 500 mW
TAAmbient Temperature Range –55 to +125 °C
Tstg Storage Temperature Range –65 to +150 °C
TLLead Temperature
(8–Second Soldering) 260 °C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS
v
(Vin or Vout)
v
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
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A = Assembly Location
WL or L = W afer Lot
YY or Y = Year
WW or W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14512BCP PDIP–16 2000/Box
MC14512BD SOIC–16 48/Rail
MC14512BDR2 SOIC–16 2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14512BCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B 1
16
14512B
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14512B
AWLYWW
MC14512BF SOEIAJ–16 See Note 1.
MC14512BFL1 SOEIAJ–16 See Note 1.
MC14512B
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2
TRUTH TABLE
C B A Inhibit Disable Z
0 0 0 0 0 X0
0 0 1 0 0 X1
0 1 0 0 0 X2
0 1 1 0 0 X3
1 0 0 0 0 X4
1 0 1 0 0 X5
1 1 0 0 0 X6
1 1 1 0 0 X7
X X X 1 0 0
X X X X 1 High
Impedance
X = Don’t Care
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
B
C
Z
DIS
VDD
X7
INH
A
X3
X2
X1
X0
VSS
X6
X5
X4
MC14512B
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3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
V
DD
– 55
_
C 25
_
C 125
_
C
Characteristic Symbol
VDD
Vdc Min Max Min Typ (4.) Max Min Max Unit
Output Voltage “0” Level
Vin = VDD or 0 VOL 5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD
VOH 5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL 5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH 5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH 5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL 5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current Iin 15 — ± 0.1 —±0.00001 ± 0.1 —± 1.0 µAdc
Input Capacitance
(Vin = 0) Cin — — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package) IDD 5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current (5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (0.8 µA/kHz) f + IDD
IT = (1.6 µA/kHz) f + IDD
IT = (2.4 µA/kHz) f + IDD
µAdc
Three–State Leakage Current ITL 15 — ± 0.1 —± 0.0001 ± 0.1 —± 3.0 µAdc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25
_
C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
MC14512B
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4
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25
_
C, See Figure 1) All Types
Characteristic Symbol VDD Typ (8.) Max Unit
Output Rise and Fall T ime
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL 5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay T ime (Figure 2)
Inhibit, Control, or Data to Z tPLH 5.0
10
15
330
125
85
650
250
170
ns
Propagation Delay T ime (Figure 2)
Inhibit, Control, or Data to Z tPHL 5.0
10
15
330
125
85
650
250
170
ns
3–State Output Delay T imes (Figure 3)
“1” or “0” to High Z, and
High Z to “1” or “0”
tPHZ, tPLZ,
tPZH, tPZL 5.0
10
15
60
35
30
150
100
75
ns
7. The formulas given are for the typical characteristics only at 25
_
C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Power Dissipation Test Circuit and Waveform
VDD
ID
CL
Z
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7 VSS
PULSE
GENERATOR
50%Vin 50%
DUTY
CYCLE
MC14512B
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5
Parameter Test Conditions
Inhibit to Z A, B, C = VSS, XO = VDD
A, B, C to Z Inh = VSS, XO = VDD
Figure 2. AC Test Circuit and Waveforms
VDD
VSS
VOH
VOL
VDD
VSS
VOH
VOL
V
DD
CL
Z
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
VSS
PULSE
GENERATOR
20 ns 20 ns
90%
50%
10%
tPLH tPHL
90%
10%
50%
DATA
Z
tTLH tTHL
TEST CONDITIONS:
INHIBIT = VSS
A, B, C = VSS
20 ns 20 ns
tPHL tPLH
50%
90%
10%
tTHL tTLH
Z
INHIBIT,
A, B, OR C 90%
50%
10%
Figure 3. 3–State AC Test Circuit and Waveform
Test S1 S2 S3 S4
tPHZ Open Closed Closed Open
tPLZ Closed Open Open Closed
tPZL Closed Open Open Closed
tPZH Open Closed Closed Open
Switch Positions for 3–State Test
Z
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
VSS
PULSE
GENERATOR
VDD
VDD
CL
1k S1
S2
VSS
VDD
S3
S4
VSS
VDD
VOH
VOL
20 ns
90%
50%
10%
tPLZ tPZL
20 ns
DISABLE
INPUT
OUTPUT
OUTPUT
VSS
VOH
VOL
10%
90%
90%
10%
tPHZ tPZH
≈2.5 V @ VDD = 5 V,
10 V, AND 15 V
≈2 V @ VDD = 5 V
≈6 V @ VDD = 10 V
≈10 V @ VDD = 15 V
MC14512B
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6
LOGIC DIAGRAM
13
12
11
1
2
3
4
5
6
7
9
X7
X6
X5
X4
X3
X2
X1
X0
B
C
A
15
10
14
DISABLE
INHIBIT
VDD
Z
VSS
11
IN OUT IN
2
OUT
2
TRANSMISSION
GATE
SELECTED
DEVICE
MC14512B
MC14512B
MC14512B
IOD
ITL
ITL
ILLOAD
DATA
BUS
3–STATE MODE OF OPERATION
Output terminals of several MC14512B 8–Bit Data
Selectors can be connected to a single date bus as shown.
One MC14512B is selected by the 3–state control, and the
remaining devices are disabled into a high–impedance “off”
state. The number of 8–bit data selectors, N, that may be
connected to a bus line is determined from the output drive
current, IOD, 3–state or disable output leakage current, ITL,
and the load current, IL, required to drive the bus line
(including fanout to other device inputs), and can be
calculated by:
ITL
N = + 1
IOD – IL
N must be calculated for both high and low logic state of the
bus line.
MC14512B
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7
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
MC14512B
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8
PACKAGE DIMENSIONS
HE
A1
DIM MIN MAX MIN MAX
INCHES
––– 2.05 ––– 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
––– 0.78 ––– 0.031
A1
HE
Q1
LE
_
10
_
0
_
10
_
LEQ1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION A T MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
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MC14512B/D
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