aan Zhe FuOn- 7A > SU SEMICONDUCTOR FUATSU SEMICONDUCTOR] AQ 0 mi Ae | DS05-20812-1E gm FLASH MEMORY CMOS 4M (512K x 8/256K x 16) MBM29F400TA/MBM29F400BA ory i m DISTINCTIVE CHARACTERISTICS 5.0 V + 10% read, write and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as E?PROMs Compatible with JEDEC-standard word-wide pinouts 7 48-pin TSOP (Package suffix: PETN Normal Bend Type, PFTR - Reversed Bend Type) 44-pin SOP (Package suffix: PF) . Minimum 100,000 write/erase cycles High performance 70 ns maximum access time Sector erase architecture - One 16 Kbyte, two 8 Kbytes, one 32 Kbyte and seven 64 Kbytes. Any combination of sectors can be cancurrently erased. Also supports full chip erase. Embedded Erase Algorithms ~ _ Automatically pre-programs and erases the chip or any sector Embedded Program Algorithms Automatically writes ang verifies data at specified address Data Polling and Toggle Sit feature for detection of program or erase cycle completion Low power consumption 20 mA typical active read current for Byte Mode 28 mA typical active read current for Word Mode 30 mA typical write/erase current 25 pA typical standby current Low Vcc write inhibit < 3.2 V Sector protection Hardware method disables any combination of sectors from write or erase operations Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device Boot Code Sector Architecture T=Top sector B=Bottom sector Embedded Erase, Embedded Program and ExpressFlash are trademarks of Advanced Micro Devices, Inc.| BM29F400TA/400BA M eee m GENERAL DESCRIPTION The MBM29F400TA/BA is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each or 256K words of 16 bits each. The MBM29F400TA/BA is offered in a 48-pin TSOP and 44-pin SOP packages. This device is designed to be programmed in-system with the standard system 5.0 V Vcc supply. A 12.0 V Ver is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The MBM29F400TA/BA is erased when shipped from the factory. The standard MBM29F400TA/BA offers access times between 70 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE) and output enable (OE) controls. The MBM29F400TA/BA is pin and command set compatible with JEDEC standard AM-bit E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices. The MBM29F400TA/BA is programmed by executing the program command sequence. This will invoke the Em- bedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in less than one second. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The entire chip or any individual sector is typically erased and verified in 1.5 seconds (if already completely preprogrammed.) This device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device features single 5.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low Vcc detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ, by the Toggle Bit feature on DQe, or the RY/BY pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability and cost effectiveness. The MBM29F400TA/BA memory electrically erases the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/ word at a time using the EPROM programming mechanism of hot electron injection.ae a f MBM29F400TA/400BA m PRODUCT SELECTOR GUIDE Part Nos ~ MBM29F-400TA/MBM29F400BA Ordering Part No: Max Access Time (ns) CE (E) Access (ns) OE (G) Access (ns) m BLOCK DIAGRAM DQo to DQis RY/BY Buffer Vec __e Vss Erase Voltage Input/Output Generator Buffers . WE State BYTE" Control RESET Command | Register Program Voltage - Generator Chip Enable | r Output Enable STB} Data Latch CE >| Logic | OE - | pd STB Y-Decoder > Y-Gating V cc Detector Timer Address Latch X-Decoder Cell Matrix Ao to A17 = A-1MBM29F400TA/400BA .. m PACKAGE (FPT-48P-M20) 48-pin TSOP (FPT-48P-M19) 44-pin SOP - lageMBM29F400TA/400BA m@ CONNECTION DIAGRAMS NC RY/BY Ar Ao As As Ai Ao CE Vss OE DQo DQs DQ: DQs DQz DQio DQs DQn CIPI ICI Iara Pa ap Pa PP a Pa Pe SOP mr 10 44 2 43 3 42 4 4 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 TSOP Ais (-] 1 48 {_] Ars ] RESET Au Cd 2 47 (0 BYTE WE Ai C7] 3 46 [(_] Vss Ai C_] 4 45 [] DQ is/A-1 | As Auf} 5 44 [7] DQ; Aw CC] 6 43 [77] DO iz As] 7 42 [_] DQs As (_j 8 41 (7) DQis | Ato NCL] 9 40 [J 0Qs NC [7] 10 39 [7 DQ P} An WEC] 1 38 [=] DQs RESET Co] 12 MBM29F400TA/MBM29F400BA 37 [1] Veo | Anz NC C7] 13 Standard Pinout 36 [J 0Qn NC (J 14 35 [] 0Qs Ass RY/BY (J 15 34 [J] DQi NC C_] 16 33 [) DQ2 | Au Air CJ 17 32 [-] DQs | Ar] 18 31 (1) DQ) Ais As (_] 19 30 {-_] DQs il Ate As [] 20 29 [1 DQo Aa CJ 21 28 [1 OE As CJ 22 27 [- Vss ] BYTE A2 | 23 26 [ICE a Vss Ai CI 24 25 [__} Ao f] Da wA-t i DQ; Ae(T]1 VY 48 [_] Ais BYTE (-} 2 47 [1] Aus [] Das. Vss ("] 3 46 [2] Ar r pa DQ wA-1 C7] 4 45 [Ar DQ; [7] 5 44 (7) An |] DQis DQu 7) 6 43 [7] Aw DQs (1) 7 42 [7 As i DQs DQis C7 8 41 [7 As DQs (-} 9 40 (J NC |] DQ: DQiz [4 10 39 [7] NC DQ. (7 11 38 (FI WE |] Da. Vec C] 12 MBM29F400TA/MBM29F400BA _ 37 [-) RESET DQn (J 13 Reverse Pinout 36 (0 NC || Vee DQs CJ] 14 35 [LINC DQ C7] 15 34 [-9 RY/BY DQ2 CJ] 16 33 (NC DQs [J 17 32 [7 Aw DQ: (74 18 31 (I Ar DQs [7] 19 30 [--) As DQo [} 20 29 [7] As OE Cj 21 28 [1 Aa Vss [] 22 27 [J As CE 23 26 [__] Az Ao 24 25 [IAMBM29F400TA/400BA m LOGIC SYMBOL 18 A-1 Ao to Ai7 CE (E) OE (G) WE (W) RY/BY RESET BYTE DQo to DQ is 160r8 Table 1 MBM29F400TA/BA Pin Configuration va dg ed ot 7 Bin? oan . a Funetion Bk A-1, Aato A17 | Address Inputs DQo to DQis | Data Input/Output CE Chip Enable OE Output Enable WE Write Enable RY/BY Ready-Busy Input RESET Hardware Reset Pin/Sector Protect Unlock BYTE Selects 8-bit or 16-bit mode NC No Internal Connection Vss Device Ground Veo Device Power Supply (5.0V10% or +5%)MBM29F400TA/400BA m@ ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number (Valid Combination) is formed by a combination of: MBM29F400 TA -70 PFTN PACKAGE TYPE PFTN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout PF = 44-Pin Small Outline Package SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE TA = Top sector BA = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29F 400 4Mega-bit (512K x 8-Bit or 256K x 16-Bit) CMOS Fiash Memory 5.0 V-only Read, Write and Erase Valid Combinations Valid Combinations . Valid Combinations list configurations planned to be sup- MBM29F400T A/BA-70 ported in volume for this device. Consult the local Fujitsu MBM29F 400TA/BA-90 PFTN, PFTR, PF sales office to confirm availability of specific valid combi- nations and to check on newly released combinations. MBM29F400TA/BA-120MBM29F400TA/400BA Table 2 MBM29F400TA/BA User B us Operations (BYTE = Vin) Operation OT GE OE L WE [Moh Ar | As | As [poate Dass RESET Auto-Select Manufacturer Code (1) L}t]H] ot} Leic lwo] Code H Auto-Select Device Code (1) L L H H L L Vip Code H Read (3) L L H | Ao} At: As | Ag Dout H Standby H X X X xX X X HIGH-Z H Output Disable L H H X X X X HIGH-Z H Write L H L Ao | At As | Ag Din H Enable Sector Protect (2) L Vio L x x ! xX Vio xX H Verify Sector Protect (2) L L H L H L Vio Code H Temporary Sector Unprotect X X X Xx X Xx X X Vio Reset (Hardware)/Standby X Xx X X X x xX HIGH-Z L Table 3 MBM29F400TA/BA User Bus Operations (BYTE = Vit) "Operation 2. PGE Le | WEL -Aach ae Tas _[ Ae | DQo to'DQr| RESET Auto-Select Manufacturer Code (1) L L H L L L Vip Code H Auto-Select Device Code (1) L L H H L L Vio Code H Read (3) L L H Ao | At As | Ag Dout H Standby H X X x X X X HIGH-Z H Output Disable L H H xX X X x HIGH-Z H Write L H L Ao | Ar | As | Ag Din H Enable Sector Protect (2) L Vio L x xX Xx Vio x H Verify Sector Protect (2) L L H L H L Vio Code H Temporary Sector Unprotect X x X X X X X Xx Vio Reset (Hardware)/Standby X Xx X X X Xx x HIGH-Z L Legend: L = Vi, H = Vin, X = Don't Care. See DC Characteristics for voltage levels. Notes: 1, Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 7. 2. Refer to the section on Sector Protection. 3. WE can be Vit if OE is Vi, OE at Vin initiates the write operations.MBM29F400TA/400BA Read Mode The MBM29F400TAVBA has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tacc) is equal to the delay from stable addresses to valid output data. The chip enable access time (tce) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses have been stable for at feast tacc-toe time). Standby Mode The MBM29F400TA/BA has two standby modes, a CMOS standby mode (CE input held at Vcc + 0.5 V), when the current consumed 1s less than 100 pA; and a TTL standby mode (CE is held at Vin) when the current required is reduced to approximately 1 mA. In the standby mode the outputs are in a high impedance state, independent of the OE input. If the device is deselected during erasure or programming, the device will draw active current until the operation is completed. Output Disable With the OE input at a logic high level (Vin), output from the device is disabled. This will cause the output pins to be ina high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force Vin (11.5 V to 12.5 V) on address pin As. Two identifier bytes may then be sequenced from the device outputs by toggling address Ao from Vit to Vin. All ad- dresses are don't cares except Ao, Ai and Ae. The manufacturer and device codes may also be read via the command register, for instances when the MBM29F400TA/BA is erased or programmed in a system without access to high voltage on the Ag pin. The com- mand sequence is illustrated in Table 7 (refer to Autoselect Command section). Byte 0 (Ao = Vit) represents the manufacturer's code (Fujitsu = 04H) and byte 1 (Ao = Viv) the device identifier code (MBM29F400TA = 23H and MBM29F400BA = ABH for x8 mode; MBM29F400TA = 2223H and MBM29F400BA = 22ABH for x16 mode). These two bytes/words are given in the table below. All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect, Ai must be Vit (see Tables 4.1 and 4.2). 10 eMBM29F400TA/400BA Table 4.1 MBM29F400TA/BA Sector Protection Verify Autoselect Codes Self Type Ayatodar bos As AN ag OS > Gode (HEX) Manufacturer's Code xX VIL Vir Vit 04H Byte 23H MBM29F400TA x Vit Vit ViH MBM29F400A Word 2223H Device Bvt Code yle ABH MBM29F400BA X Vit Vit Vin Word 22ABH . Sector Sector Protection Addresses Vit Vin Vit O1H *Outputs 01H at protected sector addresses Table 4.2 Expanded Autoselect Code Table S775 Type -., | Gade [OGs/0q/00 Dds Ddss|OQio} Dae BOs | NGr DOs | DOs! NGs/ DAs} DA2| DQ: |Nds Manufacturer's Code O4H]} 0}/0!10/;/0/0;0}0)/0);0;0/0),0;, 03 1 0 | 0 MBM29F400TA (B)} 23H! A-t [HI-Z}HI-Z/HI-Z|HI-Z}HI-Z}HI-Z}HI-Z} 0 | O} 1} 0) 0;]04 144 MBM29F400A w)}2223H} 0} 0} 1}/o0;o0;/o0}]1]}/o0;}0;/0}1};0]o0}o}1]1 Device Code MBM29F400BA (B)} ABH] A-t |HI-Z|HI-Z{HF-Z|HE-Z}HFZ}HI-Z}HI-Z} 1} 04; 1) 0] 41; 0/] 4 44 wl22aABH} Oj; 0; 1/o0}o;o]i1}o}1}o}1foj;ry;o;1]t Sector Protection O1H} O10/)/0/0}/0;0]/0;0};0;/0/0}]0;0;,0;,0)1 (B): Byte mode (W): Word mode Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register Is written by bringing WE to Vit, while CE 1s at Vi and OE is at Vin. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE , whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Protection The MBM29F400TA/BA features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 10). The sector protect feature is enabled using programming equipment at the user's site. The device is shipped with all sectors unprotected. Alternatively, Fujitsu may program and protect sectors in the factory prior to shipping the device (AMD's Express Flash service). 1MBM29F400TA/400BA To activate this mode, the programming equipment must force Vio on address pin As and control pin OE , (suggest Vio = 11.5 V) and CE = Vit. The sector addresses (A17, Ais, A1s, A14, Ats, and Aiz) should be set to the sector to be protected. Tables 5 and 6 define the sector address for each of the eleven (11) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE VE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. Refer to figures 14 and 20 for sector protec- tion algorithm and waveforms. To verify programming of the protection circuitry, the programming equipment must force Vio on address pin Ag with CE and OF at Vu and WE at Vin. Scanning the sector addresses (A17, A1s, Ais, A1a, Ai3. and At2) while (Ae, A1, Ao) = (0, 1, 0) will produce a logical 1 code at device output DQo for a protected sector. Otherwise the device will produce OOH for unprotected sector. In this mode, the lower order addresses, except for Ao, Ai and As are don't care. Address locations with A1 = Vit are reserved for Autoselect manufacturer and device codes. It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02H, where the higher order addresses (A17, A1s, A15, Ai4, Ai3 and A12) are the sector address will produce a logical 1 at DQo for a protected sector. See Table 4.1 for Autoselect codes. Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors of the MBM29F400TA/BA device in order to change data. The Sector Unprotect mode is activated by setting the RESET pin to high voltage (12V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the 12V is taken away from the RESET pin, all the previously protected sectors will be protected again. Sector Unprotect The MBM29F400TA/BA also features a sector unprotect mode, so that a protected sector may be unprotected to incorporate any changes in the code. All sectors should be protected prior to unprotecting any sector. To active this mode, the programming equipment must force Vio on control pin OE and address pin As. The CE and Ao pins must be set at Vit. Pins As and Ai must be set to Vin. Refer to Figure 21 for the sector unprotect algorithm. The unprotection mechanism begins on the falling edge of theWE pulse and is terminated with the rising edge of the same. It is also possible to determine if a sector is unprotected in the system by writing the autoselect command and As is set at Vit. Performing a read operation at address location XXX2H, where the higher order addresses (Ai17, Ais, A1s, Aia, A13 and A12) define a particular sector address, will produce OOH at data outputs (DQo to DQ7) for an unpro- tected sector. Command Definitions Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (BO) and Erase Resume (30) commands are valid only while the Sector Erase operation is in progress. Either of the two reset commands will reset the device (when applicable). Please note that commands are always written at DQo to DQ7 and DQs to DQis bits are ignored. 12 eMBM29F400TA/400BA Table 5 Sector Address Tables (MBM29F400TA) Berton Agr * Ass - 2 Ate ok Ate As . Ase SAE. Address Range SAQ 0 0 0 X X X O0O0000h-OFFFFh SA1 0 0 1 X X X 10000h-1FFFFh SA2 0 1 0 X X X 20000h2FFFFh SA3 0 1 1 X X X 30000h3FFFFh SA4 1 0 0 x X X 40000h-4FFFFh SA5 1 0 1 X X X 50000h5FFFFh SA6 1 1 0 X X X 60000h6FFFFH SA7 1 1 1 0 X X 70000h77FFFh SA8 1 1 1 1 0 0 78000h79FFFh SAQ 1 1 1 1 0 1 7AQ00h-7BFFFh SA10 1 1 1 1 1 X 7C000h-7FFFFh Table 6 Sector Address Tables (MBM29F400BA) Seer ae | ae fom | Aes | aa | Ai, | <S*Address Range SA0 0 0 0 0 0 X 00000h03FFFh SAI 0 0 0 0 1 0 04000h-O5FFFh SA2 0 0 0 0 1 1 06000h-07FFFh SA3 0 0 0 1 X X OQ8000h-OFFFFh SA4 0 0 1 X X x 10000h-1FFFFh SA5 0 1 0 X X X 20000h-2FFFFh SA6 0 1 1 X X X 30000h-3F FFFh SA7 1 0 0 X X X 40000h4FFFFh SA8 1 0 1 X X X 50000h-5FFFFh SA9 1 1 0 X x X 60000h-6FFFFh SA10 1 1 1 xX X X 70000h7FFFFh 13MBM29F400TA/400BA Table 7 MBM29F400TA/BA Command Definitions - comnisna |S, Fifet Bus <-| Second BUS | {Third Bus | FOUMENS ith Bus) Sixth Bus ry me | Wri |} Write. Cycle! Write Cycle | 7 -* -| Write Cycle | Write Cycle Sequence * [gy] Mite Sie | Weta CHee,| Wile PrP. 1 oyeia | MER RR ME - Read/Reset .. PRead oy ~~. wos Et ea S = anf a ree . ob | Addr | Data | Addr Dala Addr Data Addr | Data Addr. Dala | Addr; Bata Read/Reset WO] 1 }oomxt| FOH | Byte Word 5555H 2AAAH 5555H Read/Reset Byte 4 AAH 5656H 55H FOH | RA RD Word 5555H 2AAAH 5555H Autoselect Byte 4 AAAAH AAH 5555H 55H NAAAH 90H Program Byte 4 ESSE) AAH eat 55H |229 q AOH | PA | Data Word 5555H 2AAAH 5555H 5555H 2AAAH 5555H Chip Erase Byte 6 AAH 5555H 55H ; 4 80H | AAH 5555H 55H NADH 10H Sector Erase Byte 6 BBect AAH ee SSH Soest 80H S585 aa ZOABH 5sH | SA | 30H Sector Erase Suspend Erase can be suspended during sector erase with Addr (don't care). Data (BOH) Sector Erase Resume Erase can be resumed after suspend with Addr (don't care). Data (80H) Notes: 1. Address bit Ais = X = Don't Care for all address commands except or Program Address (PA) and Sector Address (SA). Write Sequences may be initiated with A1s in either state. 2. Address bit A1e = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA). 3. Bus operations are defined in Table 2 and 3. 4. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A16, Ais, A14, Ai3 and Ai2 will uniquely select any sector. 5. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of WE. 6. The system should generate the following address patterns: Word Mode: 5555H or 2AAAH to addresses Ao to A14 Byte Mode: AAAAH or 5555H to addresses A-1 to Ata Read/Reset Command The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. 14MBM29F400TA/400BA Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manu- facture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising Ag to a high voltage. However, multiplexing high voltage onto the address lines 1s not generally desired system design practice. The device contains an autoselect command operation to supplement traditional PROM programming methodol- ogy. The operation is initiated by writing the autoselect command sequence into the command register. Following the command write, a read cycle from address XXOOH retrieves the manufacture code of 04H. A read cycle from address XX01H returns the device code (MBM29F400TA = 23H and MBM29F400BA = ABH for x8 mode; MBM29F400TA = 2223H and MBM29F400BA = 22ABH for x16 mode). (See Tables 4.1 and 4.2.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Scanning the sector addresses (A17, Ais, Ais, Ata, A13 and A12) while (As, A1, Ao) = (0, 1, 0) will produce a logical 1 at device output DQe for a protected sector. To terminate the operation, it is necessary to write the read/reset command sequence into the register. Byte/Word Programming The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two unlock write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ? is equivalent to data written to this bit (see Write Operation Status section) at which time the device returns to the read mode and addresses are no longer latched. Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being pro- grammed. Any commands written to the chip during this period will be ignored. Programming is allowed in any sequence and across sector boundaries. Beware that a data O cannot be pro- grammed back to a 1. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from reset/read mode will show that the data is still 0. Only erase operations can convert Os to 1"s. Figure 16 illustrates the Embedded Programming Algorithm using typical command strings and bus Operations. Chip Erase Chip erase is a six bus cycle operation. There are two unlock write cycles. These are followed by writing the set- up command. Two more unlock write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is 1 (see Write Operation Status section) at which time the device returns to read the mode. Figure 17 illustrates the Embedded Erase Algorithm using typical command strings and bus operations. 15MBM29F400TA/400BA Sector Erase Sector erase is a six bus cycle operation. There are two unlock write cycles. These are followed by writing the set-up command. Two more unlock write cycles are then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (Data=30H) is latched on the rising edge of WE. A time-out of 50 ps from the rising edge of the last sector erase command will initiate the sector erase command(s). Multiple sectors may be erased sequentially by writing the six bus cycle operations as described above. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concur- rently erased. The time between writes must be less than 50 ps otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condi- tion. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 ps from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the 50 ps time-out window the timer is reset. (Monitor DQs to determine if the sector erase timer window is still open, see section DQs, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once execution has begun will corrupt the data in that sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 10). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the 50 ps time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ is 1 (see Write Operation Status section) at which time the device returns to the read mode. Data polling must be performed at an address within any of the sectors being erased. Figure 17 illustrates the Embedded Erase Algorithm using typical command strings and bus operations. Erase Suspend Erase Suspend command allows the user to interrupt the chip and then perform data reads (not program) froma non-busy sector during a Sector Erase operation (which may take up to several seconds). This command is appli- cable ONLY during the Sector Erase operation and will be ignored if written during the chip Erase or Programming operation. The Erase Suspend command (BOH) which is allowed only during the Sector Erase Operation includes the sector erase time-out period after the Sector Erase commands (30H). Writing this command during the time-out will result in immediate termination of the time-out period. Any subsequent writes of the Sector Erase command will be taken as the Erase Resume command. Note that any other commands during the time out will reset the device to read mode. The addresses are don't-cares when writing the Erase Suspend or Erase Resume commands. When the Erase Suspend command is written during a Sector Erase operation, the chip will take between 0.1 1s to 15 ps to suspend the erase operation and go into erase suspended read mode (pseudo-read mode), during which the user can read from a sector that is NOT being erased. A read from a sector being erased may result in invalid data. The user must monitor the toggle bit (DQ) to determine if the chip has entered the pseudo-read mode, at which time the toggle bit stops toggling. An address of a sector NOT being erased must be used to read the toggle bit, otherwise the user may encounter intermittent problems. Note that the user must keep track of what state the chip is in since there is no external indication of whether the chip is in pseudo-read mode or actual read mode. After the user writes the Erase Suspend command, the user must wait until the toggle bit stops toggling before data reads from the device can be performed. Any further writes of the Erase Suspend command at this time will be ignored. 16MBM29F400TA/400BA Every time an Erase Suspend command followed by an Erase Resume command is written, the internal (pulse) counters are reset. These counters are used to count the number of high voltage pulses the memory cell requires to program or erase. If the count exceeds a certain limit, then the DQs bit will be set (Exceeded Time Limit flag). This resetting of the counters is necessary since the Erase Suspend command can potentially interrupt or disrupt the high voltage pulses. To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Write Operation Status Table 8 Hardware Sequence Flags Status +) 20 ESA Gr pep DOs s{P DAs <]DAs* | DGz ta DQe In Progress Auto-Programming DQ? Toggle 0 0 D) . (Note 1) Program/Erase in Auto Erase 0 Toggle 0 1 Auto-Programming DQ7 Toggle 1 1 _ Exceeded (D) Time Limits ProgramVErase in Auto-Erase 0 Toggle 1 1 (Note 1) Notes: 1. DQo, DQ: and DQz2 are reserve pins for future use. 2. DQs to DQis5 = Don't Care for x16 mode. 3. DQs is for Fujitsu internal use only. DQ; Data Polling The MBM29F400TA/BA device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a O at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a 1 at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 18. For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the MBM29F400TAVBA data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ; output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQo to DQs may be still invalid. The valid data on DQo to DQ7 will be read on the successive read attempts. 17MBM29F400TA/400BA The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out (see Table 8). See Figure 8 for the Data Polling timing specifications and diagrams. DQe Toggle Bit The MBM29F400TA/BA also features the Toggle Bit as a method to indicate to the host system that the Embed- ded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will result in DQs toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQs will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 ys and then stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 ps and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQe to toggle. In addition, an Erase Suspend/Resume command will cause DQs to toggle. See Figure 9 for the Toggle Bit timing specifications and diagrams. DQs Exceeded Timing Limits DQs will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQs will produce a 1. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in Table 2 and 3. If this failure condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this failure condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. It this failure condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). The DQs failure condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ bit and DOs never stops toggling. Once the device has exceeded timing limits, the DQs bit will indicate a 1. Please note that this 1s not a device failure condition since the device was incorrectly used. 18MBM29F400T A/400BA DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQs will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase com- mand sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If DQ3 is low (0), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQs were high on the second status check, the command may not have been accepted. Refer to Table 8: Hardware Sequence Flags. RY/BY Ready/Busy The MBM29F400TA/BA provides a RY/BY output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands. If the MBM29F400TA/BA is placed in an Erase Suspend mode, the RY/BY output will be high. Also, since this is an open drain output, many RY/BY pins can be tied together in parallel with a pull up resistor to Vcc. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin should be ig- nored while RESET 's at Vit. Refer to Figure 13 fora detailed timing diagram. RESET Hardware Reset The MBM29F400TA/BA device may be reset by driving the RESET pin to Vit. The RESET pin has a pulse require- ment and has to be kept low (Vi) for at least 500 ns in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset 20 ps after the RESET pinis driven low. Furthermore, once the RESET pin goes high, the device requires an additional 50 ns before it will allow read access. When the RESET pinis low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. Refer to Figure 11 for the timing diagram. Refer to Temporary Sector Unprotect for additional functionality. Byte/Word Configuration The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29F400TA/BA device. When this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQo to DQ15. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, the DQ:15/A-1 pin becomes the lowest address bit and DQe to DQus bits are tristated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQo to DQ7 and the DQs to DQ15 bits are ignored. Refer to Figures 12 and 13 for the timing diagram. 19MBM29F400TA/400BA Data Protection The MBM29F400TA/BA is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting form Vcc power-up and power-down transitions or system noise. Low Vcc Write Inhibit To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 3.2 V (typically 3.7 V). If Voc < Viko, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the Vcc level is greater than Viko. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 3.2 V. Write Pulse Glitch Protection Noise pulses of less than 5 ns (typical) on OE, CE or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = Vu, CE = Vin or WE = Vin. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the device with WE = CE =Vi. and OE = Vin will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. 20MBM29F400TA/400BA m ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages ............:.seseccssereeeeseeees 65C to +125C Ambient Temperature with Power Applied ............csseseseeereees -55C to +125C Voltage with Respect to Ground All pins except As (Note 1)...... -2.0Vto+7.0V VicG (NOt@ 1) .0..... ec ccececesseeececceeseseseeoseaeceessseeasessseeeeensesesaenensneesnees -2.0V to +7.0V Aa (NOG 2) vo... ccc cesccessseeceesnceeceeeeeesseteeenecsancersacenaueessaesneaesecensosanes -2.0V to +14.0V Output Short Circuit Current (Note 3) oo... es eeeececeeeseeseeeneeneees 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may negative overshoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is Vcc +0.5 V. During voltage transitions, outputs may overshoot to Vcc +2.0 V for periods of up to 20 ns. 2. Minimum DC input voltage on As pin is -0.5 V. During voltage transitions, As may negative overshoot Vss to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on As is +13.5 V which may overshoot to 14.0 V for periods of up to 20 ns. 3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. m@ OPERATING RANGES Commercial Devices Ambient Temperature (TA) 0... ceecceescsesseeesssesnsseesaseceseeeeeseeenseas 0C to +70C Vcc Supply Voltages Voc for MBM29F400TA-70/BA-70 ..... ec eeeeeeseeseececesseesteeenssesaesens +4.75 V to +5.25 V Vcc for MBM29F400TA-90, 12 /BA-90, 12.0... lee ece tee teeteeeee +4.50 V to +5.50 V Operating ranges define those limits between which the functionality of the device is guaranteed. 21MBM29F400TA/400BA m@ MAXIMUM OVERSHOOT r+20 ns f* 20 ns 20 ns > rey OXON. LZ -0.5V -2.0V Figure 1 Maximum Negative Overshoot Waveform Vcc +2.0V Vcc +0.5V 20V Yo NANAK 20 ns >] Figure 2 Maximum Positive Overshoot Waveform 22MBM29F400TA/400BA m@ DC CHARACTERISTICS + TTLINMOS Compatible Paramter| pdameter Daseription copes : rest Conditions yn. | Min: Max. | unit Symbol pe ES . we es fa ME ane wee SE Byer spt Ep lu input Leakage Current Vin = Vss to Vec, Voc = Vec Max +1.0 pA uit Ag Input Leakage Current Vcc = Vcc Max, Ag = 12.5V 50 BA lLo Output Leakage Current Vout = Vss to Vee, Vec = Vec Max | +1.0 pA lect Vcc Active Current (Note 1) CE = Vit, OF = Vin Byte | 40 mA Word 50 lcc2 | Vcc Active Current (Note 2, 3) CE = Vit, OE = Vin 60 mA lec3 Vcc Standby Current Voc = Vec Max, CE = Vin, OF = Vin | 1.0 mA Vit Input Low Level ~0.5 0.8 V ViH Input High Level 2.0 | Vcc+0.5| V Vio youae for Autoselect and Sector Voc = 5.0V 115 12.5 V Vou Output Low Voltage fo. = 5.8mA, Vcc = Vcc Min _ 0.45 V Vou Output High Level loH = 2.5mA, Vcc = Vec Min 2.4 _ V ViKo Low Vcc Lock-Out Voltage 3.2 4.2 V Notes: 1. The Icc current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at Vin. 2. Ic active while Embedded Algorithm (program or erase) is in progress. 3. Not 100% tested. 23MBM29F400TA/400BA + CMOS Compatible Parametet!- parameter Description ||: * Test Conditions -:. <<], Min Max. | Unit Symbol es vers es a re ePta ye te tee tt . wf tay . oS fu Input Leakage Current Vin = Vss to Voc, Vcc = Vcc Max +1.0 pA luit Ag Input Leakage Current Vcc = Vcc Max, Ag = 12.5V 50 pA ILo Output Leakage Current Vout = Vss to Voc, Voc = Vec Max +1.0 pA lect Voc Active Current (Note 1) | CE = Vu, OE = Vin Byte 40 mA Word 50 Icca Vcc Active Current (Note 2, 3) CE = Vit, OE = Vin 60 mA Voc = Vec Max, CE = Vect0.5V, Ica Vcc Standby Current OE - Vie, c 100 pA Vit Input Low Level -0.5 0.8 V Vin Input High Level 0.7xVec | Vec+0.3| V Voltage for Autoselect and V = Sector Protect Vec = 5.0V 11.5 12.5 V Vou Output Low Voltage lo. = 5.8 mA, Vcc = Vcc Min _ 0.45 Vv Vout ioH = -2.5 MA, Vcc = Vce Min 0.85Vcc _ V Output High Voltage Von2 lon = -100 pA, Vcc = Vcc Min Vec-0.4 Vv ViKo Low Vcc Lock-out Voltage 3.2 4.2 V Notes: 1. The Icc current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at Vin. 2. Icc active while Embedded Algorithm (program or erase) is in progress. 3. Not 100% tested. 24MBM29F400TA/400BA m@ AC CHARACTERISTICS Read Only Operations Characteristics Parameter [oo so 3c ee eB - Sumas Pe pe 70. cat powieehe Sia ORS Q | ete Wy : AN ti 2 {Note 2) 7} 4 tAVAV | tRC Read Cycle Time (Note 4) Min. 70 90 120 ns CE = Vi tavev |tacc | Address to Output Delay __ Max. 70 90 120 ns OE = Vit teLQv |tce | Chip Enable to Output Delay OE = Vir | Max. 70 90 120 ns tGLQV | {OE Output Enable to Output Delay Max. 30 35 50 ns tEHQz | {DF Chip Enable to Output High-Z (Notes 3, 4) Max. 20 20 30 ns Output Enable to Output High-Z (GHQz | toF (Notes 3, 4) Max. 20 20 30 ns Output Hold Time From Addresses, XOX /10H | GE or OE , Whichever Occurs First Min. 0 0 0 ns READY} RESET pin low to read mode Max. 20 20 20 us tELFL | = . . te.ry | CE Or BYTE switching low or high Max. 5 5 5 ns Notes: 1. Test Conditions: 2. Test Conditions: 3. Output driver disable time. Output Load: 1 TTL gate and 30 pF Output Load: 1 TTL gate and 100 pF 4. Not 100% tested. input rise and fall times: 5 ns Input rise and fall times: 20 ns Input pulse levels: 0.0V to 3.0V Input pulse levels: 0.45V to 2.4V Timing measurement reference level Timing measurement reference level Input: 1.5V Input: 0.8 and 2.0V Output: 1.5V Output: 0.8 and 2.0V 25MBM29F400TA/400BA n OQ < wl IN3064 or Equivalent Device 1 Under | Test IN 6.2 kQ Ct | Notes: For -70. Ci = 30 pF including jig capacitance For all others Cu = 100 pF including jig capacitance IHC *- Figure 3 Test Conditions 2.7 kQ Diodes = IN3064 or Equivalent - Write/Erase/Program Operations Alternate WE Controlledn Writes ye 2 a oe > ss an < a oy . . ged rs a Parameter Symbols} os, Esk A IER Tope es sDeseription - Soke el [arate eg? Pad P unit JEDEG | Standard cose gist Fev ltet LEE plage he aS Sake Ode LAVAV twe Write Cycle Time (Note 3) Min. 70 90 120 ns tAVWL LAS Address Setup Time Min. 0 0 0 ns IWLAX (AH Address Hold Time Min. 45 45 50 ns LDVWH {Ds Data Setup Time Min. 30 45 50 ns IWHDX LDH Data Hold Time Min. 0 0 0 ns tOEs Output Enable Setup Time (Note 3) Min. 0 0 0 ns Output Read (Note 3) Min. 0 0 0 ns tOEH Enable Hold Time! Toggle and Data Polling (Note 3) | Min. 10 10 10 ns Notes: (Continued) 1. This does not include the preprogramming time. 2. These timings are for Sector Protect operation. 3. Not 100% tested. 4. Output Driver Disable Time. 5. These timings are for Sector Unprotect operation. 26MBM29F400TA/400BA (Continued) Parameter Symbols poets, ben? ees ve ed oes Me epee] Pe Desoription <9 Cp es pe POL 9G J 12, | Unit tGHWL (GHWL Read Recover Time Before Write Min. 0 0 0 ns LELWL {cs CE Setup Time Min. 0 0 0 ns tWHEH IcH CE Hold Time Min. 0 0 0 ns tWLWH twP Write Pulse Width Min. 35 45 50 ns tWHWL twPH Write Pulse Width High Min. 20 20 20 ns twHWHi| UWHWHI | Byte Programming Operation Typ. 16 16 16 Ls Typ. 1.5 1.5 1.5 sec twHwH2| (WHWH2 | Erase Operation (Note 1) Max. 30 30 30 sec tvcs Vcc Set Up Time (Note 3) Min. 50 50 50 ps IVLHT Voltage Transition Time (Notes 2, 3, 5) Min. 4 4 4 ps tweP Write Pulse Width (Note 2) Min. | 100 100 100 ps twPP2 Write Pulse Width (Note 5) Min. 10 10 10 ms toesP _| OE Setup Time to WE Active (Notes 2,3,5) |Min.| 4 4 4 us tcsP CE Setup Time to WE Active (Note 3) Min.| 4 4 4 us tRP RESET Pulse Width Min.| 500 | 500 | 500 | ns {FLQZ BYTE Switching Low to Output High-Z (Notes 3, 4)| Max. 20 30 30 ns IBUSY Program/Erase Valid to RD/BY Delay (Note 3) Min. 30 35 50 ns Notes: 1. This does not include the preprogramming time. 2. These timings are for Sector Protect operation. 3. Not 100% tested. 4. Output Driver Disable Time. 5. These timings are for Sector Unprotect operation. 27MBM29F400TA/400BA + Write/Erase/Program Operations Alternate CE Controlled Writes Patameter Syibols oe a ee Pe x 2p Unit JEDEC | Standard | : es LAVAV twe Write Cycle Time (Note 4) Min. 70 90 120 ns LAVEL tas Address Setup Time Min. 0 0 0 ns tELAX AH Address Hold Time Min. 45 45 50 ns {DVEH {Ds Data Setup Time Min.; 30 45 50 ns tEHDX {DH Data Hold Time Min. 0 0 0 ns toEs Output Enable Setup Time Min. 0 0 0 ns Output Enable | Read (Note 4) Min. 0 0 0 ns tOEH Hold Time (Note 4) Toggle and Data Polling Min. 10 10 10 ns 1GHEL tcHEL | Read Recover Time Before Write Min. 0 0 0 ns tWLEL tws WE Setup Time Min.| 0 0 0 ns tEHWH tWH WE Hold Time Min. 0 0 0 ns tELEH tcp CE Pulse Width Min.| 35 45 50 ns tEHEL tCPH CE Pulse Width High Min.} 20 20 20 ns tWHWH1 twHwH! | Byte Programming Operation Typ. 16 16 16 pS Typ.; 1.5 1.5 1.5 sec tWHWH2 twHwu2 | Erase Operation (Note 1) Max.| 30 30 30 sec tvcs Vcc Set Up Time (Note 4) Typ. 50 50 50 ps tRP RESET Pulse Width Min.| 500 500 500 | ns tr.qz__| BYTE Switching Low to Output High-Z (Notes 3, 4)} Max.| 20 30 30 ns tsusy | Program/Erase Valid to RD/BY Delay (Note 4) | Min.| 30 35 50 ns Notes: 1. This does not include the preprogramming time. 2. These timings are for Sector Protect/Unprotect operations. 3. This timing is only for Sector Unprotect. 4. Not 100% tested. 28MBM29F400TA/400BA m SWITCHING WAVEFORMS Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from H to L from H to L May Will Be Change Changing from L toH from L to H Don't Care: Changing Any Change State Permitted Unknown Does Not Center Line Is Apply High- impedance Off State tre | y Addresses x Addresses Stable {acc CE J toe >} (tor) OE ] a WE / (tce) -> High-Z y XY NL. High-Z Outputs 2 Kee Output Valid Sa (ton) 4 Figure 4 AC Waveforms for Read Operations 29MBM29F400TA/400BA 3rd Bus Cycle t Data Polling Addresses X 5555H PA xX lL twe | J tonwe tas XX J \ Sf NE we ft wwe -+ PE RO Data 5.0V Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. Dour is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6. These waveforms are for the x16 mode. Figure 5 Program Operation Timings 30MBM29F400TA/400BA 3rd Bus Cycle Data Polling y a ~~] CAK n twe Tas WE / | be toneL OE \ fe ~ tc [+-___ t wow ~ tcpn ral C Data 5.0V Notes: 1. PA is address of the memory location to be programmed. 2. PD ts data to be programmed at byte address. 3. DQ is the output of the complement of the data written to the device. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6. These waveforms are for the x16 mode. Figure 6 Alternate CE Controlled Program Operation Timings 31MBM29F400TA/400BA | twe | Addresses x 5555H N 2AAAH 5555H xX 5555H xX 2AAAH xX SA x OE \ (we wef iM OW VS VS VS OM he WPH | LDH t /\ /\ /\ /\ Data ton ho] AAH sso \/ 80H \/aAH \/65H \J/10H/30H Vcc { vcs Notes: 1. SA is the sector address for Sector Erase. Addresses = 5555H for Word, AAAAH for Byte. 2. These waveforms are for the x16 mode. Figure 7 AC Waveforms Chip/Sector Erase Operations 32MBM29F400TA/400BA b- LCH yh p* tor e toH High-Z DQ7s g DQ? , OG Valid Data _ | tWHWwuHl of 2 DQo to DOs ' DQo to DQe6=!nvaiid Xeo0 bat *DQ7 = Valid Data (The device has completed the Embedded operation). Figure 8 AC Waveforms for Data Polling during Embedded Algorithm Operations toc LL e VSS VW Dat _ _ DOs= ; PGs @aviobor xX DOs= Toggle x OQs= Toggle M stop Toggling Xo rote DO _ toe *DQs stops toggling (The device has completed the Embedded operation). Figure 9 AC Waveforms for Toggle Bit during Embedded Algorithm Operations 33MBM29F400T A/400BA GE \ . / +/| The rising edge of the last WE signal \/\/ \y Entire programming or erase operations Jone | RY/BY } / leusy Figure 10 RY/BY Timing Diagram during Program/Erase Operations e \ fo . . . oe YXXXK * * RESET Figure 11 RESET/RY/BY Timing Diagram @MBM29F400TA/400BA e \ fo \ a lELFL LELFH ; Data Output Data Output DQo to DQ __~ (DQo to DQ14) A(DQo to Don) Dais \; Address \ DQis/A-1 Ouipat Input ~~ tFLQzZ ! Figure 12 BYTE Timing Diagram for Read Operations CE \ / ! The falling edge of the last WE signal ee _X) tsep - ee (tas) tHoLp (tan) Figure 13 BYTE Timing Diagram for Write Operations 35MBM29F400TA/400BA Ai7, Are Aus, Asa Aus, Ar2 Ao A6 ee peony SV -77 OE t LHT UVLHT twee CoEse Data 01H toe SAX = Sector Address for initial sector SAY = Sector Address for next sector Figure 14 AC Waveforms for Sector Protection 36MBM29F400T A/400BA Air TXT ETTETLTLITL XY 1 VLHT y- ss <s Ae OE _ wert S$ 49 WE Coese CE \ S$ s Data SS 00H 6 Execute Auto Select Command Sequence Figure 15 AC Waveforms for Sector Unprotect 37MBM29F400TA/400BA | EMBEDDED ALGORITHMS Start Y Write Program Command Sequence (See below) Data Polling Device No Increment Address Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555S5H/AAH y 2AAAH/SSH Y 5555H/A0H Y Program Address/Program Data Figure 16 Embedded Programming Algorithm Table 9 Embedded Programming Algorithm Bus Operations * *Gammiand Sequence Bee eo" OS Gomments Standby Write Program Valid Address/Data Sequence Read Data Polling to Verify Programming Standby Compare Data Output to Data Expected "Device is either powered-down, erase inhibit or program inhibit. 38MBM29F400TA/400BA EMBEDDED ALGORITHMS Start Y Sequece (See below) Write Erase Command Data Polling or Toggle Bit Successfully Completed ' Erasure Completed . Individual Sector/Multiple Sector Chip Erase Command Sequence Erase Command Sequence (Address/Command): (Address/Command): 5555H/AAH 5555H/AAH Y Y 2AAAH/SSH 2AAAH/55H Y Y 5555H/80H 5555H/80H Y t 5555H/AAH 5S55H/AAH 2AAAH/55H 2AAAHIS5SH Y Y 5555H/10H Sector Address/30H Y Sector Address/30H Additional sector erase commands are optional Sector Address/30H Figure 17 Embedded Erase Algorithm Table 10 Embedded Erase Algorithm - | Bug Operations . Cammand Sequence Comments Standby* Write Erase Read Data Polling to Verify Erasure Standby Compare Output to FFH *Device is either powered-down, erase inhibit or program inhibit. 33MBM29F400TA/400BA Start ! Read Byte (DQ 0 to DQ?) Addr = VA No Read Byte (DQa to DQ7) Addr = VA DQ7=Data ? Yes VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = XXXXH during chip erase Fail Pass Note: DQ7 1s rechecked even if DQs = 1 because DQ7 may change simultaneously with DQs. Figure 18 Data Polling Algorithm 40MBM29F400TA/400BA Start { VA = Byte address for programming ost ba ) = Any of the sector addresses Addr = VA within the sector being erased during sector erase operation = XXXXH during chip erase = Any address not within the sector in the process of an Erase Suspend operation. Read Byte (DQo to DQ7) Addr = VA Fail Pass Note: DQs is rechecked even if DQs = 1 because DQs may stop toggling at the same time as DQs changing to 1. Figure 19 Toggle Bit Algorithm 41MBM29F400TA/400BA Start Y Set Up Sector Addr A (Az, Ate, Ais, Ara, Ara, Ata) Y PLSCNT = 1 Y OE=Vi, As=Vin, CE=Vir, Increment PLSCNT . PLSCNT = 28? Device Failed Figure 20 Sector Protection Algorithm No RESET =Vin Y Activate WE Pulse Y Time out 100 ps Y Power Down OE WE = Vin, CE =OE=Vun Ag should remain V io y Read from Sector Addr = SA, AiAo= 10, As=0 Yes No Data = 01H ? Yes Protect Another Sector? Remove V0 from As Write Reset Command Sector Protection Completed 42MBM29F400TA/400BA Start Protect All Sectors Y PLSCNT = 1 Y __ Set OE =Ag= Vio CE=Vun,RESET=Vin [** Acs = 1, A: Ao = 10 Y Actate WE Pluse y increment PLSCNT 7 Time Out 10 ms v Set OF = CE = Van Ao=Voio Y Set Up Sector Addr SAO Y Read Data from Device No Increment Sector Addr Data = 00H ? PLSCNT=1000 ? Yes Yes ector Addr = SA10 Yes Device Failed Remove V0 from Ag Y Sector Unprotect Completed Notes: SAO = Sector Address for initial sector SA10 = Sector Address for last sector Please refer to Table 4 for details. Figure 21 Sector Unprotect Algorithm 43MBM29F400TA/400BA m ERASE AND PROGRAMMING PERFORMANCE - Limits). NES Pa . (<. Parameter . f TPT |, {alt Camments . an . : - Min. * ao. Typ. fos Max> ~ ae * ya t . . 1.5 Excludes 00H programming Chip and Sector Erase Time _ (Note 1) 30 sec prior to erasure . . 1000 Excludes system-level over- Byte Programming Time _ 16 (Note 2) ps head . . 8.5 Excludes system-level over- Chip Programming Time _ (Note 1) 50 sec head Erase/Program Cycle 100,000 | 1,000,000 _ Cycles Notes: 1. 25C, 5V Vcc, 100,000 cycles 2. The Embedded Algorithms allow for 48 ms byte program time. m@ LATCHUP CHARACTERISTICS Dseription 2 SS go0t : O Mins obs. Max. Input Voltage with respect to Vss on all I/O pins 1.0V Voc + 1.0V Vcc Current - 100 mA + 100 mA Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. m TSOP PIN CAPACITANCE Parameter OP ON TEL OO Mg ee St, Symbol , - Parameter Description o,. Test Setup Typ. | Max... Unit Cin Input Capacitance Vin = 0 6 7.6 pF Court Output Capacitance Vout = 0 8.5 12 pF Cin2 Control Pin Capacitance Vin =0 8 10 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions Ta = 25C, f = 1.0 MHz 44MBM29F400TA/400BA f" m SOP PIN CAPACITANCE . Pafametr re, tS seme a | une _ Symbol . Parameter Description oo . _ ai est Setup : FyPS Max. Unit CIN Input Capacitance Vin = 0 6 7.5 pF Cout Output Capacitance Vout = 0 8.5 12 pF Cin2 Control Pin Capacitance Vee =0 8 10 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions Ta = 25C, f = 1.0 MHz @ DATA RETENTION need Parameter oo oe, : s : TestCanditions me a . . Min. - Unit. 150C 10 Years C Minimum Pattern Data Retention Time 125C 20 Years 45MBM29F400TA/400BA m PACKAGE DIMENSIONS (Suffix: PFN) (FPT-44P-M16) +t 28 2020 20/1 110% 008) ) RR AAR AARAAARAR ARR ARE O INDEX LEAD No 1.27(.050)NOM _ 0 80+0 20 { 031+ 008) *2133020.20 16 00+0 30 (5242008) (6302 012) EEE *' Resin Protrusin.(Each Side 0 15( 006)MAX) + Resin Protrusin:(Each Side 0 38( 015)MAX) 4 2 80( 110) MAX (MOUNTING HEIGHT) 01500 (006+ 002) 1994 FINITSU LIMITED F48031S-1C-1 oo 10( 004) (28038 blo0.10 con 020570 =25 : = . + 016-#) (STAND OFF) 1994 FUJITSU LIMITED F44022S-1C-1 inches : mm (inches) (Suffix: PFTN) * Resin Protrusin (Each Side 0 15( 006)MAX) (FPT-48P-M19) 1.20(047)_ (MOUNTING HEIGHT) MAX 1.000 05 (039% 002) LEAD No (1) = e amy Fa vem: od srewd =a) \ INDEX pS = ox po pep 0 2240S {@[0 08( 003) B} = PS (009 002 L210 981 008) @ an po is aa = *12.0030.10 | FE ox brs (472.004) | f cm pr it or pe ct orn po i= on ES rt = fo 9. 50( 020 Pes ES rp TYP = = Be e= =@ ; _-[].0 1040 05 20 0020 20( 787 008) _ (0042 002} (STAND OFF) * 19 400 10{ 724+ 004) 0.15520 055 (006 602) a ee 0 6020.10 [JO 10( 004)] MC o24: 604) inches > mm (inches) 46MBM29F400TA/400BA (Suffix: PFTR) (FPT-48P-M20) * Resin Protrusin (Each Side 0.15( 006)MAX) 120(047) (MOUNTING HEIGHT) LEAD No (+) ox L \ INDEX og ay ad aq ag ag og og ag om oy i and a ao aod og = 20 000 20( 787+ 008) * 18 4020 10( 7244-004) 1994 FUJITSU LIMITED F480325-1C-1 MAX 1000 05 (639: 002) =1O) 4 od 1 pr D rr sm) D = 10222005 576 98,003) G) pr r (,009+ 002) = = = *12002010 | feb Er (4724004) | = = it wen) => Eo = _950( 020 po ct TYP Pr) ind =@ 5 0 1020 05 ne poas 00B) (STAND OFF) 0 15520 055 (006 002) 4 0.6030 10 (.024s 004) inches : mm (inches) 47~ SC MBM29F400TA/400BA - eee FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Electronic Devices International Operations Department KAWASAKI! PLANT, 1015, Kamikodanaka Nakahara-ku, Kawasaki-shi, Kanagawa 211, Japan Tel: (044) 754-3753 Fax: (044) 754-3332 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 DreieichBuchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 0718 Tel: 336-1600 Fax: 336-1609 P9502 FUJITSU LIMITED Printed in Japan All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Com- plete Information sufficient for construction purposes is not nec- essarily given. The information contained in this document has been carefully checked and is believed to be reliable. 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