CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1995
SEMICONDUCTOR
1
HA5022/883
Dual 125MHz Video Current
Feedback Amplifier with Disable
Description
The HA5022/883 is a dual version of the popular Harris HA-
5020. It features wide bandwidth and high slew rate, and is
optimized for video applications and gains between 1 and
10. It is a current feedback amplifier and thus yields less
bandwidth degradation at high closed loop gains than volt-
age feedback amplifiers.
The low differential gain and phase, 0.1dB gain flatness, and
ability to drive two back terminated 75Ωcables, make this
amplifier ideal for demanding video applications.
The HA5022/883 also features a disable function that signifi-
cantly reduces supply current while forcing the output to a
true high impedance state. This functionality allows 2:1 video
multiplexers to be implemented with a single IC.
The current feedback design allows the user to take advan-
tage of the amplifier’s bandwidth dependency on the feed-
back resistor. By reducing RF, the bandwidth can be
increased to compensate for decreases at higher closed
loop gains or heavy output loads.
Ordering Information
PART
NUMBER TEMPERATURE
RANGE PACKAGE
HA5022MJ/883 -55oC to +125oC 16 Lead CerDIP
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Dual Version of HA-5020
• Individual Output Enable/Disable
• Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . 125MHz
• Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475V/µs
• Differential Gain. . . . . . . . . . . . . . . . . . . . . . . . . . .0.03%
• Differential Phase. . . . . . . . . . . . . . . . . . . . . . . 0.03 Deg.
• Supply Current (per Amplifier) . . . . . . . . . . . . . . .7.5mA
• Crosstalk Rejection at 10MHz. . . . . . . . . . . . . . . . -60dB
• ESD Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . .2000V
• Guaranteed Specifications at ±5V Supplies
Applications
• Video Multiplexers; Video Switching and Routing
• Video Gain Block
• Video Distribution Amplifier/RGB Amplifier
• Flash A/D Driver
• Current to Voltage Converter
• Radar and Imaging Systems
• Medical Imaging
January 1995
Pinout
HA5022/883
(CERDIP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
-IN1
+IN1
DIS1
V-
DIS2
+IN2
NC
-IN2
OUT1
NC
V+
NC
NC
OUT2
NC
NC
+
-
+
-
Spec Number 511107-883
File Number 3729.1
2
Specifications HA5022/883
Spec Number 511107-883
Absolute Maximum Ratings Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V
Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to V-
Output Current . . . . . . . . . . . . . . . . . . . . Full Short Circuit Protected
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .< 2000V
Storage Temperature Range . . . . . . . . . . . . . .-65oC ≤ TA≤ +150oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
Thermal Resistance θJA θJC
CerDIP Package . . . . . . . . . . . . . . . . . 75oC/W 20oC/W
Maximum Package Power Dissipation at +75oC
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.33W
Package Power Dissipation Derating Factor above +75oC
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.3mW/oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage (±VS) . . . . . . . . . . . . . . . . . . . . ±5V to ±15V
Operating Temperature Range. . . . . . . . . . . . .-55oC≤ TA≤ +125oCVINCM ≤ 1/2(V+ - V-) RL≥ 50Ω
VDISABLE = V+ or 0V RF= 1kΩ
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: VSUPPLY =±5V, AV= +1, RF=1kΩ, RSOURCE = 0Ω, RL = 400Ω, VOUT = 0V, VDISABLE = V+, Unless Otherwise Specified.
PARAMETERS SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Input Offset Voltage VIO VCM = 0V 1 +25oC-33mV
2, 3 +125oC, -55oC-5 5 mV
Common Mode
Rejection Ratio CMRR ∆VCM =±2.5V
V+ = 2.5V, V- = -7.5V
V+ = 7.5V, V- = -2.5V
1 +25oC53- dB
2 +125oC38- dB
∆V
CM =±2.25V
V+ = 2.75V, V- = -7.25V
V+ = 7.25V, V- = -2.75V
3 -55oC38-dB
Power Supply
Rejection Ratio PSRR ∆VSUP =±1.5V
V+ = 6.5V, V- = -5V
V+ = 3.5V, V- = -5V
1 +25oC60- dB
2, 3 +125oC, -55oC55 - dB
Delta Input Offset
Voltage
Between Channels
∆VIO VCM = 0 1 +25oC - 3.5 mV
2,3 +125oC, -55oC - 3.5 mV
Non-Inverting Input (+IN)
Current IBSP VCM = 0V 1 +25oC-88µA
2, 3 +125oC, -55oC -20 20 µA
+IN Current Common
Mode Sensitivity CMSIBP ∆VCM =±2.5V
V+ = 2.5V, V- = -7.5V
V+ = 7.5V, V- = -2.5V
1 +25oC - 0.15 µA/V
2 +125oC - 2.0 µA/V
∆VCM =±2.25V
V+ = 2.75V, V- = -7.25V
V+ = 7.25V, V- = -2.75V
3 -55oC - 2.0 µA/V
∆Inverting Input (-IN)
Current Between
Channels
∆IBSN VCM = 0 1 +25oC -15 15 µA
2, 3 +125oC -30 30 µA
Inverting Input (-IN)
Current IBSN VCM = 0V 1 +25oC -12 12 µA
2, 3 +125oC, -55oC -30 30 µA
3
Specifications HA5022/883
-IN Current Common
Mode Sensitivity CMSIBN ∆VCM =±2.5V
V+ = 2.5V, V- = -7.5V
V+ = 7.5V, V- = -2.5V
1 +25oC - 0.4 µA/V
2 +125oC-5µA/V
∆VCM =±2.25V
V+ = 2.75V, V- = -7.25V
V+ = 7.25V, V- = -2.75V
3 -55oC-5µA/V
-IN Current Power
Supply Sensitivity PSSIBN ∆VSUP =±1.5V
V+ = 6.5V, V- = -5V
V+ = 3.5V, V- = -5V
1 +25oC - 0.2 µA/V
2, 3 +125oC, -55oC - 0.5 µA/V
+IN Current Power
Supply Sensitivity PSSIBP ∆VSUP =±1.5V
V+ = 6.5V, V- = -5V
V+ = 3.5V, V- = -5V
1 +25oC - 0.1 µA/V
2, 3 +125oC, -55oC - 0.3 µA/V
Output Voltage
Swing VOP AV = +1
RL = 150ΩVIN = -3V 1 +25oC 2.5 - V
VIN = -3V 2, 3 +125oC, -55oC 2.5 - V
VON AV = +1
RL = 150ΩVIN = +3V 1 +25oC - -2.5 V
VIN = +3V 2, 3 +125oC, -55oC - -2.5 V
Short Circuit Output
Current +ISC VIN =±2.5V
VOUT =0V 1 +25oC50-mA
2, 3 +125oC, -55oC50 - mA
-ISC VIN =±2.5V
VOUT =0V 1 +25oC - -40 mA
2, 3 +125oC, -55oC - -40 mA
Output Current +IOUT Note 1 1 +25oC20-mA
2, 3 +125oC, -55oC 16.6 - mA
-IOUT Note 1 1 +25oC - -20 mA
2, 3 +125oC, -55oC - -16.6 mA
Quiescent Power
Supply Current ICC RL= 400Ω1 +25oC - 10 mA/Op Amp
2, 3 +125oC, -55oC - 10 mA/Op Amp
IEE RL= 400Ω1 +25oC -10 - mA/Op Amp
2, 3 +125oC, -55oC -10 - mA/Op Amp
Transimpedance +AZOL1 RL= 400Ω
VOUT =±2.5V 1 +25oC1-MΩ
2 +125oC 0.5 - MΩ
VOUT =±2.25V 3 -55oC 0.5 - MΩ
-AZOL1 RL= 400Ω
VOUT =±2.5V 1 +25oC1-MΩ
2 +125oC 0.5 - MΩ
VOUT =±2.25V 3 -55oC 0.5 - MΩ
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: VSUPPLY =±5V, AV= +1, RF=1kΩ, RSOURCE = 0Ω, RL = 400Ω, VOUT = 0V, VDISABLE = V+, Unless Otherwise Specified.
PARAMETERS SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Spec Number 511107-883
4
Specifications HA5022/883
Disabled Output Current +ILEAK VIN = 0V,
VOUT = +2.5V
RL= Open, VDIS =0V
1 +25oC-1µA
2, 3 +125oC, -55oC- 2 µA
-ILEAK VIN = 0V,
VOUT = -2.5V
RL= Open, VDIS =0V
1 +25oC-1µA
2, 3 +125oC, -55oC- 2 µA
Disable Pin Input Current ILOGIC VDIS = 0V 1 +25oC -1.0 - mA
2, 3 +125oC, -55oC -1.5 - mA
Minimum DISABLE Pin
Current to Disable IDIS Note 2 1 +25oC - 350 µA
2, 3 +125oC, -55oC - 350 µA
Maximum DISABLE Pin
Current to Enable IEN Note 3 1 +25oC20- µA
2, 3 +125oC, -55oC20 - µA
Disabled Power Supply
Current ICCDIS RL= Open, VDIS = 0V 1 +25oC - 7.5 mA/Op Amp
2, 3 +125oC, -55oC - 7.5 mA/Op Amp
IEEDIS RL= Open, VDIS = 0V 1 +25oC 7.5 - mA/Op Amp
NOTES:
1. Guaranteed from VOUT Test with RL= 150Ω, by: IOUT =V
OUT/150Ω.
2. RL = 100Ω, VIN = 2.5V. This is the minimum current which must be pulled out of theDisable pin in order to disable the output. The output
is considered disabled when -10mV ≤ VOUT ≤ +10mV.
3. VIN = 0V. This is the maximum current that can be pulled out of theDisable pin with the HA5022/883 remaining enabled. The HA5022/883
is considered disabled when the supply current has decreased by at least 0.5mA.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Table 2 Intentionally Left Blank.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: VSUPPLY = ±5V, AV = +2, RF= 681Ω, RL = 400Ω, Unless Otherwise Specified.
PARAMETERS SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
-3dB Bandwidth BW(+1) AV = +1, RF = 1K
VOUT =100mVRMS
1 +125oC, -55oC 70 - MHz
BW(+2) AV = +2,
VOUT = 100mVRMS
1 +125oC, -55oC 70 - MHz
Gain Flatness GF5 AV = +2, f ≤5MHz
VOUT = 100mVRMS
1 +125oC, -55oC-±0.045 dB
GF10 AV = +2, f ≤10MHz
VOUT = 100mVRMS
1 +125oC, -55oC-±0.085 dB
GF20 AV = +2, f ≤20MHz
VOUT = 100mVRMS
1 +125oC, -55oC-±0.65 dB
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: VSUPPLY =±5V, AV= +1, RF=1kΩ, RSOURCE = 0Ω, RL = 400Ω, VOUT = 0V, VDISABLE = V+, Unless Otherwise Specified.
PARAMETERS SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Spec Number 511107-883
5
Specifications HA5022/883
Slew Rate +SR(+1) AV = +1, RF = 1K
VOUT = -2V to +2V 1, 4 +125oC, -55oC 300 - V/µs
-SR(+1) AV = +1, RF = 1K
VOUT = +2V to -2V 1, 4 +125oC, -55oC 270 - V/µs
+SR(+2) AV = +2, VOUT = -2V to +2V 1, 4 +125oC, -55oC 465 - V/µs
-SR(+2) AV = +2, VOUT = +2V to -2V 1, 4 +125oC, -55oC 350 - V/µs
Rise and Fall Time TRAV = +2, VOUT =-0.5V to -0.5V 1, 2 +125oC, -55oC - 5.5 ns
TFAV = +2, VOUT =+0.5V to +0.5V 1, 2 +125oC, -55oC - 6.0 ns
Overshoot +OS AV = +2, VOUT = -0.5V to +0.5V 1, 3 +125oC, -55oC - 35 %
-OS AV = +2, VOUT =+0.5V to -0.5V 1, 3 +125oC, -55oC - 27 %
Propagation Delay +TPAV = +2, RF = 681Ω
VOUT = 0V to 1V 1, 2 +125oC, -55oC - 10 ns
-TPAV = +2, RF = 681Ω
VOUT = 1V to 0V 1, 2 +125oC, -55oC - 9.5 ns
NOTES:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These param-
eters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization
based upon data from multiple production runs which reflect lot-to-lot and within lot variation.
2. Measured between 10% and 90% points.
3. For 200ps input transition times. Overshoot decreases as input transition times increase, especially for AV= +1. Please refer to
Performance Curves.
4. Measured between 25% and 75% points.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLE 1)
Interim Electrical Parameters (Pre Burn-In) 1
Final Electrical Test Parameters 1 (Note 1), 2, 3, 4
Group A Test Requirements 1, 2, 3, 4
Groups C and D Endpoints 1
NOTE:
1. PDA applies to Subgroup 1 only.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Characterized at: VSUPPLY = ±5V, AV = +2, RF= 681Ω, RL = 400Ω, Unless Otherwise Specified.
PARAMETERS SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Spec Number 511107-883
6
HA5022/883
Test Circuits and Waveforms
FIGURE 1. TEST CIRCUIT (Applies to Table 1)
FIGURE 2. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS
FIGURE 3. SMALL SIGNAL PULSE RESPONSE CIRCUIT FIGURE 4. LARGE SIGNAL PULSE RESPONSE CIRCUIT
FIGURE 5. SMALL SIGNAL RESPONSE
Vertical Scale: VIN = 100mV/Div., VOUT = 100mV/Div.
Horizontal Scale: 20ns/Div.
FIGURE 6. LARGE SIGNAL RESPONSE
Vertical Scale: VIN = 1V/Div., VOUT = 1V/Div.
Horizontal Scale: 50ns/Div.
V+
ICC 10 0.1
13
DUT
-
+
1, 7
2, 6
4
1K
VIN
-
+
HA-5177
200pF
100K (0.01%)
VZ
VXx100 -
+470pF
VIO = VX
100
+IBIAS = VZ
100K 10 0.1
V-
IEE
-IBIAS = VX
50K K6
400 100
VOUT
NOTE: All Resistors = ±1% (Ω)
All Capacitors = ±10% (µF)
Unless Otherwise Noted
16, 10
+
+
0.1
100
0.1
K1 NC
1K
0.1
1K
510
510
0.1
K2
2
1
K2 = POSITION 1:
K2 = POSITION 2:
0.1
Chip Components Recommended
K5
50
K3
3, 5
0.1
VD
NC
+
-
50
50
DUT
HP4195
NETWORK
ANALYZER
VIN VOUT
RL
RF, 1K
100Ω
50Ω
+
-DUT VIN VOUT
RL
RF, 681 400Ω
50Ω
+
-DUT
RI
681Ω
Spec Number 511107-883
7
HA5022/883
Burn-In Circuit
HA5022MJ/883 CERAMIC DIP
NOTES:
R1 = R2 = R4 = R5 = 1kΩ,±5% (Per Socket)
R3 = R6 = 10kΩ,±5% (Per Socket)
C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum
D1 = D2 = 1N4002 or Equivalent (Per Board)
D3 = D4 = 1N4002 or Equivalent (Per Socket)
V+ = +5.5V ± 0.5V
V- = -5.5V ± 0.5V
V+
C1 D1
D2 C2
V- D4 D3
R2
R1
R3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
R4
R5
R6
+
-
+
-
Spec Number 511107-883
8
HA5022/883
Spec Number 511107-883
Die Characteristics
DIE DIMENSIONS:
65 x 100 x 19 mils ± 1 mils
1650 x 2540 x 483µm± 25.4µm
METALLIZATION:
Type: Metal 1: AlCu (1%), Metal 2: AlCu (1%)
Thickness: Metal 1: 8kű0.4kÅ, Metal 2: 16kű0.8kÅ
WORST CASE CURRENT DENSITY:
1.62 x 105 A/cm2 at 35mA
SUBSTRATE POTENTIAL (Powered Up): V-
GLASSIVATION:
Type: Nitride
Thickness: 4kű 0.4kÅ
TRANSISTOR COUNT: 124
PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA5022/883
-IN1
V+
OUT1
+IN2
DIS2
V-
NC
OUT2
-IN2
DIS1
+IN1
9
HA5022/883
Spec Number 511107-883
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
S S
ccc C A - B
MD
SSaaa C A - B
MD
SS
eA
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 0.840 - 21.34 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2 , 3
N16 168
Rev. 0 4/94
Ceramic Dual-In-Line Frit Seal Packages (CerDIP)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
DESIGN INFORMATION
January 1995
SEMICONDUCTOR
10
Typical Performance Curves
VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25oC, Unless Otherwise Specified.
FIGURE 1. NON-INVERTING FREQUENCY RESPONSE FIGURE 2. INVERTING FREQUENCY RESPONSE
FIGURE 3. PHASE RESPONSE AS A FUNCTION OF
FREQUENCY FIGURE 4. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE
FIGURE 5. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE FIGURE 6. BANDWIDTH AND GAIN PEAKING vs LOAD
RESISTANCE
+5
+4
+3
+2
+1
0
-1
-2
-3
-4
-5
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
2 10 100 200
VOUT = 0.2VP-P
CL = 10pF AV = 1, RF = 1kΩ
AV = 2, RF = 681Ω
AV = 5, RF = 1kΩ
AV = 10, RF = 383Ω
+5
+4
+3
+2
+1
0
-1
-2
-3
-4
-5 2 10 100 200
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
VOUT = 0.2VP-P
CL = 10pF
RF = 750ΩAV = -1
AV = -2
AV = -10
AV = -5
FREQUENCY (MHz)
2 10 100 200
0
-45
-90
-135
-100
-225
-270
-315
-360
+180
+135
+90
0
-45
-90
-135
+45
-180
NONINVERTING PHASE (DEGREES)
INVERTING PHASE (DEGREES)
VOUT = 0.2VP-P
CL = 10pF
AV = +10, RF = 383Ω
AV = -10, RF = 750Ω
AV = -1, RF = 750Ω
AV = +1, RF = 1kΩ
FEEDBACK RESISTOR (Ω)
500 700 900 1100 1300 1500
140
130
120 10
5
0
-3dB BANDWIDTH (MHz)
GAIN PEAKING (dB)
VOUT = 0.2VP-P
CL = 10pF
-3dB BANDWIDTH
GAIN PEAKING
AV = +1
FEEDBACK RESISTOR (Ω)
-3dB BANDWIDTH (MHz)
GAIN PEAKING (dB)
100
95
90
0
350 500 650 800 950 1100
-3dB BANDWIDTH
GAIN PEAKING
VOUT = 0.2VP-P
CL = 10pF
AV = +2
5
10
LOAD RESISTOR (Ω)
-3dB BANDWIDTH (MHz)
GAIN PEAKING (dB)
130
120
110
100
90
800 200 400 600 800 1000
6
4
2
0
VOUT = 0.2VP-P
CL = 10pF
-3dB BANDWIDTH
GAIN PEAKING
AV = +1
HA5022
Dual 125MHz Video Current
Feedback Amplifier with Disable
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
11
HA5022
FIGURE 7. BANDWIDTH vs FEEDBACK RESISTANCE FIGURE 8. SMALL SIGNAL OVERSHOOT vs LOAD
RESISTANCE
FIGURE 9. DIFFERENTIAL GAIN vs SUPPLY VOLTAGE FIGURE 10. DIFFERENTIAL PHASE vs SUPPLY VOLTAGE
FIGURE 11. DISTORTION vs FREQUENCY FIGURE 12. REJECTION RATIOS vs FREQUENCY
Typical Performance Curves
VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25oC, Unless Otherwise Specified.
(Continued)
80
60
40
20
0200 350 500 650 800 950
-3dB BANDWIDTH (MHz)
FEEDBACK RESISTOR (Ω)
VOUT = 0.2VP-P
CL = 10pF
AV = +10
LOAD RESISTANCE (Ω)
0 200 400 600 800 1000
16
6
0
OVERSHOOT (%)
VOUT = 0.1VP-P
CL = 10pF VSUPPLY = ±5V, AV = +2
VSUPPLY = ±15V, AV = +1
VSUPPLY = ±5V, AV = +1
VSUPPLY = ±15V, AV = +2
12
SUPPLY VOLTAGE (V)
3 5 7 9 11 13 15
0.10
0.08
0.06
0.04
0.02
0.00
DIFFERENTIAL GAIN (%)
FREQUENCY = 3.58MHz
RL = 75Ω
RL = 150Ω
RL = 1kΩ
0.08
0.06
0.04
0.02
0.003 5 7 9 11 13 15
SUPPLY VOLTAGE (V)
DIFFERENTIAL PHASE (DEGREES)
RL = 1kΩ
RL = 75Ω
RL = 150Ω
FREQUENCY = 3.58MHz
-40
-50
-60
-70
-80
-90
0.3 1 10
FREQUENCY (MHz)
DISTORTION (dBc)
VOUT = 2.0VP-P
CL = 30pF
HD3
HD2
3RD ORDER IMD
HD2
HD3
FREQUENCY (MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
REJECTION RATIO (dB)
0.001 0.01 0.1 1 10 30
AV = +1
CMRR
POSITIVE PSRR
NEGATIVE PSRR
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
12
HA5022
FIGURE 13. PROPAGATION DELAY vs TEMPERATURE FIGURE 14. PROPAGATION DELAY vs SUPPLY VOLTAGE
FIGURE 15. SLEW RATE vs TEMPERATURE FIGURE 16. NON-INVERTING GAIN FLATNESS vs FREQUENCY
FIGURE 17. INVERTING GAIN FLATNESS vs FREQUENCY FIGURE 18. INPUT NOISE CHARACTERISTICS
Typical Performance Curves
VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25oC, Unless Otherwise Specified.
(Continued)
TEMPERATURE (oC)
-50 -25 0 +25 +50 +75 +100 +125
8.0
7.5
7.0
6.5
6.0
PROPAGATION DELAY (ns)
RL = 100Ω
VOUT = 1.0VP-P
AV = +1
SUPPLY VOLTAGE (V)
PROPAGATION DELAY (ns)
12
10
8
6
43 5 7 9 11 13 15
RLOAD = 100Ω
VOUT = 1.0VP-P
AV = +10, RF = 383Ω
AV = +2, RF = 681Ω
AV = +1, RF =1kΩ
TEMPERATURE (oC)
-50 -25 0 +25 +50 +75 +100 +125
500
450
400
350
300
250
200
150
100
SLEW RATE (V/µs)
VOUT = 20VP-P
+ SLEW RATE
- SLEW RATE
FREQUENCY (MHz)
51015202530
+0.8
+0.6
+0.4
+0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
NORMALIZED GAIN (dB)
VOUT = 0.2VP-P
CL = 10pF
AV= +2, RF = 681Ω
AV= +5, RF = 1kΩ
AV = +1, RF = 1kΩ
AV = 10, RF =383Ω
+0.8
+0.6
+0.4
+0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
51015202530
V
OUT = 0.2VP-P
CL = 10pF
AV = -1
AV = -2
AV = -5
AV = -10
RF = 750Ω
FREQUENCY (kHz)
0.01 0.1 1 10 100
VOLTAGE NOISE (nV/√Hz)
CURRENT NOISE (pA/√Hz)
100
80
60
40
20
0
1000
800
600
400
200
0
AV = 10, RF = 383Ω
-INPUT NOISE CURRENT
+INPUT NOISE CURRENT
+INPUT NOISE VOLTAGE
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
13
HA5022
FIGURE 19. INPUT OFFSET VOLTAGE vs TEMPERATURE FIGURE 20. +INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 21. -INPUT BIAS CURRENT vs TEMPERATURE FIGURE 22. TRANSIMPEDANCE vs TEMPERATURE
FIGURE 23. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 24. REJECTION RATIO vs TEMPERATURE
Typical Performance Curves
VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25oC, Unless Otherwise Specified.
(Continued)
1.5
1.0
0.5
0.0-60 -40 -20 0 +40 +60 +80 +100 +120 +140+20
VIO (mV)
TEMPERATURE (oC)
2
0
-2
-4-60 -40 -20 0 +40 +60 +80 +100 +120 +140+20
BIAS CURRENT (µA)
TEMPERATURE (oC)
22
20
18
16
-60 -40 -20 0 +40 +60 +80 +100 +120 +140+20
TEMPERATURE (oC)
BIAS CURRENT (µA)
TEMPERATURE (oC)
4000
3000
2000
1000
TRANSIMPEDANCE (kΩ)
-60 -40 -20 0 +40 +60 +80 +100 +120 +140+20
34 5 6 7 8 9 10 11 12 13 14 15
25
20
15
10
5
ICC (mA)
SUPPLY VOLTAGE (V)
+125oC
+55oC
+25oC
58
60
62
64
66
68
70
72
74
-100 -50 0 +50 +100 +150
+PSRR
-PSRRN
CMRR
+200 +250
TEMPERATURE (oC)
REJECTION RATIO (dB)
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
14
HA5022
FIGURE 25. SUPPLY CURRENT vs DISABLE INPUT VOLTAGE FIGURE 26. OUTPUT SWING vs TEMPERATURE
FIGURE 27. OUTPUT SWING vs LOAD RESISTANCE FIGURE 28. INPUT OFFSET VOLTAGE CHANGE BETWEEN
CHANNELS vs TEMPERATURE
FIGURE 29. INPUT BIAS CURRENT CHANGE BETWEEN
CHANNELS vs TEMPERATURE FIGURE 30. DISABLE SUPPLY CURRENT vs SUPPLY
VOLTAGE
Typical Performance Curves
VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25oC, Unless Otherwise Specified.
(Continued)
10 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DISABLE INPUT VOLTAGE (V)
40
30
20
10
0
SUPPLY CURRENT (mA)
+5V +10V +15V
4.0
3.8
3.6-60 -40 -20 0 +40 +60 +80 +100 +120 +140+20
TEMPERATURE (oC)
OUTPUT SWING (V)
0.01 0.10 1.00 10.00
30
20
10
0
VOUT (VP-P)
LOAD RESISTANCE (kΩ)
VCC = ±15V
VCC = ±10V
VCC = ±4.5V
-60 -40 -20 0 +40 +60 +80 +100 +120 +140+20
1.2
1.1
1.0
0.9
0.8
VIO (mV)
TEMPERATURE (oC)
-60 -40 -20
1.5
1.0
0.5
0.0
TEMPERATURE (oC)
∆BIAS CURRENT (µA)
+40 +60 +80 +100 +120 +140+20
03456789101112131415
30
25
20
15
10
5
SUPPLY VOLTAGE (V)
ICC (mA)
-55oC
+25oC
+125oC
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
15
HA5022
FIGURE 31. CHANNEL SEPARATION vs FREQUENCY FIGURE 32. ENABLE/DISABLE TIME vs OUTPUT VOLTAGE
FIGURE 33. DISABLE FEEDTHROUGH vs FREQUENCY FIGURE 34. TRANSIMPEDANCE vs FREQUENCY
FIGURE 35. TRANSIMPEDANCE vs FREQUENCY
Typical Performance Curves
VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25oC, Unless Otherwise Specified.
(Continued)
-30
-40
-50
-60
-70
-800.1 1 10 30
SEPARATION (dBc)
FREQUENCY (MHz)
AV = +1
VOUT = 2VP-P
DISABLE
ENABLE
ENABLE
DISABLE
ENABLE TIME (ns)
20
18
16
14
12
10
8
6
4
2
0
OUTPUT VOLTAGE (V)
-2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5
32
30
28
26
24
22
20
18
16
14
12
DISABLE TIME (µs)
-20
-40
-50
-60
-70
-80
0.1 1 10 20
FEEDTHROUGH (dB)
FREQUENCY (MHz)
-30
-10
0DISABLE = 0V
VIN = 5VP-P
RF = 750Ω
-135
-90
-45
0
45
90
135
180
10
1
0.1
0.01
0.001
0.001 0.01 0.1 1 10 100
PHASE ANGLE (DEGREES)
TRANSIMPEDANCE (MΩ)
RL = 100Ω
FREQUENCY (MHz)
-135
-90
-45
0
45
90
135
180
10
1
0.1
0.01
0.001
0.001 0.01 0.1 1 10 100
PHASE ANGLE (DEGREES)
RL = 400Ω
FREQUENCY (MHz)
TRANSIMPEDANCE (MΩ)
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
16
HA5022
Application Information
Optimum Feedback Resistor
The plots of inverting and non-inverting frequency response,
see Figure 1 and Figure 2 in the Typical Performance Curves
section, illustrate the performance of the HA5022 in various
closed loop gain configurations. Although the bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may be
minimized by taking advantage of the current feedback ampli-
fier’s unique relationship between bandwidth and RF. All cur-
rent feedback amplifiers require a feedback resistor, even for
unity gain applications, and RF, in conjunction with the inter-
nal compensation capacitor, sets the dominant pole of the fre-
quency response. Thus, the amplifier’s bandwidth is inversely
proportional to RF. The HA5022 design is optimized for a
1000Ω RF at a gain of +1. Decreasing RF in a unity gain appli-
cation decreases stability, resulting in excessive peaking and
overshoot. At higher gains the amplifier is more stable, so RF
can be decreased in a trade-off of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth.
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resistors
and chip capacitors is strongly recommended. If leaded
components are used the leads must be kept short espe-
cially for the power supply decoupling components and
those components connected to the inverting input.
Attention must be given to decoupling the power supplies. A
large value (10 µF) tantalum or electrolytic capacitor in parallel
with a small value (0.1µF) chip capacitor works well in most
cases.
A ground plane is strongly recommended to control noise.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input (-IN). The larger
this capacitance, the worse the gain peaking, resulting in
pulse overshoot and possible instability. It is recommended
that the ground plane be removed under traces connected to -
IN, and that connections to -IN be kept as short as possible to
minimize the capacitance from this node to ground.
GAIN
(ACL)R
F
(Ω)BANDWIDTH
(MHz)
-1 750 100
+1 1000 125
+2 681 95
+5 1000 52
+10 383 65
-10 750 22
Driving Capacitive Loads
Capacitive loads will degrade the amplifier’s phase margin
resulting in frequency response peaking and possible oscilla-
tions. In most cases the oscillation can be avoided by placing
an isolation resistor (R) in series with the output as shown in
Figure 36.
FIGURE 36. PLACEMENT OF THE OUTPUT ISOLATION
RESISTOR, R
The selection criteria for the isolation resistor is highly
dependent on the load, but 27Ω has been determined to be
a good starting value.
Power Dissipation Considerations
Due to the high supply current inherent in dual amplifiers, care
must be taken to insure that the maximum junction tempera-
ture (TJ, see Absolute Maximum Ratings) is not exceeded.
Figure 37 shows the maximum ambient temperature versus
supply voltage for the available package styles. It is recom-
mended that thermal calculations, which take into account out-
put power, be performed by the designer.
FIGURE 37. MAXIMUM OPERATING AMBIENT TEMPERATURE
vs SUPPLY VOLTAGE
Enable/Disable Function
When enabled the amplifier functions as a normal current
feedback amplifier with all of the data in the electrical specifi-
cations table being valid and applicable. When disabled the
amplifier output assumes a true high impedance state and
the supply current is reduced significantly.
The circuit shown in Figure 38 is a simplified schematic of
VIN VOUT
CL
RT
+
-
RIRF
R
175
165
155
145
135
125
115 579111315
MAX. AMBIENT TEMPERATURE
SUPPLY VOLTAGE (V)
CERDIP
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
17
HA5022
the enable/disable function. The large value resistors in
series with the DISABLE pin makes it appear as a current
source to the driver. When the driver pulls this pin low cur-
rent flows out of the pin and into the driver. This current,
which may be as large as 350µA when external circuit and
process variables are at their extremes, is required to insure
that point “A” achieves the proper potential to disable the
output. The driver must have the compliance and capability
of sinking all of this current.
FIGURE 38. SIMPLIFIED SCHEMATIC OF ENABLE/DISABLE
FUNCTION
When VCC is +5V the DISABLE pin may be driven with a
dedicated TTL gate. The maximum low level output voltage
of the TTL gate, 0.4V, has enough compliance to insure that
the amplifier will always be disabled even though D1 will not
turn on, and the TTL gate will sink enough current to keep
point “A” at its proper voltage. When VCC is greater than +5
volts the DISABLE pin should be driven with an open collec-
tor device that has a breakdown rating greater than VCC.
Referring to Figure 8, it can be seen that R6 will act as a
pull-up resistor to +VCC if the DISABLE pin is left open. In
those cases where the enable/disable function is not
required on all circuits some circuits can be permanently
enabled by letting the DISABLE pin float. If a driver is used
to set the enable/disable level, be sure that the driver does
not sink more than 20µA when the DISABLE pin is at a high
level. TTL gates, especially CMOS versions, do not violate
this criteria so it is permissible to control the enable/disable
function with TTL.
Two Channel Video Multiplexer
Referring to the amplifier U1A in Figure 39, R1 terminates
the cable in its characteristic impedance of 75Ω, and R4
back terminates the cable in its characteristic impedance.
The amplifier is set up in a gain configuration of +2 to yield
an overall network gain of +1 when driving a double termi-
nated cable. The value of R3 can be changed if a different
network gain is desired. R5 holds the disable pin at ground
thus inhibiting the amplifier until the switch, S1, is thrown to
position 1. At position 1 the switch pulls the disable pin up to
the plus supply rail thereby enabling the amplifier. Since all
R6
15K
R7
15K
+VCC
ENABLE/DISABLE INPUT
D1
QP3
R8
QP18
A
R33
R10
of the actual signal switching takes place within the amplifier,
it’s differential gain and phase parameters, which are 0.03%
and 0.03 degrees respectively, determine the circuit’s perfor-
mance. The other circuit, U1b, operates in a similar manner.
When the plus supply rail is 5V the disable pin can be driven
by a dedicated TTL gate as discussed earlier. If a multiplexer
IC or its equivalent is used to select channels its logic must
be break before make. When these conditions are satisfied
the HA5022 is often used as a remote video multiplexer, and
the multiplexer may be extended by adding more amplifier
ICs.
Low Impedance Multiplexer
Two common problems surface when you try to multiplex
multiple high speed signals into a low impedance source
such as an A/D converter. The first problem is the low source
impedance which tends to make amplifiers oscillate and
causes gain errors. The second problem is the multiplexer
which supplies no gain, introduces all kinds of distortion and
limits the frequency response. Using op amps which have an
enable/disable function, such as the HA5022, eliminates the
multiplexer problems because the external mux chip is not
needed, and the HA5022 can drive low impedance (large
capacitance) loads if a series isolation resistor is used.
Referring to Figure 40, both inputs are terminated in their
characteristic impedance; 75Ω is typical for video applica-
tions. Since the drivers usually are terminated in their char-
acteristic impedance the input gain is 0.5, thus the
amplifiers, U2, are configured in a gain of +2 to set the circuit
gain equal to one. Resistors R2 and R3 determine the ampli-
fier gain, and if a different gain is desired R2 should be
changed according to the equation G = (1 + R3/R2). R3 sets
the frequency response of the amplifier so you should refer
to the manufacturers data sheet before changing it’s value.
R5, C1 and D1 are an asymmetrical charge/discharge time
circuit which configures U1 as a break before make switch to
prevent both amplifiers from being active simultaneously. If
this design is extended to more channels the drive logic
must be designed to be break before make. R4 is enclosed
in the feedback loop of the amplifier so that the large open
loop amplifier gain of U2 will present the load with a small
closed loop output impedance while keeping the amplifier
stable for all values of load capacitance.
The circuit shown in Figure 40 was tested for the full range
of capacitor values with no oscillations being observed; thus,
problem one has been solved. The frequency and gain char-
acteristics of the circuit are now those of the amplifier inde-
pendent of any multiplexing action; thus, problem two has
been solved. The multiplexer transition time is approximately
15µs with the component values shown.
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
18
HA5022
FIGURE 39. TWO CHANNEL HIGH IMPEDANCE MULTIPLEXER
FIGURE 40. LOW IMPEDANCE MULTIPLEXER
VIDEO INPUT #1
VIDEO INPUT #2
R1
75
R3
681
R2
681
R4
75
R5
2000
+
-
U1A
3
24
1
U1B
8
97
10 R9
75
R10
2000R7
681
R8
681
R6
75
+5V IN +5V
0.1µF10µF
-5V IN -5V
0.1µF10µF
+
+
1
R11
100
VIDEO OUTPUT
TO 75Ω LOAD
+5V
S1
2
3
ALL
OFF
NOTES:
1. U1 is HA5022
2. All resistors in Ω
3. S1 is break before make
4. Use ground plane
INPUT B
+
-
-5V
+
-
+5V
INHIBIT
CHANNEL
SWITCH
INPUT A
R1A
75
R1B
75 D1A
1N4148
U1C
U1A U1B U1D
R6
100K
R5A
2000
C1A
0.047µF
R5B
2000
D1B
1N4148
R1A
681
1
234
16
R3A
681
R4A
27
0.01µF
R2B
681 R4B
27
R3B
681
0.01µF
OUTPUT
7
6513
10
U2B
U2A
C1B
0.047µFNOTES:
1. U2: HA5022
2. U1: CD4011
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
19
Specifications HA5022
Electrical Specifications V+ = +5V, V- = -5V, RF = 1kΩ, AV = +1, RL = 400Ω, CL≤10pF, Unless Otherwise Specified
PARAMETER
(NOTE 12)
TEST
LEVEL TEMPERATURE
HA5022I
UNITSMIN TYP MAX
INPUT CHARACTERISTICS
Input Offset Voltage (VIO) A +25oC - 0.8 3 mV
A Full - - 5 mV
Delta VIO Between Channels A Full - 1.2 3.5 mV
Average Input Offset Voltage Drift B Full - 5 - µV/oC
VIO Common Mode Rejection Ratio (Note 3) A +25oC53--dB
A Full 50 - - dB
VIO Power Supply Rejection Ratio (Note 4) A +25oC60--dB
A Full 55 - - dB
Input Common Mode Range (Note 3) A Full ±2.5 - - V
Non-Inverting Input (+IN) Current A +25oC-38µA
A Full - - 20 µA
+IN Common Mode Rejection (Note 3)
(+ IBCMR =) A +25oC - - 0.15 µA/V
A Full - - 0.5 µA/V
+IN Power Supply Rejection (Note 4) A +25oC - - 0.1 µA/V
A Full - - 0.3 µA/V
Inverting Input (-IN) Current A +25oC, +85oC- 4 12 µA
A -40oC - 10 30 µA
Delta -IN BIAS Current Between Channels A +25oC, +85oC- 6 15 µA
A -40oC - 10 30 µA
-IN Common Mode Rejection (Note 3) A +25oC - - 0.4 µA/V
A Full - - 1.0 µA/V
-IN Power Supply Rejection (Note 4) A +25oC - - 0.2 µA/V
A Full - - 0.5 µA/V
Input Noise Voltage (f = 1kHz) B +25oC - 4.5 - nV/√Hz
+Input Noise Current (f = 1kHz) B +25oC - 2.5 - pA/√Hz
-Input Noise Current (f = 1kHz) B +25oC - 25.0 - pA/√Hz
1
RIN
-------
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
20
Specifications HA5022
TRANSFER CHARACTERISTICS
Transimpedance (Note 21) A +25oC 1.0 - - MΩ
A Full 0.85 - - MΩ
Open Loop DC Voltage Gain
RL = 400Ω, VOUT = ±2.5V A +25oC70--dB
A Full 65 - - dB
Open Loop DC Voltage Gain
RL = 100Ω, VOUT = ±2.5V A +25oC50--dB
A Full 45 - - dB
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 20) A +25oC±2.5 ±3.0 - V
A Full ±2.5 ±3.0 - V
Output Current (Note 20) B Full ±16.6 ±20.0 - mA
Output Current (Short Circuit, Note 13) A Full ±40 ±60 - mA
Output Current (Disabled, Notes 5, 14) A Full - - 2 µA
Output Disable Time (Note 15) B +25oC - 40 - µs
Output Enable Time (Note 16) B +25oC - 40 - ns
Output Capacitance (Disabled, Notes 5, 17) B +25oC - 15 - pF
POWER SUPPLY CHARACTERISTICS
Supply Voltage Range A +25oC5-15V
Quiescent Supply Current A Full - 7.5 10 mA/Op
Amp
Supply Current, Disabled (Note 5) A Full - 5 7.5 mA/Op
Amp
Disable Pin Input Current (Note 5) A Full - 1.0 1.5 mA
Minimum Pin 8 Current to Disable (Note 6) A Full 350 - - µA
Maximum Pin 8 Current to Enable (Note 7) A Full - - 20 µA
AC CHARACTERISTICS (AV = +1)
Slew Rate (Note 8) B +25oC 275 400 - V/µs
Full Power Bandwidth (Note 9) B +25oC 22 28 - MHz
Rise Time (Note 10) B +25oC-6-ns
Electrical Specifications V+ = +5V, V- = -5V, RF = 1kΩ, AV = +1, RL = 400Ω, CL≤10pF, Unless Otherwise Specified (Continued)
PARAMETER
(NOTE 12)
TEST
LEVEL TEMPERATURE
HA5022I
UNITSMIN TYP MAX
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
21
Specifications HA5022
Fall Time (Note 10) B +25oC-6-ns
Propagation Delay (Note 10) B +25oC-6-ns
Overshoot B +25oC - 4.5 - %
-3dB Bandwidth (Note 11) B +25oC - 125 - MHz
Settling Time to 1%, 2V Output Step B +25oC - 50 - ns
Settling Time to 0.25%, 2V Output Step B +25oC - 75 - ns
AC CHARACTERISTICS (AV = +2, RF = 681Ω)
Slew Rate (Note 8) B +25oC - 475 - V/µs
Full Power Bandwidth (Note 9) B +25oC - 26 - MHz
Rise Time (Note 10) B +25oC-6-ns
Fall Time (Note 10) B +25oC-6-ns
Propagation Delay (Note 10) B +25oC-6-ns
Overshoot B +25oC-12-%
-3dB Bandwidth (Note 11) B +25oC - 95 - MHz
Settling Time to 1%, 2V Output Step B +25oC - 50 - ns
Settling Time to 0.25%, 2V Output Step B +25oC - 100 - ns
Gain Flatness 5MHz B +25oC - 0.02 - dB
20MHz B +25oC - 0.07 - dB
AC CHARACTERISTICS (AV = +10, RF = 383Ω)
Slew Rate (Note 8) B +25oC 350 475 - V/µs
Full Power Bandwidth (Note 9) B +25oC 28 38 - MHz
Rise Time (Note 10) B +25oC-8-ns
Fall Time (Note 10) B +25oC-9-ns
Propagation Delay (Note 10) B +25oC-9-ns
Overshoot B +25oC - 1.8 - %
-3dB Bandwidth (Note 11) B +25oC - 65 - MHz
Settling Time to 1%, 2V Output Step B +25oC - 75 - ns
Settling Time to 0.1%, 2V Output Step B +25oC - 130 - ns
Electrical Specifications V+ = +5V, V- = -5V, RF = 1kΩ, AV = +1, RL = 400Ω, CL≤10pF, Unless Otherwise Specified (Continued)
PARAMETER
(NOTE 12)
TEST
LEVEL TEMPERATURE
HA5022I
UNITSMIN TYP MAX
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as
application and design information only. No guarantee is implied.
22
Specifications HA5022
VIDEO CHARACTERISTICS
Differential Gain (Notes 18, 20) B +25oC - 0.03 - %
Differential Phase (Notes 18, 20) B +25oC - 0.03 - Degrees
NOTES:
1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Func-
tional operation under any of these conditions is not necessarily implied.
2. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty
cycle) output current should not exceed 15mA for maximum reliability.
3. VCM = ±2.5V. At -40oC Product is tested at VCM = ±2.25V because short test duration does not allow self heating.
4. ±3.5V ≤ VS≤±6.5V.
5. Disable = 0V.
6. RL = 100Ω, VIN = 2.5V. This is the minimum current which must be pulled out of theDisable pin in order to disable the output. The output
is considered disabled when -10mV ≤ VOUT ≤ +10mV.
7. VIN = 0V. This is the maximum current that can be pulled out of the Disable pin with the HA5024 remaining enabled. The HA5024 is con-
sidered disabled when the supply current has decreased by at least 0.5mA.
8. VOUT switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points.
9.
10. RL = 100Ω, VOUT = 1V. Measured from 10% to 90% points for rise/fall times; from 50% points of input and output for propagation delay.
11. RL = 400Ω, VOUT = 100mV.
12. A. Production Tested; B. Guaranteed Limit or Typical based on characterization; C. Design Typical for information only.
13. VIN = ±2.5V, VOUT = 0V.
14. VOUT = ±2.5V, VIN = OV.
15. VIN = +2V, Disable = +5V to 0V. Measured from the 50% point of Disable to VOUT = 0V.
16. VIN = +2V, Disable = 0V to +5V. Measured from the 50% point of Disable to VOUT = 2V.
17. VIN = 0V, Force VOUT from 0V to ±2.5V, tR = tF = 50ns.
18. Measured with a VM700A video tester using an NTC-7 composite VITS.
19. Maximum power dissipation, including output load, must be designed to maintain junction temperature below +175oC for die, and below
+150oC for plastic packages. See Applications Information section for safe operating area information.
20. RL = 150Ω .
21. VOUT =± 2.5V. At -40oC Product is tested at VOUT = ±2.25V because short test duration does not allow self heating.
22. ESD Protection is for human body model tested per MIL-STD-883, Method 3015.7.
Electrical Specifications V+ = +5V, V- = -5V, RF = 1kΩ, AV = +1, RL = 400Ω, CL≤10pF, Unless Otherwise Specified (Continued)
PARAMETER
(NOTE 12)
TEST
LEVEL TEMPERATURE
HA5022I
UNITSMIN TYP MAX
FPBW Slew Rate
2πVPEAK
------------------- ;V
PEAK 2V==
