DS92CK16 www.ti.com SNAS044C - NOVEMBER 1999 - REVISED APRIL 2013 DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver Check for Samples: DS92CK16 FEATURES DESCRIPTION * The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling (BLVDS) technology. This clock distribution device is designed for applications requiring ultra low power dissipation, low noise, and high data rates. The BLVDS side is a transceiver with a separate channel acting as a return/source clock. 1 2 * * * * * * * * * Master/Slave Clock Selection in a Backplane Application 125 MHz Operation (Typical) 100 ps Duty Cycle Distortion (Typical) 50 ps Channel to Channel Skew (Typical) 3.3V Power Supply Design Glitch-free Power on at CLKI/O Pins Low Power Design (20 mA @ 3.3V Static) Accepts Small Swing (300 mV Typical) Differential Signal Levels Industrial Temperature Operating Range (-40C to +85C) Available in 24-pin TSSOP Packaging The DS92CK16 accepts LVDS (300 mV typical) differential input levels, and translates them to 3V CMOS output levels. An output enable pin OE , when high, forces all CLKOUT pins high. The device can be used as a source synchronous driver. The selection of the source driving is controlled by the CrdCLKIN and DE pins. This device can be the master clock, driving the inputs of other clock I/O pins in a multipoint environment. Easy master/slave clock selection is achieved along a backplane. Function Diagram and Truth Table Table 1. Receive Mode Truth Table INPUT OUTPUT OE DE CrdCLKIN (CLKI/O+)-(CLKI/O-) CLKOUT H H X X H L H X VID 0.07V H L H X VID -0.07V L 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2013, Texas Instruments Incorporated DS92CK16 SNAS044C - NOVEMBER 1999 - REVISED APRIL 2013 www.ti.com Table 2. Driver Mode Truth Table INPUT OUTPUT OE DE CrdCLKIN CLK/I/O+ CLKI/O- L L L L H L H L H H X CLKOUT L L H L H H L H L L H H H H L H Z Z H Connection Diagram TSSOP Package See Package Number PW (R-PDSO-G24) TSSOP PACKAGE PIN DESCRIPTIONS Pin Name Pin # Type CLKI/O+ 6 I/O True (Positive) side of the differential clock input. CLKI/O- 7 I/O Complementary (Negative) side of the differential clock input. OE 2 I OE; this pin is active Low. When High, this pin forces all CLKOUT pins High. When Low, CLKOUT pins logic state is determined by either the CrdCLKIN or the VID at the CLK/I/O pins with respect to the logic level at the DE pin. This pin has a weak pullup device to VCC. If OE is floating, then all CLKOUT pins will be High. DE 11 I DE; this pin is active LOW. When Low, this pin enables the CardCLKIN signal to the CLKI/O pins and CLKOUT pins. When High, the Driver is TRI-STATE, the CLKI/O pins are inputs and determine the state of the CLKOUT pins. This pin has a weak pullup device to VCC. If DE is floating, then CLKI/O pins are TRI-STATE. 13, 15, 17, 19, 21, 23 O 6 Buffered clock (CMOS) outputs. Input clock from Card (CMOS level or TTL level). CLKOUT CrdCLKIN Description 9 I VCC 16, 20, 24 Power VCC; Analog VCCA (Internally separate from VCC, connect externally or use separate power supplies). No special power sequencing required. Either VCCA or VCC can be applied first, or simultaneously apply both power supplies. GND 1, 12, 14, 18, 22 Ground GND VCCA 4 Power Analog VCCA (Internally separate from VCC, connect externally or use separate power supplies). No special power sequencing required. Either VCCA or VCC can be applied first, or simultaneously apply both power supplies. GNDA 5, 8 Ground Analog Ground (Internally separate from Ground must be connected externally). NC 3, 10 2 No Connects Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: DS92CK16 DS92CK16 www.ti.com SNAS044C - NOVEMBER 1999 - REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage (VCC) -0.3V to +4V Enable Input Voltage (DE, OE, CrdCLKIN) -0.3V to +4V -0.3V to (VCC + 0.3V) Voltage (CLKOUT) -0.3V to +4V Voltage (CLKI/O) Driver Short Circuit Current momentary Receiver Short Circuit Current momentary Maximum Package Power Dissipation at +25C PW Package 1500 mW Derate PW Package 8.2 mW/C above +25C JA 95C/W JC 30C/W -65C to +150C Storage Temperature Range Lead Temperature Range (Soldering, 4 sec.) ESD Ratings: HBM CDM (2) (3) >3000V (3) Machine Model (1) 260C (3) >1000V (3) >200V "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be verified. These ratings are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. ESD Rating: ESD qualification is performed per the following: HBM (1.5 k, 100 pF), Machine Model (250V, 0), IEC 1000-4-2. All VCC pins connected together, all ground pins connected together. Recommended Operating Conditions Supply Voltage (VCC) Min Typ Max Units +3.0 +3.3 +3.6 V VCC V +85 C CrdCLKIN, DE, OE Input Voltage 0 Operating Free Air Temperature (TA) -40 25 DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified Symbol Parameter Conditions VTH Input Threshold High VTL Input Threshold Low VCMR Common Mode Voltage Range (3) VID = 250 mV pk to pk IIN Input Current VIN = 0V to VCC, DE = VCC, OE = VCC, Other Input = 1.2V 50 mV (1) (2) (3) Pin CLKI/O+, CLKI/O- (1) (2) . Min Typ Max Units 25 +70 mV -70 -35 |VID|/2 -20 5 mV 2.4 - |VID|/2 V +20 A Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VID, VOD, VTH, and VTL. All typicals are given for: VCC = +3.3V and TA = +25C. The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 0.2V to 2.2V A VID up to |VCC-0V| may be applied between the CLKI/O+ and CLKI/O- inputs, with the Common Mode set to VCC/2. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: DS92CK16 3 DS92CK16 SNAS044C - NOVEMBER 1999 - REVISED APRIL 2013 www.ti.com DC Electrical Characteristics (continued) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2). Symbol Parameter Conditions Pin Min Typ CLKOUT VCC-0.4 2.9 VCC-0.8 2.5 VOH1R Output High Voltage VID = 250 mV, IOH = -1.0 mA VOH2R Output High Voltage VID = 250 mV, IOH = -6 mA VOL1R Output Low Voltage IOL = 1.0 mA, VID = -250 mV VOL2R Output Low Voltage IOL = 6 mA, VID = -250 mV 0 IODHR CLKOUT Dynamic Output Current (4) VID = +250 mV, VOUT = VCC-1V -8 IODLR CLKOUT Dynamic Output Current (4) VID = -250 mV, VOUT = 1V 10 VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VIN = VCC or 2.4V IIL Input Low Current VIN = GND or 0.4V IINCRD Input Current VIN = 0V to VCC, OE = VCC CrdCLKIN -5 VCL Input Voltage Clamp IOUT = -1.5 mA OE, DE, CrdCLKIN -0.8 ICC No Load Supply Current Outputs Enabled, No VID Applied OE = DE = 0V, CrdCLKIN = VCC or GND, CLKI/O () = Open CLKOUT (0:5) = Open Circuit No Load Supply Current Outputs Enabled, VID over Common Mode Voltage Range OE = GND DE = VCC CrdCLKIN = VCC or GND, VID = 250 mV (0.125V VCM 2.275V), CLKOUT (0:5) = Open Circuit Driver Loaded Supply Current DE = OE = 0V, CrdCLKIN = VCC or GND, RL = 37.5 between CLKI/O+ and CLKI/O-, CLKOUT (0:5) = Open Circuit ICC1 ICCD Units V V 0.3 V 0.4 V -16 -30 mA 21 35 mA V DE, OE, CrdCLKIN 2.0 VCC GND 0.8 V OE, DE -10 -2 +10 A -20 -5 +20 A +5 A V VCC mA 10 mA 20 25 mA 350 450 mV 10 20 mV 1.29 1.5 V 5 20 mV 1.35 1.8 V Driver Output Differential Voltage VOD Driver VOD Magnitude Change VOS Driver Offset Voltage VOS Driver Offset Voltage Magnitude Change VOHD Driver Output High VOLD Driver Output Low IOS1D Driver Differential Short Circuit Current (5) CrdCLKIN = VCC or GND, VOD = 0V, (outputs shorted together) DE = 0V |30| |50| mA IOS2D Driver Output Short Circuit Current to VCC (5) CrdCLKIN = GND, DE = 0V, CLKI/O+ = VCC 36 70 mA IOS3D Driver Output Short Circuit Current to VCC (5) CrdCLKIN = VCC, DE = 0V, CLKI/O- = VCC 34 70 mA IOS4D Driver Output Short Circuit Current to GND (5) CrdCLKIN = VCC, DE = 0V, CLKI/O+ = 0V -47 -70 mA IOS5D Driver Output Short Circuit Current to GND (5) CrdCLKIN = GND, DE = 0V, CLKI/O- = 0V -50 -70 mA IOFF Power Off Leakage Current VCC = 0V or Open, VAPPLIED = 3.6V 20 A 4 CLKI/O+, CLKI/O- 13 VOD (4) (5) RL = 37.5, Figure 5 DE = 0V 0.06 Max 250 1.1 0.80 1.05 V Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating. Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: DS92CK16 DS92CK16 www.ti.com SNAS044C - NOVEMBER 1999 - REVISED APRIL 2013 Switching Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified Symbol Parameter (1) (2) . Conditions Min Typ Max Units Differential Propagation Delay High to Low. CLKI/O to CLKOUT CL = 15 pF VID = 250 mV Differential Propagation Delay Low to High. CLKI/O to CLKOUT Figure 1 Figure 2 Duty Cycle Distortion (3) (pulse skew) |tPLH-tPHL| 1.3 2.8 3.8 ns 1.3 2.9 3.8 ns 100 400 ps 30 80 ps 2.5 ns DIFFERENTIAL RECEIVER CHARACTERISTICS tPHLDR tPLHDR tSK1R tSK2R Channel to Channel Skew; Same Edge tSK3R Part to Part Skew (5) tTLHR Transition Time Low to High (20% to 80% ) tTHLR Transition Time High to Low (6) (80% to 20% ) tPLHOER Propagation Delay Low to High ( OEto CLKOUT) tPHLOER Propagation Delay High to Low (OE to CLKOUT) fMAX (4) (6) Maximum Operating Frequency CL = 15 pF Figure 3 Figure 4 (7) 0.4 1.4 2.4 ns 0.4 1.3 2.2 ns 1.0 3 4.5 ns 1.0 3 4.5 ns 100 125 0.5 1.8 2.5 ns 0.5 1.8 2.5 ns 2.0 4.5 6.0 ns 2.0 4.5 6.0 ns 600 ps 2.0 ns MHz DIFFERENTIAL DRIVER TIMING REQUIREMENTS tPHLDD Differential Propagation Delay High to Low. CrdCLKIN to CLKI/O tPLHDD Differential Propagation Delay Low to High. CrdCLKIN to CLKI/O tPHLCrd CrdCLKIN to CLKOUT Propagation Delay High to Low tPLHCrd CrdCLKIN to CLKOUT Propagation Delay Low to High tSK1D Duty Cycle Distortion (pulse skew) |tPLH-tPHL| (8) tSK2D Differential Part-to-Part Skew tTLHD Differential Transition Time (20% to 80% ) tTHLD Differential Transition Time (80% to 20% ) (6) tPHZD Transition Time High to TRI-STATE. DE to CLKI/O tPLZD Transition Time Low to TRI-STATE. DE to CLKI/O tPZHD Transition Time TRI-STATE to High. DE to CLKI/O tPZLD Transition Time TRI-STATE to Low. DE to CLKI/O (1) (2) (3) (4) (5) (6) (7) (8) (9) CL = 15 pF Figure 8 Figure 9 (9) (6) fMAX CL = 15 pF RL = 37.5 Figure 6 Figure 7 Maximum Operating Frequency 0.4 0.75 1.4 ns 0.4 0.75 1.4 ns 10 ns 10 ns 32 ns 32 ns VIN = 0V to VCC CL = 15 pF, RL = 37.5 Figure 10 Figure 11 (7) 100 125 MHz CL includes probe and fixture capacitance. Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50, tr = 1 ns, tf = 1 ns (10%-90%). To ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1 ns/V; control signals not slower than 3 ns/V. In general, the faster the input edge rate, the better the AC performance. tSK1R is the difference in receiver propagation delay (|tPLH-tPHL|) of one device, and is the duty cycle distortion of the output at any given temperature and VCC. The propagation delay specification is a device to device worst case over process, voltage and temperature. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This parameter is specified by design and characterization. tSK3R, part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. TSK3R is defined as Max-Min differential propagation delay.This parameter is specified by design and characterization. All device output transition times are based on characterization measurements and are specified by design. Generator input conditions: tr/tf < 1 ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle, VOL(max) 0.4V, VOH(min) 2.7V, Load = 7 pF (stray plus probes). tSK1D is the difference in driver propagation delay (|tPLH-tPHL|) and is the duty cycle distortion of the CLKI/O outputs. tSK2D part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSK2D is defined as Max-Min differential propagation delay. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: DS92CK16 5 DS92CK16 SNAS044C - NOVEMBER 1999 - REVISED APRIL 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION Figure 1. Receiver Propagation Delay and Transition Time Test Circuit Generator waveform for all test unless otherwise specified: f = 25 MHz, 50% Duty Cycle, Zo = 50, tTLH = 1 ns, tTHL = 1 ns. Figure 2. Receiver Propagation Delay and Transition Time Waveforms Figure 3. Output Enable (OE) Delay Test Circuit Figure 4. Output Enable (OE) Delay Waveforms 6 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: DS92CK16 DS92CK16 www.ti.com SNAS044C - NOVEMBER 1999 - REVISED APRIL 2013 Figure 5. Differential Driver DC Test Figure 6. Driver Propagation Delay Test Circuit Figure 7. Driver Propagation Delay and Transition Time Waveforms Figure 8. CrdCLKIN Propagation Delay Time Test Circuit Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: DS92CK16 7 DS92CK16 SNAS044C - NOVEMBER 1999 - REVISED APRIL 2013 www.ti.com Figure 9. CrdCLKIN Propagation Delay Time Waveforms Figure 10. Driver TRI-STATE Test Circuit Figure 11. Driver TRI-STATE Waveforms 8 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: DS92CK16 DS92CK16 www.ti.com SNAS044C - NOVEMBER 1999 - REVISED APRIL 2013 APPLICATIONS INFORMATION General application guidelines and hints for BLVDS/LVDS transceivers, drivers and receivers may be found in the following application notes: LVDS Owner's Manual, AN805(SNOA233), AN807(SNLA027), AN808(SNLA028), AN903(SNLA034), AN905(SNLA035), AN916(SNLA219), AN971(SNLA165), AN977(SNLA166) . BLVDS drivers and receivers are intended to be used in a differential backplane configuration. Transceivers or receivers are connected to the driver through a balanced media such as differential PCB traces. Typically, the characteristic differential impedance of the media (Zo) is in the range of 50 to100. Two termination resistors of Zo each are placed at the ends of the transmission line backplane. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. The effects of mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS92CK16 differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance (100 ohms) and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The output current is typically 9.330 mA. The current changes as a function of load resistor. The current mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop. Unterminated configurations are not allowed. The 9.33 mA loop current will develop a differential voltage of about 350mV across 37.5 (double terminated 75 differential transmission backplane) effective resistance, which the receiver detects with a 280 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350 mV - 70 mV = 280 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 700 mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz-50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1F in parallel with 0.01F, in parallel with 0.001F at the power supply pin as well as scattered capacitors over the printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 4.7F (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board. PC BOARD CONSIDERATIONS Use at least 4 PCB layers (top to bottom); BLVDS signals, ground, power, TTL signals. Isolate TTL signals from BLVDS signals, otherwise the TTL may couple onto the BLVDS lines. It is best to put TTL and BLVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (BLVDS port side) connectors as possible to create short stub lengths. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: DS92CK16 9 DS92CK16 SNAS044C - NOVEMBER 1999 - REVISED APRIL 2013 www.ti.com DIFFERENTIAL TRACES Use controlled impedance traces which match the differential impedance of your transmission medium (ie. backplane or cable) and termination resistor(s). Run the differential pair trace lines as close together as possible as soon as they leave the IC . This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. Plus, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number or vias and other discontinuities on the line. Avoid 90 turns (these cause impedance discontinuities). Use arcs or 45 bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. STUB LENGTH Stub lengths should be kept to a minimum. The typical transition time of the DS92CK16 BLVDS output is 0.75ns (20% to 80%). The 100 percent time is 0.75/0.6 or 1.25ns. For a general approximation, if the electrical length of a trace is greater than 1/5 of the transition edge, then the trace is considered a transmission line. For example, 1.25ns/5 is 250 picoseconds. Let velocity equal 160ps per inch for a typical loaded backplane. Then maximum stub length is 250ps/160ps/in or 1.56 inches. To determine the maximum stub for your backplane, you need to know the propagation velocity for the actual conditions (refer to application notes AN- 905(SNLA035) and AN-808(SNLA028)). TERMINATION Use a resistor which best matches the differential impedance of your loaded transmission line. Remember that the current mode outputs need the termination resistor to generate the differential voltage. BLVDS will not work without resistor termination. Surface mount 1% to 2% resistors are best. PROBING BLVDS TRANSMISSION LINES Always use high impedance (> 100k), low capacitance (< 2pF) scope probes with a wide bandwidth (1GHz) scope. Improper probing will give deceiving results. CABLES AND CONNECTORS, GENERAL COMMENTS Use controlled impedance media. The connectors you use should have a matched differential impedance of about Zo . They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M d 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. 10 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: DS92CK16 DS92CK16 www.ti.com SNAS044C - NOVEMBER 1999 - REVISED APRIL 2013 REVISION HISTORY Changes from Revision B (April 2013) to Revision C * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 10 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: DS92CK16 11 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) DS92CK16TMTC ACTIVE TSSOP PW 24 61 TBD Call TI Call TI -40 to 85 DS92CK16T MTC DS92CK16TMTC/NOPB ACTIVE TSSOP PW 24 61 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 DS92CK16T MTC DS92CK16TMTCX/NOPB ACTIVE TSSOP PW 24 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 DS92CK16T MTC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS92CK16TMTCX/NOPB TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92CK16TMTCX/NOPB TSSOP PW 24 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE PW0024A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 22X 0.65 24 1 2X 7.15 7.9 7.7 NOTE 3 12 13 B 0.30 0.19 0.1 C A B 24X 4.5 4.3 NOTE 4 1.2 MAX 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0 -8 0.75 0.50 DETAIL A A 20 TYPICAL 4220208/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com EXAMPLE BOARD LAYOUT PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE SYMM 24X (1.5) (R0.05) TYP 1 24 24X (0.45) 22X (0.65) SYMM 13 12 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND NON-SOLDER MASK DEFINED (PREFERRED) 0.05 MIN ALL AROUND SOLDER MASK DEFINED SOLDER MASK DETAILS 15.000 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24 24X (0.45) 22X (0.65) SYMM 12 13 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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