General Description
The MAX696/MAX697 supervisory circuits reduce the
complexity and number of components required for
power-supply monitoring and battery-control functions
in microprocessor (µP) systems. These include µP reset
and backup-battery switchover, watchdog timer, CMOS
RAM write protection, and power-failure warning. The
MAX696/MAX697 significantly improve system reliability
and accuracy compared to that obtained with separate
ICs or discrete components.
The MAX696 and MAX697 are supplied in 16-pin pack-
ages and perform six functions:
1) A reset output during power-up, power-down, and
brownout conditions. The threshold for this “low-
line” reset is adjustable by an external voltage-
divider.
2) A reset pulse if the optional watchdog timer has not
been toggled within a specified time.
3) Individual outputs for low-line and watchdog fault
conditions.
4) The reset time may be left at its default value of
50ms, or may be varied with an external capacitor
or clock pulses.
5) A separate 1.3V threshold detector for power-fail
warning, low-battery detection, or to monitor a
power supply other than VCC.
The MAX696 also has battery-backup switching for
CMOS RAM, CMOS microprocessor, or other low-
power logic.
The MAX697 lacks battery-backup switching, but has
write-protection pins (CE IN and CE OUT) for CMOS
RAM or EPROM. In addition, it consumes less than 250
microamperes.
Applications
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical µP Power Monitoring
Features
♦Adjustable Low-Line Monitor and Power-Down
Reset
♦Power-OK/Reset Time Delay
♦Watchdog Timer—100ms, 1.6s, or Adjustable
♦Minimum Component Count
♦1µA Standby Current
♦Battery-Backup Power Switching (MAX696)
♦On-Board Gating of Chip-Enable Signals
(MAX697)
♦Separate Monitor for Power-Fail or Low-Battery
Warning
MAX696/MAX697
Microprocessor Supervisory Circuits
________________________________________________________________ Maxim Integrated Products 1
19-0829; Rev 3; 11/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
VOUT
VBATT
VCC
GND LLIN
MAX696
1
2
3
4
16
15
14
13
N.C.
BATT ON
PFI
WDI
5
6
7
8
12
11
10
9
OSC IN
OSC SEL
PFO
LOW LINE
TOP VIEW
RESET
RESET
WDO
Pin Configurations
Ordering Information
PART TEMP RANGE
PIN-PACKAGE
MAX696C/D 0°C to +70°C Dice
MAX696CPE 0°C to +70°C 16 PDIP
MAX696CWE 0°C to +70°C 16 Wide SO
MAX696EPE -40°C to +85°C 16 PDIP
MAX696EJE -40°C to +85°C 16 CERDIP
MAX696EWE -40°C to +85°C 16 Wide SO
MAX696MJE -55°C to +125°C 16 CERDIP
Devices in PDIP and SO packages are available in both lead-
ed and lead-free packaging. Specify lead free by adding the +
symbol at the end of the part number when ordering. Lead free
not available for CERDIP package.
Ordering Information continued at end of data sheet.
Pin Configurations continued at end of data sheet.
Typical Operating Circuit appears at end of data sheet.
MAX696/MAX697
Microprocessor Supervisory Circuits
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = full operating range, VBATT = 2.8V, TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
MAX696 V
CC
3.0 5.5
MAX696 V
BATT
2.0 V
CC
-
0.3V
Operating Voltage Range T
A
= full
MAX697 V
CC
3.0 5.5
V
Supply Current (MAX697) T
A
= full
160
300 µA
BATTERY-BACKUP SWITCHING (MAX696)
I
OUT
= 1mA, T
A
= full V
CC
-
0.3
V
CC
-
0.1
V
OUT
Output Voltage
I
OUT
= 50mA, T
A
= full V
CC
-
0.5
V
CC
-
0.25
V
V
OUT
in Battery-Backup Mode I
OUT
= 250µA, V
CC
< (V
BATT
- 0.2V), T
A
= full V
BATT
-
0.1
V
BATT
- 0.02
V
I
OUT
= 1mA 1.5 4
Supply Current (Excludes I
OUT
)I
OUT
= 50mA 2.5 7 mA
V
CC
= 0V, V
BATT
= 2.8V, T
A
= +25°C 0.6 1
Supply Current in Battery-Backup
Mode V
CC
= 0V, V
BATT
= 2.8V, T
A
= full 10 µA
T
A
= +25°C
-100 +20
nA
Battery Standby Leakage Current
5.5V > V
CC
> (V
BATT
+
0.3V) T
A
= full
-1.00 +0.02
µA
Power-up 70
Battery Switchover Threshold
V
CC
- V
BATT
Power-down 50 mV
Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage I
SINK
- 1.6mA 0.4 V
BATT ON = V
OUT
= 2.4V sink current 7 mA
BATT ON Output Short-Circuit
Current BATT ON = V
OUT
, V
CC
= 0V 0.5 2.5
25.0
µA
RESET AND WATCHDOG TIMER
Low-Line Voltage Threshold
(LL
IN
)V
CC
= +5V, +3V; T
A
= full
1.25 1.30 1.35
V
Note 1: The input voltage limits on PFI and WDI may be exceeded providing the input current is limited to less than 10mA.
Terminal Voltage (with respect to GND)
VCC .......................................................................-0.3V to +6V
VBATT....................................................................-0.3V to +6V
All Other Inputs (Note 1).......................-0.3V to (VOUT + 0.5V)
Input Current
VCC.............................................................................................200mA
VBATT............................................................................................50mA
GND..............................................................................................20mA
Output Current
VOUT .............................................................Short-Circuit Protected
All Other Outputs ......................................................................20mA
Rate-of-Rise, VBATT, VCC ........................................................100V/µs
Operating Temperature Range
C Suffix ..........................................................................0°C to +70°C
E Suffix .......................................................................-40°C to +85°C
M Suffix....................................................................-55°C to +125°C
Power Dissipation (TA= +70°C)
16-Pin PDIP (derated 7mW/°C above +70°C)................600mW
16-Pin SO (derated 7mW/°C above +70°C) ...................600mW
16-Pin CERDIP (derated 10mW/°C above +85°C)........600mW
Storage Temperature Range ..................................-65°C to +160°C
Lead Temperature (soldering, 10s).......................................+300°C
MAX696/MAX697
Microprocessor Supervisory Circuits
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = full operating range, VBATT = 2.8V, TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
Reset Timeout Delay Figure 6, OSC SEL HIGH, V
CC
= 5V 35 50 70 ms
Long period, V
CC
= 5V
1.00
1.6
2.25
s
Watchdog Timeout Period,
Internal Oscillator Short period, V
CC
= 5V 70
100
140 ms
Long period
4032 4097
Watchdog Timeout Period,
External Clock Short period 960
1025
Clock
cycles
Minimum WDI Input Pulse Width V
IL
= 0.4V, V
IH
= 3.5V, V
CC
= 5V 200 ns
I
SINK
= 400µA, V
CC
= 2V, V
BATT
= 0V 0.4
I
SINK
= 1.6mA, 3V < V
CC
< 5.5V 0.4
RESET and RESET Output
Voltage (Note 2)
I
SOURCE
= 1µA, V
CC
= 5V 3.5
V
I
SINK
= 800µA, T
A
= full 0.4
LOW LINE and WDO Output
Voltage I
SOURCE
= 1µA, V
CC
= 5V, T
A
= full 3.5 V
Output Short-Circuit Current RESET, RESET, WDO, LOW LINE 1325µA
Logic-low 0.8
Logic-high (MAX696) 3.5WDI Input Threshold V
CC
= 5V
(Note 3)
Logic-high (MAX697) 3.8
V
WDI = V
OUT
20 50
WDI Input Current WDI = 0V -50 -15 µA
POWER-FAIL DETECTOR
PFI Input Threshold V
CC
= 3V, 5V 1.2 1.3 1.4 V
PFI - LL
IN
Threshold Difference V
CC
= 3V, 5V
±15 ±50
mV
PFI Input Current
±0.01 ±25
nA
MAX697 -25
±0.01 +25
LL
IN
Input Current MAX696
-500 ±0.01 +25
nA
I
SINK
= 1.6mA 0.4
PFO Output Voltage I
SOURCE
= 1µA, V
CC
= 5V 3.5 V
PFO Short-Circuit Source Current
PFI = 0V, PFO = 0V 1 3 25 µA
CHIP-ENABLE GATING (MAX697)
V
IL
0.8
CE IN Thresholds V
IH
, V
CC
= 5V 3.0 V
CE IN Pullup Current 3µA
I
SINK
= 1.6mA 0.4
I
SOURCE
= 800µA V
CC
-
0.5V
CE OUT Output Voltage
I
SOURCE
= 1µA, V
CC
= 0V V
CC
-
0.05V
V
CE Propagation Delay V
CC
= 5V 80 150 ns
OSCILLATOR
OSC IN Input Current ±2 µA
OSC SEL Input Pullup Current 5µA
OSC IN Frequency Range OSC SEL = 0V 0 250 kHz
OSC IN Frequency with External
Capacitor OSC SEL = 0V, C
OSC
= 47pF 4 kHz
Note 2: TA= full operating range.
Note 3: WDI is guaranteed to be in the mid-level (inactive) state if WDI is floating and VCC is in the operating voltage range. WDI is
internally biased to 38% of VCC with an impedance of approximately 125kΩ.
MAX696/MAX697
Microprocessor Supervisory Circuits
4_______________________________________________________________________________________
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX696
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
VCC MODE
543
0.25
0.50
0.75
1.00
1.25
1.50
0
0.25
0.50
0.75
1.00
1.25
1.50
0
26
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
SUPPLY CURRENT (µA)
BATTERY MODE
MAX697
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
543
50
100
150
200
250
0
26
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
RESET TIMEOUT DELAY
(ms)
543
50
100
150
200
250
300
0
26
RESET TIMEOUT DELAY AS A
FUNCTION OF SUPPLY VOLTAGE
TA = 25°C
VCC MODE
TA = +25°C
TA = +25°C
BATTERY MODE
MAX696/MAX697
Microprocessor Supervisory Circuits
_______________________________________________________________________________________ 5
Pin Description
PIN
MAX696 MAX697 NAME FUNCTION
1—V
BATT
Backup-Battery Input. Connect to ground if a backup battery is not used.
2—V
OUT
The higher of V
CC
or V
BATT
is internally switched to V
OUT
. Connect V
OUT
to V
CC
if
V
OUT
and V
BATT
are not used.
33V
CC
+5V Input
45GND 0V Ground Reference for All Signals
5—BATT ON
BATT ON goes High when V
OUT
is Internally Switched to the V
BATT
Input. It goes low
when V
OUT
is internally switched to V
CC
. The output typically sinks 7mA and can
directly drive the base of an external pnp transistor to increase the output current
above the 50mA rating of V
OUT
.
66LOW LINE LOW LINE goes Low when LL
IN
Falls Below 1.3V. It returns high as soon as LL
IN
rises above 1.3V. See Figure 5.
77OSC IN
OSC IN Sets the Reset Delay Timing and Watchdog Timeout Period when OSC SEL
Floats or is Driven Low. The timing can also be adjusted by connecting an external
capacitor to this pin. See Figure 7. When OSC SEL is high, OSC IN selects between
fast and slow watchdog timeout periods
88OSC SEL
When OSC SEL is Unconnected or Driven High, the Internal Oscillator Sets the Reset
Time Delay and Watchdog Timeout Period. When OSC SEL is low, the external
99PFI PFI is the Noninverting Input to the Power-Fail Comparator. When PFI is less than
1.3V, PFO goes low. Connect PFI to GND or V
OUT
when not used. See Figure 1.
10 10 PFO PFO is the Output of the Power-Fail Comparator. It goes low when PFI is less than
1.3V. The comparator is turned off and PFO goes low when V
CC
is below V
BATT
.
11 11 WDI
The Watchdog Input, WDI, is a Three-Level Input. If WDI remains either high or low
for longer than the watchdog timeout period, RESET pulses low and WDO goes low.
The watchdog timer is disabled when WDI is left floating or is driven to mid-supply.
The timer resets with each transition at the watchdog timer input.
12 2 N.C. No Connection. Leave this pin open.
13 4 LL
IN
Low-Line Input. LL
IN
is the CMOS input to a comparator whose other input is a
precision 1.3V reference. The output is LOW LINE and is also connected to the reset
pulse generator. See Figure 2.
14 14 WDO
The Watchdog Output, WDO, goes Low if WDI Remains either High or Low for
Longer than the Watchdog Timeout Period. WDO is set high by the next transition at
WDI. If WDI is unconnected or at mid-supply, WDO remains high. WDO also goes
high when LOW LINE goes low.
15 15 RESET
RESET goes Low whenever LL
IN
Falls Below 1.3V or V
CC
Falls Below the V
BATT
Input Voltage. RESET remains low for 50ms after LL
IN
goes above 1.3V. RESET also
goes low for 50ms if the watchdog timer is enabled but not serviced within its
timeout period. The RESET pulse width can be adjusted as shown in Table 1.
16 16 RESET RESET is an Active-High Output. It is the inverse of RESET.
MAX696/MAX697
6_______________________________________________________________________________________
Pin Description (continued)
PIN
MAX696 MAX697 NAME FUNCTION
—1TEST Used During Maxim Manufacture Only. Always ground this pin.
—12CE OUT CE OUT goes low only when CE IN is low and LLIN is above 1.3V. See Figure 5.
—13CE IN The Input to the CE Gating Circuit. Connect to GND or VOUT if not used.
Typical Applications
MAX696
A typical connection for the MAX696 is shown in Figure
1. CMOS RAM is powered from VOUT. VOUT is internally
connected to VCC when power is present, or to VBATT
when VCC is less than the battery voltage. VOUT can sup-
ply 50mA from VCC, but if more current is required, an
external pnp transistor can be added. When VCC is high-
er than VBATT, the BATT ON output goes low, providing
7mA of base drive for the external transistor. When VCC
is lower than VBATT, an internal 200ΩMOSFET connects
the backup battery to VOUT. The quiescent current in the
battery-backup mode is 1µA maximum when VCC is
between 0V and (VBATT - 700mV).
Reset Output
A voltage detector monitors VCC and generates a RESET
output to hold the microprocessor’s RESET line low when
LLIN is below 1.3V. An internal monostable holds RESET
0.1µF
0.1µF
35
2
VOUT
V
VCC
BATT
RESETRESET
LOW LINE
RESET
LLIN
PFO
WDO
BATT ON
CMOS
RAM
A0–A15
MICROPROCESSOR
11
10
15
18
I/O
NMI
WDI
OTHER SYSTEM RESET SOURCES
SYSTEM STATUS INDICATORS
AUDIBLE
ALARM
146
+5V
V
INPUT
CC
1
9
4
7
8
13
PFI
GND
OSC IN
OSC SEL
NO CONNECTION
RESET
3V
BATTERY
MAX696
Figure 1. MAX696 Typical Application
Microprocessor Supervisory Circuits
low for 50ms after LLIN rises above 1.3V. This prevents
repeated toggling of RESET even if the VCC power drops
out and recovers with each power line cycle.
The crystal oscillator normally used to generate the clock
for microprocessors takes several milliseconds to start.
Since most microprocessors need several clock cycles
to reset, RESET must be held low until the microproces-
sor clock oscillator has started. The power-up RESET
pulse lasts 50ms to allow for this oscillator startup time.
An inverted, active-high RESET output is also supplied.
Power-Fail Detector
The MAX696 issues a nonmaskable interrupt (NMI) to
the microprocessor when a power failure occurs. The
power line is monitored by two external resistors con-
nected to the power-fail input (PFI). When the voltage at
PFI falls below 1.3V, the power-fail output (PFO) drives
the processor’s NMI input low. An earlier power-fail
warning can be generated if the unregulated DC input
of the regulator is available for monitoring.
Watchdog Timer
The microprocessor drives the watchdog input (WDI)
with an I/O line. When OSC IN and OSC SEL are uncon-
nected, the microprocessor must toggle the WDI pin
once every 1.6 seconds to verify proper software execu-
tion. If a hardware or software failure occurs so that WDI
is not toggled, the MAX696 will issue a 50ms RESET
pulse after 1.6 seconds. This typically restarts the micro-
processor’s power-up routine. A new RESET pulse is
issued every 1.6 seconds until WDI is again strobed.
The watchdog output (WDO) goes low if the watchdog
timer is not serviced within its timeout period. Once
WDO goes low, it remains low until a transition occurs
at WDI while RESET is high. The watchdog timer fea-
ture can be disabled by leaving WDI unconnected.
OSC IN and OSC SEL also allow other watchdog timing
options, as shown in Table 1 and Figure 7.
MAX696/MAX697
Microprocessor Supervisory Circuits
_______________________________________________________________________________________ 7
+
-
+
-
+
-
BATT ON (MAX696)
V (MAX696)
OUT
V (MAX696)
BATT
VCC
CHIP-ENABLE OUTPUT (MAX697)
LOW LINE
RESET
RESET
WATCHDOG OUTPUT
POWER-FAIL OUTPUT
2
12
6
15
16
14
10
WATCHDOG
TIMER
GROUND
4
1.30V
POWER-FAIL
INPUT
WATCHDOG TRANSITION
DETECTOR
TIMEBASE FOR RESET
AND
WATCHDOG
RESET GENERATOR
WATCHDOG INPUT
9
11
8
7
LLIN
OSC IN
OSC SEL
(MAX697) CHIP-ENABLE INPUT
13
3
15
Figure 2. MAX696/MAX697 Block Diagram
MAX696/MAX697
Microprocessor Supervisory Circuits
8_______________________________________________________________________________________
+
-
+
-
P
700mV
100mV
3V
BATTERY
INPUT
BASE DRIVE
VCC
0.1µF
TO CMOS
RAM AND
REAL-TIME
CLOCK
V IN
CC
BATT ON
p-CHANNEL
MOSFET
INTERNAL
SHUTDOWN
SIGNAL WHEN
V > V + 0.7V
BATT CC
LOW IQ MODE SELECT
VOUT
V
+5V
CC
V
BATT
Figure 3. MAX696 Battery-Switchover Block Diagram
MAX697
The MAX697 is nearly identical to the MAX696. The
MAX697 lacks the battery-backup feature, so it does
not have the VBATT, VOUT, or BATT ON pins. This
allows the MAX697 to consume less than 250 microam-
peres, and it allows the inclusion of RAM write-protec-
tion pins. See Figure 2.
Detailed Description
Battery Switchover and VOUT (MAX696)
The battery-switchover circuit compares VCC to the
VBATT input, and connects VOUT to whichever is higher.
Switchover occurs when VCC is 50mV greater than
VBATT as VCC falls, and when VCC is 70mV more than
VBATT as VCC rises (see Figure 3). The switchover com-
parator has 20mV of hysteresis to prevent repeated,
rapid switching if VCC falls very slowly or remains near-
ly equal to the battery voltage.
When VCC is higher than VBATT, VCC is internally switched
to VOUT with a low-saturation pnp transistor. VOUT has
50mA output current capability. Use an external pnp pass
transistor in parallel with the internal transistor if the out-
put current requirement at VOUT exceeds 50mA or if a
lower VCC - VOUT voltage differential is desired. The
BATT ON output can directly drive the base of the
external transistor.
It should be noted that the MAX696 need only supply the
average current drawn by the CMOS RAM if there is ade-
quate filtering. Many RAM data sheets specify a 75mA
maximum supply current, but this peak current spike
lasts only 100ns. A 0.1µF bypass capacitor at VOUT sup-
plies the high instantaneous current, while VOUT need
only supply the average load current, which is much
less. A capacitance of 0.1µF or greater must be connect-
ed to the VOUT terminal to ensure stability.
A 200ΩMOSFET connects the VBATT input to VOUT
during battery backup. This MOSFET has very low
input-to-output differential (dropout voltage) at the low
current levels required for battery backup of CMOS
RAM or other low-power CMOS circuitry. When VCC
equals VBATT, the supply current is typically 12µA.
When VCC is between 0V and (VBATT - 700mV), the typ-
ical supply current is only 600nA (typ), 1µA (max).
MAX696/MAX697
Microprocessor Supervisory Circuits
_______________________________________________________________________________________ 9
The MAX696 operates with battery voltages from 2.0V
to 4.25V. The battery voltage should not be within 0.5V
of VCC, or switchover may occur. High-value capaci-
tors, either standard electrolytic or the farad-size dou-
ble-layer capacitors, can also be used for short-term
memory backup. The capacitor charging voltage
should include a diode to limit the fully charged voltage
to approximately 0.5V less than VCC. The charging
resistor for rechargeable batteries should be connect-
ed to VOUT since this eliminates the discharge path that
exists if the resistor is connected to VCC.
A small leakage current of typically 10nA (20nA max)
flows out of the VBATT terminal. This current varies with
the amount of current that is drawn from VOUT, but its
polarity is such that the backup battery is always slight-
ly charged, and is never discharged while VCC is in its
operating voltage range. This extends the shelf life of
the backup battery by compensating for its self-dis-
charge current. Also note that this current poses no
problem when lithium batteries are used for backup
since the maximum current (20nA) is safe for even the
smallest lithium cells.
If the battery-switchover section is not used, connect
VBATT to GND and connect VOUT to VCC. Table 2
shows the state of the inputs and output in the low-
power battery-backup mode.
Reset Output
RESET is an active-low output that goes low whenever
LLIN falls below 1.3V. It remains low until LLIN rises
above 1.312V for 50ms. (See Figures 4 and 5.)
The guaranteed minimum and maximum low-line thresh-
olds of the MAX696/MAX697 are 1.2V and 1.4V. The
LLIN comparator has approximately 12mV of hysteresis.
The response time of the reset voltage comparator is
about 100µs. LLIN should be bypassed to ensure that
glitches do not activate the RESET output.
RESET also goes low if the watchdog timer is enabled
and WDI remains either high or low longer than the
watchdog timeout period. RESET has an internal 3µA
pullup, and can either connect to an open-collector
reset bus or directly drive a CMOS gate without an
external pullup resistor.
(MAX697) CE IN CE OUT (MAX697)
LOW LINE
VCC
LLIN
WATCHDOG
FROM
WATCHDOG
TIMER
10kHz CLOCK
FROM TIMEBASE
SECTION
RESET RESET
TIME Qn
+
-
POWER-ON
RESET
RESET
RESET
13V
Figure 4. Reset Block Diagram
MAX696/MAX697
Microprocessor Supervisory Circuits
10 ______________________________________________________________________________________
CE
Gating and
RAM Write Protection
The MAX697 uses two pins to control the CE or WRITE
inputs of CMOS RAMs. When LLIN is > 1.3V, CE OUT is
a buffered replica of CE IN, with a 50ns propagation
delay. If LLIN input falls below 1.3V (1.2V min, 1.4V
max), an internal gate forces CE OUT high, indepen-
dent of CE IN. The CE output is also forced high when
VCC is less than VBATT. (See Figure 4.)
CE OUT typically drives the CE, CS, or WRITE input of
battery backed up CMOS RAM. This ensures the
integrity of the data in memory by preventing write
operations when VCC is at an invalid level. Similar pro-
tection of EEPROMs can be achieved by using the CE
OUT to drive the STORE or WRITE inputs of an EEP-
ROM, EAROM, or NOVRAM.
If the 50ns typical propagation delay of CE OUT is too
long, connect CE IN to GND and use the resulting CE
OUT to control a high-speed external logic gate. A sec-
ond alternative is to AND the LOW LINE output with the
CE or WR signal. An external logic gate and the RESET
output of the MAX696/MAX697 can also be used for
CMOS RAM write protection.
1.25V Comparator and Power-Fail Warning
The power-fail input (PFI) is compared to an internal
1.3V reference. The power-fail output (PFO) goes low
when the voltage at PFI is less than 1.3V. Typically PFI
is driven bay an external voltage-divider that senses
either the unregulated DC input to the system’s VCC
regulator or the regulated output. The voltage-divider
ration can be chosen so the voltage at PFI falls below
1.3V several milliseconds before the LLIN falls below
1.3V. PFO is normally used to interrupt the micro-
processor so that data can be stored in RAM before
LLIN falls below 1.3V and the RESET output goes low.
The power-fail detector can also monitor the backup
battery to warn of a low-battery condition. To conserve
battery power, the power-fail detector comparator is
turned off and PFO is forced low when VCC is lower
than the VBATT input voltage.
Watchdog Timer and Oscillator
The watchdog circuit monitors the activity of the micro-
processor. If the microprocessor does not toggle the
watchdog input (WDI) within the selected timeout period,
a 50ms RESET pulse is generated. Since many systems
cannot service the watchdog timer immediately after a
reset, the MAX696/MAX697 have a longer timeout period
after a reset is issued. The normal timeout period
LLIN
1.3V 1.312V 1.3V 1.312V
50ms 50ms
LOW LINE
OUTPUT
(MAX697) CE IN
(MAX697) CE OUT
RESET
OUTPUT
Figure 5. MAX697 Reset Timing
becomes effective following the first transition of WDI
after RESET has gone high. The watchdog timer is
restarted at the end of reset, whether the reset was
caused by lack of activity on WDI or by LLIN falling
below 1.3V. If WDI remains either high or low, reset puls-
es will be issued every 1.6s. The watchdog monitor can
be deactivated by floating the watchdog input (WDI).
The watchdog output (WDO) goes low if the watchdog
timer times out, and it remains low until set high by the
next transition on the watchdog input. WDO is also set
high when LLIN goes below 1.3V.
The watchdog timeout period defaults to 1.6s and the
reset pulse width defaults to 50ms. The MAX696 and
MAX697 allow these times to be adjusted per Table 1.
The internal oscillator is enabled when OSC SEL is high
or floating. In this mode, OSC IN selects between the 1.6s
and 100ms watchdog timeout periods. In either case,
immediately after a reset, the timeout period is 1.6s. This
gives the microprocessor time to reinitialize the system.
WD transmissions while RESET is low are ignored. If OSC
IN is low, then the 100ms watchdog period becomes
effective after the first transition of WDI. The software
should be written so the I/O port driving WDI is left in its
power-up reset state until the initialization routines are
completed and the microprocessor is able to toggle WDI
at the minimum 70ms watchdog timeout period.
MAX696/MAX697
Microprocessor Supervisory Circuits
______________________________________________________________________________________ 11
WATCHDOG
TIMEOUT
SELECTOR
LOGIC
WATCHDOG
COUNTER
PRESCALER
RESET
COUNTER
Q6
Q11
Q13
Q15RR Q10/12
WATCHDOG
FAULT FF
LONG/SHORT
FF
RESET
FLIP FLOP
R
QQ Q
10.24kHz FROM INTERNAL OSCILLATOR
OR EXTERNALLY SET FREQUENCY FROM
OSC IN PIN
SR SRSQ
LOW
LINE
GOES HIGH AT THE
END OF WATCHDOG
TIMEOUT PERIOD
RESET RESET
TRANSITION
DETECTOR
LOW LINE
(HI IF LL < 1.3V)
IN
FOR EACH TRANSITION
+
-
+
-
VCC
1.0V
2.7V
WATCHDOG INPUT
HI IF WATCHDOG
INPUT IS FLOATING WATCHDOG TIMEOUT SELECT
WATCHDOG OUTPUT
Figure 6. Watchdog Timer Block Diagram
MAX696/MAX697
Microprocessor Supervisory Circuits
12 ______________________________________________________________________________________
Applications Information
Adding Hysteresis to the Power-Fail
Comparator
Since the power-fail comparator circuit is noninverting,
hysteresis can be added by connecting a resistor
between the PFO output and the PFI input as shown in
Figure 7. When PFO is low, resistor R3 sinks current
from the summing junction at the PFI pin. When PFO is
high, the series combination of R3 and R4 source cur-
rent into the PFI summing junction.
Alternate Watchdog Input Drive Circuits
The watchdog feature can be enabled and disabled
under program control by driving WDI with a three-state
buffer (Figure 8). The drawback to this circuit is that a
software fault may erroneously three-state the buffer,
thereby preventing the MAX696/MAX697 from detect-
ing that the microprocessor is no longer working. In
most cases, a better method is to extend the watchdog
period rather than disabling the watchdog. See Figure
9. When the control input is high, the OSC SEL pin is
low and the watchdog timeout is set by the external
capacitor. A 0.01µF capacitor sets a watchdog timeout
delay of 100s. When the control input is low, the OSC
SEL pin is driven high, selecting the internal oscillator.
The 100ms or the 1.6s period is chosen, depending on
which diode in Figure 9 is used.
MAX696
MAX697
VCC
PFO
PFI GND
7805
7V - 15V +5V
R1
75kΩ
R4
10kΩ
R2
13kΩ
R3
300kΩ
TO µP
VH = 9.125V
VL = 7.9V
HYSTERESIS = 1.23V
V = 1.3V
V = 1.3V
H
L
{ }
1 + +
R1
R2
R1
R3
{ }
1 + +
R1
R2
(5V - 1.3V) R1
1.3V (R3 + R4)
HYSTERESIS ≈ 5V x R1
R3
ASSUMING R4 << R3
Figure 7. Adding Hysteresis to the Power-Fail Voltage
Comparator
MAX696
MAX697
WDI
GND
+5V
WATCHDOG
STROBE
WATCHDOG
DISABLE
EN
VCC
Figure 8. Disabling the Watchdog Under Program Control
MAX696
MAX697
OSC SEL
OSC IN
GND
+5V
VCC
LOW = INTERNAL
WATCHDOG TIMEOUT
HI = EXTERNAL
WATCHDOG
TIMEOUT
CONNECT FOR
100ms TIMEOUT
WHEN INTERNAL
TIMEOUT IS
SELECTED CONNECT FOR
1.6s INTERNAL
TIMEOUT
Figure 9. Selecting Internal or External Watchdog Timeout
MAX696/MAX697
Microprocessor Supervisory Circuits
______________________________________________________________________________________ 13
WATCHDOG TIMEOUT PERIOD
OSC SEL
(Note 3) OSC IN NORMAL IMMEDIATELY
AFTER RESET
RESET TIMEOUT
PERIOD
Low
External Clock Input
1024 clocks 4096 clocks 512 clocks
Low External Capacitor 400ms/47pF x C 1.6s/47pF x C 200ms/47pF x C
High/Floating Low 100ms 1.6s 50ms
High/Floating Floating 1.6s 1.6s 50ms
Table 1. MAX696 and MAX697 Reset Pulse Width and Watchdog Timeout Selections
(Notes 1, 2)
Note 1: When the MAX696/MAX697 OSC SEL pin is low, OSC IN can be driven by an external clock signal, or an external capacitor
can be connected between OSC IN and GND. The nominal internal oscillator frequency is 10.24kHz. The nominal oscillator
frequency with external capacitor is fOSC (Hz) = 184,000/COSC (pF).
Note 2: See the Electrical Characteristics table for minimum and maximum timing values.
Note 3: High for the OSC SEL pin should be connected to VOUT, not VCC (on the MAX696).
I/O STATUS
VBATT, VOUT VBATT is connected to VOUT with an internal MOSFET (MAX696 only).
RESET Logic-low.
RESET Logic-high. The open-circuit output voltage is equal to VOUT.
LOW LINE Logic-low.
BATT ON Logic-high (MAX696 only).
WDI
WDI is internally disconnected from its internal pullup and does not source or sink current as
long as its input voltage is between GND and VOUT. The input voltage does not affect supply
current.
WDO Logic-high.
PFI The power-fail comparator is turned off and the power-fail input voltage has no effect on the
power-fail output.
PFO Logic-low.
CE IN
CE IN is internally disconnected from its internal pullup and does not source or sink current
as long as its input voltage is between GND and VOUT. The input voltage does not affect
supply current (MAX696 only).
CE OUT Logic-high (MAX697 only).
OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.
VCC
Approximately 12µA is drawn from the VBATT input when VCC is between (VBATT + 100mV)
and (VBATT - 700mV). The supply current is 1µA maximum when VCC is less than VBATT -
700mV.
Table 2. Input and Output Status in Battery-Backup Mode
Typical Operating Circuit
POWER TO
CMOS RAM
µP
POWER
µP
SYSTEM
VOUT
VBATT
VCC
µP RESET
RESET
LLIN
PFO
WDI I/O
LINE
µP NMI
-5V
PFI
GND
RESET
MAX696
MAX696/MAX697
Microprocessor Supervisory Circuits
14 ______________________________________________________________________________________
Ordering Information
PART TEMP RANGE
PIN-PACKAGE
MAX697C/D 0°C to +70°C Dice
MAX697CPE 0°C to +70°C 16 PDIP
MAX697CWE 0°C to +70°C 16 Wide SO
MAX697EPE -40°C to +85°C 16 PDIP
MAX697EJE -40°C to +85°C 16 CERDIP
MAX697EWE -40°C to +85°C 16 Wide SO
MAX697MJE -55°C to +125°C 16 CERDIP
CE IN
VCC
LLIN
MAX697
N.C. RESET
RESET
TEST
WDO
1
2
3
4
16
15
14
13
GND
LOW LINE
OSC SEL
OSC IN
PFI
WDI
5
6
7
8
12
11
10
9
TOP VIEW
PFO
CE OUT
Pin Configurations (continued)
Devices in PDIP and SO packages are available in both lead-
ed and lead-free packaging. Specify lead free by adding the +
symbol at the end of the part number when ordering. Lead free
not available for CERDIP package.
MAX696/MAX697
Microprocessor Supervisory Circuits
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Chip Topography
Package Information
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