MIC502YM T&R - Micrel Semiconductor, Inc.

August 2001 1 MIC502

MIC502 Micrel

MIC502

Fan Management IC

Final Information

Features

• Temperature-proportional fan speed control

• Low-cost, efficient PWM fan drive

• 4.5V to 13.2V IC supply range

• Controls any voltage fan

• Overtemperature detection with fault output

• Integrated fan startup timer

• Automatic user-specified sleep mode

• Supports low-cost NTC/PTC thermistors

• 8-pin DIP and SOIC packages

Applications

• NLX and ATX power supplies

• Personal computers

• File servers

• Telecom and networking hardware

• Printers, copiers, and office equipment

• Instrumentation

• Uninterruptable power supplies

• Power amplifiers

Ordering Information

Part Number Temperature Range Package

MIC502BN –40°C to +85°C 8-pin Plastic DIP

MIC502BM –40°C to +85°C 8-pin SOIC

General Description

The MIC502 is a thermal and fan management IC which

supports the features for NLX/ATX power supplies and other

control applications.

Fan speed is determined by an external temperature sensor,

typically a thermistor-resistor divider, and (optionally) a sec-

ond signal, such as the NLX “FanC” signal. The MIC502

produces a low-frequency pulse-width modulated output for

driving an external motor drive transistor. Low-frequency

PWM speed control allows operation of standard brushless

dc fans at low duty cycle for reduced acoustic noise and

permits the use of a very small power transistor. The PWM

time base is determined by an external capacitor.

An open-collector overtemperature fault output is asserted if

the primary control input is driven above the normal control

range.

The MIC502 features a low-power sleep mode with a user-

determined threshold. Sleep mode completely turns off the

fan and occurs when the system is asleep or off (both control

inputs very low). A complete shutdown or reset can also be

initiated by external circuitry as desired.

The MIC502 is available as 8-pin plastic DIP and SOIC

packages in the –40°C to +85°C industrial temperature

range.

Typical Application

VT1

VSLP

GND

VDD

OUT

OTF

VT2

R1T1

R4 CF

12V

RBASE

Overtemperature

Fault Output

MIC502

Secondary

Fan-control

Input

Fan

Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com

MIC502 Micrel

MIC502 2 August 2001

Pin Description

Pin Number Pin Name Pin Function

1 VT1 Thermistor 1 (Input): Analog input of approximately 30% to 70% of VDD

produces active duty cycle of 0% to 100% at driver output (OUT). Connect to

external thermistor network (or other temperature sensor). Pull low for

shutdown.

2 CF PWM Timing Capacitor (External Component): Positive terminal for the

PWM triangle-wave generator timing capacitor. The recommended CF is

0.1µF for 30Hz PWM operation.

3 VSLP Sleep Threshold (Input): The voltage on this pin is compared to VT1 and VT2.

When VT1 < VSLP and VT2 < VSLP the MIC502 enters sleep mode until VT1 or

VT2 rises above VWAKE. (VWAKE = VSLP + VHYST.) Grounding VSLP

disables the sleep-mode function.

4 GND Ground

5 VT2 Thermistor 2 (Input): Analog input of approximately 30% to 70% of VDD

produces active duty cycle of 0% to 100% at driver output (OUT). Connect to

motherboard fan control signal or second temperature sensor.

6 /OTF Overtemperature Fault (Output): Open-collector output (active low).

Indicates overtemperature fault condition (VT1 > VOT) when active.

7 OUT Driver Output: Asymmetical-drive active-high complimentary PWM output.

Typically connect to base of external NPN motor control transistor.

8 VDD Power Supply (Input): IC supply input; may be independent of fan power

supply.

Pin Configuration

VDD

OUT

OTF

VT2

VT1

VSLP

GND

8-Pin SOIC (M)

8-Pin DIP (N)

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Absolute Maxim um Ratings (Note 1)

Supply Voltage (VDD) ..................................................+14V

Output Sink Current (IOUT(sink))..................................10mA

Output Source Current (IOUT(source)) ..........................25mA

Input Voltage (any pin) .........................–0.3V to VDD +0.3V

Junction Temperature (TJ) ...................................... +125°C

Storage Temperature (TA) ....................... –65°C to +150°C

Lead Temperature (Soldering, 5 sec.) ...................... 260°C

ESD, Note 3

Operating Ratings (Note 2)

Supply Voltage (VDD) ................................ +4.5V to +13.2V

Sleep Voltage (VSLP)........................................GND to VDD

Temperature Range (TA) ...........................–40°C to +85°C

Power Dissipation at 25°C

SOIC ...................................................................800mW

DIP ......................................................................740mW

Derating Factors

SOIC ...............................................................8.3mW/°C

Plastic DIP.......................................................7.7mW/°C

Electrical Characteristics

4.5V ≤ VDD ≤ 13.2V, Note 4; TA = 25, bold values indicate –40°C ≤ TA ≤ +85°C; unless noted

Symbol Parameter Condition Min Typ Max Units

IDD Supply Current, Operating VSLP = grounded, OTF, OUT = open, 0.5 1.2 mA

CF = 0.1µF, VT1 = VT2 = 0.7 VDD

IDD(slp) Supply Current, Sleep VT1 = grounded, 240 400 µA

VSLP, OTF, OUT = open, CF = 0.1µF

Driver Output

tROutput Rise Time, Note 5 IOH = 10mA TBD 50 µs

tFOutput Fall Time, Note 5 IOL = 1mA TBD 50 µs

IOL Output Sink Current VOL = 0.5V 0.9 mA

IOH Output Source Current 4.5V ≤ VDD ≤ 5.5V, VOH = 2.4V 10 mA

10.8V ≤ VDD ≤ 13.2V, VOH = 3.2V 10 mA

IOS Sleep-Mode Output Leakage VOUT = 0V 1 µA

Thermistor and Sleep Inputs

VPWM(max) 100% PWM Duty Cycle 67 70 73 %VDD

Input Voltage

VPWM(span) VPWM(max) – VPWM(min) 37 40 43 %VDD

VHYST Sleep Comparator Hysteresis 811 14 %VDD

VIL VT1 Shutdown Threshold 0.7 V

VIH VT1 Startup Threshold 1.1 V

VOT VT1 Overtemperature Fault Note 6 74 77 80 %VDD

Threshold

IVT, IVSLP VT1, VT2, VSLP Input Current –2.5 1 µA

tRESET Reset Setup Time minimum time VT1 < VIL, to guarantee reset, 30 µs

Note 5

Oscillator

f Oscillator Frequency, Note 7 4.5V ≤ VDD ≤ 5.5V, CF = 0.1µF24 27 30 Hz

10.8V ≤ VDD ≤ 13.2V, CF = 0.1µF27 30 33 Hz

fMIN, fMAX Oscillator Frequency Range Note 7 15 90 Hz

tSTARTUP Startup Interval 64/f s

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MIC502 4 August 2001

Symbol Parameter Condition Min Typ Max Units

Overtemperature Fault Output

VOL Active (Low) Output Voltage IOL = 2mA 0.3 V

IOH Off-State Leakage V/OTF = VDD 1µA

Note 1. Exceeding the absolute maximum rating may damage the device.

Note 2. The device is not guaranteed to function outside its operating rating.

Note 3. Devices are ESD sensitive. Handling precautions recommended.

Note 4: Part is functional over this VDD range; however, it is characterized for operation at 4.5V ≤ VDD ≤ 5.5V and 10.8V ≤ VDD ≤ 13.2V ranges. These

ranges correspond to nominal VDD of 5V and 12V, respectively.

Note 5. Guaranteed by design.

Note 6. VOT is guaranteed by design to always be higher than VPWM(max).

Note 7. Logic time base and PWM frequency. For other values of CF,

f(Hz) = 30Hz0.1 F

, where C is in µF.

Timing Diagrams

50% 80% 40% 0% 100% 40%70%

STARTUP

PWM

Output

Duty Cycle

ABCDE

0.7V

0.3V

SLP

100%

30%

70%

80%

50% 40% 40%

Input

Signal

Range

OUT

OTF

Figure 1. Typical System Behavior

Note A. Output duty-cycle is initially determined by VT1, as it is greater than VT2.

Note B. PWM duty-cycle follows VT1 as it increases.

Note C. VT1 drops below VT2. VT2 now determines the output duty-cycle.

Note D. The PWM duty-cycle follows VT2 as it increases.

Note E. Both VT1 and VT2 decrease below VSLP but above VIL. The device enters sleep mode.

Note F. The PWM ‘wakes up’ because one of the control inputs (VT1 in this case) has risen above VWAKE. The startup timer is triggered, forcing OUT

high for 64 clock periods. (VWAKE = VSLP + VHYST. See “Electrical Characteristics.”)

Note G. Following the startup interval, the PWM duty-cycle is the higher of VT1 and VT2.

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40% 60% 30% 0%100%

STARTUP

PWM

Output

Duty Cycle

0.7V

0.3V

SLP

100%

20%

60%

40% 30% PWM

Range

OUT

OTF

100%

Figure 2. MIC502 Typical Power-Up System Behavior

Note H. At power-on, the startup timer forces OUT on for 64 PWM cycles of the internal timebase (tPWM). This insures that the fan will start from a

dead stop.

Note I. The PWM duty-cycle follows the higher of VT1 and VT2, in the case, VT1.

Note J. The PWM duty-cycle follows VT1 as it increases.

Note K. PWM duty-cycle is 100% (OUT constantly on) anytime VT1 > VPWM(max).

Note L. /OTF is asserted anytime VT1 > VOT. (The fan continues to run at 100% duty-cycle.)

Note M. /OTF is deasserted when VT1 falls below VOT; duty-cycle once again follows VT1.

Note N. Duty-cycle follows VT1 until VT1 < VT2, at which time VT2 becomes the controlling input signal. Note that VT1 is below VSLP but above VIH; so

normal operation continues. (Both VT1 and VT2 must be below VSLP to active sleep mode.)

Note O. All functions cease when VT1 < VIL; this occurs regardless of the state of VT2.

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MIC502 6 August 2001

Typical Characteristics

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

02468101214

(mA)

(V)

Supply Current

vs. Supply Voltage

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

0.18

0.20

02468101214

(V)

vs.

Supply Volta

= 0.9mA

0.2

0.4

0.6

0.8

1.2

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

VOL (V)

IOL (mA)

VOL vs. IOL

=12V

=5V

02468101214

(mV)

(V)

vs.

Supply Volta

= 100µA

0.05

0.10

0.15

0.20

0.25

-40 -20 0 20 40 60 80 100

VOL(V)

TEMPERATURE (°C)

VOL

vs. Temperature

VDD =12V

VDD = 5V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-40 -20 0 20 40 60 80 100

IDD(mA)

TEMPERATURE (°C)

Supply Current

vs. Temperature

VDD = 12V

VDD = 5V

0.05

0.1

0.15

0.2

0.25

0.3

-40 -20 0 20 40 60 80 100

IDD

SLEEP

(mA)

TEMPERATURE (°C)

IDD

SLEEP

vs.

Temperature

= 12V

= 5V

0.5

1.5

2.5

3.5

02468101214

VOH(V)

VDD (V)

VOH vs.

Supply Volta

IOH = 10mA

0.05

0.1

0.15

0.2

0.25

0.3

02468101214

IDD

SLEEP

(mA)

(V)

IDDSLEEP vs.

Suppl

Volta

0.5

1.5

2.5

3.5

4.5

02468101214

(V)

vs.

Supply Volta

= 100µA

0.5

1.5

2.5

3.5

35791113151719

(V)

(mA)

vs. I

=12V

=5V

0.5

1.5

2.5

3.5

4.5

-40 -20 0 20 40 60 80 100

VOH(V)

TEMPERATURE (°C)

VOH vs.

Temperature

VDD = 12V

VDD = 5V

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0.2

0.4

0.6

0.8

1.2

02468101214

PWM

(NORMALIZED)

(V)

PWM Frequency(Normalized)

vs. Supply Volta

-40 -20 0 20 40 60 80 100

VPWM(MAX)(V)

TEMPERATURE (°C)

VPWM(max)

vs. Temperature

VDD =12V

VDD = 5V

02468101214

(V)

VOT vs.

Supply Voltage

100

1000

3000

0.001 0.01 0.1 1

FREQUENCY (Hz)

CAPACITANCE (µF)

PWM Frequency vs.

Timing Capacitor Value

0.2

0.4

0.6

0.8

1.2

-40 -20 0 20 40 60 80 100

PWM

(NORMALIZED)

TEMPERATURE (°C)

PWM Frequency (normalized)

vs. Temperature

= 12V

= 5V

02468101214

VPWM (V)

VDD (V)

PWM(max)

vs.

Supply Voltage

-40 -20 0 20 40 60 80 100

VOT(V)

TEMPERATURE (°C)

VOT

vs. Temperature

VDD = 12V

VDD = 5V

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MIC502 8 August 2001

Functional Diagram

Oscillator

Start-Up

Timer

CLK

RESET OUT

VT2

VT1

OTF

OUT

Driver

GND

VSLP

Power-On

Reset

ENABLE

Sleep

Control

VDD

Overtemperature

Reset

Sleep

Bias

PWM

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Functional Description

Oscillator

A capacitor connected to CF determines the frequency of the

internal time base which drives the state-machine logic and

determines the PWM frequency. This operating frequency

will be typically 30Hz to 60Hz. (CF = 0.1µF for 30Hz.)

Pulse-Width Modulator

A triangle-wave generator and threshold detector comprise

the internal pulse-width modulator (PWM). The PWM’s out-

put duty-cycle is determined by the higher of VT1 or VT2. A

typical voltage range of 30% to 70% of VDD applied to the VT1

and VT2 pins corresponds to 0% to 100% duty-cycle. Since

at least one of the control voltage inputs is generally from a

thermistor-resistor divider connected to VDD, the PWM out-

put duty cycle will not be affected by changes in the supply

voltage.

Driver Output

OUT is a complementary push-pull digital output with asym-

metric drive (approximately 10mA source, 1mA sink—see

“Electrical Characteristics”). It is optimized for directly driving

an NPN transistor switch in the fan’s ground-return. See

“Applications Information” for circuit details.

Shutdown/Reset

Internal circuitry automatically performs a reset of the MIC502

when power is applied. The MIC502 may be shut down at any

time by forcing VT1 below its VIL threshold. This is typically

accomplished by connecting the VT1 pin to open-drain or

open-collector logic and results in an immediate and asyn-

chronous shutdown of the MIC502. The OUT and /OTF pins

will float while VT1 is below VIL.

If VT1 then rises above VIH, a device reset occurs. Reset is

equivalent to a power-up condition: the state of /OTF is

cleared, a startup interval is triggered, and normal fan opera-

tion begins.

Startup Interval

Any time the fan is started from the off state (power-on or

coming out of sleep mode or shutdown mode), the PWM

output is automatically forced high for a startup interval of 64

× tPWM. Once the startup interval is complete, PWM operation

will commence and the duty-cycle of the output will be

determined by the higher of VT1 or VT2.

Overtemperature Fault Output

/OTF is an active-low, open-collector logic output. An over-

temperature condition will cause /OTF to be asserted. An

overtemperature condition is determined by VT1 exceeding

the normal operating range of 30% to 70% of VDD by > 7% of

VDD. Note that VOT is guaranteed by design to always be

higher than VPWM(max).

Sleep Mode

When VT1 and VT2 fall below VSLP, the system is deemed

capable of operating without fan cooling and the MIC502

enters sleep mode and discontinues fan operation. The

threshold where the MIC502 enters sleep mode is deter-

mined by VSLP. Connecting the VSLP pin to ground disables

sleep mode.

Once in sleep mode, all device functions cease (/OTF in-

active, PWM output off) unless VT1 or VT2 rise above VWAKE.

(VWAKE = VSLP + VHYST.) VHYST is a fixed amount of hyster-

esis added to the sleep comparator which prevents erratic

operation around the VSLP operating point. The result is

stable and predictable thermostatic action: whenever pos-

sible the fan is shut down to reduce energy consumption and

acoustic noise, but will always be activated if the system

temperature rises.

If the device powers-up or exits its reset state, the fan will not

start unless VT1 or VT2 rises above VWAKE.

System Operation

Power Up

•A complete reset occurs when power is applied.

•OUT is off (low) and /OTF is inactive (high/floating).

•If VT1 < VIL, the MIC502 remains in shutdown.

•The startup interval begins. OUT will be on (high) for 64

clock cycles (64 × tPWM).

•Following the startup interval, normal operation begins.

Reset Startup Timer;

Deassert /OTF;

OUT Off (Low).

> V

POWER ON

< V

OUT Held On (High)

During Startup

Interval.

Startup Interval

Finished

Deassert OUT

(OUT = Low)

YES

Assert /OTF While

> V

NORMAL

OPERATION

YES

Figure 3. Power-Up Behavior

MIC502 Micrel

MIC502 10 August 2001

Normal Operation

Normal operation consists of the PWM operating to control

the speed of the fan according to VT1 and VT2. Exceptions to

this otherwise indefinite behavior can be caused by any of

three conditions: VT1 exceeding VOT, an overtemperature

condition; VT1 being pulled below VIL initiating a device

shutdown and reset; or both VT1 and VT2 falling below VSLP,

activating sleep mode. Each of these exceptions is treated as

follows:

Overtemp?

> V

NORMAL

OPERATION

and V

< V

SLEEP

OUT Duty Cycle

Proportional to

Greater of V

, V

YES

Assert /OTF while

> V

Reset?

< V

?POWER ON

SLEEP

YES

Figure 4. Normal System Behavior

•

Overtemperature:

If the system temperature rises

typically 7% above the 100% duty-cycle operating point,

/OTF will be activated to indicate an overtemperature

fault. (VT1 > VOT) Overtemperature detection is essen-

tially independent of other operations—the PWM

continues its normal behavior; with VT1 > VPWM(max), the

output duty-cycle will be 100%. If VT1 falls below VOT,

the overtemperature condition is cleared and /OTF is no

longer asserted. It is assumed that in most systems, the

/OTF output will initiate power supply shutdown.

•

Shutdown/Reset:

If VT1 is driven below VIL an immedi-

ate, asynchronous shutdown occurs. While in shutdown

mode, OUT is off (low), and /OTF is unconditionally

inactive (high/floating). If VT1 subsequently rises above

VIH, a device reset will occur. Reset is indistinguishable

from a power-up condition. The state of /OTF is cleared,

a startup interval is triggered, and normal fan operation

begins.

•

Sleep:

If VT1 and VT2 fall below VSLP, the device enters

sleep mode. All internal functions cease unless VT1 or

VT2 rise above VWAKE. (VWAKE = VSLP + VHYST.) The

/OTF output is unconditionally inactive (high/floating)

and the PWM is disabled during sleep. (OUT will float.)

Sleep Mode

During normal operation, if VT1 and VT2 fall below VSLP, the

device will go into sleep mode and fan operation will stop. The

MIC502 will exit sleep mode when VT1 or VT2 rise above VSLP

by the hysteresis voltage, VHYST. When this occurs, normal

operation will resume. The resumption of normal operation

upon exiting sleep is indistinguishable from a power-on reset.

(See “Sleep: Normal Operation,” above.)

Disable PWM

Reset Released

> V

SLEEP

Reset Initiated

< V

YES

Wake Up?

or V

SLP

HYST

POWER ON

YES

Figure 5. Sleep-Mode Behavior

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MIC502 Micrel

Applications Information

The Typical Application drawing on page 1 illustrates a typical

application circuit for the MIC502. Interfacing the MIC502

with a system consists of the following steps:

1. Selecting a temperature sensor

2. Interfacing the temperature sensor to the VT1 input

3 Selecting a fan-drive transistor, and base-drive current

limit resistor

4. Deciding what to do with the Secondary

Fan-Control Input

5. Making use of the Overtemperature Fault Output.

Temperature Sensor Selection

Temperature sensor T1 is a negative temperature coefficient

(NTC) thermistor. The MIC502 can be interfaced with either

a negative or positive tempco thermistor; however, a nega-

tive temperature coefficient thermistor typically costs less

than its equivalent positive tempco counterpart. While a

variety of thermistors can be used in this application, the

following paragraphs reveal that those with an R25 rating

(resistance at 25°C) of from about 50kΩ to 100kΩ lend

themselves nicely to an interface network that requires only

a modest current drain. Keeping the thermistor bias current

low not only indicates prudent design; it also prevents self-

heating of the sensor from becoming an additional design

consideration. It is assumed that the thermistor will be located

within the system power supply, which most likely also

houses the speed-controlled fan.

Temperature Sensor Interface

As shown by the Electrical Characteristics table, the working

voltage for input VT1 is specified as a percentage of VDD. This

conveniently frees the designer from having to be concerned

with interactions resulting from variations in the supply volt-

age. By design, the operating range of VT1 is from about 30%

of VDD to about 70% of VDD.

VPWM(min) = VPWM(max) – VPWM(span)

When VT1 = VPWM(max) ≈ 0.7VDD, a 100% duty-cycle motor

drive signal is generated. Conversely, when VT1 = VPWM(min)

≈ 0.3VDD, the motor-drive signal has a 0% duty cycle.

Resistor voltage divider R1 || T1, R2 in the Typical Application

diagram is designed to preset VT1 to a value of VPWM that

corresponds to the slowest desired fan speed when the

resistance of thermistor T1 is at its highest (cold) value. As

temperature rises the resistance of T1 decreases and VT1

increases because of the parallel connection of R1 and T1.

Since VT1 = VPWM(min) represents a stopped fan (0% duty-

cycle drive), and since it is foreseen that at least some cooling

will almost always be required, the lowest voltage applied to

the VT1 input will normally be somewhat higher than 0.3VDD

(or >VPWM(min)). It is assumed that the system will be in sleep

mode rather than operate the fan at a very low duty cycle

(<< 25%). Operation at very low duty cycle results in relatively

little airflow. Sleep mode should be used to reduce acoustic

noise when the system is cool. For a given minimum desired

fan speed, a corresponding VT1(min) can be determined via

the following observation:

sinceVPWM(max) = 70% of VDD ∝ 100% RPM

and VPWM(min) = 30% of VDD ∝ 0% RPM

then VPWM(span) = 40% of VDD ∝ 100% RPM

range

Figure 6 shows the following linear relationship between the

voltage applied to the VT1 input, motor drive duty cycle, and

approximate

motor speed.

sinceVT1 = 0.7VDD ∝ 100% PWM

then VT1 = 0.6VDD ∝ 75% PWM

and VT1 = 0.5VDD ∝ 50% PWM

and VT1 = 0.4VDD ∝ 25% PWM.

In addition to the R25 thermistor rating, sometimes a data

sheet will provide the ratio of R25/R50 (resistance at 25°C

divided by resistance at 50°C) is given. Sometimes this is

given as an R0/R50 ratio. Other data sheet contents either

specify or help the user determine device resistance at

arbitrary temperatures. The thermistor interface to the MIC502

usually consists of the thermistor and two resistors.

100

0 20406080100

DUTY CYCLE (%)

/SUPPLY VOLTAGE (%)

Figure 6. Control Voltage vs. Fan Speed

Design Example

The thermistor-resistor interface network is shown in the

Typical Application drawing. The following example describes

the design process: A thermistor data sheet specifies a

thermistor that is a candidate for this design as having an R25

resistance of 100kΩ. The data sheet also supports calcula-

tion of resistance at arbitrary temperatures, and it was discov-

ered the candidate thermistor has a resistance of 13.6k at

70°C (R70). Accuracy is more important at the higher tem-

perature end of the operating range (70°C) than the lower end

because we wish the overtemperature fault output (/OTF) to

be reasonably accurate—it may be critical to operating a

power supply crowbar or other shutdown mechanism, for

example. The lower temperature end of the range is less

important because it simply establishes minimum fan speed,

which is when less cooling is required.

MIC502 Micrel

MIC502 12 August 2001

Referring to the “Typical Application,” the following approach

can be used to design the required thermistor interface

network:

Let R1 = ∞

RT1 = 13.6k (at 70°C)

and VT = 0.7VDD (70% of VDD)

Since

V= VR2

R||R1+R2

TDD

()

0.7= R2

R+R2

()

0.7RT1 + 0.7R2 = R2

0.7RT1 = 0.3R2

and R2 = 2.33RT1 = 2.33 × 13.6k = 31.7k ≈ 33k

Let’s continue by determining what the temperature-propor-

tional voltage is at 25°C.

Let R1 = ∞

and RT1 = 100k (at 25°C).

From

VR2

R+R2

TDD

()

V=V 33k

100k+33k

TDD

()

VT = 0.248VDD

Recalling from above discussion that the desired VT for 25°C

should be about 40% of VDD, the above value of 24.8% is far

too low. This would produce a voltage that would stop the fan

(recall from the above that this occurs when VT is about 30%

of VDD. To choose an appropriate value for R1 we need to

learn what the parallel combination of RT1 and R1 should be

at 25°C:

Again

V= VR2

R||R1+R2

TDD

()

0.4= R2

R||R1+R2

()

0.4(RT1 || R1) + 0.4R2 = R2

0.4(RT1 || R1) = 0.6R2

and RT1 || R1 = 1.5R2 = 1.5 × 33k = 49.5k

Since

RT1 = 100k

and RT1 || R1 = 49.5k ≈ 50k

let R1 = 100k

While that solves the low temperature end of the range, there

is a small effect on the other end of the scale. The new value

of VT for 70°C is 0.734, or about 73% of VDD. This represents

only a 3% shift from the design goal of 70% of VDD. In

summary, R1 = 100k, and R2 = 33k. The candidate thermistor

used in this design example is the RL2010-54.1K-138-D1,

manufactured by Keystone Thermometrics.

The R25 resistance (100kΩ) of the chosen thermistor is

probably on the high side of the range of potential thermistor

resistances. The result is a moderately high-impedance

network for connecting to the VT1 and/or VT2 input(s). Be-

cause these inputs can have up to 1µA of leakage current,

care must be taken if the input network impedance becomes

higher than the example. Leakage current and resistor accu-

racy could require consideration in such designs. Note that

the VSLP input has this same leakage current specification.

Secondary Fan-Control Input

The above discussions also apply to the secondary fan-

control input, VT2, pin 5. It is possible that a second ther-

mistor, mounted at another temperature-critical location out-

side the power supply, may be appropriate. There is also the

possibility of accommodating the NLX “FanC” signal via this

input. If a second thermistor is the desired solution, the VT2

input may be treated exactly like the VT1 input. The above

discussions then apply directly. If, however, the NLX FanC

signal is to be incorporated into the design then the operating

voltage (VDD = 5V vs. VDD = 12V) becomes a concern. The

FanC signal is derived from a 12V supply and is specified to

swing at least to 10.5V. A minimum implementation of the

FanC signal would provide the capability of asserting full-

speed operation of the fan; this is the case when 10.5V ≤

FanC ≤ 12V. This FanC signal can be applied directly to the

VT2 input of the MIC502, but only when its VDD is 12V. If this

signal is required when the MIC502 VDD = 5V a resistor

divider is necessary to reduce this input voltage so it does not

exceed the MIC502 VDD voltage. A good number is 4V

(80%VDD).

Because of input leakage considerations, the impedance of

the resistive divider should be kept at ≤ 100kΩ. A series

resistor of 120kΩ driven by the Fan C signal and a 100kΩ

shunt resistor to ground make a good divider for driving the

VT2 input.

Transistor and Base-Drive Resistor Selection

The OUT motor-drive output, pin 7, is intended for driving a

medium-power device, such as an NPN transistor. A rather

ubiquitous transistor, the 2N2222A, is capable of switching

up to about 400mA. It is also available as the PN2222A in a

plastic TO-92 package. Since 400mA is about the maximum

current for most popular computer power supply fans (with

many drawing substantially less current) and since the MIC502

provides a minimum of 10mA output current, the PN2222A,

with its minimum β of 40, is the chosen motor-drive transistor.

August 2001 13 MIC502

MIC502 Micrel

The design consists soley of choosing the value RBASE in

Figures 7 and 8. To minimize on-chip power dissipation in the

MIC502, the value of RBASE should be determined by the

power supply voltage. The Electrical Characteristics table

specifies a minimum output current of 10mA. However,

different output voltage drops (VDD – VOUT) exist for 5V vs.

12V operation. The value RBASE should be as high as

possible for a given required transistor base-drive current in

order to reduce on-chip power dissipation.

Referring to the “Typical Application” and to the “Electrical

Characteristics” table, the value for RBASE is calculated as

follows. For VDD = 5V systems, IOH of OUT (pin 7) is

guaranteed to be a minimum of 10mA with a VOH of 2.4V.

RBASE then equals (2.4V – VBE) ÷ 10mA = 170Ω.

For VDD = 12V systems, RBASE = (3.4 – 0.7) ÷ 0.01 = 250Ω.

Overtemperature Fault Output

The /OTF output, pin 6, is an open-collector NPN output. It is

compatible with CMOS and TTL logic and is intended for

alerting a system about an overtemperature condition or

triggering a power supply crowbar circuit. If VDD for the

MIC502 is 5V the output should not be pulled to a higher

voltage. This output can sink up to 2mA and remain compat-

ible with the TTL logic-low level.

Timing Capacitors vs. PWM Frequency

The recommended CF (see first page) is 0.1µF for opertaion

at a PWM frequency of 30Hz. This frequency is factory

trimmed within ±3Hz using a 0.1% accurate capacitor. If it is

desired to operate at a different frequency, the new value for

CF is calculated as follows:

C=3

f, where C is in µF and f is in Hz.

The composition, voltage rating, ESR, etc., parameters of the

capacitor are not critical. However, if tight control of frequency

vs. temperature is an issue, the temperature coefficient may

become a consideration.

VT1

VSLP

GND

VDD

OUT

OTF

VT2

100k

56k

56k C

33k

BASE

Overtemperature

Fault Output

MIC502

NLX FanC

Signal Input

Yate Loon

YD80SM-12

or similar fan

0.1µF

180Ω

100k

47k

Keystone Thermonics

RL2010-54.1K-138-D1

or similar

120k

12V

Figure 7. Typical 5V VDD Application Circuit

VT1

VSLP

GND

VDD

OUT

OTF

VT2

100k

56k

56k C

33k

12V

BASE

Overtemperature

Fault Output

MIC502

NLX FanC

Signal Input

Yate Loon

YD80SM-12

or similar fan

0.1µF

280Ω

4.7k

47k

Keystone Thermonics

RL2010-54.1K-138-D1

or similar

Figure 8. Typical 12V VDD Application Circuit

MIC502 Micrel

MIC502 14 August 2001

Package Information

0.380 (9.65)

0.370 (9.40)

0.135 (3.43)

0.125 (3.18)

PIN 1

DIMENSIONS:

INCH (MM)

0.018 (0.57)

0.100 (2.54)

0.013 (0.330)

0.010 (0.254)

0.300 (7.62)

0.255 (6.48)

0.245 (6.22)

0.380 (9.65)

0.320 (8.13)

0.0375 (0.952)

0.130 (3.30)

8-Pin Plastic DIP (N)

45°

0°–8°

0.244 (6.20)

0.228 (5.79)

0.197 (5.0)

0.189 (4.8) SEATING

PLANE

0.026 (0.65)

MAX)

0.010 (0.25)

0.007 (0.18)

0.064 (1.63)

0.045 (1.14)

0.0098 (0.249)

0.0040 (0.102)

0.020 (0.51)

0.013 (0.33)

0.157 (3.99)

0.150 (3.81)

0.050 (1.27)

TYP

PIN 1

DIMENSIONS:

INCHES (MM)

0.050 (1.27)

0.016 (0.40)

8-Pin SOP (M)

MICREL INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or

other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.