SPICE Device Model Si2323DS Vishay Siliconix P-Channel 20-V (D-S) MOSFET CHARACTERISTICS * P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit mode is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70111 27-Mar-03 www.vishay.com 1 SPICE Device Model Si2323DS Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data VGS(th) VDS = VGS, ID = - 250A 0.74 Measured Data Unit Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltage a ID(on) rDS(on) V VDS - 5V, VGS = - 4.5V 98 VGS = - 4.5V, ID = - 4.7A 0.031 0.031 VGS = - 2.5V, ID = - 4.1 0.043 0.041 A VGS = - 1.8V, ID = - 2 0.059 0.054 gfs VDS = - 5V, ID = - 4.7A 15 16 S VSD IS = - 1A, VGS = 0V - 0.78 - 0.70 V 12.1 12.5 1.7 1.7 b Dynamic Total Gate Charge Qg Gate-Source Charge Qgs VDS = - 10V, VGS = - 4.5V, ID = - 4.7A Gate-Drain Charge Qgd 3.3 3.3 Turn-On Delay Time td(on) 24 25 22 43 60 71 13 48 Rise Time Turn-Off Delay Time Fall Time tr td(off) tf VDD = - 10V, RL = 10 ID - 1A, VGEN = - 4.5V, RG = 6 nC ns Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 70111 27-Mar-03 SPICE Device Model Si2323DS Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 70111 27-Mar-03 www.vishay.com 3