SPICE Device Model Si2323DS
Vishay Siliconix
P-Channel 20-V (D-S) MOSFET
CHARACTERISTICS
P-Channel Vertical DMOS
Macro Model (Subcircuit Model)
Level 3 MOS
Apply for both Linear and Switching Application
Accurate over the 55 to 125°C Temperature Range
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
mode is extracted and optimized over the 55 to 125°C temperature
ranges under the pulsed 0-to-5V gate drive. The saturated output
impedance is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 70111 www.vishay.com
27-Mar-03 1
SPICE Device Model Si2323DS
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions
Simulated
Data
Measured
Data Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = − 250µA 0.74 V
On-State Drain Currenta ID(on) VDS 5V, VGS = 4.5V 98 A
VGS = 4.5V, ID = 4.7A 0.031 0.031
VGS = 2.5V, ID = − 4.1Α 0.043 0.041
Drain-Source On-State Resistancea r
DS(on)
VGS = 1.8V, ID = − 2Α 0.059 0.054
Forward Transconductancea g
fs VDS = 5V, ID = 4.7A 15 16 S
Diode Forward Voltagea V
SD IS = 1A, VGS = 0V - 0.78 - 0.70 V
Dynamicb
Total Gate Charge Qg 12.1 12.5
Gate-Source Charge Qgs 1.7 1.7
Gate-Drain Charge Qgd
VDS = 10V, VGS = 4.5V, ID = 4.7A
3.3 3.3
nC
Turn-On Delay Time td(on) 24 25
Rise Time tr 22 43
Turn-Off Delay Time td(off) 60 71
Fall Time tf
VDD = 10V, RL = 10
ID 1A, VGEN = 4.5V, RG = 6
13 48
ns
Notes
a. Pulse test; pulse width 300 µs, duty cycle 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com Document Number: 70111
2 27-Mar-03
SPICE Device Model Si2323DS
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 70111 www.vishay.com
27-Mar-03 3