DS34C87T
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SNLS376B –MAY 1998–REVISED APRIL 2013
DS34C87T CMOS Quad TRI-STATE Differential Line Driver
Check for Samples: DS34C87T
1FEATURES DESCRIPTION
The DS34C87T is a quad differential line driver
2• TTL Input Compatible designed for digital data transmission over balanced
• Typical Propagation Delays: 6 ns lines. The DS34C87T meets all the requirements of
• Typical Output Skew: 0.5 ns EIA standard RS-422 while retaining the low power
characteristics of CMOS. This enables the
• Outputs Won't Load Line When VCC = 0V construction of serial and terminal interfaces while
• Meets the Requirements of EIA Standard RS- maintaining minimal power consumption.
422 The DS34C87T accepts TTL or CMOS input levels
• Operation from Single 5V Supply and translates these to RS-422 output levels. This
• TRI-STATE Outputs for Connection to System part uses special output circuitry that enables the
Buses individual drivers to power down without loading down
the bus. This device has separate enable circuitry for
• Low Quiescent Current each pair of the four drivers. The DS34C87T is pin
• Available in Surface Mount compatible to the DS3487T.
All inputs are protected against damage due to
electrostatic discharge by diodes to VCC and ground.
Connection and Logic Diagrams
Top View
Figure 2. Logic Diagram
See PIN DESCRIPTIONS for details.
Figure 1. PDIP Package
See Package Numbers D0016A or NFG0016E
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1998–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS34C87T
SNLS376B –MAY 1998–REVISED APRIL 2013
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Truth Table(1)
Input Control Non-Inverting Inverting
Input Output Output
H H H L
L H L H
X L Z Z
(1) L = Low logic state
H = High logic state
X = Irrelevant
Z = TRI-STATE (high performance)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)(4)
Supply Voltage (VCC)−0.5 to 7.0V
DC Voltage (VIN)−1.5 to VCC +1.5V
DC Output Voltage (VOUT )−0.5 to 7V
Clamp Diode Current (IIK , IOK) ±20 mA
DC Output Current, per pin (I OUT) ±150 mA
DC VCC or GND Current (ICC) ±150 mA
Storage Temperature Range (T STG)−65°C to +150°C
Maximum Power Dissipation (PD) @ 25°C(5)
PDIP Package 1736 mW
SOIC Package 1226 mW
Lead Temperature (TL)
(Soldering 4 sec) 260°C
This device does not meet 2000V ESD rating.(6)
(1) Unless otherwise specified, all voltages are referenced to ground. All currents into device pins are positive; all currents out of device
pins are negative.
(2) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be specified. They are not meant to imply
that the device should be operated at these limits. The table of “Electrical Characteristics” provide conditions for actual device operation.
(3) ESD Rating: HBM (1.5 kΩ, 100 pF) Inputs ≥1500V Outputs ≥1000V EIAJ (0Ω, 200 pF) All Pins ≥350V
(4) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(5) Ratings apply to ambient temperature at 25°C. Above this temperature derate NFG0016E Package 13.89 mW/°C, and D0016A Package
9.80 mW/°C.
(6) ESD Rating: HBM (1.5 kΩ, 100 pF) Inputs ≥1500V Outputs ≥1000V EIAJ (0Ω, 200 pF) All Pins ≥350V
Operating Conditions Min Max Units
Supply Voltage (VCC) 4.50 5.50 V
DC Input or Output Voltage (VIN, VOUT) 0 VCC V
Operating Temperature Range (TA) DS34C87T −40 +85 °C
Input Rise or Fall Times (tr, tf) 500 ns
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SNLS376B –MAY 1998–REVISED APRIL 2013
DC Electrical Characteristics(1)
VCC = 5V ±10% (unless otherwise specified)
Parameter Test Conditions Min Typ Max Units
VIH High Level Input 2.0 V
Voltage
VIL Low Level Input 0.8 V
Voltage
VOH High Level Output V IN = VIH or VIL, 2.5 3.4 V
Voltage I OUT =−20 mA
VOL Low Level Output V IN = VIH or VIL, 0.3 0.5 V
Voltage I OUT = 48 mA
VTDifferential Output R L= 100 Ω2.0 3.1 V
Voltage See(2)
|VT|–| VT| Difference In R L= 100 Ω0.4 V
Differential Output See(2)
VOS Common Mode R L= 100 Ω2.0 3.0 V
Output Voltage See(2)
|VOS– VOS| Difference In R L= 100 Ω0.4 V
Common Mode Output See(2)
IIN Input Current V IN = VCC, GND, VIH, or VIL ±1.0 μA
ICC Quiescent Supply I OUT = 0 μA,
Current V IN = VCC or GND 200 500 μA
VIN = 2.4V or 0.5V(3) 0.8 2.0 mA
IOZ TRI-STATE Output V OUT = VCC or GND ±0.5 ±5.0 μA
Leakage Current Control = VIL
ISC Output Short V IN = VCC or GND −30 −150 mA
Circuit Current See(2) and (4)
IOFF Power Off Output VCC = 0V VOUT = 6V 100 μA
Leakage Current See(2) VOUT =−0.25V −100 μA
(1) Unless otherwise specified, min/max limits apply across the −40°C to 85°C temperature range. All typicals are given for VCC = 5V and
TA= 25°C.
(2) See EIA Specification RS-422 for exact test conditions.
(3) Measured per input. All other inputs at VCC or GND.
(4) This is the current sourced when a high output is shorted to ground. Only one output at a time should be shorted.
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Switching Characteristics(1)
VCC = 5V ±10%, t r, tf≤6 ns (Figure 3,Figure 4,Figure 5,Figure 6)
Parameter Test Conditions Min Typ Max Units
tPLH, tPHL Propagation Delay Input to Output S1 Open 6 11 ns
Skew See(2) S1 Open 0.5 3 ns
tTLH, tTHL Differential Output Rise And Fall Times S1 Open 6 10 ns
tPZH Output Enable Time S1 Closed 12 25 ns
tPZL Output Enable Time S1 Closed 13 26 ns
tPHZ Output Disable Time(3) S1 Closed 4 8 ns
tPLZ Output Disable Time(3) S1 Closed 6 12 ns
CPD Power Dissipation Capacitance(4) 100 pF
CIN Input Capacitance 6 pF
(1) Unless otherwise specified, min/max limits apply across the −40°C to 85°C temperature range. All typicals are given for VCC = 5V and
TA= 25°C.
(2) Skew is defined as the difference in propagation delays between complementary outputs at the 50% point.
(3) Output disable time is the delay from the control input being switched to the output transistors turning off. The actual disable times are
less than indicated due to the delay added by the RC time constant of the load.
(4) CPD determines the no load dynamic power consumption, PD= CPD V2CC f + ICC VCC, and the no load dynamic current consumption, IS
= CPD VCC f + ICC.
Comparison Table of Switching Characteristics into “LS-Type” Load(1)
VCC = 5V, TA= +25°C, tr≤6 ns, tf≤6 ns (Figure 6,Figure 7,Figure 8,Figure 9,Figure 10,Figure 11)
DS34C87 DS3487
Parameter Test Conditions Units
Typ Max Typ Max
tPLH, tPHL Propagation Delay 6 10 10 15 ns
Input to Output
Skew See(2) 1.5 2.0 ns
tTHL, tTLH Differential Output Rise 4 7 10 15 ns
and Fall Times
tPHZ Output Disable Time CL= 50 pF, RL= 200Ω, 8 11 17 25 ns
See(3) S1 Closed, S2 Closed
tPLZ Output Disable Time CL= 50 pF, RL= 200Ω, 7 10 15 25 ns
See(3) S1 Closed, S2 Closed
tPZH Output Enable Time CL= 50 pF, RL=∞, 11 19 11 25 ns
S1 Open, S2 Closed
tPZL Output Enable Time CL= 50 pF, RL= 200Ω, 14 21 15 25 ns
S1 Closed, S2 Open
(1) This table is provided for comparison purposes only. The values in this table for the DS34C87 reflect the performance of the device but
are not tested or ensured.
(2) Skew is defined as the difference in propagation delays between complementary outputs at the 50% point.
(3) Output disable time is the delay from the control input being switched to the output transistors turning off. The actual disable times are
less than indicated due to the delay added by the RC time constant of the load.
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SNLS376B –MAY 1998–REVISED APRIL 2013
AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS
Note: C1 = C2 = C3 = 40 pF (including Probe and Jig Capacitance), R1 = R2 = 50Ω, R3 = 500Ω
Figure 3. AC Test Circuit
Input pulse; f = 1 MHz, 50%, tr≤6 ns, tf≤
Figure 4. Propagation Delays 6ns
Figure 6. Differential Rise and Fall Times
Figure 7. Propagation Delays Test Circuit
for “LS-Type” Load
Figure 5. Enable and Disable Times
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SNLS376B –MAY 1998–REVISED APRIL 2013
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Figure 8. Differential Rise and Fall Times
Test Circuit for “LS-Type” Load Figure 9. Load Enable and Disable Times
Test Circuit for “LS-Type” Load
Figure 10. Load Propagation Delays for “LS-Type” Load
Figure 11. Load Enable and Disable Times for “LS-Type” Load
TYPICAL APPLICATIONS
*RTis optional although highly recommended to reduce reflection.
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SNLS376B –MAY 1998–REVISED APRIL 2013
PIN DESCRIPTIONS
Pin Number
(PDIP or SOIC Pin Name Function
package)
1 INPUT A Channel A - TTL/CMOS input
2 OUTPUT A - True True Output for Channel A,
RS422 Levels
3 OUTPUT A - Inverting Inverting Output for Channel A,
RS422 Levels
4 A/B CONTROL Enable Pin for Channels A and B,
Active High, TTL/CMOS Levels
5 OUTPUT B - Inverting Inverting Output for Channel B,
RS422 Levels
6 OUTPUT B - True True Output for Channel B,
RS422 Levels
7 INPUT B Channel B - TTL/CMOS input
8 GND Ground Pin (0 V)
9 INPUT C Channel C - TTL/CMOS input
10 OUTPUT C - True True Output for Channel C,
RS422 Levels
11 OUTPUT C - Inverting Inverting Output for Channel C,
RS422 Levels
12 C/D CONTROL Enable Pin for Channels C and D,
Active High, TTL/CMOS Levels
13 OUTPUT D - Inverting Inverting Output for Channel D,
RS422 Levels
14 OUTPUT D - True True Output for Channel D,
RS422 Levels
15 INPUT D Channel D - TTL/CMOS input
16 VCC Power Supply Pin, 5.0V typical
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SNLS376B –MAY 1998–REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision A (April 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 7
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS34C87TM/NOPB ACTIVE SOIC D 16 48 Green (RoHS
& no Sb/Br) Call TI | SN Level-1-260C-UNLIM -40 to 85 DS34C87TM
DS34C87TMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 DS34C87TM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS34C87TMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Mar-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS34C87TMX/NOPB SOIC D 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Mar-2019
Pack Materials-Page 2
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