©2004 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM Rev. C
RFD14N05, RFD14N05SM
14A, 50V, 0.100 Ohm, N-Channel Power
MOSFETs
These are N-channel power MOSFETs manufactured using
the MegaFET proc es s. This proces s, which uses fea ture
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. These transistors can be operated
directly from integra ted circuits.
Formerly developmental type TA09770.
Features
• 14A, 50V
•r
DS(ON) = 0.100Ω
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
•175
oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-251AA JEDEC TO-252AA
Ordering Information
PART NUMBER PACKAGE BRAND
RFD14N05 TO-251AA F14N05
RFD14N05SM TO-252AA F14N05
NO TE: When ordering , use the ent ire part number . Add t he suffix 9A to
obtain the TO-25 2AA variant in th e tape and reel, i .e., RFD14N 05SM9A. G
D
S
SOURCE
DRAIN (FLANGE)
GATE
DRAIN
GATE
SOURCE
DRAIN (FLANGE)
Data Sheet February 2004
©2004 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM Rev. C
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD14N05, RFD14N05SM UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 50 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 50 V
Gate to Sou rc e Volta g e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 14
Refer to Peak Current Curve A
Pulsed Aval a nche Ra tin g. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Refer to UIS Curve
Power Dis sipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate abov e 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
0.32 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
P ackage Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: St resses above those l isted in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a stress on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 9) 50 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA2-4V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 14A, VGS = 10V, (Figure 11) - - 0.100 Ω
Turn-On Time tON VDD = 25V, ID ≈ 14A, VGS = 10V,
RGS = 25Ω, RL = 1.7Ω
(Figure 13)
- - 60 ns
Turn-On Delay Time td(ON) -14- ns
Rise Time tr-26- ns
Turn-Off Delay Time td(OFF) -45- ns
Fall Ti me tf-17- ns
Turn-Off Time tOFF - - 100 ns
Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 40V, ID = 14A,
RL = 2.86Ω
Ig(REF) = 0.4mA
(Figure 13)
- - 40 nC
Gate Charge at 5V Qg(10) VGS = 0V to 10V - - 25 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 2V - - 1.5 nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12) - 570 - pF
Output Capacitance COSS - 185 - pF
Reverse Transfer Capacitance CRSS -50- pF
Thermal Resistance Junction to Case RθJC - - 3.125 oC/W
Thermal Resistance Junction to Ambient RθJA - - 100 oC/W
Sour ce to Drain Diode Specificatio ns
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage (Note 2) VSD ISD = 14A - - 1.5 V
Diode Reverse Recovery Time trr ISD = 14A, dISD/dt = 100A/µs - - 125 ns
NOTES:
2. Pulse Te st: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
RFD14N05, RFD14N05SM
©2004 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM Rev. C
Typical Performance Curves Unless Otherwise Specified
FIGURE 1. NORMALIZED PO WER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
TC, CASE TEMPERATURE (oC)
25 50 75 100 125 150 1750
POWER DISSIPATION MULTIPLIER
0
0
0.2
0.4
0.6
0.8
1.0
1.2
8
4
025 50 75 100 125 150
12
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
16
175
t, RECTANGULAR PULSE DURATION (s)
10-3 10-2 10-1 100
0.01
0.1
1
10-5 101
10-4
THERMAL IMPEDANCE
ZθJC, NORMALIZED
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
0.5
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
VDS, DRAIN TO SOURCE VO LTAGE (V)
10 100
1
100
10
1
ID, DRAIN CURRENT (A)
DC
100µs
100ms
1ms
10ms
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
TJ = MAX RATED
TC = 25oC
SINGLE PULSE
t, PULSE WIDTH (s)
10
10-5 10-4 10-3 10-2 10-1 100101
VGS = 10V
100
IDM, PEAK CURRENT CAPABILITY (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 20V
II
25 175 TC
–
150
---------------------
=
RFD14N05, RFD14N05SM
©2004 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM Rev. C
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTE RISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOW N
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD V OLT AGE vs
JUNCTION TEMPERATURE FIGURE 11. NORMALIZED DRAIN T O SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves Unless Otherwise Specified (Continued)
0.1 1 10
10
0.01
50
1
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AV ALANCHE (ms)
STARTING TJ = 25oC
STARTING TJ = 150oC
0
5
10
15
02468
20
25
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 4.5V
VGS = 5V
VGS = 6V
VGS = 7V
VGS = 20V
30
35
VGS = 8V
VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
0468102
0
5
10
15
20
25 175oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
IDS(ON), DRAIN TO SOURCE CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
-55oC
30
35
-25oC
2.0
1.5
1.0
0.5
0
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
200
ID = 250µA
-80 -40 0 40 80 120 160
0
0.5
1.0
1.5
2.0
VGS(TH), NORMALIZED GATE
THRESHOLD VOLTAGE
TJ, JUNCTION TEMPERATURE (oC) 200
VGS = VDS, ID = 250µA
0
0.5
1.0
1.5
2.0
-80 -40 0 40 80 120 160
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC) 200
2.5
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS= 10V, ID = 14A
RFD14N05, RFD14N05SM
©2004 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM Rev. C
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260,
FIGURE 13. NORMALIZED SWITCHING W AVEFORMS FOR
CONSTANT CURRENT GATE DRIVE
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAV EFORMS
Typical Performance Curves Unless Otherwise Specified (Continued)
700
500
200
00 5 10 15 20 25
C, CAPACITANCE (pF)
400
VDS, DRAIN TO SOURCE VOLTAGE (V)
CISS
COSS
CRSS
300
100
600
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
30
15
0
20IGREF()
IGACT()
----------------------t, TIME (µs) 80IGREF()
IGACT()
----------------------
10
5.0
2.5
0
VDD = BVDSS VDD = BVDSS
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
RL = 3.57Ω
IG(REF) = 0.4mA
VGS = 10V
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
60
7.5
45
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RGS
DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
RFD14N05, RFD14N05SM
©2004 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM Rev. C
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
IG(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
IG(REF)
0
0
RFD14N05, RFD14N05SM
©2004 Fairchild Semiconductor Corporation RFD14N05, RFD14N05SM Rev. C
PSPICE Electrical Model
.SUBCKT RFD14N05 2 1 3 ; rev 9/12/94
CA 12 8 8.84e-10
CB 15 14 9.34e-10
CIN 6 8 5.2e-10
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 62.87
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 4.34e-9
LSOURCE 3 7 3.79e-9
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 2.2e-3
RGATE 9 20 5.64
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 42.3e-3
RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.82
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/50,6))}
.MODEL DBDMOD D (IS = 1.5e-13 RS = 10.9e-3 TRS1 = 2.3e-3 TRS2 = -1.75e-5 CJO = 6.84e-10 TT = 4.2e-8)
.MODEL DBKMOD D (RS = 4.15e-1 TRS1 = 3.73e-3 T RS2 = -3.21e-5)
.MODEL DPLCAPMOD D (CJO = 26.2e-11 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (V TO = 3.91 KP = 12.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 7.73e-4 TC2 = 2.12e-6)
.MODEL RDSMOD R ES (TC1 = 5.0e-3 TC2 = 2.53e-5)
.MODEL RSCLMOD RES (T C1 = 2.05e-3 TC2 = 1.35e-5)
.MODEL RVTOMOD RES (TC1 = -4.44e-3 TC2 = -6.45e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.29 VOFF= -3.29)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.29 VOFF= -5.29)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.25 VOFF= 2.75)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.75 VOFF= -2.25)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-ci rcuit for the Power MOSFET Feat ur ing Global
Te mpe rature Options; written by William J. Hepp and C. Frank Wheatley.
EVTO
+
13
CA CB
EGS EDS
RIN CIN
MOS1
MOS2
DBREAK
EBREAK
DBODY
LDRAIN
DRAIN
RSOURCE LSOURCE
SOURCE
RBREAK
RVTO
VBAT
IT
VTO
DPLCAP
6
10 5
16
21
8
14
73
17 18
19
2
+
+
+
RDRAIN
ESCL
RSCL1
RSCL2 51
50
+
S1A S2A
S2BS1B
12 15
13
814
13
6
8
+
-5
8
-
-
18
8
RGATE
GATE
LGATE
209
1
ESG +
-6
811 +
-
17
18
5
51
RFD14N05, RFD14N05SM
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS P ATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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F ACT Quiet Series™
FAST
FASTr™
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Across the board. Around the world.™
The Power Franchise™
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