General Description
The MAX9153/MAX9154 low-jitter, low-voltage differential
signaling (LVDS) repeaters are ideal for applications that
require high-speed data or clock distribution while mini-
mizing power, space, and noise. The devices accept a
single LVDS input (MAX9153) or single LVPECL input
(MAX9154) and repeat the signal at 10 LVDS outputs.
Each differential output drives 100Ω, allowing point-to-
point distribution of signals on transmission lines with
100Ωtermination at the receiver input.
Ultra-low 90psp-p (max) added deterministic jitter and
1psRMS (max) added random jitter ensure reliable com-
munication in high-speed links that are highly sensitive to
timing error, especially those incorporating clock-and-
data recovery or serializers and deserializers. The high-
speed switching performance guarantees 800Mbps data
rate and less than 60ps (max) skew between channels
while operating from a single +3.3V supply.
Supply current at 800Mbps is 118mA and reduces to
2µA in power-down mode. LVDS inputs and outputs con-
form to the ANSI/EIA/TIA -644 standard. A fail-safe fea-
ture on the MAX9153 sets the output high when the input
is undriven and open, terminated, or shorted. The
MAX9153/MAX9154 are available in a 28-pin TSSOP
package and are specified for the -40°C to +85°C
extended temperature range.
Refer to the MAX9150 data sheet for a pin-compatible
10-port LVDS repeater capable of driving a double-termi-
nated (50Ω) LVDS link.
Refer to the MAX9110/MAX9112 and MAX9111/MAX9113
data sheets for LVDS line drivers and receivers.
Applications
Cellular Phone Base-Stations
Add/Drop Muxes
Digital Cross-Connects
Network Switches/Routers
Backplane Interconnect
Clock Distribution
Features
♦Ultra-Low 90psp-p (max) Added Deterministic
Jitter at 800Mbps (223-1) PRBS Pattern
♦1psRMS (max) Added Random Jitter
♦60ps (max) Skew Between Channels
♦Guaranteed 800Mbps Data Rate
♦LVDS (MAX9153) or LVPECL (MAX9154) Input
Versions
♦Fail-Safe Circuit Sets Output High for Undriven
Inputs (MAX9153)
♦High-Impedance Differential Input when VCC = 0
♦2µA Power-Down Supply Current
♦Conforms to ANSI/EIA/TIA-644 LVDS Standard
♦Pin-Compatible Upgrade to DS90LV110
MAX9153/MAX9154
Low-Jitter, 800Mbps, 10-Port LVDS
Repeaters with 100
Ω
Drive
________________________________________________________________ Maxim Integrated Products 1
19-2167; Rev 0; 10/01
EVALUATION KIT
AVAILABLE
Ordering Information
PART TEMP.
RANGE
PIN-
PACKAGE INPUT
MAX9153EUI -40°C to +85°C 28 TSSOP LVDS
MAX9154EUI -40°C to +85°C 28 TSSOP LVPECL
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configuration appears at end of data sheet.
100Ω
LVDS
LVDS
BACKPLANE
OR CABLE
1
10
100Ω
100Ω
MAX9153
MAX9154 RX
RX
MAX9111
MAX9111
TX
MAX9110
*
*(LVPECL INPUT FOR MAX9154)
Typical Application Circuit
MAX9153/MAX9154
Low-Jitter, 800Mbps, 10-Port LVDS
Repeaters with 100
Ω
Drive
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL= 100Ω±1%, differential input voltage |VID| = 0.05V to 1.2V, MAX9153 LVDS input common-mode voltage
VCM = |VID/2| to 2.4V - |VID/2|, MAX9154 LVPECL input voltage range = 0 to VCC, PWRDN = high, TA= -40°C to +85°C, unless other-
wise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA= +25°C.) (Notes 1 and 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND...........................................................-0.3V to +4.0V
RIN+, RIN- to GND ................................................-0.3V to +4.0V
PWRDN to GND..........................................-0.3V to (VCC + 0.3V)
DO_+, DO_- to GND..............................................-0.3V to +4.0V
Short-Circuit Duration (DO_+, DO_-) .........................Continuous
Continuous Power Dissipation (TA= +70°C)
28-Pin TSSOP (derate 12.8mW/°C above +70°C) .....1026mW
Storage Temperature.........................................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
ESD Protection
Human Body Model (RIN+, RIN-, DO_+, DO_-) ..............±8kV
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CONTROL INPUT (PWRDN)
Input High Voltage VIH 2.0 VCC V
Input Low Voltage VIL GND 0.8 V
Input Current IIN PWRDN = high or low -20 20 µA
DIFFERENTIAL INPUT (RIN+, RIN-)
Differential Input High Threshold VTH -3 50 mV
Differential Input Low Threshold VTL -50 -3 mV
0.05V ≤ | VID | ≤ 0.6V, PWRDN = high or low
(Figure 1) -15 -3 15
Input Current (MAX9153) IRIN+,
IRIN- 0.6V < | VID | ≤ 1.2V, PWRDN = high or low
(Figure 1) -20 -4 20
µA
0.05V ≤ | VID | ≤ 0.6V, VCC = 0 or open,
PWRDN = 0 or open (Figure 1) -15 3 15
Power-Off Input Current
(MAX9153)
IRIN+ (OFF),
IRIN-
(
OFF
)
0.6V < | VID | ≤ 1.2V, VCC = 0 or open,
PWRDN = 0 or open (Figure 1) -20 4 20
µA
PWRDN = high or low (Figure 1) 103
Input Resistor 1 (MAX9153) RIN1 VCC = 0 or open, PWRDN = 0 or open
(Figure 1) 103 kΩ
PWRDN = high or low (Figure 1) 154
Input Resistor 2 (MAX9153) RIN2 VCC = 0 or open, PWRDN = 0 or
open(Figure 1) 154 kΩ
VRIN+ = 3.6V, VRIN- = 3.6V or 0, PWRDN =
high or low (Figure 2) -10 3 10
Input Current (MAX9154) IRIN+,
IRIN- VRIN+ = 0, VRIN- = 3.6V or 0, PWRDN =
high or low (Figure 2) -10 ±3 10
µA
VRIN+ = 3.6V, VRIN- = 0, VCC = 0 or open,
PWRDN = 0 or open (Figure 2) -10 3 10
Power-Off Input Current
(MAX9154)
IRIN+ (OFF),
IRIN-
(
OFF
)
VRIN+ = 0, VRIN- = 3.6V, VCC = 0 or open,
PWRDN = 0 or open (Figure 2) -10 3 10
µA
MAX9153/MAX9154
Low-Jitter, 800Mbps, 10-Port LVDS
Repeaters with 100
Ω
Drive
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL= 100Ω±1%, differential input voltage |VID| = 0.05V to 1.2V, MAX9153 LVDS input common-mode voltage
VCM = |VID/2| to 2.4V - |VID/2|, MAX9154 LVPECL input voltage range = 0 to VCC, PWRDN = high, TA= -40°C to +85°C, unless other-
wise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA= +25°C.) (Notes 1 and 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWRDN = high or low (Figure 2) 360
Input Resistor 3 (MAX9154) RIN3 VCC = 0 or open, PWRDN = 0 or open
(Figure 2) 360 kΩ
LVDS OUTPUT (DO_+, DO_-)
Differential Output Voltage VOD Figure 3 250 380 450 mV
Charge in VOD Between
Complementary Output States ∆VOD Figure 3 1 25 mV
Offset (Common-Mode) Voltage VOS Figure 3 1.125 1.26 1.375 V
Change in VOS Between
Complementary Output States ∆VOS Figure 3 3 25 mV
Output High Voltage VOH Figure 3 1.6 V
Output Low Voltage VOL Figure 3 0.9 V
PWDRN = high or low
Differential Output Resistance RODIFF VCC = 0 PWDRN = 0 or open 150 238 330 Ω
RIN+, RIN- undriven with short, open, or
100Ω termination (MAX9153) 250 450
Differential High Output
Voltage in Fail-Safe VOD+
RIN+, RIN- open (MAX9154) 250 450
mV
PWDRN = low; VDO_+ = 3.6V or 0, DO_- +
open; or VDO_- = 3.6V or 0, DO_+ = open -1 1
Single-Ended Output Short-
Circuit Current IOZ VCC = 0, PWRDN = 0 or open; VDO_+ = 3.6V
or 0, DO_- = 3.6V or VDO_- = 3.6V or 0,
DO_+ = open
-1 1
µA
VID = +50mV, VDO_+ = 0 or VCC, VDO_- = 0
or VCC
Single-Ended Output
Short-Circuit Current IOS VID = -50mV, VDO_+ = 0 or VCC, VDO_- = 0
or VCC
-15 15 mA
VID = +50mV, VOD = 0
Differential Output Short-Circuit
Current (Note 3) IOSD VID = -50mV, VOD = 0 -15 15 mA
SUPPLY
DC, RL = 100Ω (Figure 4) 70 95
200MHz (400Mbps), RL = 100Ω90 115Supply Current ICC
400MHz (800Mbps), RL = 100Ω
Figure 4
(Note 3) 118 145
mA
Power-Down Supply Current ICCZ PWDRN = low 2 20 µA
MAX9153/MAX9154
Low-Jitter, 800Mbps, 10-Port LVDS
Repeaters with 100
Ω
Drive
4 _______________________________________________________________________________________
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced
to ground except VTH, VTL, VID, VOD, and ∆VOD.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are
production tested at TA= +25°C.
Note 3: Guaranteed by design and characterization.
Note 4: CLincludes scope probe and test jig capacitance.
Note 5: Signal generator conditions unless otherwise noted: frequency = 400MHz, 50% duty cycle, RO= 50Ω, tR= 0.6ns,
and tF= 0.6ns (0% to 100%).
Note 6: Device jitter added to the input signal.
Note 7: tCCS is the magnitude difference in differential propagation delay between outputs for a same-edge transition.
Note 8: tPPS1 is the magnitude difference of any differential propagation delays between devices operating over rated
conditions at the same supply voltage, input conditions, and ambient temperature.
Note 9: TPPS2 is the magnitude difference of any differential propagation delays between devices operating over rated conditions.
Note 10: Device meets VOD DC specification, and AC specifications while operating at fMAX.
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, differential input voltage |VID| = 0.15V to 1.2V, MAX9153 LVDS input common-
mode voltage VCM = |VID/2| to 2.4V - |VID/2|, MAX9154 LVPECL input voltage range = 0 to VCC, PWRDN = high, TA= -40°C to +85°C,
unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA= +25°C.) (Notes 3, 4, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Rise Time tLHT 150 220 450 ps
Fall Time tHLT
Figures 4, 5 150 220 450 ps
400Mbps (NRZ) 13 50
Added Deterministic Jitter
(Note 6) tDJ VID = 200mV, 223 - 1
PRBS data, VCM = 1.2V 800Mbps (NRZ) 24 90
ps
(p-p)
200MHz 1
Added Random Jitter (Note 6) tRJ VID = 200mV, 50% duty
cycle input, VCM = 1.2V 400MHz 1
ps
(RMS)
Differential Propagation Delay
Low to High tPLHD 1.6 2.3 3.3
Differential Propagation Delay
High to Low tPHLD
Figures 4, 5
1.6 2.3 3.3
ns
Pulse Skew | tPLHD - tPHLD |t
SKEW Figures 4, 5 27 80 ps
Channel-to-Channel Skew
(Note 7) tCCS Figures 4, 5 35 60 ps
Differential Part-to-Part Skew 1
(Note 8) tPPS1 1.2 ns
Differential Part-to-Part Skew 2
(Note 9) tPPS2
Figures 4, 5
1.7 ns
Maximum Input Frequency
(Note 10) fMAX Figures 4, 5 800 Mbps
Power-Down Time tPD 10 20 ns
Power-Up Time tPU
Figures 6, 7 20 40 µs
MAX9153/MAX9154
Low-Jitter, 800Mbps, 10-Port LVDS
Repeaters with 100
Ω
Drive
_______________________________________________________________________________________ 5
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
3.0 3.23.1 3.3 3.4 3.5 3.6
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9153/54 toc02
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPLHD
tPHLD
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
50 70 90 110 130 150
DIFFERENTIAL PROPAGATION DELAY
vs. OUTPUT LOAD
MAX9153/54 toc03
OUTPUT LOAD (Ω)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPLHD
tPHLD
70
100
110
120
130
140
150
160
170
10 100 1000
SUPPLY CURRENT vs. FREQUENCY
MAX9153/54 toc01
INPUT FREQUENCY (MHz)
SUPPLY CURRENT (mA)
90
80
Typical Operating Characteristics
(VCC = +3.3V, RL= 100Ω, CL= 5pF, |VID| = 200mV, VCM = 1.2V, fIN = 200MHz, TA= +25°C, unless otherwise noted.)
5
15
10
25
20
30
35
DIFFERENTIAL OUTPUT-TO-OUTPUT
SKEW vs. SUPPLY VOLTAGE
MAX9153/54 toc05
SUPPLY VOLTAGE (V)
DIFFERENTIAL OUTPUT-TO-OUTPUT SKEW (ps)
3.0 3.2 3.33.1 3.4 3.5 3.6
H
B
A, F
D
E
GI
C
A = DO5 - DO1
C = DO5 - DO3
E = DO5 - DO6
G = DO5 - DO8
I = DO5 - D010
B = DO5 - DO2
D = DO5 - DO4
F = DO5 - DO7
H = DO5 - DO9
190
210
200
240
230
220
270
260
250
280
3.0 3.23.1 3.3 3.4 3.5 3.6
TRANSITION TIME vs. SUPPLY VOLTAGE
MAX9153/54 toc06
SUPPLY VOLTAGE (V)
TRANSITION TIME (ps)
tHLT
tLHT
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
0 0.5 1.0 1.5 2.0 2.5
DIFFERENTIAL PROPAGATION DELAY
vs. INPUT COMMON-MODE VOLTAGE
MAX9153/54 toc04
INPUT COMMON MODE-MODE VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPLHD
tPHLD
200
300
250
400
350
500
450
550
597111315
TRANSITION TIME vs. LOAD CAPACITANCE
MAX9153/54 toc08
LOAD CAPACITANCE (pF)
TRANSITION TIME (ps)
tHLT
tLHT
200
210
205
220
215
230
225
235
50 9070 110 130 150
TRANSITION TIME vs. OUTPUT LOAD
MAX9153/54 toc07
OUTPUT LOAD (Ω)
TRANSITION TIME (ps)
tHLT
tLHT
Detailed Description
LVDS is a signaling method for point-to-point data com-
munication over a controlled-impedance medium as
defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 stan-
dards. LVDS uses a lower voltage swing than other
common communication standards, achieving higher
data rates with reduced power consumption, while
reducing EMI emissions and system susceptibility to
noise.
The MAX9153/MAX9154 are 800Mbps, 10-port
repeaters for high-speed, point-to-point, low-power
applications. The MAX9153 accepts an LVDS input and
has a fail-safe input circuit. The MAX9154 accepts an
LVPECL input. Both devices repeat the input at 10 LVDS
outputs. The devices detect differential signals as low
as 50mV and as high as 1.2V within the 0 to 2.4V input
voltage range as specified in the LVDS standards.
The MAX9153/MAX9154 outputs use a current-steering
configuration to generate a 2.5mA to 4.5mA output cur-
rent. This current-steering approach induces less
ground bounce and no shoot-through current, enhanc-
ing noise margin and system speed performance. The
outputs are short-circuit current limited and are high
PIN NAME FUNCTION
1, 3, 11, 13,
16, 18, 20,
24, 26, 28
DO2+, DO1+, DO10+,
DO9+, DO8+, DO7+,
DO6+, DO5+, DO4+, DO3+
2, 4, 12, 14,
15, 17, 19,
23, 25, 27
DO2-, DO1-, DO10-, DO9-,
DO8-, DO7-,
DO6-, DO5-, DO4-, DO3-
Differential LVDS Outputs
5PWRDN Power Down. Drive PWRDN low to disable all outputs and reduce supply current
to 2µA. Drive PWRDN high for normal operation.
6, 9, 21 GND Ground
10, 22 VCC Power. Bypass each VCC pin to GND with 0.1µF and 1nF ceramic capacitors.
7 RIN+
8 RIN-
LVDS (MAX9153) or LVPECL (MAX9154) Differential Inputs. RIN+ and RIN- are
high-impedance inputs. Connect a resistor from RIN+ to RIN- to terminate the
input signal.
Pin Description
MAX9153/MAX9154
Low-Jitter, 800Mbps, 10-Port LVDS
Repeaters with 100
Ω
Drive
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VCC = +3.3V, RL= 100Ω, CL= 5pF, |VID| = 200mV, VCM = 1.2V, fIN = 200MHz, TA= +25°C, unless otherwise noted.)
220
320
270
420
370
470
520
50 150
DIFFERENTIAL OUTPUT vs.
OUTPUT LOAD
MAX9153/54 toc10
OUTPUT LOAD (Ω)
DIFFERENTIAL OUTPUT (mV)
9070 110 130
380
386
384
382
388
390
392
394
396
398
400
3.0 3.23.1 3.3 3.4 3.5 3.6
DIFFERENTIAL OUTPUT vs.
SUPPLY VOLTAGE
MAX9153/54 toc09
SUPPLY VOLTAGE (V)
DIFFERENTIAL OUTPUT (mV)
MAX9153/MAX9154
Low-Jitter, 800Mbps, 10-Port LVDS
Repeaters with 100
Ω
Drive
_______________________________________________________________________________________ 7
impedance (to ground) when PWRDN = low or the
device is not powered. The outputs have a typical dif-
ferential resistance of 238Ω. The internal differential
output resistance terminates induced noise and reflec-
tions from the primary termination located at the LVDS
receiver.
The MAX9153/MAX9154 current-steering output
requires a resistive load to terminate the signal and
complete the transmission loop. Because the devices
switch the direction of current flow and not voltage lev-
els, the output voltage swing is determined by the value
of the termination resistor multiplied by the output cur-
rent. With a typical 3.8mA output current, the
MAX9153/MAX9154 produce a 380mV output voltage
when driving a transmission line terminated with a 100Ω
resistor (3.8mA x 100Ω= 380mV). Logic states are
determined by the direction of current flow through the
termination resistor.
Fail-Safe
The fail-safe feature of the MAX9153 sets the outputs
high when the differential input is:
•Open
•Undriven and shorted
•Undriven and terminated
Without a fail-safe circuit, when the input is undriven,
noise at the input may switch the outputs and it may
appear to the system that data is being sent. Open or
undriven terminated input conditions can occur when a
cable is disconnected or cut, or when an LVDS driver
output is in high impedance. A shorted input can occur
because of a cable failure.
When the input is driven with signals meeting the LVDS
standard, the input common-mode voltage is less than
VCC - 0.3V and the fail-safe circuit is not activated. If
the input is open, undriven and shorted, or undriven
and parallel terminated, an internal resistor in the fail-
safe circuit pulls both inputs above VCC - 0.3V, activat-
ing the fail-safe circuit and forcing the outputs high
(Figure 1).
The MAX9154 is essentially the MAX9153 without the
fail-safe circuit. The MAX9154 accepts input voltages
from 0 to VCC (vs. 0 to 2.4V for the MAX9153), which
allows interfacing to LVPECL input signals while retain-
ing a good common-mode tolerance.
Table 1. Input/Output Function Table
Note: VID = RIN+ - RIN-, VOD = DO_+ - DO_-
High = 450mV > VOD > 250mV
Low = -250mV > VOD > -450mV
MAX9153
VCC
RIN2
VCC - 0.3V
COMPARATOR
RIN1/2
RIN1/2
RIN+
RIN-
RECEIVER
DO1+
DO1-
DO10+
DO10-
Figure 1. MAX9153 Input Fail-Safe Circuit
MAX9154
RIN3
RIN3
RIN+
RIN-
DO1+
DO1-
DO10+
DO10-
VCC
RECEIVER
Figure 2. MAX9154 Input Bias Resistors
INPUT, VID OUTPUTS, VOD
+50mV High
-50mV Low
Open
MAX9153
MAX9154 High
Undriven short MAX9153 High
Undriven terminated MAX9153 High
MAX9153/MAX9154
Low-Jitter, 800Mbps, 10-Port LVDS
Repeaters with 100
Ω
Drive
8 _______________________________________________________________________________________
Applications Information
Supply Bypassing
Bypass each VCC with high-frequency surface-mount
ceramic 0.1µF and 1nF capacitors in parallel as close
to the device as possible, with the smaller value capac-
itor closest to the VCC pin.
Traces, Cables, and Connectors
The characteristics of input and output connections
affect the performance of the MAX9153/MAX9154. Use
controlled-impedance traces, cables, and connectors
with matched characteristic impedance.
Ensure that noise couples as common mode by run-
ning the traces of a differential pair close together.
Reduce within-pair skew by matching the electrical
length of the traces of a differential pair. Excessive
skew can result in a degradation of magnetic field can-
cellation. Maintain the distance between traces of a dif-
ferential pair to avoid discontinuities in differential
impedance. Minimize the number of vias to further pre-
vent impedance discontinuities.
Avoid the use of unbalanced cables, such as ribbon
cable. Balanced cables, such as twisted pair, offer
superior signal quality and tend to generate less EMI
due to canceling effects. Balanced cables tend to pick
up noise as common mode, which is rejected by the
LVDS receiver.
Termination
The MAX9153/MAX9154 are specified for 100Ωdiffer-
ential characteristic impedance but can operate with
90Ωto 132Ωto accommodate various types of inter-
connect. The termination resistor should match the dif-
ferential characteristic impedance of the interconnect
and be located close to the LVDS receiver input. Use a
±1% surface-mount termination resistor.
The output voltage swing is determined by the value of the
termination resistor multiplied by the output current. With a
typical 3.8mA output current, the MAX9153/MAX9154 pro-
duce a 380mV output voltage when driving a transmission
line terminated with a 100Ωresistor (3.8mA x 100Ω=
380mV).
Chip Information
TRANSISTOR COUNT: 1394
PROCESS: CMOS
Figure 3. Driver-Load Test Circuit
RIN+
RIN-
GENERATOR
50Ω
50Ω
MAX9153
MAX9154
DO1+
DO10+
DO10-
DO1-
VOD VOS
50Ω
50Ω
50Ω
50Ω
VOS
VOD
Test Circuits and Timing Diagrams
MAX9153/MAX9154
Low-Jitter, 800Mbps, 10-Port LVDS
Repeaters with 100
Ω
Drive
_______________________________________________________________________________________ 9
Test Circuits and Timing Diagrams (continued)
Figure 5. Propagation Delay and Transition Time Waveforms
RIN-
RIN+
tPHLD
VOD = (VDO_+) - (VDO_-)
tHLT
20%
80%
80%
50% O O 50%
tLHT
20%
DIFFERENTIAL
0
tPLHD
VID
Figure 4. Propagation Delay and Transition Time Test Circuit
DO1+
DO10+
RL
100Ω
RL
100Ω
DO10-
DO1-
RIN+
RIN-
GENERATOR
50Ω
50Ω
CL
5pF
CL
5pF
CL
5pF
CL
5pF
MAX9153
MAX9154
MAX9153/MAX9154
Low-Jitter, 800Mbps, 10-Port LVDS
Repeaters with 100
Ω
Drive
10 ______________________________________________________________________________________
Figure 6. Power-Up/Down Delay Test Circuit
RIN+
1.05V
1.0V
1.05V
1.0V
RIN-
PWRDN
GENERATOR
50Ω
DO1+
DO10+
DO10-
DO1-
1.2V
1.2V
RL
50Ω
RL
50Ω
RL
50Ω
RL
50Ω
CL
5pF
CL
5pF
CL
5pF
CL
5pF
MAX9153
MAX9154
Figure 7. Power-Up/Down Delay Waveforms
1.2V
1.2V
VDO_+ WHEN VID = +50mV
VDO_- WHEN VID = -50mV
VDO_+ WHEN VID = -50mV
VDO_- WHEN VID = +50mV
VCC
VOH
VOL
O
tPU
tPU
50%
50%
50%
50%
50%
tPD
tPD
50%
PWRDN
Test Circuits and Timing Diagrams (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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Package Information
TSSOP,NO PADS.EPS
Low-Jitter, 800Mbps, 10-Port LVDS
Repeaters with 100ΩDrive
MAX9153/MAX9154
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DO3+
DO3-
DO4+
DO4-
DO5+
DO5-
DO8-
VCC
GND
DO6+
DO6-
DO7+
DO7-
DO8+
DO9-
DO9+
DO10-
DO10+
VCC
GND
RIN-
RIN+
GND
DO1-
DO1+
DO2-
DO2+
TOP VIEW
MAX9153
MAX9154
PWRDN
TSSOP
Pin Configuration
