INTEGRATED CIRCUITS Xilinx has acquired the entire Philips CoolRunner Low Power CPLD Product Family. For more technical or sales information, please see: www.xilinx.com XCR3320 320 macrocell SRAM CPLD Product specification Supersedes data of 1998 Jul 22 IC27 Data Handbook 1999 Apr 16 Philips Semiconductors Product specification 320 macrocell SRAM CPLD XCR3320 Xilinx has acquired the entire Philips CoolRunner Low Power CPLD Product Family. For more technical or sales information, please see: www.xilinx.com FEATURES DESCRIPTION * 320 macrocell SRAM based CPLD * Configuration times of under 1.0 second * IEEE 1149.1 compliant JTAG testing capability The PZ3320 device is a member of the CoolRunner family of high-density SRAM-based CPLDs (Complex Programmable Logic Device) from Philips Semiconductors. This device combines high speed and deterministic pin-to-pin timing with high density. The PZ3320 uses the patented Fast Zero Power (FZP) design technique that combines high speed and low power for the first time ever in a CPLD. FZP allows the PZ3320 to have true pin-to-pin timing delays of 7.5ns, and standby currents of 100 microamps without the need for `turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used since the bipolar era) with a cascaded chain of pure CMOS gates, both standby and dynamic power are dramatically reduced when compared to other CPLDs. The FZP design technique is also what allows Philips to offer a true CPLD architecture in a high density device. - 5 pin JTAG interface - IEEE 1149.1 TAP controller * In system configurable * 3.3 volt device with 5V tolerant I/O * Innovative XPLA2 Architecture combines extreme flexibility and high speeds * 8 synchronous clock networks with programmable polarity at every macrocell * Up to 32 asynchronous clocks support complex clocking needs * Innovative XOR structure at every macrocell provides excellent The Philips PZ3320C/PZ3320N devices use the XPLA2 (eXtended Programmable Logic Array) architecture. This architecture combines the best features of both PAL- and PLA-type logic structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA2 architecture is constructed from 80 macrocell Fast Modules that are connected together by an interconnect array. Within each Fast Module are four Logic Blocks of 20 macrocells each. Each Logic Block contains a PAL structure with four dedicated product terms for each macrocell. In addition, each Logic Block has 32 additional product terms in a PLA structure that can be shared through a fully programmable OR array to any of the 20 macrocells. This combination efficiently allocates logic throughout the Logic Block, which increases device density and allows for design changes without re-defining the pinout or changing the system timing. The PZ3320 offers pin-to-pin propagation delays of 7.5ns through the PAL array of a Fast Module; and if the PLA array is used, an additional 1.5ns is added to the delay, no matter how many PLA product terms are used. If the interconnect array between Fast Modules is used, there is a second fixed delay of 2.0ns. This means that the worst case pin-to-pin propagation delay within a fast module is 7.5 + 1.5 = 9.0 ns, and the delay from any pin to any other pin across the entire chip is 7.5 + 2.0 = 9.5ns if only the PAL array is used, and 7.5 + 1.5 + 2.0 = 11.0ns if the PLA array is used. logic reduction capability * Logic expandable to 36 product terms on a single macrocell * Advanced 0.35 SRAM process * Design entry and verification using industry standard and Philips CAE tools * Control Term structure provides either sum terms or product terms in each logic block for: - 3-State buffer control - Asynchronous macrocell register reset/preset * Global 3-State pin facilitates `bed of nails' testing without sacrificing logic resources * Programmable slew rate control * Small form factor packages with high I/O counts * Available in commercial and industrial temperature ranges Table 1. PZ3320C/PZ3320N Features Each macrocell also has a two input XOR gate with the dedicated PAL product terms on one input and the PLA product terms on the other input. This patent-pending Versatile XOR structure allows for very efficient logic optimization compared to competing XOR structures that have only one product term as the second input to the XOR gate. The Versatile XOR allows an 8 bit XOR function to be implemented in only 20 product terms, compared to 65 product terms for the traditional XOR approach. PZ3320C/PZ3320N Usable gates 10,000 Maximum inputs 192 Maximum I/Os 192 Number of macrocells 320 Propagation delay (ns) 7.5 Packages The PZ3320 is SRAM-based, which means that it is configured from an external source at power up. See the configuration section of this data sheet for more information. The device supports the full JTAG specification (IEEE 1149.1) through an industry standard JTAG interface. It can also be configured through the JTAG port, which is very useful for prototyping. See section titled Configuring the Device Through JTAG for more information. 160 pin LQFP 256 pin PBGA Software support for the PZ3320 is through industry standard CAE tools (Cadence, Mentor, Synopsys, Viewlogic, Exemplar Logic, and Orcad) as well as Philips' own XPLA software. Entry methods include both text (ABEL, PHDL, VHDL, Verilog) and/or schematic. Design verification uses industry standard simulators for functional and timing simulation, and development tools are supported on personal computer, SPARC, and HP Workstation platforms. 1999 Apr 16 2 853-2158 21266 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N ORDERING INFORMATION ORDER CODE PACKAGE, PROPAGATION DELAY DESCRIPTION DRAWING NUMBER PZ3320C7BE 160-pin LQFP, 7.5 ns tPD Commercial temp. range, 3.3 volt power supply 10% SOT435-1 PZ3320C10BE 160-pin LQFP, 10 ns tPD Commercial temp. range, 3.3 volt power supply 10% SOT435-1 PZ3320C7EB 256-pin PBGA, 7.5 ns tPD Commercial temp. range, 3.3 volt power supply 10% SOT471-1 PZ3320C10EB 256-pin PBGA, 10 ns tPD Commercial temp. range, 3.3 volt power supply 10% SOT471-1 PZ3320N8BE 160-pin LQFP, 8.5 ns tPD Industrial temp. range, 3.3 volt power supply 10% SOT435-1 PZ3320N8EB 256-pin PBGA, 8.5 ns tPD Industrial temp. range, 3.3 volt power supply 10% SOT471-1 1999 Apr 16 3 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N macrocells each inside. There are eight dedicated, low-skew, global clocks for the device; and each Fast Module has access to any two of these clocks (there are additional asynchronous clocks available in the Fast Modules, see Figure 3). There are also Global 3-state (gts) and Global Reset (rstn) pins that are common to all Fast Modules. When gts is pulled high, all output buffers in the device will be disabled, causing all I/O pins to be tri-stated. When rstn is pulled low, all flip-flops of the device will be reset. XPLA2 ARCHITECTURE Figure 1 shows a high level block diagram of the PZ3320 implementing the XPLA2 architecture. The XPLA2 architecture is a multi-level, modular hierarchy that consists of Fast Modules interconnected by a virtual crosspoint switch called the Global Zero Power Interconnect Array (GZIA). Each Fast Module accepts 64 bits from the GZIA and outputs 64 bits to the GZIA. Each Fast Module is essentially an 80 macrocell CPLD with four logic blocks of 20 DEDICATED CLOCK INPUTS 8 64 2 64 FAST MODULE 64 FAST MODULE 2 FAST MODULE 2 64 GZIA 64 2 64 FAST MODULE 64 64 gts rstn SP00655 Figure 1. Philips XPLA2 CPLD Architecture 1999 Apr 16 4 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N (LZIA). The LZIA is a virtual crosspoint switch that connects the Logic Blocks to each other and to the GZIA. The feedback from all 80 macrocells, input from the I/O pins, and the 64 bit input bus from the GZIA are input into the LZIA. The LZIA outputs 36 signals into each Logic Block and 64 signals into the GZIA. XPLA2 Fast Module Each Fast Module consists of four Logic Blocks of 20 macrocells each. Depending on the package, either 7 or 12 of the 20 macrocells in each Logic Block are connected to I/O pins, and the remaining macrocells are used as buried nodes. These four Logic Blocks are connected together by the Local Zero Power Interconnect Array MC0 MC1 I/O MC0 LOGIC BLOCK 36 36 LOGIC BLOCK MC19 MC1 I/O MC19 20 20 LZIA MC0 MC1 I/O MC0 LOGIC BLOCK 36 36 LOGIC BLOCK MC19 MC1 I/O MC19 20 20 64 64 SP00656 Figure 2. Philips XPLA2 Fast Module 1999 Apr 16 5 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N Each macrocell has 4 dedicated product terms from the PAL array. When additional logic is required, each macrocell takes the extra product terms from the PLA array. The PLA array consists of 32 extra product terms that are shared between the 20 macrocells of the Logic Block. The PAL product terms can be connected to the PLA product terms through either an OR gate or an XOR gate. One input to the XOR gate can be connected to all the PLA terms, which provides for extremely efficient logic synthesis. An eight bit XOR function can be implemented in only 20 product terms. Each macrocell can use the output from the OR gate or the XOR gate in either normal or inverted state. XPLA2 Logic Block Architecture Figure 3 illustrates the XPLA2 Logic Block architecture. Each Logic Block contains 8 control terms, a PAL array, a PLA array, and 20 macrocells. The 36 inputs from the LZIA are available to all control terms and to each product term in both the PAL and the PLA array. The 8 control terms can individually be configured as either SUM or PRODUCT terms, and are used to control the asynchronous preset and reset functions of the macrocell registers, the output enables of the 20 macrocells, and for asynchronous clocking. The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. LZIA INPUTS 36 8 CONTROL 4 MC0 4 MC1 4 PAL ARRAY MC2 4 MC19 PLA ARRAY (32) PATENT PENDING SP00589A Figure 3. Philips XPLA2 Logic Block Architecture 1999 Apr 16 6 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N applied, and that the preset/reset feature for each macrocell can also be disabled. Each macrocell can choose between an asynchronous reset or an asynchronous preset function, but both cannot be simultaneously used on the same register. The global rstn function can always be used, regardless of whether or not asynchronous reset or preset control terms are enabled. Control terms CT2, CT3, CT4 and CT5 are used to enable or disable the macrocell's output buffer. The output buffers can also be always enabled or always disabled. All CoolRunner devices also provide a Global 3-State (gts) pin, which, when pulled high, will 3-State all the outputs of the device. This pin is provided to support "In-Circuit Testing" or "Bed-of-Nails" testing used during manufacturing. XPLA2 Macrocell Architecture Figure 4 shows the XPLA2 macrocell architecture used in the PZ3320. The macrocell can be configured as either a D- or T-type flip-flop or a combinatorial logic function. A D-type flip-flop is generally more useful for implementing state machines and data buffering while a T-type flip-flop is generally more useful in implementing counters. Each of these flip-flops can be clocked from any one of four sources. Two of the clock sources (CLK0 and CLK1) are from the eight dedicated, low-skew, global clock networks designed to preserve the integrity of the clock signal by reducing skew between rising and falling edges. These clocks are designated as "synchronous" clocks and must be driven by an external source. Both CLK0 and CLK1 can clock the macrocell flip-flops on either the rising edge or the falling edge of the clock signal. The other clock sources are designated as "asynchronous" and are connected to two of the eight control terms (CT6 and CT7) provided in each logic block. These clocks can be individually configured as any PRODUCT term or SUM term equation created from the 36 signals available inside the logic block. Thus, in each Logic Block, there are up to four possible clocks; and in each Fast Module, there are up to 10 possible clocks. Throughout the entire device, there are up to 40 possible clocks--eight from the dedicated, low-skew, global clocks, and two for each of the 16 logic blocks. For the macrocells in the Logic Block that are associated with I/O pins, there are two feedback paths to the LZIA: one from the macrocell, and one from the I/O pin. The LZIA feedback path before the output buffer is the macrocell feedback path, while the LZIA feedback path after the output buffer is the I/O pin feedback path. When these macrocells are used as outputs, the output buffer is enabled, and either feedback path can be used to feedback the logic implemented in the macrocell. When the I/O pins are used as inputs, the output buffer of these macrocells will be 3-Stated and the input signal will be fed into the LZIA via the I/O feedback path. In this case the logic functions implemented in the buried macrocell can be fed back into the LZIA via the macrocell feedback path. For macrocells that are not associated with I/O pins, there is one feedback path to the LZIA. Logic functions implemented in these buried macrocells are fed back into the LZIA via this path. All unused inputs and I/O pins should be properly terminated. Please refer to the section on terminations. The remaining six control terms of each logic block (CT0-CT5) are used to control the asynchronous preset/reset of the flip-flops and the enable/disable of the output buffers in each macrocell. Control terms CT0 and CT1 are used to control the asynchronous preset/reset of the macrocell's flip-flop. Note that the power-on reset leaves all macrocells in the "zero" state when power is properly TO LZIA D/T Q gts INIT* CLK0 CLK0 GND CT0 CLK1 CLK1 CT1 CT6 GND CT7 rstn CT2 CT3 CT4 CT5 VCC GND *SEE XPLA2 MACROCELL ARCHITECTURE DESCRIPTION SP00590 Figure 4. PZ3320 Macrocell Architecture 1999 Apr 16 7 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N there are fixed delays added for use of the PLA array or the GZIA. The tCO (pin-to-pin) timing specification never changes. For example, a combinatorial logic function of four or fewer product terms constructed from inputs within the same logic block would have a tPD delay of 7.5ns. If the logic function were more than four product terms wide, the delay would be tPD plus the fixed PLA delay, or 7.5 + 1.5 = 9.0ns. A function that used the PAL array and inputs from a different Fast Module would have a propagation delay of tPD plus the fixed GZIA delay, or 7.5 + 2.0 = 9.5ns. Simple Timing Model Figure 5 shows the PZ3320 timing model. The PZ3320 timing model is very simple compared to the models of competing architectures. There are three main timing parameters: the pin-to-pin delay for combinatorial logic functions (tPD), the input pin to register set up time (tSU), and the register clock to valid output time (tCO). As the model shows, timing is only dependent on whether or not you use the PLA array, and whether or not the logic function is created within a single Fast Module or uses the GZIA. The timing starts with a set time for tPD and tSU through the PAL array in a Fast Module, and Within a Fast Module: INPUT PIN INPUT PIN tPD_PAL = COMBINATORIAL PAL tPD_PLA = COMBINATORIAL PAL + PLA REGISTERED tSU_PAL = PAL tSU_PLA = PAL + PLA D Q REGISTERED tCO OUTPUT PIN OUTPUT PIN GLOBAL CLOCK PIN Using the Global ZIA: INPUT PIN INPUT PIN tPD_PAL = COMBINATORIAL PAL + GZD tPD_PLA = COMBINATORIAL PAL + PLA ,+ GZD REGISTERED tSU_PAL = PAL + GZD tSU_PLA = PAL + PLA + GZD D Q REGISTERED tCO OUTPUT PIN OUTPUT PIN GLOBAL CLOCK PIN SP00591B Figure 5. PZ3320 Timing Model 1999 Apr 16 8 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N breaking the paradigm that to have low power, you must have low performance. This also makes it possible to manufacture high density CPLDs like the PZ3320 that consume a fraction of the power of competing devices. Refer to Figure 6 and Table 2 showing the IDD vs. Frequency of the PZ3320 TotalCMOS CPLD (data taken with 20 16-bit counters @ 3.3V, 25C, output buffers disabled). TotalCMOS Design Technique for Fast Zero Power Philips is the first to offer a TotalCMOS CPLD, both in process technology and design technique. Philips employs a cascade of CMOS gates to implement its product terms instead of the traditional sense amp approach. This CMOS gate implementation allows Philips to offer CPLDs which are both high performance and low power, IDD (mA) 200 180 160 140 120 100 80 60 40 20 0 0 20 40 60 80 100 120 FREQUENCY (MHz) SP00657 Figure 6. IDD vs. Frequency @ VDD = 3.3V, 25C Table 2. IDD vs. Frequency VDD = 3.3V FREQUENCY (MHz) Typical IDD (mA) 0 1 20 40 60 80 100 120 0.01 1.3 26 51 77 102 126 152 unused I/O pins on the PZ3320C/PZ3320N device be left unconnected. Terminations The CoolRunner PZ3320C/PZ3320N CPLDs are TotalCMOS devices. As with other CMOS devices, it is important to consider how to properly terminate unused inputs and I/O pins when fabricating a PC board. Allowing unused inputs and I/O pins to float can cause the voltage to be in the linear region of the CMOS input structures, which can increase the power consumption of the device. It can also cause the voltage on a configuration pin to float to an unwanted voltage level, interrupting device operation. There are no on-chip pull-down structures associated with dedicated pins used for device configuration or special device functions like global reset and global 3-state. Philips recommends that these pins be terminated consistent with pin functionality. Philips recommends the use of weak pull-up and pull-down resistors for terminating these pins. See the appropriate configuration section for more information on terminating dedicated pins. The PZ3320C/PZ3320N CPLDs have programmable on-chip pull-down resistors on each I/O pin. These pull-downs are automatically activated by the fitter software for all unused I/O pins. Note that an I/O macrocell used as buried logic that does not have the I/O pin used for input is considered to be unused, and the pull-down resistors will be turned on. We recommend that any 1999 Apr 16 When using the JTAG Boundary Scan functions, it is recommended that 10k pull-up resistors be used on the tdi, tms, tck, and trstn pins. The tdo signal pin can be left floating unless it is connected to the tdi of another device. Letting these signals float can cause the voltage on tms to come close to ground, which could cause the device to enter JTAG/ISP mode at unspecified times. 9 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N configuration data can be transmitted to the PZ3320 serially or in parallel bytes. As a master, the PZ3320 generates the clock and control signals to strobe configuration data into the PZ3320. As a slave device, a clock is generated externally, and provided into the PZ3320's cclk pin. In the peripheral mode, the PZ3320 interfaces as a microprocessor peripheral. Please note that M3 should always be high. Table 3 lists the states for the other mode pins by configuration mode. CONFIGURATION INTRODUCTION The Philips CoolRunner series are available in technologies which use non-volatile (EEPROM-based) and volatile (SRAM based) configuration memory. The functionality of the XPLA2 family of the CoolRunner series is defined by on-chip SRAM. The devices are configured in a manner similar to that of most FPGAs. This section describes the configuration of the PZ3320, and applies to all similarly configured devices to be produced by Philips. Either Philips or third party software is used to generate a JEDEC file. The JEDEC file contains the configuration data, which is loaded into the PZ3320 configuration memory to control the PZ3320 functionality. This is done at power-up and/or with configure command. This section provides some of the trade-offs in selecting a configuration mode, and provides debug hints for configuration problems. Design Flow Overview Figure 7 is a diagram of the steps used in configuring the PZ3320. The development system is used to generate configuration data in the JEDEC file. Using the <design>.jed file, there are two general methods of configuring the PZ3320. The utility download can load the configuration data from a PC or workstation hard disk into the PZ3320. Alternately, the PZ3320 can be loaded from non-volatile ICs such as serial or parallel EEPROMs, after converting the JEDEC file to an MCS file using the jed2mcs utility. There are several different methods of configuring the PZ3320. The mode used is selected using the mode select pins. There are three basic configuration methods: master, slave, and peripheral. The Table 3. Configuration Modes M2 M1 M0 cclk CONFIGURATION MODE DATA FORMAT 0 0 0 Output Master serial Serial 0 0 1 Input Slave parallel Parallel 0 1 0 Reserved 0 1 1 Input Synchronous peripheral Parallel 1 0 0 Output Master parallel - up Parallel 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Input Slave serial Serial DESIGN COMPILATION AND FIT jed jed2mcs download PROM PROGRAMMER SLAVE SERIAL CONFIGURATION SP00676 Figure 7. Design flow 1999 Apr 16 10 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N is complete when the internal length count equals the loaded length count in the length count field, and the required end of configuration frame is written. PZ3320 STATES OF OPERATION Prior to becoming operational, the PZ3320 goes through a sequence of states, including initialization, configuration, and start-up. This section discusses these three states. In the master configuration modes, the PZ3320 is the source of configuration clock (cclk). All configuration I/Os used as inputs operate with TTL-level input thresholds during configuration. All I/Os that are not used during the configuration process are 3-Stated with internal pull-downs. During configuration, registers are reset. The combinatorial logic begins to function as the PZ3320 is configured. Figure 8 shows the flow between the initialization, configuration, and start-up states. Figure 9 gives the general timing information for configuring the device. When configuration is initiated, a counter in the PZ3320 is set to 0 and begins to count configuration clock cycles applied to the PZ3320. As each configuration data frame is supplied to the PZ3320, it is internally assembled into data words. Each data word is loaded into the internal configuration memory. The configuration loading process POWER-UP - POWER-ON TIME DELAY - crcerrn HIGH INITIALIZATION - hdc LOW, ldcn HIGH - done LOW resetn OR prgmn LOW crcerrn LOW YES NO CONFIGURATION CRC ERROR - - - - - M[3:0] MODE IS SELECTED CONFIGURATION DATA FRAME WRITTEN hdc HIGH, ldcn LOW dout ACTIVE crcerrn HIGH, done LOW resetn OR prgmn LOW DEVICE CONFIGURATION COMPLETE - done RELEASED - dout ACTIVE NO done HIGH YES START-UP - ALL MACROCELL FF'S ARE RESET prgmn LOW OPERATION - I/O BECOMES ACTIVE SP00622 Figure 8. Flow chart of initialization, configuration, and operating states 1999 Apr 16 11 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N VDD tpord tPW prgmn tr crcerrn resetn tcclk cclk tsmode M[3:0] tCL I/O active done tIL hdc ldcn INITIALIZATION CONFIGURATION START UP OPERATIONAL SP00652 Figure 9. General configuration mode timing diagram Table 4. General configuration mode timing characteristics SYMBOL PARAMETER All configuration modes tSMODE M[3:0] setup time to prgmn high tHMODE M[3:0] hold time from done high tPW prgmn pulse width low tgtsr Global 3-state disable tIL Initialization latency (prgmn high to hdc high) PZ3320 tPORD Power-on reset delay tr Configuration signal rise time Master modes tCCLK cclk period tCL Configuration latency (non-compressed) PZ3320 Slave serial, slave parallel, and Synchronous peripheral modes tCCLK cclk period eriod tCL Configuration latency (non-compressed) (non-com ressed) PZ3320 1999 Apr 16 M3 = 1 12 MIN MAX UNIT 0 10 50 - - - 40 700 1.0 ns s ns ns ns s s 250 1 - M3 = 1 M3 = 1 714 135 1667 316 ns ms Single device Daisy-chain Single device Daisy-chain 100 1000 19 189 - - - - ns ns ms ms Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N During initialization and configuration, all I/O's are 3-stated and the internal weak pull-downs are active. See the section on terminations for more information. Initialization Upon power-up, the device goes through an initialization process. First, an internal power-on-reset circuit is triggered when power is applied. When VDD reaches the voltage at which portions of the PZ3320 begin to operate (1.5V), the configuration pins are set to be inputs or outputs based on the configuration mode, as determined by the mode select inputs M[2:0]. The mode pins must be stable tsmode nanoseconds before the rising edge of prgmn or resetn. A time-out delay is initiated when VDD reaches between 1.0V and 2.0V to allow the power supply voltage to stabilize. The done output is low. At power-up, if the power supply does not rise from 1.0V to VDD in less than 25ms, the user should delay configuration by inputting a low into prgmn or resetn until VDD is greater than the recommended minimum operating voltage (3.0V for commercial devices). If prgmn has a rise time of greater than one microsecond, resetn must be held low until after prgmn goes high. If the rise time for prgmn is 1 microsecond or less, the order in which these pins go high is arbitrary. Start-up After configuration, the PZ3320 enters the start-up phase. This phase is the transition between the configuration and operational states. This transition occurs within three cclk cycles of the done pin going high (it is acceptable to have additional cclk cycles beyond the three required). The system design task in the start-up phase is to ensure that multi-function pins (see pin function on page NO TAG) transition from configuration signals to user definable I/Os without inadvertently activating devices in the system or causing bus contention. The done signal goes high at the beginning of the start up phase, which allows configuration sources to be disconnected so that there is no bus contention when the I/Os become active. In addition to controlling the PZ3320 during start-up, additional start-up techniques to avoid contention include using isolation devices between the PZ3320 and other circuits in the system, re-assigning I/O locations, and keeping I/Os 3-stated until contentions are resolved. For example, Figure 10 shows how to use the global tri-state (gts) signal to avoid signal contention when any multi-function pins are used as I/O after configuration is finished. Holding gts high until after the multi-function pins are disconnected from the driving source allows these pins to transition from configuration pins to user definable I/O without signal contention. In this case, the I/O become active a tgtsr delay after the gts pin is pulled low. The High During Configuration (hdc), Low During Configuration (ldcn), and done signals are active outputs in the PZ3320's initialization and configuration states. hdc, ldcn, and done can be used to provide control of external logic signals such as reset, bus enable, or EEPROM enable during configuration. For master parallel configuration mode, these signals provide EEPROM enable control and allow the data pins to be shared with user logic signals. If configuration has begun, an assertion of resetn or prgmn initiates an abort, returning the PZ3320 to the initialization state. The resetn and prgmn pins must be high before the PZ3320 will enter the configuration state, and the mode pins must be stable tsmode nanoseconds before they rise. During the start-up and operating states, only the assertion of prgmn causes a re-configuration. 1999 Apr 16 The flip-flops are reset one cycle after done goes high so that operation begins in a known state. The done outputs from multiple PZ3320s can be wire ANDed and used as an active-high ready signal, to disable PROMs with active-low enable(s), or to reset to other parts of the system (see Figure 27). 13 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N VDD tpord tPW prgmn tr crcerrn resetn cclk tsmode tsmode M[3:0] tCL I/O active tgtsr tgtsh GTS tHMODE done tIL hdc ldcn INITIALIZATION CONFIGURATION START UP OPERATIONAL INITIALIZATION SP00653 Figure 10. Using gts signal with power up to avoid signal contention with multi-function pins used as I/O The ordering of the data packets may be random, but they cannot be mixed with other devices' data packets. Alignment bits are not required between data packets. If used, alignment bits must be included in the length count, and they must be at least 2 bits long. CONFIGURATION DATA FORMAT OVERVIEW The PZ3320 functionality is determined by the state of internal configuration RAM. This section discusses the configuration data format, and the function of each field in configuration data packets. Configuration Data Packets 27 Configuration of the PZ3320 is done using configuration packets. The configuration packet is shown in Figure 11. The data packet consists of a header and a data frame. There are four types of data frames. The header is shifted into the device first, followed by one data frame. Configuration of a single PZ3320 requires 338 data packets, one for each address. All preceding data must contain only 1's. Once a device is configured, it re-transmits data of any polarity. Before and during configuration, all data re-transmitted out the daisy-chain port (dout) are 1's. 1999 Apr 16 DATA FRAME MSB HEADER LSB SP00593 Figure 11. Data Packet 14 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N cr_reg[0] < cr_reg[15]^din; cr_reg[15] <= cr_reg[15]^din^cr_reg[14]; If a CRC error is detected, configuration is halted and must be restarted. Table 5. Configuration Frame Size DEVICE PZ3320 Number of frames 338 Data bits/standard frame 560 Data bits/compressed frame 14 Data bits/user_code frame 560 Data bits/isc_code frame 560 Maximum configuration data-- # bits/frame x # frames 189280 2 16 1 4 w4 COMPRESSION BITS CRC BITS CRC ENABLE PREAMBLE/ POSTAMBLE LEADING 1s MSB Compression Bits: This 2-bit field defines the use of compression of the data packets. 00 - Standard mode: The data packet contains both address and data 01 - Reset mode: The data packet contains only the address field. This pattern causes the configuration register to be reset. 10 - Hold mode: The data packet contains only the address field. This pattern causes the configuration register to hold its value. 11 - Set mode: The data packet contains only the address field. This pattern causes the configuration register to be set. LSB SP00594 Data Frames Figure 12. 27-bit Header The four types of data frames are standard, compressed, user_code, and isc_code. All fields must be completely filled, with 1s used to fill unused bits. The definition of each frame is described below: The header is fixed and consists of five fields: - Leading 1s, - Preamble, - CRC Enable, - CRC Bits, - Compression Bits. Standard frame The leading 1s enter the device first. The following is a description of each field in the header. 11 546 1 (0) 2 (11) ADDRESS DATA FRAME STOP BIT ALIGN BITS MSB LSB Leading 1s: This is a four or greater bit field consisting of 1s. SP00595 Figure 13. Standard Frame Preamble/Postamble: This is a four bit field which indicates the start of a frame or the end of configuration: Preamble: 0010 - signals the beginning of a configuration data packet Postamble: 0100 - signals the end of configuration All other values of the preamble field force configuration of the entire system to restart. Address: This is an 11 bit field for providing 338 (336 SRAM plus 2 user) addresses. Data: 546 bit field. Stop bit: This is a one bit field which must be 0. The segments CRC Enable, CRC Bits, and Compression Bits are valid only if the Preamble field is 0010. Align bit: This is a two bit field which must be 11. Cyclic Redundancy Check (CRC) Enable: In this single bit field, a 0 disables CRC checking of the data stream. If the CRC is disabled the 16 bit CRC field must be the default described below. A 1 enables CRC error checking of the data stream. Compressed frame CRC Error Checking: The CRC field is a 16 bit field. The default value is 1010_1010_1010_1010. The calculated value is from data, address, stop bit, and first alignment bit (starting with crc_reg[15:0] = [0]). Using verilog operators, the crc is calculated as: crc_reg[14:2] <= cr_reg[14:2] << 1; cr_reg[2] <= cr_reg[15]^din^cr_reg[1]; cr_reg[1] <= cr_reg[0]; 1999 Apr 16 11 1 (0) 2 (11) ADDRESS STOP BIT ALIGN BITS MSB LSB SP00597 Figure 14. Compressed Frame The compressed frame contains no data. 15 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N User code frame The user code is located at address 336. cclk is an output with a nominal frequency of 1 MHz. In slave modes, cclk is an input with a maximum frequency of 10 MHz if configuring only a single device, and 1 MHz if devices are daisy chained. 11 274 24 32 216 1 (0) 2 (11) ADDRESS UNUSED LENGTH COUNT DEVICE ID USER CODE STOP BIT ALIGN BITS MSB Master Serial Mode In the master serial mode, the PZ3320 loads the configuration data from an external serial ROM. The configuration data is either loaded automatically at start-up or on a command to reconfigure. Serial EEPROMs from Altera, Atmel, Lucent, Microchip, and Xilinx can be used to configure the PZ3320 in the master serial mode. This provides a simple four-pin interface in an eight-pin package. Serial EEPROMs are available in 32K, 64K, 128K, 256K, and 1M bit densities. LSB SP00598 Figure 15. User code Frame Length count: This is a 24 bit field containing the length of the data stream transmitted to configure all of the devices in the daisy chain. This field is only used by a PZ3320 if it is in the master mode. Configuration in the master serial mode can be done at power-up and/or upon a configure command. The system or the PZ3320 must activate the serial EEPROM's RESET/OE and CE inputs. At power-up, the PZ3320 and serial EEPROM each contain internal power-on reset circuitry which allows the PZ3320 to be configured without the system providing an external signal. The power-on reset circuitry causes the serial EEPROMs' internal address pointer to be reset. After power-up, the PZ3320 automatically enters its initialization phase. Device ID: This is a 32-bit field containing PZ3320 device ID: 0000_001_001_010000_1_000_00000010101_1 User code: This is a 216 bit field reserved for user information. The serial EEPROM/PZ3320 interface used depends on such factors as the availability of a system reset pulse, availability of an intelligent host to generate a configure command, whether a single serial EEPROM is used or multiple serial ROMs are cascaded, whether the serial EEPROM contains a single or multiple configuration programs, etc. ISC code frame The isc_code address is 337. 11 272 272 1 (0) 2 (11) ISC CODE UNUSED STOP BIT ALIGN BITS 2 ADDRESS MSB Data is read into the PZ3320 sequentially from the serial ROM. The DATA output from the serial EEPROM is connected directly into the din input of the PZ3320. The cclk output from the PZ3320 is connected to the CLOCK input of the serial EEPROM. During the configuration process, cclk clocks one data bit into the PZ3320 on each rising edge. LSB UNUSED SP00599 Figure 16. ISC Frame Since the data and clock are direct connects, the PZ3320/serial EEPROM interface task is to use the system or PZ3320 to enable the RESET/OE and CE of the serial EEPROM(s). The serial EEPROM's RESET/OE is programmable to function with RESET active-low and OE active-high, which allows hdc from the PZ3320 to control this function. The ISC frame allows the user to write an ISC code to the device. Re-configuration To reconfigure the PZ3320 when the device is operating in the system, a low pulse is input into prgmn. The I/Os not used for configuration are 3-Stated. The PZ3320 then samples the mode select inputs and begins re-configuration. The mode pins are continuously sampled, so the signals must be stable while prgmn is low. When configuration is compete, done is released, allowing it to be pulled high. Likewise, the serial EEPROM could be programmed to function with RESET active high and OE active low, allowing the ldcn pin from the PZ3320 to control this function. The PZ3320 done pin is connected to the serial EEPROM CE to enable the EEPROMs during configuration and disable them when configuration is complete. In Figure 17, the serial EEPROMs RESET/OE pin has been programmed to function with RESET active low and OE active high, and it is controlled by the PZ3320's hdc pin. This resets the serial EEPROMs during the initialization state and enables their output during the configuration state. If a bit error is found during configuration, hdc will go low, signifying the PZ3320 is back in initialization state and also resetting the EEPROMs. This restarts the configuration process. CRC Error Checking CRC checking is done on each frame if enabled by setting the CRCen bit in the header. If there is an error, a CRC error is flagged by pulling crcerrn low. The PZ3320 is forced into the initialization state, and then moves into the configuration state after prgmn and resetn go high. The PZ3320 will also pull crcerrn low if an invalid preamble is detected within a configuration data packet. The PZ3320 done pin is routed to the CE pin of the EEPROMs. The low signal on done during configuration enable the serial EEPROMs. At the completion of configuration, the high on done disables the EEPROMs. PZ3320 CONFIGURATION MODES The method for configuring the PZ3320 is selected by the m0, m1, and m2 inputs. The m3 input should be high for all modes. In master modes, 1999 Apr 16 16 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N DATA din CLK cclk CE done RESET/OE dout TO DAISY-CHAINED DEVICES hdc VCC CEO PZ3320 prgmn VCC VCC M3 M2 M1 M0 EXTERNAL CONTROLLER IF DESIRED resetn SP00666 Figure 17. Master Serial Configuration In Figure 17, a serial EEPROM is programmed to configure a PZ3320. When configuration data requirements exceed the capacity of a single serial EEPROM, multiple serial EEPROMs can be cascaded to support the configuration of a single (or multiple) PZ3320(s). After the last bit from the first serial ROM is read, the serial ROM outputs CEO low and 3-States the DATA output. The next serial ROM recognizes the low on CE input and outputs configuration data on the DATA output. After configuration is complete, the PZ3320's done output into CE disables the serial EEPROMs. In applications in which a serial EEPROM stores multiple configuration programs, the subsequent configuration program(s) are stored in EEPROM locations that follow the last address for the previous configuration program. The user must ensure that the serial EEPROMs address pointer is not reset, causing the first device configuration to be reloaded. Contention on the PZ3320's din pin must be avoided. During configuration, din receives configuration data. After configuration, it is a user I/O. tCL CCLK tCH tS DIN tH BIT N tD DOUT BIT N SP00584 Figure 18. Master Serial Configuration Mode Timing Diagram Table 6. Master serial configuration mode timing characteristics SYMBOL MIN NOM MAX UNIT tS din setup time 60 - - ns tH din hold time 0 - - ns tD cclk to dout delay - - 300 ns tCL cclk low time M3 = 1 357 500 833 ns tCH cclk high time M3 = 1 357 500 833 ns tC cclk frequency M3 = 1 0.6 1.0 1.4 MHz 1999 Apr 16 PARAMETER 17 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N significant bit, D0. The starting memory address is 00000 Hex and the PZ3320 increments the address for each byte loaded. The starting address is output when the device enters the configuration state. The PZ3320 latches the data byte on the second rising edge of CCLK. This next data byte is latched in the PZ3320 seven cclk cycles later. Master Parallel Mode The master parallel configuration mode is generally used to interface to industry-standard byte-wide memory such as 256K and larger EEPROMs. Figure 19 provides the interface for master parallel mode. The PZ3320 outputs a 20-bit address on A[19:0] to memory and reads one byte of configuration data every eighth cclk. The parallel bytes are internally serialized starting with the least dout TO DAISY-CHAINED DEVICES cclk A[19:0] A[19:0] D[7:0] D[7:0] EEPROM PZ3320 OE done (SEE PIN DESCRIPTION) mpmi VCC CE prgmn EXTERNALLY CONTROLLED IF DESIRED VDD M3 M2 M1 M0 resetn EXTERNALLY CONTROL IF DESIRED SP00667 Figure 19. Master Parallel Configuration 1999 Apr 16 18 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N A[19:0] tS D[7:0] BYTE N tH BYTE N + 1 tCH CCLK tCL DOUT D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 tD BYTE N BYTE N + 1 SP00585 Figure 20. Master Parallel Configuration Mode Timing Diagram Table 7. Master parallel configuration mode timing characteristics SYMBOL MIN NOM MAX UNIT tAV cclk to address valid 0 - 200 ns tS D[7:0] setup time to cclk high 60 - ns tH D[7:0] hold time from cclk high - ns tCL cclk low time M3 = 1 357 500 833 ns tCH cclk high time M3 = 1 357 500 833 ns tD cclk to dout delay fC cclk frequency 1999 Apr 16 PARAMETER 0 - M3 = 1 19 0.6 1.0 300 ns 1.4 MHz Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N used for the lead PZ3320 for daisy-chained devices. Note that the cclk frequency for daisy-chained operation is limited to 1 MHz. Synchronous Peripheral Mode In the synchronous peripheral mode, byte-wide data is input into D[7:0] on the rising edge of the cclk input. The first data byte is clocked in on the second cclk after hdc goes high. Subsequent data bytes are clocked in on every eighth rising edge of cclk. The process repeats until all of the data is loaded into the PZ3320. The serial data begins shifting out on dout 0.5 cycles after the parallel data was loaded. It requires additional cclks after the last byte is loaded to complete the shifting. Figure 21 shows the interface for synchronous peripheral mode. When configuring a single device, the frequency of cclk can be up to 10 MHz. As with master modes, this mode can be Also note that CS1 is a multi-function pin, which means that it is available as a user I/O during normal device operation. As with all user I/O on the PZ3320, CS1 has an internal pull-down resistor that is automatically activated if the I/O pin is not used (see section on terminations for more information). If CS1 is left attached to VCC after configuration, and it is not used as an I/O, the internal pull-down must be disabled or a path from VCC to ground is created. To disable the pull-down, use the XPLA property statement `signal name:pin number tri-state' to disable the resistor. TO DAISY-CHAINED DEVICES 8 D[7:0] dout done crcerrn cclk MICRO- PROCESSOR OR SYSTEM VCC prgmn VCC PZ3320 cs1 cs0n resetn EXTERNALLY CONTROLLED IF DESIRED wrn M3 M2 SPMI SEE TABLE 9 M1 M0 SP00675 Figure 21. Synchronous Peripheral Configuration 1999 Apr 16 20 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N tCH CCLK tCL CS0N CS1 hdc tH tS D[7:0] BYTE 0 BYTE 1 tD DOUT D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 SP00609 Figure 22. Synchronous Peripheral Configuration Mode Timing Diagram Table 8. Synchronous peripheral configuration mode timing characteristics SYMBOL PARAMETER tS D[7:0] setup time tH D[7:0] hold time tCH C cclk high time tCL C cclk low time fC cclk frequency 1999 Apr 16 21 MIN MAX UNIT 20 0 ns 0 - ns Single device 50 - ns Daisy-chain device 500 - ns Single device 50 - ns Daisy-chain device 500 - ns Single device - 10 MHz Daisy-chain device - 1 MHz Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N into all slave serial mode devices in parallel and the frequency is limited to 1 MHz. The dout pin of the lead device is connected to the din pin of the next device and so on. In daisy-chained operation, all downstream devices use slave serial mode regardless of the configuration mode of the lead device. Slave Serial Mode Figure 23 shows the interface for the slave serial configuration mode. The configuration data is provided into the PZ3320's din input synchronous with the cclk input. After the PZ3320 has loaded its configuration data, it re-transmits incoming configuration data on dout. When configuring a single device, the frequency of cclk can be up to 10 MHz. Multiple slave PZ3320s can be loaded with identical configurations simultaneously. This is done by loading the configuration data into the din inputs in parallel. A device in slave serial mode can be used as the lead device in a daisy-chain. When used in daisy-chained operation, cclk is routed TO DAISY-CHAINED DEVICES dout PZ3320 crcerrn prgmn MICRO- PROCESSOR OR DOWNLOAD CABLE done cclk VCC din VCC EXTERNALLY CONTROLLED IF DESIRED resetn M3 M2 M1 M0 SP00668 Figure 23. Slave Serial Configuration Schematic DIN BIT N - 1 BIT N tS BIT N + 1 tH CCLK tD DOUT tCL BIT N - 1 tCH BIT N + 1 BIT N SP00610 Figure 24. Slave Serial Configuration Mode Timing Diagram Table 9. Slave serial configuration mode timing characteristics SYMBOL PARAMETER MIN MAX UNIT tS din setup time 20 0 ns tH din hold time 0 - ns Single device 50 - ns tCH C cclk high time Daisy-chain device 500 - ns Single device 50 - ns tCL C cclk low time Daisy-chain device 500 - ns Single device - 10 MHz fC cclk frequency Daisy-chain device - 1 MHz 1999 Apr 16 22 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N PZ3320. The serial data begins shifting out on dout 0.5 cycles after the parallel data was loaded. It requires additional cclks after the last byte is loaded to complete the shifting. Figure 25 shows the interface for slave parallel mode. When configuring a single device, the frequency of cclk can be up to 10 MHz. Slave Parallel Mode The slave parallel mode is essentially the same as the synchronous peripheral mode, except that the chip select pins (cs1 and cs0n) are not used. As in the synchronous peripheral mode, byte-wide data is input into D[7:0] on the rising edge of the cclk input. The first data byte is clocked in on the second cclk after hdc goes high. Subsequent data bytes are clocked in on every eighth rising edge of cclk. The process repeats until all of the data is loaded into the As with synchronous peripheral mode, the slave parallel mode can be used as the lead PZ3320 for daisy-chained devices. Note that the cclk frequency for daisy-chain operation is limited to 1 MHz. TO DAISY-CHAINED DEVICES dout PZ3320 crcerrn prgmn MICRO- PROCESSOR done cclk 8 VCC D[7:0] VCC EXTERNALLY CONTROLLED IF DESIRED resetn M3 CS1 M2 M1 M0 WRN CS0N SP00669 Figure 25. Slave Parallel Configuration Schematic tCH CCLK tCL hdc tH tS D[7:0] BYTE 0 BYTE 1 tD DOUT D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 SP00654 Figure 26. Slave Parallel Configuration Mode Timing Diagram 1999 Apr 16 23 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N Table 10. Slave parallel configuration mode timing characteristics SYMBOL PARAMETER tS D[7:0] setup time tH D[7:0] hold time tCH cclk high time tCL cclk low time fC cclk frequency Multiple PZ3320s can be configured by using a daisy-chain of PZ3320s. Daisy-chaining uses a lead PZ3320 and one or more PZ3320s configured in slave serial mode. The lead PZ3320 can be configured in any mode. Figure 27 shows the connections for loading multiple PZ3320s in a daisy-chain configuration with the lead devices configured in master parallel mode. Figure 28 shows the connections for loading multiple PZ3320's with the lead device configured in master serial mode. 0 - ns Single device 50 - ns Daisy-chain device 500 - ns Single device 50 - ns Daisy-chain device 500 - ns Single device - 10 MHz Daisy-chain device - 1 MHz The development software can create a composite configuration file for configuring daisy-chained PZ3320s. The configuration data consists of multiple concatenated data packets. cclk din MASTER PARALLEL/LEAD EEPROM D[7:0] D[7:0] OE done PROGRAM ns cclk din dout dout A[19:0] A[19:0] CE UNIT 0 The generation of cclk for the daisy-chained devices which are in slave serial mode differs depending on the configuration mode of the lead device. A master parallel mode device uses its internal timing generator to produce an internal cclk. If the lead device is configured in either synchronous peripheral, slave serial mode, or slave parallel mode, cclk is an input and is mated to the lead device and to all of the daisy-chained devices in parallel. The configuration data is read into din of slave devices on the positive edge of cclk, and shifted out dout on the negative edge of cclk. Note that daisy-chain operation is limited to a cclk frequency of 1 MHz. If a CRC error or an invalid preamble is detected by a slave device, crcerrn will be pulled low and in turn pull prgmn low, halting configuration for all devices. If a CRC error is detected by the master device, hdc will be pulled low, resetting the EEPROM to the first address and restarting configuration. Daisy-chained PZ3320s are connected in series. An upstream PZ3320 which has received the preamble outputs a high on dout, ensuring that downstream PZ3320s do not receive frame start bits. When the lead device receives the postamble, its configuration is complete. At this point, the configuration RAM of the lead device is full and its done pin is released. The lead device continues to load configuration data until the internal frame bit counter reaches the length count or all the done pins of the chain have gone high. Since the configuration RAM of the lead device is full, this data is shifted out serially to the downstream devices on the dout pin. As the configuration is completed for the downstream devices, each will release its done pin. Because the done pins of each device in the dout MAX 20 chain are wire-anded together, the done pin will be pulled high when all devices in the daisy-chain have completed configuration. All devices now move to the start-up state simultaneously. DAISY CHAIN OPERATION cclk MIN VCC VCC done done VCC prgmn prgmn M3 M2 M1 M0 SLAVE #2 SLAVE #1 crcerrn hdc ldcn M3 M2 M1 M0 VCC crcerrn hdc ldcn prgmn M3 M2 M1 M0 crcerrn hdc ldcn VCC SP00670 Figure 27. Daisy-chain Schematic with lead device in master parallel 1999 Apr 16 24 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N VCC cclk cclk din dout VCC pgrmn resetn reset/OE dout dout VCC pgrmn resetn SLAVE #2 crcerrn done VCC M3 M2 M1 M0 hdc pgrmn resetn done VCC M3 M2 M1 M0 din SLAVE #1 done VCC cclk din MASTER SERIAL LEAD EEPROM CE cclk dout crcerrn hdc M3 M2 M1 M0 crcerrn hdc SP00665 Figure 28. Daisy Chain Schematic with Master Serial Lead Device The Philips PZ3320's JTAG interface includes a TAP Port and a TAP Controller, both of which are defined by the IEEE 1149.1 JTAG Specification. As implemented in the Philips PZ3320, the TAP Port includes five pins (refer to Table 11) described in the JTAG specification: tck, tms, tdi, tdo, and trstn. These pins should be connected to an external pull-up resistor to keep the JTAG signals from floating when they are not being used. JTAG Testing Capability JTAG is the commonly-used acronym for the Boundary Scan Test (BST) feature defined for integrated circuits by IEEE Standard 1149.1. This standard defines input/output pins, logic control functions, and commands which facilitate both board and device level testing without the use of specialized test equipment. BST provides the ability to test the external connections of a device, test the internal logic of the device, and capture data from the device during normal operation. BST provides a number of benefits in each of the following areas: Table 12 defines the dedicated pins used by the mandatory JTAG signals for the PZ3320. * Testability The JTAG specifications define two sets of commands to support boundary-scan testing: high-level commands and low-level commands. High-level commands are executed via board test software on an a user test station such as automated test equipment, a PC, or an engineering workstation (EWS). Each high-level command comprises a sequence of low level commands. These low-level commands are executed within the component under test, and therefore must be implemented as part of the TAP Controller design. The set of low-level boundary-scan commands implemented in the PZ3320 is defined in Table 13. By supporting this set of low-level commands, the PZ3320 allows execution of all high-level boundary-scan commands. - Allows testing of an unlimited number of interconnects on the printed circuit board - Testability is designed in at the component level - Enables desired signal levels to be set at specific pins (Preload) - Data from pin or core logic signals can be examined during normal operation * Reliability - Eliminates physical contacts common to existing test fixtures (e.g., "bed-of-nails") - Degradation of test equipment is no longer a concern - Facilitates the handling of smaller, surface-mount components - Allows for testing when components exist on both sides of the printed circuit board * Cost - Reduces/eliminates the need for expensive test equipment - Reduces test preparation time - Reduces spare board inventories 1999 Apr 16 25 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N Table 11. JTAG Pin Description PIN NAME DESCRIPTION tck Test Clock Output Clock pin to shift the serial data and instructions in and out of the tdi and tdo pins, respectively. tck is also used to clock the TAP Controller state machine. tms Test Mode Select Serial input pin selects the JTAG instruction mode. tms should be driven high during user mode operation. tdi Test Data Input Serial input pin for instructions and test data. Data is shifted in on the rising edge of tck. tdo Test Data Output Serial output pin for instructions and test data. Data is shifted out on the falling edge of tck. The signal is tri-stated if data is not being shifted out of the device. trstn Test Reset Forces TAP controller to test logic reset state. This signal is active low. Table 12. PZ3320 JTAG Pinout by Package Type (PIN NUMBER / MACROCELL #) DEVICE PZ3320 256 pin PBGA 160 pin LQFP tck tms tdi tdo trstn V4 41 W4 43 U5 42 Y4 44 L18 97 Table 13. PZ3320 Low-Level JTAG Boundary-Scan Commands INSTRUCTION (Instruction Code) Register Used DESCRIPTION SAMPLE/PRELOAD (00010) Boundary-Scan Register The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal operation of the component to be taken and examined. It also allows data values to be loaded onto the latched parallel outputs of the Boundary-Scan Shift-Register prior to selection of the other boundary-scan test instructions. EXTEST (00000) Boundary-Scan Register The mandatory EXTEST instruction allows testing of off-chip circuitry and board level interconnections. Data would typically be loaded onto the latched parallel outputs of Boundary-Scan Shift-Register using the SAMPLE/PRELOAD instruction prior to selection of the EXTEST instruction. BYPASS (11111) Bypass Register Places the 1 bit bypass register between the tdi and tdo pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation. The BYPASS instruction can be entered by holding tdi at a constant high value and completing an Instruction-Scan cycle. IDCODE (00001) Boundary-Scan Register Selects the IDCODE register and places it between tdi and tdo, allowing the IDCODE to be serially shifted out of tdo. The IDCODE instruction permits blind interrogation of the components assembled onto a printed circuit board. Thus, in circumstances where the component population may vary, it is possible to determine what components exist in a product. HIGHZ (00101) Bypass Register The HIGHZ instruction places the component in a state in which all of its system logic outputs are placed in an inactive drive state (e.g., high impedance). In this state, an in-circuit test system may drive signals onto the connections normally driven by a component output without incurring the risk of damage to the component. The HIGHZ instruction also forces the Bypass Register between tdi and tdo. INTEST (00011) Boundary-Scan Register The INTEST instruction allows testing of the on-chip system logic while the component is assembled on the board. The boundary-scan register is connected between TDI and TDO. Using the INTEST instruction, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the boundary-scan register and are examined by subsequent shifting, Data would typically be loaded onto the latched parallel outputs of boundary-scan shift-register stages using the SAMPLE/PRELOAD instruction prior to selection of the INTEST instruction. NOTE: Following use of the INTEST instruction, the on-chip system logic may be in an indeterminate state that will persist until a system reset is applied. Therefore, the on-chip system logic may need to be reset on return or normal (i.e., nontest) operation. 1999 Apr 16 26 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N TCK tS tH tCH tCL TMS TDI tD TDO SP00613 Figure 29. Boundary Scan Timing Diagram Table 14. Boundary scan timing characteristics SYMBOL MIN MAX UNIT tS tdi/tms to tck setup time PARAMETER 20 - ns tH tdi/tms from tck hold time 0 - ns tCH tck high time 50 - ns tCL tck low time 50 - ns fTCK tck frequency - 10 MHz tD tck to tdo delay - 35 ns and DC specification for configuring the device through the JTAG port. DEVICE CONFIGURATION THROUGH JTAG In addition to the normal configuration modes, the PZ3320 can also be configured through the JTAG port. This feature is very useful for design prototyping and debug before the device is put into the final product. In System Configuration of the PZ3320 is supported by Philips Semiconductors' PC-ISP software. Table 15 shows the ISC commands supported by the PZ3320, and Table 16 details the AC To configure the device through the JTAG port, mode pins M0, M1, and M2 should all be held low. M3, as always, should be high and the JTAG pins should be terminated as described in the Terminations section of this data sheet. Table 15. Low Level ISP Commands INSTRUCTION (Register Used) INSTRUCTION CODE Enable (ISP Shift Register) 1001 Enables the Erase, Program, and Verify commands. Using the ENABLE instruction before the Erase, Program, and Verify instructions allows the user to specify the outputs the device using the JTAG Boundary-Scan SAMPLE/PRELOAD command. Erase (ISP Shift Register) 1010 Erases the entire EEPROM array. The outputs during this operation can be defined by user by using the JTAG SAMPLE/PRELOAD command. Program (ISP Shift Register) 1011 Programs the data in the ISP Shift Register into the addressed EEPROM row. The outputs during this operation can be defined by user by using the JTAG SAMPLE/PRELOAD command. Verify (ISP Shift Register) 1100 Transfers the data from the addressed row to the ISP Shift Register. The data can then be shifted out and compared with the JEDEC file. The outputs during this operation can be defined by the user. 1999 Apr 16 DESCRIPTION 27 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N Table 16. Programming Specifications SYMBOL PARAMETER MIN. MAX UNIT DC Parameters VCCP VCC supply program/verify ICCP ICC limit program/verify V VIH Input voltage (High) V VIL Input voltage (Low) V VSOL Output voltage (Low) V VSOH Output voltage (High) V TDO_IOL Output current (Low) mA TDO_IOH Output current (High) mA mA AC Parameters fMAX TCK maximum frequency PWE Pulse width erase MHz ms PWP Pulse width program ms PWV Pulse width verify s INIT Initialization time s TMS_SU TMS setup time before TCK ns TDI_SU TDI setup time before TCK ns TMS_H TMS hold time after TCK ns TDI_H TDI hold time after TCK ns TDO_CO TDO valid after TCK ns ABSOLUTE MAXIMUM RATINGS1 SYMBOL MIN MAX UNIT VDD Supply voltage PARAMETER -0.5 4.6 V VIN Input voltage -1.2 5.75 V VOUT Output voltage -0.5 VDD+0.5 V IIN Input current -30 30 mA TJ Junction temperature range -40 150 C TSTG Storage temperature range -65 150 C NOTE: 1. Stresses above these listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. OPERATING RANGE PRODUCT GRADE TEMPERATURE VOLTAGE Commercial 0 to 70_C 3.3 10% V Industrial -40 to 85_C 3.3 10% V 1999 Apr 16 28 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES Commercial temperature range: VDD = 3.0V to 3.6V; 0C < Tamb < 70C SYMBOL PARAMETER TEST CONDITIONS VIH Input high voltage VIL Input low voltage VOH Output high voltage IOH = -8mA VOL Output low voltage IOL = 8mA II Input leakage current VI = 0 or 5.5 V IDDSB Standby current CIN CIO MIN MAX UNIT 2.0 5.5 V -0.3 0.8 V 2.4 - V - 0.4 V -10 10 A Tamb = 25C; no output loads, inputs at VDD or VSS. - 100 A Input capacitance Tamb = 25C; VDD = 3.3V; f = 1MHz - 10 pF I/O capacitance Tamb = 25C; VDD = 3.3V; f = 1MHz - 10 pF CCLK Clock pin capacitance Tamb = 25C; VDD = 3.3V; f = 1MHz - 12 pF RDONE done pull-up resistor VDD = 3.0 V; VIN = 0 V 5 20 k RPD Unused I/O pull-down resistor VDD = 3.6V; VIN = VDD 100 400 k IOZH Input leakage VIN = 5.5 V or 3.6 V -10 10 A IOZL Input leakage VIN = 0.0 V -10 10 A 1999 Apr 16 29 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES Commercial temperature range: VDD = 3.0V to 3.6V; 0C < Tamb < 70C C7 SYMBOL PARAMETER MIN C10 MAX MIN MAX UNIT Timing requirements tCL Clock LOW time 2.5 3.0 ns tCH Clock HIGH time 2.5 3.0 ns tSU_PAL PAL setup time (Global clock) 3.0 4.0 ns tSU_PLA PLA setup time (Global clock) 4.5 5.5 ns tSU_XOR XOR setup time (Global clock) 5.5 tH Hold time (Global clock) 6.5 ns 0 0 ns 7.5 10.0 ns Output characteristics tPD_PAL Input to output delay through PAL tPD_PLA Input to output delay through PLA 9.0 11.5 ns tPD_XOR Input to output delay through XOR 10.0 12.5 ns tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL 4.5 6.0 ns tPDF_PLA Input (or feedback node) to internal feedback node delay time through PLA 6.0 7.5 ns tPDF_XOR Input (or feedback node) to internal feedback node delay time through XOR 7.0 8.5 ns tCF Global clock to feedback delay 3.0 3.5 ns tCO Global clock to out delay 6.0 7.5 ns tCS Clock skew (variance for switching outputs with common global clock) 1.0 1.5 ns fMAX1 Maximum flip-flop toggle rate fMAX2 Maximum internal frequency fMAX3 Maximum external frequency tBUFF Output buffer delay (fast) tSSR Slow slew rate incremental delay tEA Output enable delay tER Output disable delay1 tGTSA tGTSR 1 t CL ) t CH 200 166 MHz 1 t SU_PAL ) t CF 166 133 MHz 1 t SU_PAL ) t CO 111 87 MHz 3.0 4.0 ns 5.0 6.0 ns 10.0 12.0 ns 10.0 12.0 ns Global 3-State enable 10.0 12.0 ns Global 3-State disable 10.0 12.0 ns tRR Input to register reset 10.5 12.0 ns tRP Input to register preset 9.5 11.0 ns tGRR Global reset to register reset 10 12.0 ns tGZIA Global ZIA delay 2.0 2.5 ns NOTE: 1. Output CL = 5.0pF. 1999 Apr 16 30 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES Industrial temperature range: VDD = 3.0V to 3.6V; -40C < Tamb < 85C SYMBOL PARAMETER TEST CONDITIONS VIH Input high voltage VIL Input low voltage VOH Output high voltage IOH = -8mA VOL Output low voltage IOL = 8mA II Input leakage current VI = 0 or 5.5 V IDDSB Standby current CIN CIO MIN MAX UNIT 2.0 5.5 V -0.3 0.8 V 2.4 - V - 0.4 V -10 10 A Tamb = 25C; no output loads, inputs at VDD or VSS. - 100 A Input capacitance Tamb = 25C; VDD = 3.3V; f = 1MHz - 10 pF I/O capacitance Tamb = 25C; VDD = 3.3V; f = 1MHz - 10 pF CCLK Clock pin capacitance Tamb = 25C; VDD = 3.3V; f = 1MHz - 12 pF RDONE done pull-up resistor VDD = 3.0 V; VIN = 0 V 5 20 k RPD Unused I/O pull-down resistor VDD = 3.6V; VIN = VDD 100 400 k IOZH Input leakage VIN = 5.5 V or 3.6 V -10 10 A IOZL Input leakage VIN = 0.0 V -10 10 A 1999 Apr 16 31 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N AC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES Industrial temperature range: VDD = 3.0V to 3.6V; -40C < Tamb < 85C N8 SYMBOL PARAMETER MIN MAX UNIT Timing requirements tCL Clock LOW time 2.5 ns tCH Clock HIGH time 2.5 ns tSU_PAL PAL setup time (Global clock) 3.5 ns tSU_PLA PLA setup time (Global clock) 5.0 ns tSU_XOR XOR setup time (Global clock) 6.0 tH Hold time (Global clock) ns 0 ns Output characteristics tPD_PAL Input to output delay through PAL 8.5 ns tPD_PLA Input to output delay through PLA 10 ns tPD_XOR Input to output delay through XOR 11 ns tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL 5.0 ns tPDF_PLA Input (or feedback node) to internal feedback node delay time through PLA 6.5 ns tPDF_XOR Input (or feedback node) to internal feedback node delay time through XOR 7.5 ns tCF Global clock to feedback delay 3.5 ns tCO Global clock to out delay 7.0 ns tCS Clock skew (variance for switching outputs with common global clock) 1.0 ns fMAX1 Maximum flip-flop toggle rate fMAX2 Maximum internal frequency fMAX3 Maximum external frequency tBUFF Output buffer delay (fast) tSSR tEA 1 t CL ) t CH 200 MHz 1 t SU_PAL ) t CF 143 MHz 1 t SU_PAL ) t CO 95 MHz 3.5 ns Slow slew rate incremental delay 5.5 ns Output enable delay 11.0 ns tER Output disable delay1 11.0 ns tGTSA Global 3-State enable 11.0 ns tGTSR Global 3-State disable 11.0 ns tRR Input to register reset 11.5 ns tRP Input to register preset 10.0 ns tGRR Global reset to register reset 11 ns tGZIA Global ZIA delay 2.5 ns NOTE: 1. Output CL = 5.0pF. 1999 Apr 16 32 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N THEVENIN EQUIVALENT VL = 0.5 VDD 200 DUT OUTPUT 25pF SP00629 VOLTAGE WAVEFORM +3.0V 90% 10% 0V tR tF 2.0 ns 2.0 ns SP00630 MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses 1999 Apr 16 33 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N PINNING 256-pin Plastic Ball Grid Array (PBGA) A1 BALL PAD CORNER 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y BOTTOM VIEW SP00671 1999 Apr 16 34 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N Pin Functions Function is Fast Module_Logic block_Macrocell. For example, F1_0_5 means Fast Module 1, Logic block 0, Macrocell 5. Pkg Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Function GND F0_2_11 F0_2_9 cclk F0_2_5* F0_2_2* F0_3_0 F0_3_3 F0_3_6 F0_3_9 F0_3_10 F1_1_10 F1_1_7 F1_1_4 F1_1_1 F1_0_1 F1_0_4 F1_0_8 F1_0_10 F1_0_11 Pkg Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 Function F0_0_9 F0_0_10 GND pgrm F0_2_7 F0_2_4 F0_2_1 F0_3_1 FO_3_4 F0_3_7 F1_1_11 F1_1_8 F1_1_5* F1_1_2 F1_0_0 F1_0_3 F1_0_7 GND F1_2_10 F1_2_9 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 F0_0_11 GND F0_2_10 resetn F0_2_6 F0_2_3 F0_2_0* F0_3_2 F0_3_5 F0_3_8 F0_3_11 F1_1_9 F1_1_6* F1_1_3 F1_1_0 F1_0_2 F1_0_5* F1_0_9 GND F1_2_11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 F0_0_6* F0_0_7 F0_0_8 GND F0_2_8 done VCC VCC GND VCC VCC GND VCC VCC VCC F1_0_6 GND F1_2_8 F1_2_7 F1_2_6* Pkg Ball E1 E2 E3 E4 E17 E18 E19 E20 Function F0_0_2* F0_0_3 F0_0_4* F0_0_5 F1_2_5 F1_2_4 F1_2_3 F1_2_2 Pkg Ball L1 L2 L3 L4 L17 L18 L19 L20 Function clk_3 gts GND VCC VCC trstn GND CLK_7 F1 F2 F3 F4 F17 F18 F19 F20 F0_1_1 F0_1_0* F0_0_0* F0_0_1 F1_2_1 F1_2_0 F1_3_0 F1_3_1 M1 M2 M3 M4 M17 M18 M19 M20 F3_3_11 F3_3_10 F3_3_9 GND GND F2_1_9 F2_1_10 F2_1_11 G1 G2 G3 G4 G17 G18 G19 G20 F0_1_4* F0_1_3 F0_1_2* VCC VCC F1_3_2* F1_3_3 F1_3_4* N1 N2 N3 N4 N17 N18 N19 N20 F3_3_8 F3_3_7 F3_3_6 F3_3_5* F2_1_5* F2_1_6 F2_1_7 F2_1_8 H1 H2 H3 H4 H17 H18 H19 H20 F0_1_8 F0_1_7 F0_1_6 F0_1_5 F1_3_5 F1_3_6 F1_3_7 F1_3_8 P1 P2 P3 P4 P17 P18 P19 P20 F3_3_4 F3_3_3* F3_3_2 VCC VCC F2_1_2 F2_1_3* F2_1_4 J1 J2 J3 J4 J17 J18 J19 J20 F0_1_11 F0_1_10 F0_1_9 GND GND F1_3_9 F1_3_10 F1_3_11 R1 R2 R3 R4 R17 R18 R19 R20 F3_3_1* F3_3_0 F3_2_0 F3_2_1* F2_0_1* F2_0_0 F2_1_0 F2_1_1* K1 K2 K3 K4 K17 K18 K19 K20 clk_2 clk_1 clk_0 VCC VCC clk_4 clk_5 clk_6 T1 T2 T3 T4 T17 T18 T19 T20 F3_2_2 F3_2_3* F3_2_4 F3_2_5 F2_0_5 F2_0_4 F2_0_3* F2_0_2 *Represents multi-function pins 1999 Apr 16 35 Pkg Ball U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 Function F3_2_6* F3_2_7 F3_2_8 GND tdi VCC VCC VCC GND VCC VCC GND VCC VCC F2_2_6 F2_2_8 GND F2_0_8 F2_0_7 F2_0_6* Pkg Ball W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Function F3_2_11 GND F3_0_9 tms F3_0_6 F3_0_3 F3_0_0* F3_1_2 F3_1_5 F3_1_8 F3_1_11 F2_3_9 F2_3_6* F2_3_3* F2_3_0 F2_2_2* F2_2_5* F2_2_10 GND F2_0_11 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 F3_2_9 F3_2_10 GND tck F3_0_7 F3_0_4* F3_0_1 F3_1_1 F3_1_4* F3_1_7 F2_3_11 F2_3_8 F2_3_5* F2_3_2 F2_2_0* F2_2_3 F2_2_7 GND F2_0_10 F2_0_9 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 F3_0_11 F3_0_10 F3_0_8 tdo F3_0_5* F3_0_2* F3_1_0* F3_1_3 F3_1_6 F3_1_9 F3_1_10 F2_3_10 F2_3_7 F2_3_4 F2_3_1* F2_2_1 F2_2_4 F2_2_9 F2_2_11 GND Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N Table 17. Pin Description SYMBOL PIN NUMBER TYPE VDD D7, D8, D10, D11, D13, D14, D15, G4, G17, K4, K17, L4, L17, P4, P17, U6, U7, U8, U10, U11, U13, U14 - Positive power supply. GND A1, B2, B19, C3, C18, D4, D9, D12, D17, J4, J17, L3, L19, M4, M17, U4, U9, U12, U17, V3, V18, W2, W19, Y20 - Ground supply. resetn B4 I During configuration, resetn forces the start of initialization. After configuration, resetn is a direct input which can be used to asynchronously reset all the flip-flops. If the global reset is not being used, this pin should be pulled high. If the rise time of the prgmn signal is greater than 1 microsecond, this signal must be held low until prgmn is high. cclk A4 I/O In the master modes, cclk is an output which strobes configuration data in. In the slave or synchronous peripheral mode, cclk is an input synchronous with the data on din or D[7:0]. After configuration, this pin should be pulled low. done D6 I/O done is a bi-directional signal with a weak pull-up resistor attached. As an output, done pulling high indicates configuration is complete. As an input, a low level on done will delay the enabling of user I/O. If only one device is used, this pin can be left floating. If multiple devices are daisy chained, an external pull-up should be used. prgmn C4 I prgmn is an active-low input that forces the restart of configuration and initialization and resets the boundary-scan circuitry. After configuration, the pin should be pulled high. This signal must have a rise time less than 1 microsecond. If the rise time of this signal is greater than 1 microsecond, resetn must be held low until prgmn is high. spmi Y5 O Special purpose configuration pin that must be left floating during configuration for all configuration modes. After configuration the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. mpmi W13 O Special purpose configuration pin that must be left floating during configuration for all configuration modes. After configuration the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. din E1 I During slave serial or master serial configuration modes, din accepts serial configuration data synchronous with cclk. During parallel configuration modes, din is the D[0] input. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. M2 N17 I M0 G18 M1 G20 M2/M1/M0 are used to select the configuration mode. After configuration, the pins are user-programmable bl I/O I/O, and d no external t l ttermination i ti iis required. i d S See th the section ti on tterminations i ti for more information information. M3 A6 I M3 should be pulled high during configuration for all configuration modes. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. tdi tdo tck tms trstn U5 Y4 V4 W4 L18 I O I I I Test Data In, Test Data Out, Test Clock, Test Mode Select, Test Reset are dedicated pins for boundary-scan through the JTAG port. If JTAG is not being used, tdi, tck, tms, and trstn should be terminated with a weak pull-up resistor. tdo can be left unterminated. See section on terminations for more information. hdc B7 O High During Configuration (hdc) is output high when the PZ3320 is in the configuration state. hdc is used as a control output indicating that configuration is in progress. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. ldcn V9 O Low During Configuration (ldcn) is output low when the PZ3320 is in the configuration state. ldcn is used as a control output indicating that configuration is in progress. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. 1999 Apr 16 DESCRIPTION 36 Philips Semiconductors Product specification 320 macrocell SRAM CPLD SYMBOL PZ3320C/PZ3320N PIN NUMBER TYPE crcerrn C13 I/O crcerrn goes low when the PZ3320 detects a CRC error or an invalid peramble during configuration. The PZ3320 that detected the error will go into the initialization state and will not resume configuration until prgmn and resetn are both high. Once configuration has resumed crcerrn will go high. During configuration, an internal pull-up is enabled. If only one device is used, this pin can be left floating. If multiple devices are daisy chained, an external pull-up should be used. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. gts L2 I Global 3-State is an active-high dedicated input used to 3-state the I/Os and activate the internal pull-down resistors. If this feature is not used, the pin should be pulled low. cs0n cs1 wrn B17 W17 B13 I cs0n/cs1/wrn are used in the peripheral configuration mode. The PZ3320 is selected when cs0n and wrn are low and cs1 is high. After configuration, these pins are user-programmable I/O. cs0N and wrn require no external termination. See the section on terminations for more information. If cs1 is not used as an I/O after configuration in synchronous peripheral mode, the tristate property should be used to disable the internal pull-down resistor. See the section on synchronous peripheral configuration for more information. A[19:0] N4, P2, R1, R4, T2, P19, U1, V6, Y6, W7, Y7, V13, W14, Y15, V15, W16, U20, T19, R17, R20 O In the master parallel configuration mode, A[19:0] address the configuration EEPROM. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. D[7:0] G1, A5, G3, D1, F2, F3, E3, E1 I During master parallel, peripheral, and slave parallel configuration modes, D[7:0] receive configuration data. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. dout D20 O During configuration, dout is the serial data out that is used to drive the din of daisy-chained slave devices. Data on dout changes on the falling edge of cclk. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. 1999 Apr 16 DESCRIPTION 37 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N PZ3320 - 160-Pin Plastic Low Profile Quad Flat Package 160 121 120 1 LQFP 40 81 41 80 SP00672 Pin Functions Function is Fast Module_Logic block_Macrocell. For example, F1_0_5 means Fast Module 1, Logic block 0, Macrocell 5. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Function F0_0_6* F0_0_5 F0_0_4* F0_0_3 F0_0_2* F0_0_1 F0_0_0* GND F0_1_0* F0_1_1 F0_1_2* F0_1_3 F0_1_4* F0_1_5 VCC F0_1_6 GND clk_0 clk_1 clk_2 clk_3 gts VCC GND F3_3_6 F3_3_5* F3_3_4 F3_3_3* F3_3_2 F3_3_1* F3_3_0 GND Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Function F3_2_0 F3_2_1* F3_2_2 F3_2_3* F3_2_4 F3_2_5 F3_2_6* VCC TCK TDI TMS TDO F3_0_6 F3_0_5* GND F3_0_4* F3_0_3 F3_0_2* F3_0_1 F3_0_0* VCC F3_1_0* F3_1_1 F3_1_2 F3_1_3 F3_1_4* F3_1_5 GND F3_1_6 VCC F2_3_6* GND Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Function F2_3_5* F2_3_4 F2_3_4* F2_3_2 F2_3_1* F2_3_0 VCC F2_2_0* F2_2_1 F2_2_2* F2_2_3 F2_2_4 GND F2_2_5* F2_2_6 VCC VCC F2_0_6* F2_0_5 F2_0_4 F2_0_3* F2_0_2 F2_0_1* F2_0_0 GND F2_1_0 F2_1_1* F2_1_2 F2_1_3* F2_1_4 F2_1_5* F2_1_6 *Represents multi-function pins 1999 Apr 16 38 Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Function TRSTN GND VCC CLK_7 CLK_6 CLK_5 CLK_4 GND F1_3_6 VCC F1_3_5 F1_3_4* F1_3_3 F1_3_2* F1_3_1 F1_3_0 GND F1_2_0 F1_2_1 F1_2_2 F1_2_3 F1_2_4 F1_2_5 F1_2_6* VCC F1_0_6 F1_0_5* GND F1_0_4 F1_0_3 F1_0_2 F1_0_1 Pin 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Function F1_0_0 VCC F1_1_0 F1_1_1 F1_1_2 F1_1_3 F1_1_4 F1_1_5* GND F1_1_6* VCC F0_3_6 GND F0_3_5 F0_3_4 F0_3_3 F0_3_2 F0_3_1 F0_3_0 VCC F0_2_0* F0_2_1 F0_2_2* F0_2_3 F0_2_4 GND F0_2_5* F0_2_6 CCLK DONE RESETN PGRM Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N Table 18. Pin Description SYMBOL PIN NUMBER TYPE VDD 15, 23, 40, 53, 62, 71, 80, 81, 99, 106, 121, 130, 139, 148 - Positive power supply. GND 8, 17, 24, 32, 47, 60, 64, 77, 89, 98, 104, 113, 124, 137, 141, 154 - Ground supply. resetn 159 I During configuration, resetn forces the start of initialization. After configuration, resetn is a direct input which can be used to asynchronously reset all the flip-flops. If the global reset is not being used, this pin should be pulled high. If the rise time of the prgmn signal is greater than 1 microsecond, this signal must be held low until prgmn is high. cclk 157 I/O In the master modes, cclk is an output which strobes configuration data in. In the slave or synchronous peripheral mode, cclk is an input synchronous with the data on din or D[7:0]. After configuration, this pin should be pulled low. done 158 I/O done is a bi-directional signal with a weak pull-up resistor attached. As an output, done pulling high indicates configuration is complete. As an input, a low level on done will delay the enabling of user I/O. If only one device is used, this pin can be left floating. If multiple devices are daisy chained, an external pull-up should be used. prgmn 160 I prgmn is an active-low input that forces the restart of configuration and initialization and resets the boundary-scan circuitry. After configuration, the pin should be pulled high. This signal must have a rise time less than 1 microsecond. If the rise time of this signal is greater than 1 microsecond, resetn must be held low until prgmn is high. spmi 46 O Special purpose configuration pin that must be left floating during configuration for all configuration modes. After configuration the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. mpmi 63 O Special purpose configuration pin that must be left floating during configuration for all configuration modes. After configuration the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. din 5 I During slave serial or master serial configuration modes, din accepts serial configuration data synchronous with cclk. During parallel configuration modes, din is the D[0] input. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. M2 95 I M0 110 M1 108 M2/M1/M0 are used to select the configuration mode. After configuration, the pins are user-programmable bl I/O I/O, and d no external t l ttermination i ti iis required. i d S See th the section ti on tterminations i ti for more information information. M3 151 I M3 should be pulled high during configuration for all configuration modes. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. tdi tdo tck tms trstn 42 44 41 43 97 I O I I I Test Data In, Test Data Out, Test Clock, Test Mode Select, Test Reset are dedicated pins for boundary-scan through the JTAG port. If JTAG is not being used, tdi, tck, tms, and trstn should be terminated with a weak pull-up resistor. tdo can be left unterminated. See section on terminations for more information. hdc 149 O High During Configuration (hdc) is output high when the PZ3320 is in the configuration state. hdc is used as a control output indicating that configuration is in progress. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. ldcn 58 O Low During Configuration (ldcn) is output low when the PZ3320 is in the configuration state. ldcn is used as a control output indicating that configuration is in progress. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. crcerrn 136 I/O crcerrn goes low when the PZ3320 detects a CRC error or an invalid peramble during configuration. The PZ3320 that detected the error will go into the initialization state and will not resume configuration until prgmn and resetn are both high. Once configuration has resumed crcerrn will go high. During configuration, an internal pull-up is enabled. If only one device is used, this pin can be left floating. If multiple devices are daisy chained, an external pull-up should be used. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. 1999 Apr 16 DESCRIPTION 39 Philips Semiconductors Product specification 320 macrocell SRAM CPLD SYMBOL PZ3320C/PZ3320N PIN NUMBER TYPE gts 22 I Global 3-State is an active-high dedicated input used to 3-state the I/Os and activate the internal pull-down resistors. If this feature is not used, the pin should be pulled low. cs0n cs1 wrn 123 78 138 I cs0n/cs1/wrn are used in the peripheral configuration mode. The PZ3320 is selected when cs0n and wrn are low and cs1 is high. After configuration, these pins are user-programmable I/O. cs0N and wrn require no external termination. See the section on terminations for more information. If cs1 is not used as an I/O after configuration in synchronous peripheral mode, the tristate property should be used to disable the internal pull-down resistor. See the section on synchronous peripheral configuration for more information. A[19:0] 26, 28, 30, 34, 36, 93, 39, 48, 50, 52, 54, 65, 67, 69, 72, 74, 82, 85, 87, 91 O In the master parallel configuration mode, A[19:0] address the configuration EEPROM. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. D[7:0] 13, 155, 11, 1, 9, 7, 3, 5 I During master parallel, peripheral, and slave parallel configuration modes, D[7:0] receive configuration data. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. dout 120 O During configuration, dout is the serial data out that is used to drive the din of daisy-chained slave devices. Data on dout changes on the falling edge of cclk. After configuration, the pin is a user-programmable I/O, and no external termination is required. See the section on terminations for more information. 1999 Apr 16 DESCRIPTION 40 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N BGA256: plastic ball grid array package; 256 balls; body 27 x 27 x 1.55 mm 1999 Apr 16 41 SOT471-1 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N LQFP160: plastic low profile quad flat package; 160 leads; body 24 x 24 x 1.4 mm 1999 Apr 16 42 SOT435-1 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N NOTES 1999 Apr 16 43 Philips Semiconductors Product specification 320 macrocell SRAM CPLD PZ3320C/PZ3320N Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Date of release: 04-99 Document order number: 1999 Apr 16 44 9397 750 05502