Alt er a Cor pora t ion 1
FLEX 10KE
Embedded Programmable
Logic Device
Jan uary 2003, ver. 2.5 Data Sheet
DS-F10KE-2.5
®
Features... ■Embedded programmable logic devices (PLDs), providing
system-on-a-programmable-chip (SOPC) integration in a single
device
– Enhanced embe dded array for imp l ementing megafuncti o ns
such as efficient memory and specialized logic functions
– Dual-port capability with up to 16-bit width per embedded array
block (EAB)
– Logic a rray for general logic functions
■High density
– 30,000 to 200,000 typical gates (see Tables 1 and 2)
– Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be
used with out red ucin g logi c capacity
■System-le vel features
– MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V de vice s
– Low power consumption
– Bidire ctio nal I/ O performance (tSU and tCO) up to 212 MHz
– Fully compliant with the PCI Special Interest Group (PCI SIG)
PCI Local Bus Specification, Revision 2.2 for 3. 3-V ope r ation at
33 MHz or 66 MHz
– -1 speed grade dev ices are comp lian t with PCI Local Bus
Specification, Revision 2.2, for 5.0-V operation
– Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) cir cuitry compliant with IEEE Std. 11 49.1-1990, available
without consuming additional device logic
fFor information on 5.0- V FLEX® 10K or 3.3-V FLEX 10KA devices, see the
FLEX 10K Embedded Programmable Logic Family Data Sheet.
Table 1. FLEX 10KE Device Features
Feature EPF10K30E EPF10K50E
EPF10K50S
Typical gates (1) 30,000 50,000
Maximum system gates 119,000 199,000
Logic ele m ent s (LE s) 1,72 8 2,88 0
EABs 6 10
Total RA M bits 24,576 40,960
Maximu m us er I/O pin s 220 254
2Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Note to ta bles:
(1) The embedded IEEE S td. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum
system gates.
(2) New E PF10K 100B designs sh ould use EPF10K 100E devices.
...and More
Features
– Fa bric a ted on an advanced pr ocess an d ope r ate with a 2.5-V
inte rnal supp ly voltage
– In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
– ClockLockTM a nd ClockBoostTM options for reduced clock
delay/skew and clock multiplication
– Built-in low-skew clock distribution trees
–100% functiona l te st ing of a ll device s; test vectors or scan cha ins
are not required
– Pull-up on I/O pins before and during configura tion
■F lexible interconnect
–FastTrack
® Interconnect continuous routing structure for fast,
predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
softw are tools and megafunctions)
– Dedicated cascade chain that implements high-speed,
high-fan-in logic functi ons (automat ically used by software tools
and megafunctions)
– Tri-state emulation that implements internal tri-state buses
– Up to six global clock signals and four global clear signals
■Powerful I/O pins
– Individual tri-state output enable control for each pin
– Open-drain option on each I/O pin
– Programmable output slew-rate control to reduce switching
noise
–Clamp to V
CCIO user-sel ectabl e on a pin-by -pin basis
– Supports hot-socketing
Tabl e 2. FLEX 10 KE Dev ic e Fea t ures
Feature EPF10K100E (2) EPF10K130E EPF10K200E
EPF10K200S
Typic al gat es (1) 100,000 130,000 200,000
Maxim um sys te m ga tes 257, 000 342,000 513 ,00 0
Logic elements (LEs) 4,992 6,656 9,984
EABs 12 16 24
Total R AM bits 49,1 52 65,53 6 98,304
Maxim um us er I/O pins 338 413 470
Altera Corporation 3
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
■Soft ware des ign sup port and automat ic place- and-rou te provi ded by
Altera’s development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800
■Flexible package options
– Ava ilable in a var iety of packag es with 144 to 6 72 pins, inclu ding
the innovative FineLine BGATM packa ge s ( see Tables 3 and 4)
–SameFrame
TM pin-out compatibility between FLEX 10KA and
FLEX 10KE devices across a range of device densiti es an d pin
counts
■Additi ona l design entry and simula tion support pr ovide d by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Design War e compone nts , Verilog HDL, VHDL, a nd othe r interfa ce s
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Men tor Graphics, OrCAD, Synopsys, Synplici ty,
VeriBes t, an d V i ew logic
Notes:
(1) FLEX 10KE device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat
pack (R QF P), pin-gri d array (PGA) , and bal l-g r id ar ray (BGA) pa cka ges.
(2) D ev i c es in the same pac k age are pin-comp at ib le, although so me devices h av e more I/O pins than ot h er s . Wh en
planning device migra tion, use the I/O pins that are common to all devices.
(3) Th is op t ion is supported with a 484-pin FineL i ne BG A package. B y us ing SameF rame pin migration, all
Fi ne Lin e BGA p ac ka ges a re pi n- com pat i bl e. Fo r e xam pl e, a b oar d ca n b e d es i gne d t o su pp or t 256 - pi n, 4 84- p in, an d
672-pin FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration
is set.
Table 3. FLEX 10KE Package O ptions & I/O Pin Count Notes (1), (2)
Device 144-Pin
TQFP 208-Pin
PQFP 240-Pin
PQFP
RQFP
256-Pin
FineLine
BGA
356-Pin
BGA 484-Pin
FineLine
BGA
599-Pin
PGA 600-Pin
BGA 672-Pin
FineLine
BGA
EPF10K30E 102 147 176 220 220 (3)
EPF10K50E 102 147 189 191 254 254 (3)
EPF10K50S 102 147 189 191 220 254 254 (3)
EPF10K100E 147 189 191 274 338 338 (3)
EPF10K130E 186 274 369 424 413
EPF10K200E 470 470 470
EPF10K200S 182 274 369 470 470 470
4Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
General
Description
Altera FLEX 10 KE devices are enhanced versions of FLEX 10K devices.
Based on reconfigurable CMOS SRAM elements, the FLEX architectur e
incorporates all features necessary to implement common gate array
megafunctions. With up to 200,000 typical gates, FLEX 10KE devices
provide the density, speed, and features to integrate entire systems,
including multiple 32-bit buses, into a single device.
The ability to reconfigure FLEX 10KE devices enables 100% testing prior
to shipment and allows the designer to focus on simulation and design
verification. FLEX 10KE reconfigurability eliminates inventory
manag ement for gate arr ay designs a nd gener ation of te st vector s for fault
coverage.
Table 5 shows FLEX 10KE performance for some common designs. All
performance values were obtained with Synopsys DesignWare or LPM
functions. Special design techniques are not requir ed to implement the
applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Table 4. FLEX 10KE Package Sizes
Device 144-
Pin
TQFP
208-Pin
PQFP 240-Pin
PQFP
RQFP
256-Pin
FineLine
BGA
356-
Pin
BGA
484-Pin
FineLine
BGA
599-Pin
PGA 600-
Pin
BGA
672-Pin
FineLine
BGA
Pitch (mm) 0.50 0.50 0.50 1.0 1.27 1.0 – 1.27 1.0
Area (mm2) 484 936 1,197 289 1,225 529 3,904 2,025 729
Length × wi dth
(mm × mm) 22 × 22 30.6 × 30.6 34.6 × 34.6 17 × 17 35 × 35 23 × 23 62.5 × 62.5 45 × 45 27 × 27
Altera Corporation 5
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Notes:
(1 ) Th is application uses combinat o r ial inputs and outputs.
(2) This application uses registered inputs and outputs.
Table 6 shows F L EX 1 0KE pe r for m anc e for mo re com pl ex designs. T he se
designs are available as Altera MegaCore® functions.
Note:
(1) These values are for calculation time. Calculation time = number of clocks required/fmax. Number of clocks
requir ed = ceilin g [lo g 2 (poin t s)/ 2] × [points +14 + ceiling]
Table 5. FLEX 10KE Performance
Applic ation Resourc es Used Perfo rmance Unit s
LEs EABs -1 Speed Grade -2 Speed Grade -3 Speed Grade
16-bit loadable counter 16 0 285 250 200 MHz
16-bit accumulator 16 0 285 250 200 MHz
16-to- 1 mu ltip lex er (1) 10 0 3.5 4.9 7.0 ns
16-bit multiplier with 3-stage
pipeline (2) 592 0 156 131 93 MHz
256 × 16 RAM read cycle
speed (2) 0 1 196 154 118 MHz
256 × 16 RAM wr ite cycle
speed (2) 0 1 185 143 106 MHz
Table 6. FLEX 10KE Performance for Complex Designs
Application LEs Used Performance Units
-1 Speed Grade -2 Speed Grade -3 Speed Grade
8-bit, 16-tap parallel finite impulse
resp onse (F IR) fi l te r 597 192 156 116 MSPS
8-bit, 512-point fast Fou rier
tran sfo r m (F FT) fu nc ti o n 1,854 23.4 28.7 38.9 µs (1)
113 92 68 MHz
a16450 universal async hronous
receiver/transmitter (UART) 342 36 28 20.5 MHz
6Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Similar to the FLEX 10KE architecture, embedded gate arrays are the
fastest- g row ing segment of th e g ate array mar k et . As with stand ard gat e
arrays, embedded gate arrays implement general logic in a conventional
“sea-of-gates” architecture. Additionally, embedded gate arrays have
dedicated die areas for implementing large, specialized functions. By
embedding functions in silicon, embedded gate arrays reduce die area
and increase speed when compare d to standard gate arrays. While
embedded megafunctions typically cannot be customized, FLEX 10KE
devices are programmable, providing the designer with full control over
embedded megafunctions a nd general logic, while facilitating iterative
desig n c hanges during debuggi ng.
Each FLEX 10KE device contains an embedded array and a logi c ar ray.
The em be dded array i s used to impl ement a var iety of memor y fu nctio ns
or complex logic functions, such as digital signal processing (DSP), wide
data-path manipulation, microcontroller applications, and data-
transformation functions. The logic array performs the same function as
the sea-of-gates in the gate array and is us ed to implemen t general logi c
such as counters, adders, state machine s, and multiplexers. The
combination of embedded and logic arrays provides the high
performan ce and hi gh densit y of emb edded gate arrays, enablin g
desi gn ers to implem e nt an ent i re sys te m on a single devic e.
FLEX 10KE devices are configured at system power-up with data stored
in an Altera serial configuration device or provided by a system
controller. Altera offers the EPC1, EPC2, and EPC16 configuration
devi ce s, whi ch configur e FLEX 10KE devices via a serial data stream.
Configurat ion d ata ca n a lso b e dow nloa ded fr om syste m RAM or via th e
Altera B it Bla st er TM, ByteB lasterMVTM, or MasterBlas te r dow nloa d cabl e s.
After a FLEX 10KE device has been configured, it can be reconfigured
in-circuit by resetting the device and loading new data. Because
reconfiguration requires less than 85 ms, real-time changes can be made
during system operation.
FLEX 10KE devices contain an interface that permits microprocessors to
configure FLEX 10KE d evices se ri ally or in-parallel, a nd synchrono usly or
asynchronously. The interface also enables microprocessors to treat a
FLEX 10KE device as memory and configure it by writing to a virtual
memory location, making it easy to reconfigure the device.
Altera Corporation 7
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
fFor more information on FLEX device configuration, see the following
documents:
■Configuration Devices for APEX & FLEX Devices Data Sheet
■BitBlaster Serial Download Cable Data Sheet
■ByteBlasterMV Parallel Port Download Cable Data Sheet
■MasterBlaster Download Cable Data Sheet
■Appl i cat i on Note 116 (Con f ig u r ing APEX 20K, F L EX 10K, & FL E X 60 00
Devices)
FLEX 10KE devices are supported by the Altera development systems,
which are integrated packages that offer sche matic, text (including
AHD L), and wavefo rm design entr y, compil ation and lo gi c synthesi s, full
simula tion and w orst-case timi ng ana lysis, and d evice con figuration . The
Alte ra software prov ides ED IF 2 0 0 and 3 0 0, LPM , VHDL, Ve rilog HDL,
and other interfaces for additional design entry and simulation support
from other indu stry-standard PC- and U NIX w o rkstation-base d EDA
tools.
The Altera software works easily with common gate array EDA tools for
synthesis and simulation. For example, the Altera software can generate
Verilog HDL files for simulation with tools such as Cadence Verilog-XL.
Additionally, the Altera software contains EDA libraries that use device-
specific features such as carry chains, which are used for fast counter and
arithme tic funct ions . Fo r insta nce , the Synop sy s Desig n Compiler libr ary
supplied with the Altera development system includes DesignWare
fu nct ions tha t are o ptimized fo r the FLEX 10K E ar chit ec tur e .
The Altera development system runs on Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800.
fSee the MAX+PLUS II Programmable Logic Development System & Software
Data Sheet and the Quartus Programmable Logic Development System &
Software Data Sheet for more information.
8Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Functional
Description
Each FLEX 10KE device contains an enhanced embedded array to
implement memory and specialized logic functions, and a logic array to
implement general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 4,096 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions, such as mult ipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
The logic array consists of logic array blocks (LABs). Each LAB contains
eight LEs and a local int erconnec t. An LE consists of a four-input look-up
table (LUT), a programmable flipflop, and dedicated signal paths for carry
and cascade functions. The eight LEs can be used to create medium-sized
blocks of logic—such as 8-bit counters, address decoders, or state
machines—or combined across LABs to create larger logic blocks. Each
LAB represents about 96 usable gates of logic.
Signal inte rconnect ions within FLEX 10KE devices (as well as to and from
device pin s) ar e provided by the Fas tT rac k Intercon nect routin g structur e,
which is a serie s of fast, continuous r ow and column ch annels that run th e
entire length and width of the dev ice.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect routing structure. Each IOE
contains a bidirectional I/O buffer and a flipflop that can be used as either
an output or input register to feed input, output, or bidirectional signals.
When used with a dedicated clock pin, these registers provide exceptional
performance. As inputs, they provide setup times as low as 0.9 ns and
hold times of 0 ns. As outputs, these registers provide clock-to-output
times as low as 3.0 ns. IOEs provide a variety of features, such as JTAG
BST support, sle w-rat e cont ro l, tri-s tate buf fers, and open-drain outp uts .
Altera Corporation 9
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 1 shows a block diagram of the FLEX 10KE architecture. Each
group of LE s is combine d i nto an L AB; grou ps of L ABs a re arra ng ed int o
rows and column s. Each row also co ntains a single EAB . The LABs and
EABs ar e in ter c onnected by the FastTr ac k In te rconne ct routing st ru cture.
IOEs are located at the end of each row and column of the FastTrack
Interconnect routing structure.
Figure 1. FLEX 10KE Device Bl ock Di agram
FLEX 10KE devices provide six dedicated inputs that drive the flipflops’
control inputs and ensure the efficient dist ribution of high-speed, low-
skew (less than 1.5 ns) control signals. These signals use dedicated routing
chan ne ls t hat provide s hor te r d ela ys an d lowe r sk ew s tha n t he Fa stTr ac k
Interconnect routing structure. Four of the dedicated inputs drive four
global signals. These four global sig nals can also be driven by internal
logic, providing an ideal solution for a clock divider or an internally
generat ed asynchro nous clear signal that clears many register s in the
device.
I/O Element
(IOE)
Logic Array
Block (LAB)
Row
Interconnect
IOEIOE
IOEIOE
IOE
IOE
IOE
Local Interconnec
t
IOEIOE
IOEIOE IOEIOE
IOEIOE
IOEIOE
Logic Element (LE
)
Column
Interconnect
IOE
EAB
EAB
Logic
Array
IOEIOE
IOEIOE IOEIOE
Embedded Array Block (EAB)
Embedded Array
IOE
IOE
Logic Array
IOE
IOE
10 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Embed ded A rray Bloc k
The EAB is a flexible block of RAM, wit h registers on the inpu t and output
ports, that is used to implement common gate array megafunctions.
Because it is large and flexible, the EAB is suitable for functions such as
multipliers, vector scalars, and error correction circuits. These functions
can be combined in applications such as digital filters and
microcontrollers.
Logic functions are implemented by programming the EAB with a read-
only patte rn during configuration, thereby creating a large LUT. With
LUTs, combinatorial functions are implemented by looking up the results,
rather than by computing them. This implementation of combinatorial
functions can be faster than using algorithms implemented in general
logic, a performan ce advanta ge that is furt her enhanc ed by the fast a ccess
times of EABs. The large capacity of EABs enables designers to implement
complex fun ctions in on e logic leve l without t he routin g delays as sociated
with linked LEs or field-programmable gate array (FPGA) RAM blocks.
For exam ple, a single EA B can imple ment any function with 8 inp uts an d
16 outputs. Parameterized functions such as LPM functions can take
advantage of the EAB automatically.
The FLEX 10KE EAB provides adva ntages over FPGAs, which implement
on-board RAM as arrays of small, distributed RAM blocks. These small
FPGA RAM blocks must be connected together to make RAM blocks of
manageable size. The RA M blocks ar e conne cted together us ing
multiplexers implemented with more logic blocks. These extra
multiple xers cause extra del ay, which slo ws down the RAM block . FPGA
RAM blocks are also prone to routing problems because small blocks of
RAM m ust be connec ted tog ether to m ake larger bl ocks. In co ntrast, E ABs
can be used to implement large, dedicated blocks of RAM that eliminate
th ese timing and routing con cerns.
The FLEX 10KE e nhanced EAB adds dual-p o rt capability to the existing
EAB structure. The dual-port structure is ideal for FIFO buffers with one
or two clocks. The FLEX 10KE EAB can also support up to 16-bit-wide
RAM blocks and is backward-compatible with any design containing
FLEX 10K EABs. The FLEX 10KE EAB can act in dual-port or single-port
mode. When in dual-port mode, separate clocks may be used for EAB read
and write sections, which allows the EAB to be written and read at
differ e nt rate s. It also has sep ar a te sy nch ro nous cloc k ena b le sig nals for
the EAB read and write sections, which allow independent control of
these s ections.
Altera Corporation 11
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
The EAB can also be used for bidirectional, dual-port memory
applications where two ports read or write simultaneously. To implement
this type of dual-port memory, two EABs are used to support two
simulta neous r ead or writes.
Alte rnat ivel y, one clock and clock en able ca n b e use d to con tr ol t he inp ut
registers of the EAB, while a different clock and clock enable cont rol the
out put r e gister s (see Figure 2).
Figure 2. FLEX 10KE Device in Dual-Port RAM Mode Notes (1)
Notes:
(1) All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
(2) EP F10K30E and E PF10K50E dev i c es ha ve 88 EA B local intercon ne ct chan n el s; EP F1 0K 100E, EPF10 K 130E, and
EPF10K200E devices have 104 EAB local interconnect channels.
Column Interconnect
E
AB Local
I
nterconnect (2)
Dedicated Clocks
24
D
ENA Q
D
ENA
Q
D
ENA Q
D
ENA Q
D
ENA
Q
data[ ]
rdaddress[ ]
wraddress[ ]
RAM/ROM
256 × 16
512 × 8
1,024 × 4
2,048 × 2
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out
4, 8, 16, 32
4, 8, 16, 32
outclocken
inclocken
inclock
outclock
D
ENA Q
Write
Pulse
Generator
rden
wren
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Row Interconnect
4, 8
Dedicated Inputs &
Global Signals
12 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
The EAB can also use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in Figure 3.
Figure 3. FLEX 10KE EAB in Dual-Port RAM Mode
The FLEX 10KE EAB can be used in a single-port mode, which is useful for
backward-compatibility with FLEX 10K designs (see Figure 4).
Port A Port B
address_a[] address_b[]
data_a[] data_b[]
we_a we_b
clkena_a clkena_b
Clock A Clock B
Altera Corporation 13
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Figure 4. FLEX 10KE Device in Single-Port RAM Mode
Note:
(1) EPF10K30E, EPF10K50E, and EPF10K50S devices have 88 EAB local interconnect channels; EPF10K100E,
EPF1 0K 130E, EPF1 0K 200E, and EPF10K200S dev ices h ave 104 EAB local interconnect chann els.
EABs can be us ed to imple ment sy nchronous RAM, wh ich is easie r to u se
than asynchronous RAM. A circuit using asynchronous RAM must
generate the RAM write enable signal, while ensuring that its data and
address signals meet setup and hold time specifications relative to the
write enable s ignal. I n contr ast, t he EAB’ s synchron ous RAM g enerates its
own write enable signal and is self-timed with respect to the input or write
clock . A circuit using the EAB’ s self-tim ed RAM must onl y meet the setup
and hold time specifications of the global clock.
Column Interconnect
EAB Local
Interconnect (1)
Dedicated Inputs
& Global Signals
DQ
DQ
RAM/ROM
256 × 16
512 × 8
1,024 × 4
2,048 × 2
Data In
Address
Write Enable
Data Out
4, 8, 16, 32
4, 8, 16, 32
DQ
DQ
4
8, 4, 2, 1
8, 9, 10, 11
Row Interconnect
Dedicated
Clocks
2
4, 8
Chip-Wide
Reset
14 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
When used as RAM, each EAB can be configured in any of the following
si zes: 256 ×16, 512 ×8, 1,024 ×4, or 2,048 ×2 (see Figure 5).
Fig ure 5. F LE X 10 KE EAB Memory Con figuratio ns
Larger blocks of RAM are created by combining multiple EABs. For
example, two 256 × 16 RAM blocks can be combined to form a 256 ×32
block; two 512 ×8 RAM blocks can be combi ned to for m a 512 ×16 block
(see Figure 6).
Figure 6. Examples of Combining FLEX 10KE EABs
If necessary, all EABs in a device can be cascaded to form a single RAM
block. EABs can be cascaded to form RAM blocks of up to 2,048 words
without impacting timin g. Th e Alte r a softw are aut om ati cally combines
EABs to me et a designer’s RAM specificati o ns.
256 × 16 512 × 8 1,024 × 4 2,048 × 2
512 × 8
512 × 8
256 × 16
256 × 16
256
×
32
512 × 16
Altera Corporation 15
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
EABs provide flexible options for driving and controlling clock signals.
Different clocks an d clock enables can be used for r ead ing and writing to
the EAB. Registers can be independently inserted on the data input, EAB
output, write address, write enable signals, read address, and read enable
sign als. The glo bal signal s and the EAB loc al intercon nect ca n drive write
enable, read enable, and clock enable signals. The global signals,
dedicated clock pins, and EAB local interconnect can drive the EAB clock
signals. Because the LEs driv e t he EAB local interconn ec t, the LEs can
control write enable, read enable, clear, clock, and clock enable signals.
An EAB is fed by a row in terconnect and can drive out to row and colu mn
inte rconnect s. Ea ch EAB ou tput ca n drive u p to two row channe ls and up
to two column channels; the unused row channe l can be driven by other
LEs. This feature increases the routing resources available for EAB
outpu ts (see Figures 2 and 4). T he c olumn int erc onne ct, which is adjac en t
to the EAB, has twice as many channels a s other columns in the device.
Logic Array Bloc k
An LAB consists of eight LEs, their associated ca rry and cascade chains,
LAB contr ol s i gnals, and the LA B l ocal interconnect. The LA B provides
the coarse-grained structure to the FLEX 10KE architecture, facilitating
efficient routing with optimum device utilization and high performance
(see Figure 7).
16 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 7. FLEX 10KE LAB
Notes:
(1) EPF 10K30E, EPF 10K 50E, and EPF 10K50S devices have 22 i np u ts to th e LA B local interconn ect channel from the
row; EPF10K100E, EPF10K130E, EPF10K200E, and EPF10K200S devices have 26.
(2) EPF 10K30E, EPF 10K 50E, and EPF 10K50S devices have 30 LAB local intercon n ec t chan n els; EPF10K 100E,
EPF10 K1 30E, E PF10K200E, an d EPF 10K 200S devic es ha ve 34.
2
8
Carry-In
&
Cascade-In
LE1
LE8
LE2
LE3
LE4
LE5
LE6
LE7
Column
Inter
connect
ter
connect
ter
Row Inter
connect
ter
connect
ter
(1
)
LAB Local
Inter
connect (2
ter
connect (2
ter
)
(2
)
(2
Column-to-Row
Inter
connect
ter
connect
ter
Carry-Out
&
Cascade-Out
16
24 to 48
to
to
LAB Contro
l
Signal
s
nal
s
nal
See Figure 12
for details
.
6
Dedicated Inputs
&
Global Signal
s
16
6
8
4
4
4
4
4
4
4
4
4
4
2
8
Altera Corporation 17
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as clocks,
the oth er t wo ca n b e use d for c lea r /pre set control. The L AB clocks can b e
driven by the dedicated clock input pins, global signals, I/O signals, or
internal signals via the LAB local interconnect. The LAB preset and clear
control signals can be driven by the global signals, I/O signals, or internal
signals via the LAB local interconnect. The global control signals are
typi ca lly used for global clock, clear , or preset signa ls because they
provide asynchronous control with very low skew across the device. If
logic is require d on a contr ol sig nal, it can b e genera ted in one or more LE
in any LAB and driven into the local inte rconnect of the target LAB. In
addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the FLEX 10KE architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
four-input LUT, which is a function generator that can quickly compute
any function of four variables. In addition, each LE contains a
programmable flipflop with a synchronous clock enable, a carry chain,
and a cascade chain . Each LE dr ives b oth th e loc al and the FastTrack
Interconnect routing structure (see Figure 8).
Figure 8. FLEX 10KE Logic Element
LAB Local
Interconnect
Carry-In
Clock
Select
Carry-Out
Look-Up
Table
(LUT)
Clear/
Preset
Logic
Carry
Chain Cascade
Chain
Cascade-In
Cascade-Out
FastTrack
Interconnect
Programmable
Register
PRN
CLRN
DQ
ENA
Register Bypass
data1
data2
data3
data4
labctrl1
labctrl2
labctrl4
labctrl3
Chip-Wide
Reset
18 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
The programmabl e flipflop in the LE can be config ured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combina toria l funct ions, the flipflop is bypa ssed and the output
of the LUT drives the output of the LE.
The LE has two outputs that drive the interconnect: one drives the local
interconnect and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
regist er driv es th e oth er outp ut. T his fe atu re, ca lled r egister pac ki ng, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.
The FLEX 10KE arc hitecture provides two ty pe s of ded ica te d h igh -spe ed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and ca scade chains. The carry chain supports
hi gh-speed counters and ad d e rs and the cascade chain implements
wide-inp ut fu nct ions wit h min i mum del ay . Carry and cascade chains
connect all LEs in a LAB as well as all LABs in the same row. Inte nsive use
of carry and cascade chains can reduce routing flexibility. Therefore, the
use of these chains should be limit ed to speed- critica l portion s o f a des ign.
Carry Chain
The carry chain provides a very fast (as low as 0.2 ns) carry-forward
function be tween LEs. The ca rry-i n signal from a lower - or der bit drives
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This fe ature allows the
FLEX 10KE architecture to implement high-speed counters, adders, and
comparators of arbitrary width efficiently. Carry chain logic can be
creat e d aut omatic ally b y th e Altera Compiler d uri ng design processing,
or manually by the designer during design entry. Parameterized functions
such as LPM and Design Ware function s aut omat ica lly take advan ta ge of
carry chains.
Carry chains longer than eight LEs are automatically implemented by
linking LABs together. For enhanced fitting, a long carry chain skips
al ternate LABs in a r ow. A carry chain longer than one LA B skips either
from even-numbered LAB to even-numbered LAB, or from odd-
nu mbered LAB to odd-number ed LAB. For example, the last LE of the
first LAB in a row carries to the first LE of the third LAB in the row. The
carry c hain does no t c ro ss the EAB at the mi dd le of the r ow. For instance,
in the E PF10 K50E de vice, th e car ry chain stop s at the eight eenth LAB and
a new one beg ins at the nin e tee nth LAB.
Altera Corporation 19
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Figure 9 shows how an n- bit full adde r can be impleme nte d in n+1 LEs
with the car ry chain. One port ion of th e LUT gene rates the sum of t wo bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for an accumulator function. Another portion of the LUT and th e carry
chain logic generates th e carry-out signal, which is routed directly to the
carry-in signal of the next-higher-order bit. The final carry-out signal is
routed to an LE, where it can be used as a general-purpose signal.
Figure 9. FLEX 10KE Carry Chain Ope rati on (n-Bit Full Adder)
LUT
a1
b1
Carry Chain
s1
LE1
Register
a2
b2
Carry Chain
s2
LE2
Register
Carry Chain
sn
LEn
Register
an
bn
Carry Chain
Carry-Out
LEn + 1
Register
Carry-In
LUT
LUT
LUT
20 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Cascade Chain
With the cascade chain, the FLEX 10KE architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connec ts the i ntermediat e value s. The ca scade ch ain can use a logica l AND
or logical OR (via De Morgan’s inversion) to connect the outputs of
adjace nt LEs. An a delay as low as 0.6 ns per LE, each additional LE
provides four more inputs to the effective width of a function. Cascade
chain logic can be created automatically by the Altera Compiler during
design processing, or manually by the designer during design entry.
Cascade chains longer than eight bits are implemented automatically by
linking se veral LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips ei ther from even-numbere d LAB to even-n umbered LAB, or fro m
odd-numbe red LAB to odd-numbered LA B (e.g., the last LE of the first
LAB in a row cascades to the first LE of the third LAB). The cascade chain
does not cross the center of the row (e.g., in the EPF10K50E device, the
cascade chain stops at the eighteenth LAB and a new one begins at the
ninet eenth LAB). This break is du e to the EAB’s placement in the middl e
of the row.
Figure 10 shows how the cascade function can connect adjacent LEs to
form functions with a wide fan-in. These examples show functions of
4n variables implemented with n LEs. The LE del ay is 0.9 ns ; th e c as cade
chain delay is 0.6 ns. Wi th the cascade chain, 2. 7 ns are needed to dec ode
a 16-bit address.
Figure 10. FLEX 10KE Cascade Chain Operation
LE1
LUT
LE2
LUT
d[3..0]
d[7..4]
d[(4n – 1)..(4n – 4)]
d[3..0]
d[7..4]
LEn
LE1
LE2
LEn
LUT
LUT
LUT
LUT
AND Cascade Chain OR Cascade Chain
d[(4n – 1)..(4n – 4)]
Altera Corporation 21
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
LE Operat ing M ode s
The FLEX 10KE LE can operate in the follow ing four modes:
■Normal mode
■Arithmet ic mode
■Up/down counter mo de
■Clea r able cou nter mo d e
Each of these modes u ses LE resources differently . In ea ch mode, seven
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and casc ade- i n from t he previous LE—are directed to different
destinations to implement the desired logic function. Three inputs to the
LE provide clock, clear, and preset control for the register. The Altera
software, in conjunction with parameterized functions such as LPM and
DesignWare functions, automatically chooses the appropriate mode for
common functions such as counters, adders, and multipliers. If required,
the designer can also create special-purpose functions that use a specific
LE operating mode for optimal performance.
The a rchitect ure provid es a sy nchro nous cloc k enable t o the register in all
four modes. The Altera software can set DATA1 to enable the register
synchronously, providing easy implementation of fully synchronous
designs.
22 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 11 shows the LE operating modes.
Figure 11. FLEX 10KE LE Operating Modes
ENA
PRN
CLRN
DQ
4-Input
LUT
Carry-In
Cascade-Out
Cascade-In
LE-Out to F astTrack
Interconnect
LE-Out to Local
Interconnect
ENA
Normal Mode
PRN
CLRN
DQ
Cascade-Out
LE-Out
Cascade-In
3-Input
LUT
Carry-In
3-Input
LUT
Carry-Out
Arithmetic Mode
Up/Down Counter Mode
PRN
CLRN
DQ
3-Input
LUT
Carry-In Cascade-In
LE-Out
3-Input
LUT
Carry-Out
1
0
Cascade-Out
Clearable Counter Mode
PRN
CLRN
DQ
3-Input
LUT
Carry-In
LE-Out
3-Input
LUT
Carry-Out
1
0
Cascade-Out
ENA
ENA
data1
data4
data3
data2
data1
data2
data1 (ena)
data2 (u/d)
data4 (nload)
data3 (data)
data1 (ena)
data2 (nclr)
data4 (nload)
data3 (data)
Altera Corporation 23
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Normal Mode
The normal mode is suitable for general logic applica tions and wide
de cod ing f un ctions that can take adv a nt ag e of a cas ca de chain. In normal
mode, four data inputs from the LAB local interconnect and th e carry-in
are inpu ts to a fou r-input LUT . The A lte ra Com piler aut omati cally select s
the ca rry-in or the DATA3 signal as one of the inputs to the LUT. The LUT
output can be combined with the cascade-in signal to form a cascade chain
thr ough th e casc ade -out sign al. Either the reg ister or th e LUT ca n be used
to drive both the local interconnect and the FastTrack Interconnect routing
str uct ur e at the same time .
The LUT and the regist er in the LE can be used indep endently (regi ster
packin g). To suppor t regi ster pa cking , the LE h as tw o outputs ; one dr ives
the local interconnect, and the other drives the FastTrack Interconnect
routing st ructure. The DATA4 si gnal can drive the reg ister dir ectly,
allowing the LUT to compute a function that is independent of the
regis tered s ignal; a thre e-input function can be compute d in the LUT, and
a fourth independent signal can be registered. Alternatively, a four-input
function can be generated, and one of the in puts to this function can be
used to drive the register. The register in a packed LE can still use the clock
enable, clear, and preset signals in the LE. In a packed LE, the register can
drive the FastTrack Interconnect routing structure while the LUT drives
the local interconnect, or vice versa.
Arithmetic Mode
The arithmetic mode offers 2 three-input L UTs th at are ideal for
implementing adders, accumulators, and comparators. One LUT
computes a three-input function; the other generates a carr y output. As
shown in Figure 11 on page 22, the first LUT uses the car r y-in si gnal and
two data inputs from the LAB local interconnect to generate a
combi nator ial o r regi ste r ed out put. For e xample , in a n a dde r, th is output
is the sum of three signals: a, b, and carry-in. The second LUT uses the
same thr e e signals to ge ne rate a carry-out signal, th er eb y cre ating a carr y
chai n. The ar ithmetic m ode al so support s simultane ous use of the casc ade
chain.
Up/Down Counter Mode
The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
sign als ar e g e ner a te d by the da ta inpu ts f rom th e L AB loca l int er co nne ct,
the carry-in signal, and output feedback from the programmable register.
Use 2 three-input LUTs: one generates the counter data, and the other
generates the fast carry bit. A 2-to-1 multiplexer provides synchronous
loading. Data can also be loaded asynchronously with the clear and preset
regist er co ntrol signals wi thout using t he LU T reso urc e s.
24 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Cleara ble Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
supports a synchronous clear instead of the up/down control. The clear
function is substituted for the cascade-in signal in the up/down counter
mode. Use 2 three-input LUTs: one generates the counter data, and the
other generates the fast carry bit. Synchronous loading is provided by a
2-to-1 multiplexer. The output of this multiplexer is AND ed with a
synchronou s clear signal.
Internal Tri-State Emulation
Inter nal tri- st at e emulation provide s intern al tr i-st ate s with out the
limitations of a physical tri-state bus. In a physica l tri-state bus, the
tri-st at e bu f fer s’ output enable (OE) signals se lec t whic h sig nal drive s the
bus. Howeve r, if multiple OE sig nals a re ac tive, c ontendi ng si gnals c an be
driven onto the bus. Conversely, if no OE signals are act i ve , the bus will
float. Int ernal tri-st ate em ulation resolve s conte nding tri-s tate buffe rs to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and pres et control str uc ture of the LE asynch r onous ly loads signals
into a register. Either LABCTRL1 or LABCTRL2 can control the
asynchronous clear. Alternatively, the registe r can be set up so that
LABCTRL1 implements an asynchronous load. The data to be loaded is
driven t o DATA3; w hen LABCTRL1 is asserte d , DATA3 is loaded into the
register.
During compil ati on, the Altera Compile r automat ica lly se lects the best
control s i gnal imple m entat ion. Because the c lea r an d pre set fun cti ons are
active-low, the Compiler automatically assigns a logic high to an unused
clear or preset.
The clear and preset logic is implemented in one of the following six
modes ch osen during design entry:
■Asynchronous clear
■Asynchronous preset
■As ynchronou s clear and p r eset
■Asynchronous load with cle ar
■Asynchronous load with preset
■Asynchronous load without clear or preset
Altera Corporation 25
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
In ad dition t o the six cle ar an d prese t mode s, FLEX 10KE device s provide
a chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-w ide reset overrides all other si gna ls. R e gisters with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset. Figure 12 shows examples
of how to setup the p reset and c lear inputs fo r the de sire d func tionality.
Figure 12. FL EX 10K E LE Clear & Preset Mo des
Asynchronous Clear Asynchronous Preset Asynchronous Preset & Clear
Asynchronous Load without Clear or Preset
labctrl1
(Asynchronous
Load) PRN
CLRN
DQ
NOT
NOT
labctrl1
(Asynchronous
Load)
Asynchronous Load with Clear
labctrl2
(Clear)
PRN
CLRN
DQ
NOT
NOT
(Asynchronous
Load)
Asynchronous Load with Preset
NOT
NOT
PRN
CLRN
DQ
labctrl1 or
labctrl2
PRN
CLRN
DQ
VCC
Chip-Wide Reset
Chip-Wide Reset
Chip-Wide Reset
Chip-Wide Reset
PRN
CLRN
DQ
PRN
CLRN
DQ
VCC
Chip-Wide Reset
Chip-Wide Reset
data3
(Data)
labctrl1
labctrl2
(Preset)
data3
(Data)
data3
(Data)
labctrl1 or
labctrl2
labctrl1
labctrl2
26 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this
mod e, the preset signal is tied to VCC to de activate it.
Async hronous Pres et
An asynchronous preset is implemented as an asynchronous load, or with
an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1
asynchronously loads a one into the register. Alternatively, the Altera
software can provide preset control by using the clear and inverting the
input and output of the register. Inve rsion control is available for the
inputs to both LEs and IOEs. Therefore, if a register is preset by only one
of the two LABCTRL signa ls, the DATA3 input is not needed and can be
used for one of the LE operating modes.
Async hronous Pres et & Clear
When implementing asynchronous clear and preset , LABCTRL1 controls
the pr es et an d LABCTRL2 controls the clear. DATA3 is t ied to VCC, so that
asserting LABCTRL1 asynchronously loads a one into the register,
effectively presetting the register. Asserting LABCTRL2 clear s th e reg iste r.
Async hr onous Load with Clear
When implem enting an async hr onou s loa d in conjunction with t he clea r ,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
th e regi ster pr eset and cl ear. LABCTRL2 imple ments the clear by
controlling the register clear; LABCTRL2 do es not hav e to fe ed the pres et
circuits.
Async hr onous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the regist er. Asserting LABCTRL2 presets the
register, while assertin g LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register’s output.
Async hr onous Load without Pr es et or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
th e regi ster pr eset and cl ear.
Altera Corporation 27
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
FastTrack Int er co nnec t Rout ing Structure
In the FLEX 10KE architecture, connections between LEs, EABs, and
device I/O pins are provided by the FastTrack Interconnect routing
structure, which is a series of continuous horizontal and vertical routing
chan ne ls t hat trav er se s t he devic e. This global routing st r uctu r e prov id es
pred icta ble perf orm ance, even in complex designs. In contrast, the
segmented routing in FPGAs requires switch matrices to connect a
variable number of routing paths, increasing the delays between logic
resour c es and re ducing perfor ma nce .
The F ast Tra ck I nte rconn ec t r outing structure cons ist s of ro w an d colum n
interconnect channe ls that span the entire device . Each row of LABs is
served by a de di ca te d ro w interconnect . The ro w interconnect ca n drive
I/O pi ns and feed ot her LA Bs in the row. The c olumn inte rconnect routes
signals be twee n row s and can dri ve I/O pin s.
Row channels drive into the LAB or EAB local interconnect. The row
signal is buffered at every LAB or EAB to reduce t he effect of fan-out on
delay. A row channel can be driven by an LE or by one of three column
chan ne ls. T he se fo ur sig nals feed dual 4- to-1 mu ltip lex e rs tha t con ne ct t o
two specific row channels. T hese multiplexers, which are connected to
each LE, allow column channels to drive row channels even when all eight
LEs in a LAB drive the row interconnec t.
Each column of LABs or EABs is served by a dedicated c o l umn
interconnect. The column interconnect that serves the EABs has twice as
many channels as other column interconnects. The column interconnect
can t hen drive I/O pins or anoth er row’s int erconnect t o route the signals
to other LABs or EABs in the device. A signal from the column
interconnect, which can be either the output of a LE or an input from an
I/O pin, must be routed to the row interconnect before it can enter a LAB
or EAB. Each row channel that is driven by an IOE or EAB can drive one
specific column channel.
Access to row and column channels can be switched between LEs in
adjacent pairs of LABs. For example, a LE in one LAB can drive the row
and column channels normally driven by a particular LE in the adjacent
LAB in the same row, and vice versa. This flexibility enables routing
resource s to be used more efficiently (see Figure 13).
28 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 13. FLEX 10KE LAB Connections to Row & Column Interconnect
From Adjacent LAB
Row Channels
Column
Channels
Each LE can drive two
row channels.
LE 2
LE 8
LE 1 To Adjacent LAB
Each LE can switch
interconnect access
with an LE in the
adjacent LAB.
At each intersection,
six row channels can
drive column channels.
To Other Rows
To LAB Local
Interconnect
To Other
Columns
Altera Corporation 29
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
For improved routing, the row interconnect consists of a combination of
full-length and half-length channels. The full-length channels connect to
all LABs in a row; the half-length channels connect to the LABs in half of
the r ow. The EAB c an be driven by the h alf-length channels in th e left ha lf
of the row and b y th e fu ll-lengt h c hannel s. T he E AB d rive s out to the full-
length channels. In addition to providing a predictable, row-wide
inte r conn ect , t his architecture pro vid es inc reas ed r ou ting r e sourc es. T wo
neighboring LABs can be connected us ing a half-row channel, thereby
saving the other half of the channel for the other half of the row.
Table 7 summarizes the FastTrack Interconnect routing structure
resource s available in each FLEX 10KE device.
In addition t o gen eral-purpos e I/O pins, FLEX 10KE devices have six
ded icated in put pin s that pr ovide low -skew sig nal distr ibution across t he
device. These six inputs can be used for global clock, clear, preset, and
peripheral output enable and clock enable control signals. These signals
are available as control signals for all LABs and IOEs in the device. The
dedicated inputs can also be used as general-purpose data inputs because
they can feed the local interconnect of each LAB in the device.
Figure 14 sh o ws the interconnecti on of adja ce nt LABs and EABs, with
row, column, and local interconnects, as well as the associated ca scade
and carry chains. Each LAB is labeled according to its location: a letter
represents the row and a number represents the column. For example,
LAB B3 is in row B, column 3 .
Table 7. FLEX 10KE FastTrack Interconnect Resources
Device Rows C hannels per
Row Co lu mn s Cha nn el s pe r
Column
EPF10K30E 6 216 36 24
EPF10K50E
EPF10K50S 10 216 36 24
EPF10K100E 12 312 52 24
EPF10K130E 16 312 52 32
EPF10K200E
EPF10K200S 24 312 52 48
30 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 14. FLEX 10KE Interconnect Resources
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
eithe r as an in put regis ter for exte rnal dat a that req uire s a fast se tup ti me,
or as an output registe r for data that requires fast clock-to-output
perfo rma nce. In some cases, usi ng an LE regist er for an input registe r wil l
result in a faster setup time than using an IOE register. IOEs can be used
as input, outp ut, or bidir ect iona l pins. For bidir e cti onal regist ere d I/O
implementation, the output register should be in the IOE, and the data
input and output enable registers should be LE registers placed adjacent
to the bidirectional pin. The Altera Compiler uses the programmable
inversion option to invert signals from the row and column interconnect
automatically where appropriate. Figure 15 show s the bidirectional I/O
registers.
I/O Element (IOE)
Row
Interconnect
IOE
IOE
IOE
IOE
Column
Interconnect
LAB
B1
See Figure 17
for details.
See Figure 16
for details.
LAB
A3
LAB
B3
LAB
A1 LAB
A2
LAB
B2
IOE
IOE
Cascade &
LAB B4
LAB A4
LAB B5
LAB A5
IOE IOEIOE IOE
IOE IOE
IOEIOE IOEIOE IOEIOE
IOE
IOE
Carry Chains
Altera Corporation 31
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Figure 15. FL EX 10KE Bidirectional I/O Regist ers
Note:
(1) All FLEX 10KE devices (e xcept th e EP F10K50E and EP F10K200E de vices) have a programmable input dela y buff er
on the input path.
VCC
OE[7..0]
CLK[1..0]
ENA[5..0]
CLRN[1..0]
Peripheral
Control Bus
CLRN
DQ
ENA
VCC
2 Dedicated
Clock Inputs
Slew-Rate
Control
Open-Drain
Output
Chip-Wide
Output Enable
CLK[3..2]
212
VCC
VCC
Chip-Wide
Reset
Programmable Delay
(1)
4 Dedicated
Inputs
Row and Column
Interconnect
4
VCC
CLRN
DQ
ENA
Chip-Wide
Reset
CLRN
DQ
ENA
Chip-Wide
Reset
VCC
Input Register
(2)
Output Register
(2)
OE Register
32 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
On a ll F LEX 10K E d e v ice s (except EPF 1 0K 50 E an d E PF10K200E de vices),
the input path from the I/O pad to the FastTrack Interconnect has a
programmable delay element that can be used to guarantee a zero hold
ti me. EPF10K50S and EPF10 K200S devices also support th is fe ature.
Depending on the placement of the IOE relative to what it is driving, the
desi gner may choo se to turn on the programm abl e delay to ens ure a zero
hold time or turn it off to minimize setup time. This feature is used to
reduc e setup time fo r complex pin-to-r e gis te r paths (e.g ., PCI desi gns ).
Each I OE se lects the clock, cle ar, clock enable, an d out put enable controls
from a network of I/O control signals called the periph e ral control bus.
The peripheral control bus uses high-speed drivers to minimize signal
skew across the device and provides up to 12 peripheral control signals
that can be allocated as follows:
■Up to eight output enable signals
■Up to six clock enable signals
■Up to two clock signals
■Up to two clear signals
If more than six clock enable or eight output enable signals are required,
each IOE on the device can be controlled by clock enable and output
enable signals drive n b y spec ific L Es. I n addi ti on to th e tw o clock sig na ls
available on the peripheral control bus, each IOE can use one of two
dedica te d clock pins . Ea ch perip her a l control signal can be driven by any
of the de dicated inp ut pins or the fir st LE of eac h LAB in a particular row.
In addition, a LE in a different row can drive a column interconnect, which
cause s a row interco nne ct to driv e t he pe riphe r al con tr ol s ign al. T he ch ip-
wide reset signal resets all IOE registers, overriding any other control
signals.
When a dedicated clock pin drives IOE registers, it can be inverted for all
IOEs in the device. All IOEs must use the same sense of the clock. For
example, if any IOE us es the inve rted clock, all IOEs must use the inverted
clock and no IOE can use the non-inverted clock. However, LEs can still
use the true or complement of the clock on a LAB-by-LAB basis.
The incoming signal may be inverted at the dedicated clock pin and will
drive all IOE s. For the t rue a nd c omple ment of a cl ock to be us ed t o drive
IOEs, dr ive it in to both globa l clock p ins. One global clo ck pin w ill supp ly
the true, and the other will supply the complement.
When the true and complement of a dedicated input drives IOE clocks,
two signals on the peripheral control bus are consumed, one for each
sense of th e clock.
Altera Corporation 33
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
When dedicated inputs drive non-inverted and inverted peripheral clears,
clock enables, and output enables, two signals on the peripheral control
bus will be used.
Tables 8 and 9 lis t the sou rces for each p eriphera l control signal, a nd show
how the output enable, clock enable, clock, and clear signals share
12 peripheral control signals. The tables also show the rows that can drive
global signals.
Table 8. Peripheral Bus Sour ces for EPF10K30E, EPF10K50E & EPF10K50S Devices
Peripheral
Cont r o l Si gn al EPF10K30E EPF10K50E
EPF10K50S
OE0 Ro w A Ro w A
OE1 Ro w B Ro w B
OE2 Ro w C Ro w D
OE3 Ro w D Ro w F
OE4 Ro w E Ro w H
OE5 Ro w F Ro w J
CLKENA0/CLK0/GLOBAL0 Row A Row A
CLKENA1/OE6/GLOBAL1 Ro w B Ro w C
CLKENA2/CLR0 Ro w C Ro w E
CLKENA3/OE7/GLOBAL2 Ro w D Ro w G
CLKENA4/CLR1 Ro w E Ro w I
CLKENA5/CLK1/GLOBAL3 Row F Row J
34 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Signals on the peripheral c ontrol bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3 in Tables 8 and 9. An intern ally
gener ated sig na l ca n d ri ve a gl obal signal , p ro viding the sa m e low -sk ew,
low-delay characteristics a s a s i gnal d riven b y an input pin. An LE driv es
the global signal by driving a row line that drives the peripheral bus,
which then drives the global signal. This feature is ideal for internally
generated clear or clock signals with high fan-out. However, internally
driven global signals offer no advantage over the general-purpose
interconnect for routing data signals. The dedicated input pin should be
driven to a know n logic state (such as ground) a nd no t be al lowed to float.
The chip-wide output enable pin is an active-high pin (DEV_OE) that can
be used to tri-state all pins on the device. This option can be set in the
Altera software. On EPF10K50E and EPF10K200E devices, the built-in I/O
pin pull-up resistors (which are active during configuration) are active
when the c hip-wide outpu t enable pin is assert ed. The reg isters in the IOE
can also be r eset by the chip-wi de re set pin.
Table 9. Peripheral Bus Source s for EPF10K100E, EPF10K130E, EPF10K200E & EPF10K200S Devices
Peripheral
Control Signal EPF10K100E EPF10K130E EPF10K200E
EPF10K200S
OE0 Row A Row C Row G
OE1 Row C Row E Row I
OE2 Row E Row G Row K
OE3 Row L Row N Row R
OE4 Row I Row K Row O
OE5 Row K Row M Row Q
CLKENA0/CLK0/GLOBAL0 Row F Row H Row L
CLKENA1/OE6/GLOBAL1 Row D Row F Row J
CLKENA2/CLR0 Row B Row D Row H
CLKENA3/OE7/GLOBAL2 Row H Row J Row N
CLKENA4/CLR1 Row J Row L Row P
CLKENA5/CLK1/GLOBAL3 Row G Row I Row M
Altera Corporation 35
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Row -to -IOE Co nnectio ns
When an IOE is used as an input signal, it can drive two separate row
chan nels. T he signal is accessi ble by all LEs with in that row. Wh en an IOE
is used as an output, the signal is driven by a multiplexer that selects a
sign al f rom the row channe ls. Up to eight IOEs conn ec t to each side of
each row channel (see Figure 16).
Figure 16. FLEX 10KE Row- t o-IO E Con nect ions
Table 10 lists the FLEX 10KE row-to-IOE interconnect resources.
n
n
Each IOE is driven by an
m-to-1 multiplexer.
Each IOE can drive two
row channels.
IOE8
IOE1
m
m
Row FastTrack
Interconnect
n
The values for m and n are provided in Table 10.
Table 10. FLEX 10KE Row-to-IOE Interconnect Resources
Device Channel s per Row (n) Row Channels per Pin (m)
EPF10K30E 216 27
EPF10K50E
EPF10K50S 216 27
EPF10K100E 312 39
EPF10K130E 312 39
EPF10K200E
EPF10K200S 312 39
36 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Column-to-IOE Connections
When an IOE is used as an input, it can drive up to two separate column
channels. When an IOE is used as an output, the signal is driven by a
multiplexer that selects a signal from the column channels. Two IOEs
connect to each side of the column channels. Each IOE can be driven by
column c hannels via a multiplexer. The set of column chann els is differe nt
for each IOE (see Figure 17).
Figure 17. FLEX 10KE Column-to-IOE Co nnection s
Table 11 lists the FLEX 10KE column-to-IOE interconnect resources.
Each IOE is driven by
a m-to-1 multiplexer
Each IOE can drive two
column channels.
Column
Interconnect
n
n
m
m
n
IOE1
IOE1
The va lues for m and n are provided in Table 11.
Table 11 . FLEX 10KE C olum n -to-IOE Intercon nect Resources
Device C ha nn els per Column (n) Co lumn Chan ne ls pe r Pin (m)
EPF10K30E 24 16
EPF10K50E
EPF10K50S 24 16
EPF10K100E 24 16
EPF10K130E 32 24
EPF10K200E
EPF10K200S 48 40
Altera Corporation 37
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
SameFrame
Pin-Outs
FLEX 10KE devices support the SameFrame pin-out feature for
FineLine B GA pa ckages. Th e Same Fr ame p in-ou t feat ure is the
arrangement of balls on FineLine BGA packages such that the lower-ball-
count packages form a subset of the higher-ball-count packages.
SameFrame pin-outs provide the flexibility to migrate not only from
device to device within the same package, but also from one package to
anot her. A given printed cir cuit board (PCB) layout can support multipl e
device density/package combinations. For example, a single board layout
can support a ra nge of devices from an EPF10K30 E device in a 256-pin
FineLine BGA package to an EPF10K200S device in a 672-pin
FineLine BGA package.
The Altera software provides support to design PCBs with SameFrame
pin-out devices. De vices can be defined for present a nd fut ur e use . The
Altera software generates pin-outs describing how to lay out a board to
take advantage of this migration (see Figure 18).
Figure 18. SameFr ame Pin-Out Example
Designed for 672-Pin FineLine BGA Package
Printed Circuit Board
256-Pin FineLine BGA Package
(Reduced I/O Count or
Logic Requirements)
672-Pin FineLine BGA Package
(Increased I/O Count or
Logic Requirements)
100-Pin
FineLine
BGA
256-Pin
FineLine
BGA
38 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
C lockLock &
ClockBoost
Features
To support hig h-sp ee d desi gns, FL EX 10K E devices off er option al
ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL)
used to increase design speed and reduce resource usage. The ClockLock
circu itry uses a sync hr oniz ing PL L that reduce s the clock d e lay a nd skew
within a device. This reduction minimizes clock-to-output and setup
times while main taining zero hold times . The Clock Boost circuitry, wh ich
provides a clock multiplier, allows the designer to enhance device area
efficiency by resource sharing within the device. The ClockBoost feature
allows the designer to distribute a low-speed clock and multiply that clock
on-device. Combined, the ClockLock and ClockBoost features provide
significant improvements in system performance and bandwidth.
All FLEX 10KE devices, except EPF10K50E and EPF10K200E devices,
support Clo ckLoc k and ClockBoos t circuit r y. EPF10K5 0S and
EPF10K200S devices support this circuitry. Devices that support Clock-
Lock a nd C loc kBoos t circuitry are distinguished with a n “ X ” suffix in the
ordering code; for instance, the EPF10K200SFC672-1X device supports
this circuit.
The ClockLock and ClockBoost features in FLEX 10 KE devices are
enabled through the Altera software. External devices are not required to
use these featur es. The output of the ClockLoc k and ClockB oost circuits is
no t available at any of the de vice pins.
The ClockL ock and Clock B oost ci rc uitry lock s ont o the rising edge of the
incoming clock. The circuit output can drive the clock inputs of registers
only; the generated clock cannot be gated or inverted.
The dedicated clock pin (GCLK1) supplies the cl ock to t he Clo ckLoc k a nd
ClockBoost circuitry. When the dedicated clock pin is driving the
ClockLock or ClockBoos t circuitr y, it c annot driv e elsewhere in the de vice.
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to the GCLK1 pin. In th e
Altera software, the GCLK1 pin can feed both the ClockLock and
ClockBoost circuitry in the FLEX 10KE device. However, when both
circuits are used, the other clock pin cannot be used.
Altera Corporation 39
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
ClockL ock & C lock Boost Timing Par amet er s
For the ClockLock and Cloc k Boost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock d uring config ura tion. Th e circ uit w ill be rea dy for us e immedi ately
after configuration. Figure 19 shows t he inco ming and gene rate d clock
specifications.
Figure 19. Specifications for Incoming & Generated Clocks
The tI parameter refers to the nominal input clock period; the tO parameter refers to the
nominal output clock period.
tRtF
tCLK1 tINDUTY tI ± fCLKDEV
tItI ± tINCLKSTB
tOUTDUTY
tOtO + tJITTER tO – tJITTER
Input
Clock
C
lockLock-
G
enerated
C
lock
40 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Tables 12 and 13 summarize the ClockLock and ClockBoost parameters
for -1 and -2 speed-grade devices, respectively.
Table 12 . ClockLock & Cloc kBoo st Parameters for -1 Speed- Grade Devices
Symbol Parameter Condition Min Typ Max Unit
tRInput rise time 5ns
tFInput fall time 5ns
tINDUTY Input duty cycle 40 60 %
fCLK1 Input clock frequency (ClockBoost
clock multiplication factor equals 1) 25 180 MHz
fCLK2 Input clock frequency (ClockBoost
clock multiplication factor equals 2) 16 90 MHz
fCLKDEV Input deviation from user
specification in the MAX+PLUS II
software (1)
25,000 (2) PPM
tINCLKSTB Input clock stability (measured
between adjacent clocks) 100 ps
tLOCK Time required for ClockLock or
ClockBoost to acquire lock (3) 10 µs
tJITTER Jitter on ClockLock or ClockBoost-
generated clock (4) tINCLKSTB < 100 250 ps
tINCLKSTB < 50 200 (4) ps
tOUTDUTY Duty cycle for ClockLock or
ClockBoost-generated clock 40 50 60 %
Altera Corporation 41
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Notes to table s:
(1) To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency.
The fCLKDEV pa ra meter spec ifies how much th e incom in g c lock can di ffer fr om the sp ecified freq uency during
device operation. Simulation does not reflect this parameter.
(2) Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
(3) During device conf iguration, the ClockL ock and Clock Boost circuitry is configu re d befo re the r est of the device. If
the incoming clock is s upplied dur ing co nfigur a t ion, t h e C lo c kLoc k a nd ClockB oost circu itry lo c ks dur in g
con figur at io n because the tLOCK value is less than the time required for configuration.
(4) The tJITTER specific ation is me as u red und er lo n g-term obser v ation . The max imum va lu e f or tJITTER is 200 ps if
tINCLKSTB is lower t han 50 ps.
I/O
Configuration
This section discusses the peripheral component interconnect (PCI)
pull-up clamping diode option, slew-rate control, open-drain output
option, and MultiVolt I/O interface for FLEX 10KE devices. The PCI
pull-up clamping diode, slew-rate control, and open-drain output options
are con trolled pin-by-pin via Alter a software logic options. The MultiVolt
I/O interfa ce is controlled by con nectin g VCCIO to a diff eren t voltag e than
VCCINT. Its effect can be simulated in the Altera software via the Global
Project Device Options dialog box (Assign menu).
Table 13. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol Parameter Condition Min Typ Max Unit
tRInput rise time 5ns
tFInput fall time 5ns
tINDUTY Input duty cycle 40 60 %
fCLK1 Input clock frequency (ClockBoost
clock multiplication factor equals 1) 25 75 MHz
fCLK2 Input clock frequency (ClockBoost
clock multiplication factor equals 2) 16 37.5 MHz
fCLKDEV Input deviation from user
specification in the MAX+PLUS II
software (1)
25,000 (2) PPM
tINCLKSTB Input clock stability (measured
between adjacent clocks) 100 ps
tLOCK Time required for ClockLock or
ClockBoost to acquire lock (3) 10 µs
tJITTER Jitter on ClockLock or ClockBoost-
generated clock (4) tINCLKSTB < 100 250 p s
tINCLKSTB < 50 200 (4) ps
tOUTDUTY Duty cycle for ClockLock or
ClockBoost-generated clock 40 50 60 %
42 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
PCI Pull-Up C lam ping Diode Option
FLEX 10KE devices have a pull-up clamping diode on every I/O,
dedicated input, and dedicated clock pin. PCI clamping diodes clamp the
signal to the VCCIO value and are required for 3.3-V PC I compliance.
Clamping diodes can also be used to limit overshoot in other systems.
Clamping diodes are controlled on a pin-by-pin basis. When VCCIO is
3.3 V, a pi n that has the c lamping diode option turned on can be driven b y
a 2.5-V or 3.3-V si gnal, but not a 5.0-V sign al. When VCCIO is 2.5 V, a pi n
that has the clamping diode option turned on can be driven by a 2.5-V
signal, but not a 3.3-V or 5.0-V signal. Additionally, a clamping diode can
be activated for a subset of pins, which would allow a device to bridge
between a 3.3-V PCI bus and a 5 .0-V d evic e.
Slew-Rate Control
The outp ut buffer in each IOE has an adjustab le output sle w rate tha t can
be configured for low-noise or high-speed performance. A slower slew
rate reduces system noise and adds a maximum delay of 4.3 ns. The fast
slew rate should be used for speed-critical outputs in systems that are
adequately protected against noise. Designers can specify the slew rate
pin-by-pin or ass ign a d e faul t sle w rate t o a ll pins on a device-wide b asi s.
The slow slew rate setting affects the falling edge of the output.
Open-Dr ain Out put Option
FLEX 10KE devices provide an optional open-drain output (electrically
equivalent to open-collector output ) for each I/O pin. This open-drain
output enables the device to provide system-level control signals (e.g.,
interrupt and write enable signals) that can be asserted by any of several
devices. It can also provide an additional wired-OR plane.
MultiVolt I/O Interface
The FLEX 10KE device architecture supports the MultiVolt I/O interface
feature, w hich a llows F LEX 10KE device s in a ll packa ges to i nter face with
systems of differing supply voltages. These devices have one set of VCC
pins for internal operation and input buffers (VCCINT), and another set for
I/O output drivers (VCCIO).
Altera Corporation 43
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
The VCCINT pins must always be connected to a 2.5-V power supply.
With a 2.5-V VCCINT level, input voltages are compatible with 2.5-V, 3.3-
V, and 5.0-V in put s. T he VCCIO pins can be connect ed t o e ither a 2.5-V or
3.3-V power supply, depending on the output requirements. When the
VCCIO pins are connected to a 2.5-V power supply, the output leve ls are
com pa tib le wit h 2.5-V sy ste m s. When the VCCIO pins are connected to a
3.3-V power supply, the output high is at 3.3 V and is therefore compatible
with 3.3-V or 5.0-V systems. Device s operating with VCCIO levels higher
than 3.0 V achieve a faster timing delay of tOD2 instead of tOD1.
Table 14 summarizes FLEX 10KE MultiVolt I/O support.
Notes:
(1) T h e PCI clam pi ng diode mu s t be d isabled to drive an inp u t wit h vo lt ag es h igher
than VCCIO.
(2) Wh e n V CCIO = 3.3 V, a FLEX 10KE device can drive a 2.5-V device that has 3.3-V
tolerant inputs .
Open-drain output pins on FLEX 10KE devices (with a pull-up resistor to
the 5.0-V supply ) can drive 5.0-V CMOS input pins that req uire a VIH of
3.5 V. When the open-drain pin is active, it will drive low. When the pin is
inactive, the trace will be pulled up to 5.0 V by the resistor. The open-drain
pin will only drive low or tri-state; it will never drive high. The rise time
is depe ndent on the valu e of the pull-up re sistor and load impe dance . The
IOL current specification should be considered when selecting a pull-up
resistor.
Power Sequencing & Hot-Soc k eti ng
Beca use F LEX 10K E de vices can be used in a mixed -voltag e envi ronmen t,
they have been designed specifically to tolerate any possible power-up
sequence. The VCCIO and VCCINT power planes can be powered in any
order.
Signals can be dri ven into FLEX 10KE devices before and during power
up without damaging the device. Additionally, FLEX 10KE devices do not
drive out during power up. Once operating conditions are reached,
FLEX 10KE devices operate as specified by the user.
Table 14. FLEX 10KE MultiVolt I/O Support
VCCIO (V) Input Signal (V) Output Sig nal (V)
2.5 3.3 5.0 2.5 3.3 5.0
2.5 vv(1) v(1) v
3.3 vv v(1) v(2) vv
44 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
IEEE Std.
1149.1 (J TAG)
Boundar y-Scan
Support
All FLEX 10KE devices provide JTAG BST circuitry that complies with the
IEEE Std. 11 49.1-1990 speci f ication. FLEX 10 KE devices can also be
configur e d using the JTAG pins thro ugh the BitBlast er or By te BlasterMV
download cable, or via hardware that uses the JamTM STAPL
programming and test language. JTAG boundary-scan testing can be
performed before or after configuration, but not during configuration.
FLEX 10KE devices support the JTAG instructions shown in Table 15.
The instruction register length of FLEX 10KE devices is 1 0 bits. The
USERCOD E register length in FLEX 10KE devices is 32 bits; 7 bits are
determined by the user, and 25 bits are pre-determined. Tables 16 and 17
show the boundary-scan register length and device IDCODE information
for FLEX 10 KE devi ces.
Table 15. FLEX 10K E JTAG I nstructi ons
JTAG Instruc tion De scription
SAM PLE/PRELOAD Allows a sn aps hot of signa ls at the dev ice pins to be capt ured and examined during
norma l dev ice operat ion, and permits an init ial data pattern to be out put at the devic e
pins.
EXT EST Allows th e ex ter nal ci rcu itry and board-lev el inte rc onnections to be test ed by forcing a
test patt ern at the ou tpu t pin s and cap tur ing te st res ult s at the input pins .
BYPASS Places t he 1-bit by pas s regis ter between the TDI and TDO pins, whic h allow s the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation.
US ER CO D E Selec ts the user elec tro nic sign atu re (U SER C OD E) register and plac es it betw een t he
TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO.
IDCODE Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shi fted out of TDO.
ICR Instructions These instructions are used when configuring a FLEX 10KE device via JTAG ports with
a BitBlast er or By te Blas t erM V dow nload cable, or us ing a Ja m File (.jam) or
Jam Byte-Code File (.jbc) via an embedded processor.
Table 16. FLEX 10KE Boundary-Scan Register Length
Device Boundary-Scan Register Length
EPF10K30E 690
EPF10K50E
EPF10K50S 798
EPF10K100E 1,050
EPF10K130E 1,308
EPF10K200E
EPF10K200S 1,446
Altera Corporation 45
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Notes:
(1) The most significant bit (MSB) is on the left.
(2) The least si g nifican t bit (LS B) for a ll JT A G IDC ODEs is 1.
FLEX 10KE devices include weak pull-up resistors on the JTAG pins.
fFor more information, see the following documents:
■Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in
Altera Devices)
■BitBlaster Serial Download Cable Data Sheet
■ByteBlasterMV Parallel Port Download Cable Data Sheet
■Jam Programming & Test Language Specification
Table 17. 32-Bit IDC ODE for FLEX 10KE Devices Note (1)
Device IDCODE (32 Bits)
Version
(4 Bits) Part Numbe r (16 Bits) Manufactu rer’s
Identity (11 Bits) 1 (1 Bit)
(2)
EPF10K30E 0001 0001 0000 0011 0000 00001101110 1
EPF10K50E
EPF10K50S 0001 0001 0000 0101 0000 00001101110 1
EPF10K100E 0010 0000 0001 0000 0000 00001101110 1
EPF10K130E 0001 0000 0001 0011 0000 00001101110 1
EPF10K200E
EPF10K200S 0001 0000 0010 0000 0000 00001101110 1
46 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 20 shows the timin g requirements for the JT AG s ignals.
Figure 20. FLEX 10KE JTAG Waveforms
Table 18 shows the timing parameters and values for FLEX 10KE devices.
Table 18. FLEX 10KE JTAG Timing Parameters & Values
Symbol Parameter Min Max Unit
tJCP TCK clock period 100 ns
tJCH TCK clo ck high t im e 50 ns
tJCL TCK clock low time 50 ns
tJPSU JTAG port se tu p time 20 ns
tJPH JTAG port hold time 45 ns
tJPCO JTAG port clo ck to outp ut 25 ns
tJPZX JTAG port high impedance t o val id out put 25 ns
tJPXZ JTAG port va lid out put to high im pedance 25 ns
tJSSU Capture register setup time 20 ns
tJSH Capture register hold time 45 ns
tJSCO Update register clock to output 35 ns
tJSZX Update register high impedance to valid output 35 ns
tJSXZ Update register valid output to high impedance 35 ns
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
tJCP tJPSU
tJCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
tJSZX
tJSSU tJSH
tJSCO tJSXZ
Altera Corporation 47
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Generic Testing Each FLEX 10KE device is functionally tested. Complete testing of each
configurable static random access memory (SRAM) bit and all logic
functionality ensures 100% yield. AC test measurements for FLEX 10KE
device s ar e mad e under co nditions equivalen t to those shown in
Figure 21. Multiple test patterns can be used to configure devices during
all stages of the production flow .
Figure 21. FLEX 10KE AC Test Conditions
Operating
Conditions
Tables 19 through 23 provide i nform ation on absol ute maximum rat ing s,
recommended operating conditions, DC operating conditions, and
capacitance for 2.5-V FLEX 10KE devices.
Test
System
C1 (includes
JIG capacitance)
Device input
rise and fall
times < 3 ns
Device
Output
703 Ω
8.06 kΩ
[481 ]
Ω
[481 ]
Ω
VCCIO
Power supply transients can affect AC
measurements. Simultaneous transitions of
mu ltiple outputs should be av oided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast-ground-
current transients normally occur as the
device outputs discharge the load
capa citanc es. When these tra nsients flow
throu gh the para sitic inductance betwee n
the device ground pin and the test system
groun d, signif icant reductions in
observable noise immunity can result.
Numbers in brackets are for 2.5-V devices
or outputs. Numbers without brackets are
for 3.3-V. devices or outputs .
Table 19. FLEX 10KE 2.5-V Device Absolute Maxi mum Ratings Note (1)
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage With respect to ground (2) –0.5 3.6 V
VCCIO –0.5 4.6 V
VIDC input volt age –2.0 5.7 5 V
IOUT DC out put current, per pin –25 25 mA
TSTG Storage temperature No bias –65 150 ° C
TAMB Ambient temperature Under bia s –65 135 ° C
TJJunction temperature PQFP, TQFP, BGA, and FineLine BGA
packages, under bias 135 ° C
Ceramic PGA pac k ages, under bias 150 ° C
48 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Table 20. 2.5-V EP F1 0K50E & EPF10K200E Device Recommended Operatin g Co nd itions
Symbol Parameter Conditions Min Max Unit
VCCINT Supply vo ltag e fo r inter nal logic
and input buffers (3), (4) 2.30 (2.30) 2. 70 (2.70) V
VCCIO Supply voltage for output buffers,
3.3-V operation (3), (4) 3.00 (3.00) 3.60 (3.60) V
Supply voltage for output buffers,
2.5-V operation (3), (4) 2.30 (2.30) 2.70 (2.70) V
VIInput vo lta ge (5) –0.5 5.75 V
VOOutp ut volt age 0 VCCIO V
TAAmbient temperature For commercial use 0 70 ° C
For indust rial us e –40 85 ° C
TJOperating temperature For commercial use 0 85 ° C
For indust rial us e –40 100 ° C
tRInput ris e time 40 ns
tFInput fa ll time 40 ns
Table 21. 2.5-V EPF10K30E, EPF1 0K50S, EPF10K100E, EPF10K130E & EPF10K200S De vice
Re com m e nde d Op er a t in g Co nditi o ns
Symbol Parameter Conditions Min Max Unit
VCCINT Supply vo ltag e fo r inter nal logic
and input buffers (3), (4) 2.375
(2.375) 2.625
(2.625) V
VCCIO Supply voltage for output buffers,
3.3-V operation (3), (4) 3.00 (3.00) 3.60 (3.60) V
Supply voltage for output buffers,
2.5-V operation (3), (4) 2.375
(2.375) 2.625
(2.625) V
VIInput vo lta ge (5) –0.5 5.75 V
VOOutp ut volt age 0 VCCIO V
TAAmbient temperature For commercial use 0 70 ° C
For indust rial us e –40 85 ° C
TJOperating temperature For commercial use 0 85 ° C
For indust rial us e –40 100 ° C
tRInput ris e time 40 ns
tFInput fa ll time 40 ns
Altera Corporation 49
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Table 22. FLEX 10KE 2.5-V Device DC Operating Conditions Notes (6), (7)
Symbol Parameter Conditions Min Typ Max Unit
VIH High -lev el input
voltage 1.7, 0.5 ×VCCIO (8) 5.75 V
VIL Low -lev el input
voltage –0.5 0.8,
0.3 ×VCCIO (8) V
VOH 3.3-V high-level TTL
outp ut volt age IOH = –8 mA DC,
VCCIO =3.00 V (9) 2.4 V
3.3-V high-level
CMOS output voltage IOH = –0.1 mA DC,
VCCIO =3.00 V (9) VCCIO –0.2 V
3.3-V high-level PCI
outp ut volt age IOH = –0.5 mA DC,
VCCIO = 3.00 to 3.60 V (9) 0.9 ×VCCIO V
2.5-V high-level output
voltage IOH = –0.1 mA DC,
VCCIO =2.30 V (9) 2.1 V
IOH = –1 mA DC,
VCCIO =2.30 V (9) 2.0 V
IOH = –2 mA DC,
VCCIO =2.30 V (9) 1.7 V
VOL 3.3-V low-level TTL
outp ut volt age IOL = 12 mA DC,
VCCIO =3.00 V (10) 0.45 V
3.3-V low-level CMOS
outp ut volt age IOL = 0.1 m A DC,
VCCIO =3.00 V (10) 0.2 V
3.3-V low-level PCI
outp ut volt age IOL = 1.5 m A DC,
VCCIO = 3.00 to 3.60 V
(10)
0.1 ×VCCIO V
2.5-V low-level output
voltage IOL = 0.1 m A DC,
VCCIO =2.30 V (10) 0.2 V
IOL = 1 mA DC,
VCCIO =2.30 V (10) 0.4 V
IOL = 2 mA DC,
VCCIO =2.30 V (10) 0.7 V
IIInpu t pin lea ka ge
current VI = VCCIOmax to 0 V (11) –10 10 µA
IOZ Tri-st at ed I/O pin
leak age c urrent VO = VCCIOmax to 0 V (11) –10 10 µA
ICC0 VCC supply cu r r ent
(standby) VI = ground, no load, no
toggling inputs 5mA
VI = ground, no load, no
toggling inputs (12) 10 mA
RCONF Value of I/O pin pull-
up resistor before and
during c onf iguration
VCCIO = 3.0 V (13) 20 50 k¾
VCCIO = 2.3 V (13) 30 80 k¾
50 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents
less than 100 mA and per iods shor t er tha n 20 ns.
(3) Numbers in parenthes es are for industri al-t e mperatur e-ra nge devices.
(4) Max i mum V CC rise time is 100 ms, and VCC must rise monotonically.
(5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(6 ) T ypica l v a lu es a r e for TA = 25° C, VCCINT = 2.5 V , and VCCIO = 2.5 V or 3.3 V.
(7) These values are spec ifi ed under the FLEX 10KE Recommended Operating Conditi ons shown in Tables 20 and 21.
(8) The FLE X 10KE inpu t buf fers ar e c ompatibl e with 2. 5-V , 3.3-V (LVTT L and LVCMO S), an d 5.0 -V TTL an d CM OS
signals. Additionally, the input buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship shown
in Figure 22.
(9) The IOH parameter refers to high-level TTL, PCI, or CMOS output cu rrent.
(10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-dra in pins
as well as outpu t pins.
(11) Thi s v alue is sp ec ifi ed for normal dev ic e opera tio n . Th e v alue may v ar y during p ower-up .
(12) This parameter applies to -1 speed-grade commercial-temperature devices and -2 speed-grade-industrial
temper ature d ev i c es .
(13) Pin pull-up resistance values will be lower if the pin is driven higher than VCCIO by an extern al sou r ce.
(14 ) Capacit ance is sa mple-test ed o n ly.
Table 23. FLEX 10KE Devi ce Capacitance Note (14)
Symbol Parameter Conditions Min Max Unit
CIN Input ca pac it anc e VIN = 0 V, f = 1.0 MHz 10 pF
CINCLK I nput ca pac it anc e on
dedic ate d clo ck pin VIN = 0 V, f = 1.0 MHz 12 pF
COUT Output capacit anc e V OUT = 0 V, f = 1.0 MHz 10 pF
Altera Corporation 51
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Figure 22 shows the requir ed relat ionship between VCCIO and VCCINT for
3.3-V PCI compliance.
Figure 22. Relationship between VCCIO & VCCINT for 3.3-V PCI Compliance
Figure 23 shows the typical output drive characteristics of FLEX 10KE
devices with 3.3-V and 2.5-V VCCIO. The output dr iver is comp liant to the
3.3-V PCI Local Bus Specification, Revi sion 2.2 (when VCCIO pins are
conne cted to 3.3 V). F LEX 10K E devices w ith a -1 speed gr ade als o comply
with the drive strength requirements of the PCI Local Bus Specification,
Re vis ion 2. 2 (whe n VCCINT pins are powered with a minimum supply of
2.3 75 V , and VCCIO pins are connected to 3.3 V). Therefore, these devices
can be used in open 5.0-V PCI systems.
3.0 3.1 3.3
VCCIOIO
3.6
2.3
2.5
2.7
VCCINT
II (V)
(V)
PCI-Compliant Region
52 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 23. Output Drive Characteristics of FLEX 10KE Devices Note (1)
Note:
(1) The se ar e tr an sie nt (A C) currents.
Tim ing Model The continuous, high-performance FastTrack Interconnect routing
resources ensur e predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a seg mented connection scheme and ther ef ore have
un predi ctabl e per formance.
Device perf orm a nce c an b e e stima te d b y following the sig na l path fr om a
source, through the interconnect, to the destination. For example, the
registered perfo r mance between two LEs on the same r ow can b e
calculated by adding the following parameters:
■LE register clock-to-output delay (tCO)
■Interconnect delay (tSAMEROW)
■LE look-up table delay (tLUT)
■LE register setup time (tSU)
The rout ing delay depends on the placement of the source and destination
LEs. A more comp lex registered pat h may involve multiple combinatorial
LEs betwe en the sour ce and de st inat ion LEs.
V
O
Output Voltage (V)
I
OL
I
OH
I
OH
V
V
V
CCINT
= 2.5
V
CCIO
= 2.5
Room Temperature
V
V
V
CCINT
= 2.5
V
CCIO
= 3.3
Room Temperature
123
10
20
30
50
60
40
70
80
90
V
O
Output Voltage (V)
123
10
20
30
50
60
40
70
80
90
I
OL
O
Typical I
Output
Current (mA)
O
Typical I
Output
Current (mA)
Altera Corporation 53
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Timing simulation and delay prediction are available with the Altera
Simulator and Timing Analyzer, or with industry-standard EDA tools.
The Sim ulator of fers both pre-sy nthes is function al si mulation to e valu ate
logic design accuracy and post-synthesis timing simulation with 0.1-ns
resolution. The Timing Analyzer provides point-to-point timing delay
inform ati on, set up and h old ti me a nal ys is, and d evice -wide pe r formanc e
analysis.
Figure 24 shows the overall t iming model, which maps t he pos sible paths
to and from the various elements of the FLEX 10KE device.
Fig ure 24. FL EX 10KE De vice Timing Model
Figures 25 through 28 show the delays that correspond to various paths
and functions wit hin the LE, IOE, EAB, and bidirectional timin g models.
Dedicated
Clock/Input Interconnect I/O Element
Logic
Element Embedded Array
Block
54 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 25. FLEX 10KE Device LE Timing Model
t
CGENR
t
CO
t
COMB
t
SU
t
H
t
PRE
t
CLR
Register
Delays
LUT Delay
t
LUT
t
RLUT
t
CLUT
Carry Chain
Delay
Carry-In Cascade-In
Data-Out
t
CGEN
t
CICO
Packed Register
Delay
t
PACKED
Register Control
Delay
t
C
t
EN
Data-In
Control-In
t
CASC
Cascade-Out
Carry-Out
t
LABCARRY
t
LABCASC
Altera Corporation 55
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Figure 26. FL EX 10KE Device IOE Timing Model
Figure 27. FL EX 10KE Device EAB Timing Model
Data-In
I/O Register
Delays
tIOCO
tIOCOMB
tIOSU
tIOH
tIOCLR
Output Data
Delay
tIOD
I/O Element
Contol Delay
tIOC
Input Register Delay
tINREG
Output
Delays
tOD1
tOD2
tOD3
tXZ
tZX1
tZX2
tZX3
I/O Register
Feedback Delay
tIOFD
Input Delay
tINCOMB
Clock Enable
Clear
Data Feedback
into FastTrack
Interconnect
Clock
Output Enable
EAB Data Input
Delays
tEABDATA1
tEABDATA2
Data-In
Write Enable
Input Delays
tEABWE1
tEABWE2
EAB Clock
Delay
tEABCLK
Input Register
Delays
tEABCO
tEABBYPASS
tEABSU
tEABH
tEABCH
tEABCL
tEABRE1
tEABRE2
RAM/ROM
Block Delays
tAA
tRP
tRASU
tRAH
tDD
tWP
tWDSU
tWDH
tWASU
tWAH
tWO
Output Register
Delays
tEABCO
tEABBYPASS
tEABSU
tEABH
tEABCH
tEABCL
tEABOUT
Address
WE
Input Register
Clock
Output Register
Clock
Data-Out
EAB Output
Delay
Read Enable
Input Delays
RE
56 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
Tables 24 through 28 describe the FLEX 10KE device internal timing
parameters. Tables 29 through 30 d escri be t he FLEX 10K E e xtern al tim ing
paramete rs and their symbols.
PRN
CLRN
DQ
PRN
CLRN
DQ
PRN
CLRN
DQ
Dedicated
Clock
Bidirectional
Pin
Output Register
tINSUBIDIR
tOUTCOBIDIR
tXZBIDIR
tZXBIDIR
tINHBIDIR
OE Register
Input Register
Table 24. LE Timing Microparameters (Part 1 of 2) Note (1)
Symbol Parameter Condition
tLUT LUT delay for data-in
tCLUT LUT delay for carry-in
tRLUT LUT delay for LE register feedback
tPACKED Data-in t o packed register delay
tEN LE register enable delay
tCICO Carry-in to carry-out delay
tCGEN Data-in to carry-out delay
tCGENR LE register feedb ac k to car ry- out delay
tCASC C as ca de-in t o ca scade-out dela y
tCLE register c ont rol s ignal delay
tCO LE register c loc k -to -out put delay
tCOMB C om binatorial delay
tSU LE register s et up time for data and enable signals befo re clo ck; LE regis t er
recovery time af t er async hronous clear, pres et , or loa d
tHLE register hold time for data and enable signa ls afte r clo ck
tPRE LE register prese t dela y
Altera Corporation 57
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
tCLR LE register clear delay
tCH Minimu m cloc k hig h time f rom clo ck pin
tCL Minimu m cloc k low t ime from cl oc k pin
Table 24. LE Timing Microparameters (Part 2 of 2) Note (1)
Symbol Parameter Condition
Table 25. IOE Timing Microparameters Note (1)
Symbol Parameter Conditions
tIOD IOE data de lay
tIOC IOE regis ter control s ignal delay
tIOCO IOE regis ter clock -to -out put delay
tIOCOMB IOE c om binatorial dela y
tIOSU IOE register setup time for data and enable signals before clock; IOE register
reco ve ry tim e after as y nc hronous clear
tIOH IOE regis ter hold time f or dat a and enable signa ls aft er clo ck
tIOCLR IOE register clear time
tOD1 Output buffer and pad delay, slo w slew rat e = off, VCCIO = 3.3 V C1 = 35 pF (2)
tOD2 Output buffer and pad delay, slo w slew rat e = off, VCCIO = 2.5 V C1 = 35 pF (3)
tOD3 Output buffer and pad delay, slo w slew rat e = on C1 = 35 pF (4)
tXZ IOE outpu t bu ffer dis able delay
tZX1 IOE outpu t bu ffer enable delay, slo w slew rat e = off, VCCIO = 3.3 V C1 = 35 pF (2)
tZX2 IOE outpu t bu ffer enable delay, slo w slew rat e = off, VCCIO = 2.5 V C1 = 35 pF (3)
tZX3 IOE outpu t bu ffer enable delay, slo w slew rat e = on C1 = 35 pF (4)
tINREG IOE input pad and buf f er to IOE regis ter delay
tIOFD IOE regis ter feed bac k de lay
tINCOMB IOE input pad and buff er to Fast Tra ck In te rco nnec t delay
58 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Table 26. EAB Ti min g Micr oparameters Note (1)
Symbol Parameter Conditions
tEABDATA1 Data or address delay to EAB for combinatorial input
tEABDATA2 Data or address delay to EAB for registered input
tEABWE1 W rite enable delay to EAB for combinatorial inp ut
tEABWE2 W rite enable delay to EAB for regis te red input
tEABRE1 R ead enable delay to EAB for com binat orial input
tEABRE2 R ead enable delay to EAB for regi stered input
tEABCLK EAB regist er cl o ck del a y
tEABCO EAB register clock-to-output delay
tEABBYPASS Bypa ss r egi ster delay
tEABSU EAB register setup t im e bef ore c loc k
tEABH EAB register hold time af t er cl ock
tEABCLR EAB register async hronous clear ti me to output delay
tAA Addres s acc es s de lay (inclu ding the read enabl e to output delay)
tWP Wr i te puls e widt h
tRP Read pul se width
tWDSU D ata setup t im e bef ore f alling edge of write pulse (5)
tWDH D ata hold ti me after fa lling edge of write pulse (5)
tWASU Address setup time before rising edge of write pulse (5)
tWAH Address hold time af te r falli ng edge of write pulse (5)
tRASU Address setup time with respect to the falli ng edge of the read enable
tRAH Address hold time with respect to the falling edge of the read enable
tWO Write enable to data outpu t valid delay
tDD Data-in to data -out va lid delay
tEABOUT D ata -out delay
tEABCH C loc k hig h time
tEABCL Clock low time
Altera Corporation 59
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Table 27. EAB Timing Macroparameters Note (1), (6)
Symbol Parameter Conditions
tEABAA EA B address acces s dela y
tEABRCCOMB EA B as yn ch ronous read cycle time
tEABRCREG EAB synchronous read cycle time
tEABWP EAB write pulse width
tEABWCCOMB EAB asyn ch ronous write cycle time
tEABWCREG EAB synchronous write cycle time
tEABDD EA B dat a-in to data-out valid delay
tEABDATACO EA B cl ock-t o-output delay whe n us ing out put regis t ers
tEABDATASU EA B dat a/ address setup time before clock wh en us ing input register
tEABDATAH EA B dat a/ address hold time af te r clock wh en us ing input register
tEABWESU EAB WE setup time before clock wh en us ing input register
tEABWEH EAB WE hold time af te r clock whe n us ing input register
tEABWDSU EA B dat a se tu p time bef ore falling edge of write puls e whe n not usin g input
registers
tEABWDH EAB data hold time after falling edge of write pulse when not using input
registers
tEABWASU EA B address setup time before rising edge of write pulse wh en not usin g
input registers
tEABWAH EA B address hold time after falli ng edge of write pulse when not usin g input
registers
tEABWO EA B w rite enable to data output va lid delay
60 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Table 28. I nterconnect Timing Microparameters Note (1)
Symbol Parameter Conditions
tDIN2IOE D elay fro m ded ic ate d input pin t o IOE con tro l input (7)
tDIN2LE D elay fro m ded ic ate d input pin t o LE or EAB c ont rol input (7)
tDCLK2IOE Delay fro m ded ic ate d clo ck pin t o IOE clock (7)
tDCLK2LE D elay fro m ded ic ate d clo ck pin t o LE or EAB c loc k (7)
tDIN2DATA Delay fro m ded ic ate d input or clo ck to LE or EAB data (7)
tSAMELAB Routing delay for an LE drivin g anot her LE in the same LAB
tSAMEROW Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
same row (7)
tSAMECOLUMN Routing delay for an LE drivin g an IO E in the same c olum n (7)
tDIFFROW Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
row (7)
tTWOROWS Routing delay for a row IOE or EAB driv ing an LE or EAB in a different row (7)
tLEPERIPH Routing delay for an LE drivin g a con tro l sign al of an IOE via th e peripheral
control bus (7)
tLABCARRY Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a dif fer ent LAB
tLABCASC Routing delay for the cascade-out signal of an LE driv ing t he c as cad e-in
signal of a different LE in a different LAB
Table 29. Ext ernal Timing Parame t ers
Symbol Parameter Conditions
tDRR Register-to-register delay via four LEs, three row interconnects, and four local
interconnects (8)
tINSU Setup ti m e with global clock at IOE regis te r (9)
tINH Hold time with global clock at IOE reg ister (9)
tOUTCO Clock-to-output delay with global clock at IOE regis te r (9)
tPCISU Setup tim e with global clock for regis t ers used in PCI des igns (9),(10)
tPCIH Hold time with global clock for regis ter s used in PC I des igns (9),(10)
tPCICO Clock-to-output delay with global clock for regis t ers use d in PCI des igns (9),(10)
Altera Corporation 61
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Notes to table s:
(1) Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured ex plicit ly .
(2) Op er ating cond itions: VCC I O = 3.3 V ±10 % for commercial or industrial use.
(3) Operating conditions: VCCIO = 2.5 V ±5% for commercial or industrial use in EPF10K30E, EPF10K50S,
EPF1 0K 100E, EPF10K 130E, and EPF 10K200S dev ices.
(4) Operating conditions: VCCIO = 3.3 V.
(5) Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE si gnal is regis tered .
(6) EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters ar e c alcula t ed by summing sel ec t ed microparame t er s .
(7) These parameters are worst-case values for ty pical applications. Post-compilation timing simulation and timing
analysis are req ui r ed to de t ermine actual worst-case perfo r man c e.
(8) Contact Altera Applications for test circuit specifications and test conditions.
(9) This timing parameter is sample-tested only.
(10) This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
Bus Specification, revision 2.2.
Table 30. External Bidirectional Timing Parameters Note (9)
Symbol Parameter Conditions
tINSUBIDIR Se tu p time f or bi-directional pins with global clock at same-row or same-
column LE register
tINHBIDIR Hold time for bidirectional pins with global clock at same-row or same-column
LE register
tINH Hold time wi th glo bal c loc k at IOE regis te r
tOUTCOBIDIR Cloc k -t o-out put delay for bidire ctional pins with glob al cl ock at IOE regis te r C1 = 35 pF
tXZBIDIR Sync hronous IOE out put buf fe r dis able delay C1 = 35 pF
tZXBIDIR Synchronous IOE output buffer enable delay, slow slew rate= off C1 = 35 pF
62 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figures 29 and 30 show the asynchronous and synchronous timing
waveforms, respectively, or the EAB macroparameters in Tables 26
and 27.
Figu re 29. EAB As ynchronous Timing W ave f or ms
EAB Asynchronous Write
EAB Asynchronous Read
WE
a0
d0 d3
t
EABRCCOMB
a1 a2 a3
d2
t
EABAA
d1
Address
Data-Out
WE
a0
din1 dout2
t
EABDD
a1 a2
din1
din0
t
EABWCCOMB
t
EABWASU
t
EABWAH
t
EABWDH
t
EABWDSU
t
EABWP
din0
Data-In
Address
Data-Out
Altera Corporation 63
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Figure 30. EA B Synchron ous Tim i ng Wavef orms
Tables 31 through 37 show EPF10K30E device internal and external
timing parameters.
WE
CLK
EAB Synchronous Read
a0
d2
t
EABDATASU
t
EABRCREG
t
EABDATACO
a1 a2 a3
d1
t
EABDATAH
a0
WE
CLK
dout0 din1 din2 din3 din2
t
EABWESU
t
EABWCREG
t
EABWEH
t
EABDATACO
a1 a2 a3 a2
din3
din2
din1
t
EABDATAH
t
EABDATASU
EAB Synchronous Write (EAB Output Registers Used)
dout1
Address
Data-Out
Address
Data-Out
Data-In
Table 31. EPF10K30E Device LE Timing Microparameters (Part 1 of 2) Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tLUT 0.7 0.8 1.1 ns
tCLUT 0.5 0.6 0.8 ns
tRLUT 0.6 0.7 1.0 ns
tPACKED 0.3 0.4 0.5 ns
tEN 0.6 0.8 1.0 ns
tCICO 0.1 0.1 0.2 ns
tCGEN 0.4 0.5 0.7 ns
64 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
tCGENR 0.1 0.1 0.2 ns
tCASC 0.6 0.8 1.0 ns
tC0.0 0.0 0.0 ns
tCO 0.3 0.4 0.5 ns
tCOMB 0.4 0.4 0.6 ns
tSU 0.4 0.6 0.6 ns
tH0.7 1.0 1.3 ns
tPRE 0.8 0.9 1.2 ns
tCLR 0.8 0.9 1.2 ns
tCH 2.0 2.5 2.5 ns
tCL 2.0 2.5 2.5 ns
Table 32. EPF 10K30E Dev i ce IOE Timing Mi croparamet ers Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tIOD 2.4 2.8 3.8 ns
tIOC 0.3 0.4 0.5 ns
tIOCO 1.0 1.1 1.6 ns
tIOCOMB 0.0 0.0 0.0 ns
tIOSU 1.2 1.4 1.9 ns
tIOH 0.3 0.4 0.5 ns
tIOCLR 1.0 1.1 1.6 ns
tOD1 1.9 2.3 3.0 ns
tOD2 1.4 1.8 2.5 ns
tOD3 4.4 5.2 7.0 ns
tXZ 2.7 3.1 4.3 ns
tZX1 2.7 3.1 4.3 ns
tZX2 2.2 2.6 3.8 ns
tZX3 5.2 6.0 8.3 ns
tINREG 3.4 4.1 5.5 ns
tIOFD 0.8 1.3 2.4 ns
tINCOMB 0.8 1.3 2.4 ns
Table 31. EPF10K30E Dev ice LE Tim i ng Mic roparameters (Par t 2 of 2) Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
Altera Corporation 65
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Table 33. EPF10K30E Device EAB Internal Microparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABDATA1 1.7 2.0 2.3 ns
tEABDATA1 0.6 0.7 0.8 ns
tEABWE1 1.1 1.3 1.4 ns
tEABWE2 0.4 0.4 0.5 ns
tEABRE1 0.8 0.9 1.0 ns
tEABRE2 0.4 0.4 0.5 ns
tEABCLK 0.0 0.0 0. 0 ns
tEABCO 0.3 0.3 0.4 ns
tEABBYPASS 0.5 0.6 0.7 ns
tEABSU 0.9 1.0 1.2 ns
tEABH 0.4 0.4 0.5 ns
tEABCLR 0.3 0.3 0.3 ns
tAA 3.2 3.8 4.4 ns
tWP 2.5 2.9 3.3 ns
tRP 0.9 1.1 1.2 ns
tWDSU 0.9 1.0 1.1 ns
tWDH 0.1 0.1 0.1 ns
tWASU 1.7 2.0 2.3 ns
tWAH 1.8 2.1 2.4 ns
tRASU 3.1 3.7 4.2 ns
tRAH 0.2 0.2 0.2 ns
tWO 2.5 2.9 3.3 ns
tDD 2.5 2.9 3.3 ns
tEABOUT 0.5 0.6 0.7 ns
tEABCH 1.5 2.0 2.3 ns
tEABCL 2.5 2.9 3.3 ns
66 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Table 34. EPF 10K30E Dev i ce EAB Internal Ti mi ng Macroparamet ers Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABAA 6.4 7.6 8.8 ns
tEABRCOMB 6.4 7.6 8.8 ns
tEABRCREG 4.4 5.1 6.0 ns
tEABWP 2.5 2.9 3.3 ns
tEABWCOMB 6.0 7.0 8.0 ns
tEABWCREG 6.8 7.8 9.0 ns
tEABDD 5.7 6.7 7.7 ns
tEABDATACO 0.8 0.9 1.1 ns
tEABDATASU 1.5 1.7 2.0 ns
tEABDATAH 0.0 0.0 0.0 ns
tEABWESU 1.3 1.4 1.7 ns
tEABWEH 0.0 0.0 0.0 ns
tEABWDSU 1.5 1.7 2.0 ns
tEABWDH 0.0 0.0 0.0 ns
tEABWASU 3.0 3.6 4.3 ns
tEABWAH 0.5 0.5 0.4 ns
tEABWO 5.1 6.0 6.8 ns
Altera Corporation 67
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Table 35. EPF10K30E Device Interconnect Timing Microparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDIN2IOE 1.8 2.4 2.9 ns
tDIN2LE 1.5 1.8 2.4 ns
tDIN2DATA 1.5 1.8 2.2 ns
tDCLK2IOE 2.2 2.6 3.0 ns
tDCLK2LE 1.5 1.8 2.4 ns
tSAMELAB 0.1 0.2 0.3 ns
tSAMEROW 2.0 2.4 2.7 ns
tSAMECOLUMN 0.7 1.0 0.8 ns
tDIFFROW 2.7 3.4 3.5 ns
tTWOROWS 4.7 5.8 6.2 ns
tLEPERIPH 2.7 3.4 3.8 ns
tLABCARRY 0.3 0.4 0.5 ns
tLABCASC 0.8 0.8 1.1 ns
Table 36. EPF10K30E External Timing Parameters Notes (1), (2)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDRR 8.0 9.5 12.5 ns
tINSU (3) 2.1 2.5 3.9 ns
tINH (3) 0.0 0.0 0.0 ns
tOUTCO (3) 2. 0 4.9 2. 0 5.9 2.0 7.6 ns
tINSU (4) 1.1 1.5 – ns
tINH (4) 0.0 0.0 – ns
tOUTCO (4) 0.5 3.9 0.5 4.9 – – ns
tPCISU 3.0 4.2 – ns
tPCIH 0.0 0.0 – ns
tPCICO 2.0 6.0 2.0 7.5 – – ns
68 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Notes to tables:
(1) All timing parameters are described in Tables 24 through 30 in this data sheet.
(2) The se paramet ers ar e spe cified by characterizati on .
(3) This parameter is meas ured without the use of the Clock L ock or Clock B oost circuits.
(4) This paramete r is measured with the u s e of the Clock L oc k or Cloc kBoost circuits.
Tables 38 through 44 show EPF10K50E device internal an d external
timing parameters.
Table 37. EPF10K30E External Bidi rectional Timing Par ameters Notes (1), (2)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tINSUBIDIR (3) 2.8 3.9 5.2 ns
tINHBIDIR (3) 0.0 0.0 0.0 ns
tINSUBIDIR (4) 3.8 4.9 – ns
tINHBIDIR (4) 0.0 0.0 – ns
tOUTCOBIDIR (3) 2.0 4.9 2.0 5.9 2.0 7.6 ns
tXZBIDIR (3) 6.1 7.5 9.7 ns
tZXBIDIR (3) 6.1 7.5 9.7 ns
tOUTCOBIDIR (4) 0.5 3.9 0.5 4.9 – – ns
tXZBIDIR (4) 5.1 6.5 – ns
tZXBIDIR (4) 5.1 6.5 – ns
Table 38. EPF10K50E Dev ice LE Tim i ng Mic roparameters (Par t 1 of 2) Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tLUT 0.6 0.9 1.3 ns
tCLUT 0.5 0.6 0.8 ns
tRLUT 0.7 0.8 1.1 ns
tPACKED 0.4 0.5 0.6 ns
tEN 0.6 0.7 0.9 ns
tCICO 0.2 0.2 0.3 ns
tCGEN 0.5 0.5 0.8 ns
tCGENR 0.2 0.2 0.3 ns
tCASC 0.8 1.0 1.4 ns
tC0.5 0.6 0.8 ns
tCO 0.7 0.7 0.9 ns
tCOMB 0.5 0.6 0.8 ns
tSU 0.7 0.7 0.8 ns
Altera Corporation 69
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
tH0.9 1.0 1.4 ns
tPRE 0.5 0.6 0.8 ns
tCLR 0.5 0.6 0.8 ns
tCH 2.0 2.5 3.0 ns
tCL 2.0 2.5 3.0 ns
Table 39. EPF10K50E Device IOE Timing Microparameters No te (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tIOD 2.2 2.4 3.3 ns
tIOC 0.3 0.3 0.5 ns
tIOCO 1.0 1.0 1.4 ns
tIOCOMB 0.0 0.0 0.2 ns
tIOSU 1.0 1.2 1.7 ns
tIOH 0.3 0.3 0.5 ns
tIOCLR 0.9 1.0 1.4 ns
tOD1 0.8 0.9 1.2 ns
tOD2 0.3 0.4 0.7 ns
tOD3 3.0 3.5 3.5 ns
tXZ 1.4 1.7 2.3 ns
tZX1 1.4 1.7 2.3 ns
tZX2 0.9 1.2 1.8 ns
tZX3 3.6 4.3 4.6 ns
tINREG 4.9 5.8 7.8 ns
tIOFD 2.8 3.3 4.5 ns
tINCOMB 2.8 3.3 4.5 ns
Table 38. EPF10K50E Device LE Timing Microparameters (Part 2 of 2) Not e (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
70 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Table 40. EPF10K50E Device EAB Internal Microparameters Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABDATA1 1.7 2.0 2.7 ns
tEABDATA1 0.6 0.7 0.9 ns
tEABWE1 1.1 1.3 1.8 ns
tEABWE2 0.4 0.4 0.6 ns
tEABRE1 0.8 0.9 1.2 ns
tEABRE2 0.4 0.4 0.6 ns
tEABCLK 0.0 0.0 0.0 ns
tEABCO 0.3 0.3 0.5 ns
tEABBYPASS 0.5 0.6 0.8 ns
tEABSU 0.9 1.0 1.4 ns
tEABH 0.4 0.4 0.6 ns
tEABCLR 0.3 0.3 0.5 ns
tAA 3.2 3.8 5.1 ns
tWP 2.5 2.9 3.9 ns
tRP 0.9 1.1 1.5 ns
tWDSU 0.9 1.0 1.4 ns
tWDH 0.1 0.1 0.2 ns
tWASU 1.7 2.0 2.7 ns
tWAH 1.8 2.1 2.9 ns
tRASU 3.1 3.7 5.0 ns
tRAH 0.2 0.2 0.3 ns
tWO 2.5 2.9 3.9 ns
tDD 2.5 2.9 3.9 ns
tEABOUT 0.5 0.6 0.8 ns
tEABCH 1.5 2.0 2.5 ns
tEABCL 2.5 2.9 3.9 ns
Altera Corporation 71
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Table 41. EPF10K50E Device EAB Internal Timing Macroparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABAA 6.4 7.6 10.2 ns
tEABRCOMB 6.4 7.6 10.2 ns
tEABRCREG 4.4 5.1 7.0 ns
tEABWP 2.5 2.9 3.9 ns
tEABWCOMB 6.0 7.0 9.5 ns
tEABWCREG 6.8 7.8 10.6 ns
tEABDD 5.7 6.7 9.0 ns
tEABDATACO 0.8 0.9 1.3 ns
tEABDATASU 1.5 1.7 2.3 ns
tEABDATAH 0.0 0.0 0.0 ns
tEABWESU 1.3 1.4 2.0 ns
tEABWEH 0.0 0.0 0.0 ns
tEABWDSU 1.5 1.7 2.3 ns
tEABWDH 0.0 0.0 0.0 ns
tEABWASU 3.0 3.6 4.8 ns
tEABWAH 0.5 0.5 0.8 ns
tEABWO 5.1 6.0 8.1 ns
Table 42. EPF10K50E Device Interconnect Timing Microparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDIN2IOE 3.5 4.3 5.6 ns
tDIN2LE 2.1 2.5 3.4 ns
tDIN2DATA 2.2 2.4 3.1 ns
tDCLK2IOE 2.9 3.5 4.7 ns
tDCLK2LE 2.1 2.5 3.4 ns
tSAMELAB 0.1 0.1 0.2 ns
tSAMEROW 1.1 1.1 1.5 ns
tSAMECOLUMN 0.8 1.0 1.3 ns
tDIFFROW 1.9 2.1 2.8 ns
tTWOROWS 3.0 3.2 4.3 ns
tLEPERIPH 3.1 3.3 3.7 ns
tLABCARRY 0.1 0.1 0.2 ns
tLABCASC 0.3 0.3 0.5 ns
72 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Notes to tables:
(1) All timing parameters are described in Tables 24 through 30 in this data sheet.
(2) The se paramet ers ar e spe cified by characterizati on .
Tables 45 through 51 show E PF1 0K 1 00 E de vice inte r nal and ex te rn al
timing parameters.
Table 43. EPF10K50E Ext ernal Timi ng Parameters Notes (1), (2)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDRR 8.5 10.0 13.5 ns
tINSU 2.7 3.2 4.3 ns
tINH 0.0 0.0 0.0 ns
tOUTCO 2.0 4.5 2.0 5.2 2.0 7.3 ns
tPCISU 3.0 4. 2 - ns
tPCIH 0.0 0. 0 - ns
tPCICO 2.0 6.0 2.0 7.7 - - ns
Table 44. EPF10K50E External Bidi rectional Timing Par ameters Notes (1), (2)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tINSUBIDIR 2.7 3.2 4.3 ns
tINHBIDIR 0.0 0.0 0.0 ns
tOUTCOBIDIR 2.0 4.5 2.0 5.2 2.0 7.3 ns
tXZBIDIR 6.8 7.8 10.1 ns
tZXBIDIR 6.8 7.8 10.1 ns
Table 45. EPF10K100E De vice LE Timi ng Mi crop aram et ers Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tLUT 0.7 1.0 1.5 ns
tCLUT 0.5 0.7 0.9 ns
tRLUT 0.6 0.8 1.1 ns
tPACKED 0.3 0.4 0.5 ns
tEN 0.2 0.3 0.3 ns
tCICO 0.1 0.1 0.2 ns
tCGEN 0.4 0.5 0.7 ns
Altera Corporation 73
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
tCGENR 0.1 0.1 0.2 ns
tCASC 0.6 0.9 1.2 ns
tC0.8 1.0 1.4 ns
tCO 0.6 0.8 1.1 ns
tCOMB 0.4 0.5 0.7 ns
tSU 0.4 0.6 0.7 ns
tH0.5 0.7 0.9 ns
tPRE 0.8 1.0 1.4 ns
tCLR 0.8 1.0 1.4 ns
tCH 1.5 2.0 2.5 ns
tCL 1.5 2.0 2.5 ns
Table 46. EPF10K100E Device IOE Timing Microparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tIOD 1.7 2.0 2.6 ns
tIOC 0.0 0.0 0.0 ns
tIOCO 1.4 1.6 2.1 ns
tIOCOMB 0.5 0.7 0.9 ns
tIOSU 0.8 1.0 1.3 ns
tIOH 0.7 0.9 1.2 ns
tIOCLR 0.5 0.7 0.9 ns
tOD1 3.0 4.2 5.6 ns
tOD2 3.0 4.2 5.6 ns
tOD3 4.0 5.5 7.3 ns
tXZ 3.5 4.6 6.1 ns
tZX1 3.5 4.6 6.1 ns
tZX2 3.5 4.6 6.1 ns
tZX3 4.5 5.9 7.8 ns
tINREG 2.0 2.6 3.5 ns
tIOFD 0.5 0.8 1.2 ns
tINCOMB 0.5 0.8 1.2 ns
Table 45. EPF10K100E Device LE Timing Microparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
74 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Table 47. EPF10K100E De vice EAB Intern al Mic ropa rameters Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABDATA1 1.5 2.0 2.6 ns
tEABDATA1 0.0 0.0 0.0 ns
tEABWE1 1.5 2.0 2.6 ns
tEABWE2 0.3 0.4 0.5 ns
tEABRE1 0.3 0.4 0.5 ns
tEABRE2 0.0 0.0 0.0 ns
tEABCLK 0.0 0.0 0.0 ns
tEABCO 0.3 0.4 0.5 ns
tEABBYPASS 0.1 0.1 0.2 ns
tEABSU 0.8 1.0 1.4 ns
tEABH 0.1 0.1 0.2 ns
tEABCLR 0.3 0.4 0.5 ns
tAA 4.0 5.1 6.6 ns
tWP 2.7 3.5 4.7 ns
tRP 1.0 1.3 1.7 ns
tWDSU 1.0 1.3 1.7 ns
tWDH 0.2 0.2 0.3 ns
tWASU 1.6 2.1 2.8 ns
tWAH 1.6 2.1 2.8 ns
tRASU 3.0 3.9 5.2 ns
tRAH 0.1 0.1 0.2 ns
tWO 1.5 2.0 2.6 ns
tDD 1.5 2.0 2.6 ns
tEABOUT 0.2 0.3 0.3 ns
tEABCH 1.5 2.0 2.5 ns
tEABCL 2.7 3.5 4.7 ns
Table 48. EPF10K100E De vice EAB Intern al Tim i ng Macrop aram et ers (Part 1 of 2) Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABAA 5.9 7.6 9.9 ns
tEABRCOMB 5.9 7.6 9.9 ns
tEABRCREG 5.1 6.5 8.5 ns
tEABWP 2.7 3.5 4.7 ns
Altera Corporation 75
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
tEABWCOMB 5.9 7.7 10.3 ns
tEABWCREG 5.4 7.0 9.4 ns
tEABDD 3.4 4.5 5.9 ns
tEABDATACO 0.5 0.7 0.8 ns
tEABDATASU 0.8 1.0 1.4 ns
tEABDATAH 0.1 0.1 0.2 ns
tEABWESU 1.1 1.4 1.9 ns
tEABWEH 0.0 0.0 0.0 ns
tEABWDSU 1.0 1.3 1.7 ns
tEABWDH 0.2 0.2 0.3 ns
tEABWASU 4.1 5.2 6.8 ns
tEABWAH 0.0 0.0 0.0 ns
tEABWO 3.4 4.5 5.9 ns
Table 49. EPF10K100E Device Interconnect Timing Microparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDIN2IOE 3.1 3.6 4.4 ns
tDIN2LE 0.3 0.4 0.5 ns
tDIN2DATA 1.6 1.8 2.0 ns
tDCLK2IOE 0.8 1.1 1.4 ns
tDCLK2LE 0.3 0.4 0.5 ns
tSAMELAB 0.1 0.1 0.2 ns
tSAMEROW 1.5 2.5 3.4 ns
tSAMECOLUMN 0.4 1.0 1.6 ns
tDIFFROW 1.9 3.5 5.0 ns
tTWOROWS 3.4 6.0 8.4 ns
tLEPERIPH 4.3 5.4 6.5 ns
tLABCARRY 0.5 0.7 0.9 ns
tLABCASC 0.8 1.0 1.4 ns
Table 48. EPF10K100E Device EAB Internal Timing Macroparameters (Part 2 of 2) Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
76 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Notes to tables:
(1) All timing parameters are described in Tables 24 through 30 in this data sheet.
(2) The se paramet ers ar e spe cified by characterizati on .
(3) This parameter is meas ured without the use of the Clock L ock or Clock B oost circuits.
(4) This paramete r is measured with the u s e of the Clock L oc k or Cloc kBoost circuits.
Table 50. EPF10K100E Extern al Timi ng Parameters Notes (1), (2)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDRR 9.0 12.0 16.0 ns
tINSU (3) 2.0 2.5 3.3 ns
tINH (3) 0.0 0.0 0.0 ns
tOUTCO (3) 2.0 5.2 2.0 6.9 2.0 9.1 ns
tINSU (4) 2.0 2.2 – ns
tINH (4) 0.0 0.0 – ns
tOUTCO (4) 0.5 3.0 0.5 4.6 – – ns
tPCISU 3.0 6.2 – ns
tPCIH 0.0 0.0 – ns
tPCICO 2.0 6.0 2.0 6.9 – – ns
Table 51. EPF10K100E External Bidir ectio nal Timing Para mete rs Notes (1), (2)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tINSUBIDIR (3) 1.7 2.5 3.3 ns
tINHBIDIR (3) 0.0 0.0 0.0 ns
tINSUBIDIR (4) 2.0 2.8 – ns
tINHBIDIR (4) 0.0 0.0 – ns
tOUTCOBIDIR (3) 2.0 5.2 2.0 6.9 2.0 9.1 ns
tXZBIDIR (3) 5.6 7.5 10.1 ns
tZXBIDIR (3) 5.6 7.5 10.1 ns
tOUTCOBIDIR (4) 0.5 3.0 0.5 4.6 – – ns
tXZBIDIR (4) 4.6 6.5 – ns
tZXBIDIR (4) 4.6 6.5 – ns
Altera Corporation 77
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Tables 52 through 58 show EPF1 0K130E device i nter nal an d external
timing parameters.
Table 52. EPF10K130E Device LE Timing Microparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tLUT 0.6 0.9 1.3 ns
tCLUT 0.6 0.8 1.0 ns
tRLUT 0.7 0.9 0.2 ns
tPACKED 0.3 0.5 0.6 ns
tEN 0.2 0.3 0.4 ns
tCICO 0.1 0.1 0.2 ns
tCGEN 0.4 0.6 0.8 ns
tCGENR 0.1 0.1 0.2 ns
tCASC 0.6 0.9 1.2 ns
tC0.3 0.5 0.6 ns
tCO 0.5 0.7 0.8 ns
tCOMB 0.3 0.5 0.6 ns
tSU 0.5 0.7 0.8 ns
tH0.6 0.7 1.0 ns
tPRE 0.9 1.2 1.6 ns
tCLR 0.9 1.2 1.6 ns
tCH 1.5 1.5 2.5 ns
tCL 1.5 1.5 2.5 ns
Table 53. EPF10K130E Device IOE Timing Microparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tIOD 1.3 1.5 2.0 ns
tIOC 0.0 0.0 0.0 ns
tIOCO 0.6 0.8 1.0 ns
tIOCOMB 0.6 0.8 1.0 ns
tIOSU 1.0 1.2 1.6 ns
tIOH 0.9 0.9 1.4 ns
tIOCLR 0.6 0.8 1.0 ns
tOD1 2.8 4.1 5.5 ns
tOD2 2.8 4.1 5.5 ns
78 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
tOD3 4.0 5.6 7.5 ns
tXZ 2.8 4.1 5.5 ns
tZX1 2.8 4.1 5.5 ns
tZX2 2.8 4.1 5.5 ns
tZX3 4.0 5.6 7.5 ns
tINREG 2.5 3.0 4.1 ns
tIOFD 0.4 0.5 0.6 ns
tINCOMB 0.4 0.5 0.6 ns
Table 54. EPF10K130E De vice EAB Intern al Mic ropa rameters (Part 1 of 2) Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABDATA1 1.5 2.0 2.6 ns
tEABDATA2 0.0 0.0 0.0 ns
tEABWE1 1.5 2.0 2.6 ns
tEABWE2 0.3 0.4 0.5 ns
tEABRE1 0.3 0.4 0.5 ns
tEABRE2 0.0 0.0 0.0 ns
tEABCLK 0.0 0.0 0.0 ns
tEABCO 0.3 0.4 0.5 ns
tEABBYPASS 0.1 0.1 0.2 ns
tEABSU 0.8 1.0 1.4 ns
tEABH 0.1 0.2 0.2 ns
tEABCLR 0.3 0.4 0.5 ns
tAA 4.0 5.0 6.6 ns
tWP 2.7 3.5 4.7 ns
tRP 1.0 1.3 1.7 ns
tWDSU 1.0 1.3 1.7 ns
tWDH 0.2 0.2 0.3 ns
tWASU 1.6 2.1 2.8 ns
tWAH 1.6 2.1 2.8 ns
tRASU 3.0 3.9 5.2 ns
tRAH 0.1 0.1 0.2 ns
tWO 1.5 2.0 2.6 ns
Table 53. EPF10K130E De vice I O E Timi ng Mi crop arame t ers No te (1 )
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
Altera Corporation 79
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
tDD 1.5 2.0 2.6 ns
tEABOUT 0.2 0.3 0.3 ns
tEABCH 1.5 2.0 2.5 ns
tEABCL 2.7 3.5 4.7 ns
Table 55. EPF10K130E Device EAB Internal Timing Macroparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABAA 5.9 7.5 9.9 ns
tEABRCOMB 5.9 7.5 9.9 ns
tEABRCREG 5.1 6.4 8.5 ns
tEABWP 2.7 3.5 4.7 ns
tEABWCOMB 5.9 7.7 10.3 ns
tEABWCREG 5.4 7.0 9.4 ns
tEABDD 3.4 4.5 5.9 ns
tEABDATACO 0.5 0.7 0.8 ns
tEABDATASU 0.8 1.0 1.4 ns
tEABDATAH 0.1 0.1 0.2 ns
tEABWESU 1.1 1.4 1.9 ns
tEABWEH 0.0 0.0 0.0 ns
tEABWDSU 1.0 1.3 1.7 ns
tEABWDH 0.2 0.2 0.3 ns
tEABWASU 4.1 5.1 6.8 ns
tEABWAH 0.0 0.0 0.0 ns
tEABWO 3.4 4.5 5.9 ns
Table 54. EPF10K130E Device EAB Internal Microparameters ( Part 2 of 2) Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
80 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Table 56. EPF10K130E De vice I nterconnect Timing Microparameters Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDIN2IOE 2.8 3.5 4.4 ns
tDIN2LE 0.7 1.2 1.6 ns
tDIN2DATA 1.6 1.9 2.2 ns
tDCLK2IOE 1.6 2.1 2.7 ns
tDCLK2LE 0.7 1.2 1.6 ns
tSAMELAB 0.1 0.2 0.2 ns
tSAMEROW 1.9 3.4 5.1 ns
tSAMECOLUMN 0.9 2.6 4.4 ns
tDIFFROW 2.8 6.0 9.5 ns
tTWOROWS 4.7 9.4 14.6 ns
tLEPERIPH 3.1 4.7 6.9 ns
tLABCARRY 0.6 0.8 1.0 ns
tLABCASC 0.9 1.2 1.6 ns
Table 57. EPF10K130E Extern al Timi ng Parameters Notes (1), (2)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDRR 9. 0 12.0 16.0 ns
tINSU (3) 1.9 2.1 3.0 ns
tINH (3) 0.0 0.0 0.0 ns
tOUTCO (3) 2.0 5.0 2.0 7.0 2.0 9.2 ns
tINSU (4) 0.9 1.1 – ns
tINH (4) 0.0 0.0 – ns
tOUTCO (4) 0.5 4.0 0.5 6.0 – – ns
tPCISU 3.0 6.2 – ns
tPCIH 0.0 0.0 – ns
tPCICO 2.0 6.0 2.0 6.9 – – ns
Altera Corporation 81
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Notes to table s:
(1) All timing parameters are described in Tables 24 through 30 in this data sheet.
(2) Th ese parameters are specified by ch ar ac terization.
(3) This parameter is measured without the use of the ClockLock or ClockBoost circuits.
(4) This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Tables 59 through 65 show EPF1 0K200E device i nter nal an d external
timing parameters.
Table 58. EPF10K130E External Bidirectional Timing Parameters Notes (1), (2)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tINSUBIDIR (3) 2.2 2.4 3.2 ns
tINHBIDIR (3) 0.0 0.0 0.0 ns
tINSUBIDIR (4) 2.8 3.0 – ns
tINHBIDIR (4) 0.0 0.0 – ns
tOUTCOBIDIR (3) 2.0 5.0 2.0 7.0 2.0 9.2 ns
tXZBIDIR (3) 5.6 8.1 10.8 ns
tZXBIDIR (3) 5.6 8.1 10.8 ns
tOUTCOBIDIR (4) 0.5 4.0 0.5 6.0 – – ns
tXZBIDIR (4) 4.6 7.1 – ns
tZXBIDIR (4) 4.6 7.1 – ns
Table 59. EPF10K200E Device LE Timing Microparameters (Part 1 of 2) Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tLUT 0.7 0.8 1.2 ns
tCLUT 0.4 0.5 0.6 ns
tRLUT 0.6 0.7 0.9 ns
tPACKED 0.3 0.5 0.7 ns
tEN 0.4 0.5 0.6 ns
tCICO 0.2 0.2 0.3 ns
tCGEN 0.4 0.4 0.6 ns
tCGENR 0.2 0.2 0.3 ns
tCASC 0.7 0.8 1.2 ns
tC0.5 0.6 0.8 ns
tCO 0.5 0.6 0.8 ns
tCOMB 0.4 0.6 0.8 ns
tSU 0.4 0.6 0.7 ns
82 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
tH0.9 1.1 1.5 ns
tPRE 0.5 0.6 0.8 ns
tCLR 0.5 0.6 0.8 ns
tCH 2.0 2.5 3.0 ns
tCL 2.0 2.5 3.0 ns
Table 60. EPF10K200E De vice I O E Timi ng Mi crop arame t ers No te (1 )
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tIOD 1.6 1.9 2.6 ns
tIOC 0.3 0.3 0.5 ns
tIOCO 1.6 1.9 2.6 ns
tIOCOMB 0.5 0.6 0.8 ns
tIOSU 0.8 0.9 1.2 ns
tIOH 0.7 0.8 1.1 ns
tIOCLR 0.2 0.2 0.3 ns
tOD1 0.6 0.7 0.9 ns
tOD2 0.1 0.2 0.7 ns
tOD3 2.5 3.0 3.9 ns
tXZ 4.4 5.3 7.1 ns
tZX1 4.4 5.3 7.1 ns
tZX2 3.9 4.8 6.9 ns
tZX3 6.3 7.6 10.1 ns
tINREG 4.8 5.7 7.7 ns
tIOFD 1.5 1.8 2.4 ns
tINCOMB 1.5 1.8 2.4 ns
Table 59. EPF10K200E De vice LE Timi ng Mi crop aram et ers (Part 2 of 2) Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
Altera Corporation 83
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Table 61. EPF10K200E Device EAB Internal Microparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABDATA1 2.0 2.4 3.2 ns
tEABDATA1 0.4 0.5 0.6 ns
tEABWE1 1.4 1.7 2.3 ns
tEABWE2 0.0 0.0 0.0 ns
tEABRE1 000ns
tEABRE2 0.4 0.5 0.6 ns
tEABCLK 0.0 0.0 0.0 ns
tEABCO 0.8 0.9 1.2 ns
tEABBYPASS 0.0 0.1 0.1 ns
tEABSU 0.9 1.1 1.5 ns
tEABH 0.4 0.5 0.6 ns
tEABCLR 0.8 0.9 1.2 ns
tAA 3.1 3.7 4.9 ns
tWP 3.3 4.0 5.3 ns
tRP 0.9 1.1 1.5 ns
tWDSU 0.9 1.1 1.5 ns
tWDH 0.1 0.1 0.1 ns
tWASU 1.3 1.6 2.1 ns
tWAH 2.1 2.5 3.3 ns
tRASU 2.2 2.6 3.5 ns
tRAH 0.1 0.1 0.2 ns
tWO 2.0 2.4 3.2 ns
tDD 2.0 2.4 3.2 ns
tEABOUT 0.0 0.1 0.1 ns
tEABCH 1.5 2.0 2.5 ns
tEABCL 3.3 4.0 5.3 ns
Table 62. EPF10K200E Device EAB Internal Timing Macroparameters (Part 1 of 2) Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABAA 5.1 6.4 8.4 ns
tEABRCOMB 5.1 6.4 8.4 ns
tEABRCREG 4.8 5.7 7.6 ns
tEABWP 3.3 4.0 5.3 ns
84 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
tEABWCOMB 6.7 8.1 10.7 ns
tEABWCREG 6.6 8.0 10.6 ns
tEABDD 4.0 5.1 6.7 ns
tEABDATACO 0.8 1.0 1.3 ns
tEABDATASU 1.3 1.6 2.1 ns
tEABDATAH 0.0 0.0 0.0 ns
tEABWESU 0.9 1.1 1.5 ns
tEABWEH 0.4 0.5 0.6 ns
tEABWDSU 1.5 1.8 2.4 ns
tEABWDH 0.0 0.0 0.0 ns
tEABWASU 3.0 3.6 4.7 ns
tEABWAH 0.4 0.5 0.7 ns
tEABWO 3.4 4.4 5.8 ns
Table 63. EPF10K200E De vice Inter connect Ti min g Microparameters Not e (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDIN2IOE 4.2 4.6 5.7 ns
tDIN2LE 1.7 1.7 2.0 ns
tDIN2DATA 1.9 2.1 3.0 ns
tDCLK2IOE 2.5 2.9 4.0 ns
tDCLK2LE 1.7 1.7 2.0 ns
tSAMELAB 0.1 0.1 0.2 ns
tSAMEROW 2.3 2.6 3.6 ns
tSAMECOLUMN 2.5 2.7 4.1 ns
tDIFFROW 4.8 5.3 7.7 ns
tTWOROWS 7.1 7.9 11.3 ns
tLEPERIPH 7.0 7.6 9.0 ns
tLABCARRY 0.1 0.1 0.2 ns
tLABCASC 0.9 1.0 1.4 ns
Table 62. EPF10K200E De vice EAB Intern al Timing Macropara mete rs (Part 2 o f 2) Note (1 )
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
Altera Corporation 85
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Notes to table s:
(1) All timing parameters are described in Tables 24 through 30 in this data sheet.
(2) Th ese parameters are specified by ch ar ac terization.
Tables 66 through 79 show E PF10K 50S and EPF10K 200S devic e external
timing parameters.
Table 64. EPF10K200E External Timing Parameters Notes (1), (2)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDRR 10.0 12.0 16.0 ns
tINSU 2.8 3.4 4.4 ns
tINH 0.0 0.0 0.0 ns
tOUTCO 2.0 4.5 2.0 5.3 2.0 7.8 ns
tPCISU 3.0 6.2 - ns
tPCIH 0.0 0.0 - ns
tPCICO 2.0 6.0 2.0 8.9 - - ns
Table 65. EPF10K200E External Bidirectional Timing Parameters Notes (1) , (2)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tINSUBIDIR 3.0 4.0 5.5 ns
tINHBIDIR 0.0 0.0 0.0 ns
tOUTCOBIDIR 2.0 4.5 2.0 5.3 2.0 7.8 ns
tXZBIDIR 8.1 9.5 13.0 ns
tZXBIDIR 8.1 9.5 13.0 ns
Table 66. EPF10K50S Device LE Timing Microparameters (Part 1 of 2) Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tLUT 0.6 0.8 1.1 ns
tCLUT 0.5 0.6 0.8 ns
tRLUT 0.6 0.7 0.9 ns
tPACKED 0.2 0.3 0.4 ns
tEN 0.6 0.7 0.9 ns
tCICO 0.1 0.1 0.1 ns
tCGEN 0.4 0.5 0.6 ns
86 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
tCGENR 0.1 0.1 0.1 ns
tCASC 0.5 0.8 1.0 ns
tC0.5 0.6 0.8 ns
tCO 0.6 0.6 0.7 ns
tCOMB 0.3 0.4 0.5 ns
tSU 0.5 0.6 0.7 ns
tH0.5 0.6 0.8 ns
tPRE 0.4 0.5 0.7 ns
tCLR 0.8 1.0 1.2 ns
tCH 2.0 2.5 3.0 ns
tCL 2.0 2.5 3.0 ns
Table 67. EPF10K50S Dev ice IOE Ti mi ng Mi crop aram eters Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tIOD 1.3 1.3 1.9 ns
tIOC 0.3 0.4 0.4 ns
tIOCO 1.7 2.1 2.6 ns
tIOCOMB 0.5 0.6 0.8 ns
tIOSU 0.8 1.0 1.3 ns
tIOH 0.4 0.5 0.6 ns
tIOCLR 0.2 0.2 0.4 ns
tOD1 1.2 1.2 1.9 ns
tOD2 0.7 0.8 1.7 ns
tOD3 2.7 3.0 4.3 ns
tXZ 4.7 5.7 7.5 ns
tZX1 4.7 5.7 7.5 ns
tZX2 4.2 5.3 7.3 ns
tZX3 6.2 7.5 9.9 ns
tINREG 3.5 4.2 5.6 ns
tIOFD 1.1 1.3 1.8 ns
tINCOMB 1.1 1.3 1.8 ns
Table 66. EPF10K50S Device LE Timing Mi croparameters (Part 2 of 2) Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
Altera Corporation 87
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Table 68. EPF10K50S Device EAB Internal Microparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABDATA1 1.7 2.4 3.2 ns
tEABDATA2 0.4 0.6 0.8 ns
tEABWE1 1.0 1.4 1.9 ns
tEABWE2 0.0 0.0 0.0 ns
tEABRE1 0.0 0.0 0.0
tEABRE2 0.4 0.6 0.8
tEABCLK 0.0 0.0 0.0 ns
tEABCO 0.8 1.1 1.5 ns
tEABBYPASS 0.0 0.0 0.0 ns
tEABSU 0.7 1.0 1.3 ns
tEABH 0.4 0.6 0.8 ns
tEABCLR 0.8 1.1 1.5
tAA 2.0 2.8 3.8 ns
tWP 2.0 2.8 3.8 ns
tRP 1.0 1.4 1.9
tWDSU 0.5 0.7 0.9 ns
tWDH 0.1 0.1 0.2 ns
tWASU 1.0 1.4 1.9 ns
tWAH 1.5 2.1 2.9 ns
tRASU 1.5 2.1 2.8
tRAH 0.1 0.1 0.2
tWO 2.1 2.9 4.0 ns
tDD 2.1 2.9 4.0 ns
tEABOUT 0.0 0.0 0.0 ns
tEABCH 1.5 2.0 2.5 ns
tEABCL 1.5 2.0 2.5 ns
88 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Table 69. EPF10K50S Devi ce EAB I nternal Timin g Macropar ameters No te (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABAA 3.7 5.2 7.0 ns
tEABRCCOMB 3.7 5.2 7.0 ns
tEABRCREG 3.5 4.9 6.6 ns
tEABWP 2.0 2.8 3.8 ns
tEABWCCOMB 4.5 6.3 8.6 ns
tEABWCREG 5.6 7.8 10.6 ns
tEABDD 3.8 5.3 7.2 ns
tEABDATACO 0.8 1.1 1.5 ns
tEABDATASU 1.1 1.6 2.1 ns
tEABDATAH 0.0 0.0 0.0 ns
tEABWESU 0.7 1.0 1.3 ns
tEABWEH 0.4 0.6 0.8 ns
tEABWDSU 1.2 1.7 2.2 ns
tEABWDH 0.0 0.0 0.0 ns
tEABWASU 1.6 2.3 3.0 ns
tEABWAH 0.9 1.2 1.8 ns
tEABWO 3.1 4.3 5.9 ns
Table 70. EPF10K50S Device Inte rconnect Timi ng Microparameters Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDIN2IOE 3.1 3.7 4.6 ns
tDIN2LE 1.7 2.1 2.7 ns
tDIN2DATA 2.7 3.1 5.1 ns
tDCLK2IOE 1.6 1.9 2.6 ns
tDCLK2LE 1.7 2.1 2.7 ns
tSAMELAB 0.1 0.1 0.2 ns
tSAMEROW 1.5 1.7 2.4 ns
tSAMECOLUMN 1.0 1.3 2.1 ns
tDIFFROW 2.5 3.0 4.5 ns
tTWOROWS 4.0 4.7 6.9 ns
tLEPERIPH 2.6 2.9 3.4 ns
tLABCARRY 0.1 0.2 0.2 ns
tLABCASC 0.8 1.0 1.3 ns
Altera Corporation 89
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Notes to table s:
(1) All timing parameters are described in Tables 24 through 30.
(2) This parameter is measured without use of the ClockLock or ClockBoost circuits.
(3) Th is p arameter is measu red with use of the Cl ockLock or ClockBoost circuits
Table 71. EPF10K50S External Timing Parameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDRR 8.0 9.5 12.5 ns
tINSU (2) 2.4 2.9 3.9 ns
tINH (2) 0.0 0.0 0.0 ns
tOUTCO (2) 2. 0 4.3 2.0 5.2 2.0 7.3 ns
tINSU (3) 2.4 2.9 ns
tINH (3) 0.0 0.0 ns
tOUTCO (3) 0.5 3.3 0.5 4.1 ns
tPCISU 2.4 2. 9 – ns
tPCIH 0.0 0.0 – ns
tPCICO 2.0 6.0 2. 0 7.7 – – ns
Table 72. EPF10K50S External Bidirectional Timing Parameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tINSUBIDIR (2) 2.7 3.2 4.3 ns
tINHBIDIR (2) 0.0 0.0 0.0 ns
tINHBIDIR (3) 0.0 0.0 – ns
tINSUBIDIR (3) 3.7 4.2 – ns
tOUTCOBIDIR (2) 2.0 4.5 2.0 5.2 2.0 7.3 ns
tXZBIDIR (2) 6.8 7.8 10.1 ns
tZXBIDIR (2) 6.8 7.8 10.1 ns
tOUTCOBIDIR (3) 0.5 3.5 0.5 4.2 – –
tXZBIDIR (3) 6.8 8.4 – ns
tZXBIDIR (3) 6.8 8.4 – ns
90 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Table 73. EPF10K200S Device Int ernal & Externa l Timing Par amet ers Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tLUT 0.7 0.8 1.2 ns
tCLUT 0.4 0.5 0.6 ns
tRLUT 0.5 0.7 0.9 ns
tPACKED 0.4 0.5 0.7 ns
tEN 0.6 0.5 0.6 ns
tCICO 0.1 0.2 0.3 ns
tCGEN 0.3 0.4 0.6 ns
tCGENR 0.1 0.2 0.3 ns
tCASC 0.7 0.8 1.2 ns
tC0.5 0.6 0.8 ns
tCO 0.5 0.6 0.8 ns
tCOMB 0.3 0.6 0.8 ns
tSU 0.4 0.6 0.7 ns
tH1.0 1.1 1.5 ns
tPRE 0.4 0.6 0.8 ns
tCLR 0.5 0.6 0.8 ns
tCH 2.0 2.5 3.0 ns
tCL 2.0 2.5 3.0 ns
Table 74. EPF10K200S Device IOE Timing Microparameters (Part 1 of 2) Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tIOD 1.8 1.9 2.6 ns
tIOC 0.3 0.3 0.5 ns
tIOCO 1.7 1.9 2.6 ns
tIOCOMB 0.5 0.6 0.8 ns
tIOSU 0.8 0.9 1.2 ns
tIOH 0.4 0.8 1.1 ns
tIOCLR 0.2 0.2 0.3 ns
tOD1 1.3 0.7 0.9 ns
tOD2 0.8 0.2 0.4 ns
tOD3 2.9 3.0 3.9 ns
tXZ 5.0 5.3 7.1 ns
tZX1 5.0 5.3 7.1 ns
Altera Corporation 91
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
tZX2 4.5 4.8 6.6 ns
tZX3 6.6 7.6 10.1 ns
tINREG 3.7 5.7 7.7 ns
tIOFD 1.8 3.4 4.0 ns
tINCOMB 1.8 3.4 4.0 ns
Table 75. EPF10K200S Device EAB Internal Microparameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABDATA1 1.8 2.4 3.2 ns
tEABDATA1 0.4 0.5 0.6 ns
tEABWE1 1.1 1.7 2.3 ns
tEABWE2 0.0 0.0 0.0 ns
tEABRE1 000ns
tEABRE2 0.4 0.5 0.6 ns
tEABCLK 0.0 0.0 0.0 ns
tEABCO 0.8 0.9 1.2 ns
tEABBYPASS 0.0 0.1 0.1 ns
tEABSU 0.7 1.1 1.5 ns
tEABH 0.4 0.5 0.6 ns
tEABCLR 0.8 0.9 1.2 ns
tAA 2.1 3.7 4.9 ns
tWP 2.1 4.0 5.3 ns
tRP 1.1 1.1 1.5 ns
tWDSU 0.5 1.1 1.5 ns
tWDH 0.1 0.1 0.1 ns
tWASU 1.1 1.6 2.1 ns
tWAH 1.6 2.5 3.3 ns
tRASU 1.6 2.6 3.5 ns
tRAH 0.1 0.1 0.2 ns
tWO 2.0 2.4 3.2 ns
tDD 2.0 2.4 3.2 ns
tEABOUT 0.0 0.1 0.1 ns
tEABCH 1.5 2.0 2.5 ns
tEABCL 2.1 2.8 3.8 ns
Table 74. EPF10K200S Device IOE Timing Microparameters (Part 2 of 2) Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
92 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Table 76. EPF10K200S De vice EAB Intern al Timing Macropara meters Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tEABAA 3.9 6.4 8.4 ns
tEABRCOMB 3.9 6.4 8.4 ns
tEABRCREG 3.6 5.7 7.6 ns
tEABWP 2.1 4.0 5.3 ns
tEABWCOMB 4.8 8.1 10.7 ns
tEABWCREG 5.4 8.0 10.6 ns
tEABDD 3.8 5.1 6.7 ns
tEABDATACO 0.8 1.0 1.3 ns
tEABDATASU 1.1 1.6 2.1 ns
tEABDATAH 0.0 0.0 0.0 ns
tEABWESU 0.7 1.1 1.5 ns
tEABWEH 0.4 0.5 0.6 ns
tEABWDSU 1.2 1.8 2.4 ns
tEABWDH 0.0 0.0 0.0 ns
tEABWASU 1.9 3.6 4.7 ns
tEABWAH 0.8 0.5 0.7 ns
tEABWO 3.1 4.4 5.8 ns
Table 77. EPF10K200S De vice I nterconnect Ti ming Microparamet ers (P art 1 of 2) Note (1)
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDIN2IOE 4.4 4.8 5.5 ns
tDIN2LE 0.6 0.6 0.9 ns
tDIN2DATA 1.8 2.1 2.8 ns
tDCLK2IOE 1.7 2.0 2.8 ns
tDCLK2LE 0.6 0.6 0.9 ns
tSAMELAB 0.1 0.1 0.2 ns
tSAMEROW 3.0 4.6 5.7 ns
tSAMECOLUMN 3.5 4.9 6.4 ns
tDIFFROW 6.5 9.5 12.1 ns
tTWOROWS 9.5 14.1 17.8 ns
tLEPERIPH 5.5 6.2 7.2 ns
tLABCARRY 0.3 0.1 0.2 ns
Altera Corporation 93
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Notes to table s:
(1) All timing parameters are described in Tables 24 through 30 in this data sheet.
(2) This parameter is measured without the use of the ClockLock or ClockBoost circuits.
(3) This parameter is measured with the use of the ClockLock or ClockBoost circuits.
tLABCASC 0.5 1.0 1.4 ns
Table 78. EPF10K200S External Timing Parameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tDRR 9.0 12.0 16.0 ns
tINSU (2) 3.1 3.7 4.7 ns
tINH (2) 0.0 0.0 0.0 ns
tOUTCO (2) 2.0 3.7 2.0 4.4 2.0 6.3 ns
tINSU(3) 2.1 2.7 – ns
tINH (3) 0.0 0.0 – ns
tOUTCO(3) 0.5 2.7 0.5 3.4 – – ns
tPCISU 3.0 4.2 – ns
tPCIH 0.0 0.0 – ns
tPCICO 2.0 6.0 2.0 8.9 – – ns
Table 79. EPF10K200S External Bidirectional Timing Parameters Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tINSUBIDIR (2) 2.3 3.4 4.4 ns
tINHBIDIR (2) 0.0 0.0 0.0 ns
tINSUBIDIR (3) 3.3 4.4 – ns
tINHBIDIR (3) 0.0 0.0 – ns
tOUTCOBIDIR (2) 2.0 3.7 2.0 4.4 2.0 6.3 ns
tXZBIDIR (2) 6.9 7.6 9.2 ns
tZXBIDIR (2) 5.9 6.6 – ns
tOUTCOBIDIR (3) 0.5 2.7 0.5 3.4 – – ns
tXZBIDIR (3) 6.9 7.6 9.2 ns
tZXBIDIR (3) 5.9 6.6 – ns
Table 77. EPF10K200S Device Interconnect Timing Microparameters (Part 2 of 2) Note (1)
Symbol -1 Sp eed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
94 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Power
Consumption
The supply powe r (P) for FLEX 10KE devices can be calculated with the
following equation:
P = PINT + PIO = (ICCSTANDBY + ICCACTIVE) × VCC + PIO
The ICCACTIVE value depends on the switching frequency and the
application logic. This valu e i s ca lcu lat ed b ased on the amount of c ur rent
that each LE typically consumes. The PIO value, which depends on the
device output load characteristics and switching frequency, can be
calculated using the guidelines given in Application Note 7 4 (Ev aluating
Power for Altera Devices).
Compar ed to the r est of the device, the embed d ed array co nsumes a
negligible amount of power. Therefore, the embedded array can be
ignored when calculating supply current.
The ICCACTIVE value can be calculated with the following equation:
ICCACTIVE = K × fMAX × N × togLC ×
Where:
fMAX = Maximum operating frequency in MHz
N = Total number of LEs used in the device
togLC = Average percent of LEs toggling at each clock
(typically 12.5%)
K=Constant
Table 80 provides the constant (K) values for FLEX 10KE devices.
This calcul ation provides an ICC e stimate b ased on t ypi cal condit ions with
no output load. The actual ICC should be verified during operation
because this measurement is sensitive to the actual pattern in the device
and the environmental operating conditions.
Table 80. FLEX 10KE K Con stant Value s
Device K Valu e
EPF10K30E 4.5
EPF10K50E 4.8
EPF10K50S 4.5
EPF10K100E 4.5
EPF10K130E 4.6
EPF10K200E 4.8
EPF10K200S 4.6
µ
A
M
Hz L
E
×
-
----------------------
----
Altera Corporation 95
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
To better reflect actual designs, the power model (and the constant K in
the power calculation equations) for continuous interconnect FLEX
devices assumes that LEs drive FastTrack Interconnect channels. In
contrast, the power model of segmented FPGAs assumes that all LEs drive
only one short interconnect segment. This assumption may lead to
inac cur at e resu lts whe n com pa red to measure d power consumption for
act ual de signs in segme nte d FPGAs.
Figure 31 shows the relationship between the current and operating
frequency of FLEX 10KE devices.
Figure 31. FL EX 10KE ICCACTIVE vs. Operating Frequency (Part 1 of 2)
0Frequency (MHz)
ICC
Supply
Current (mA)
100
80
60
40
20
50 100
EPF10K30E
0Frequency (MHz)
ICC Supply
Current (mA)
200
150
100
50
50 100
EPF10K50S
0Frequency (MHz)
300
200
100
50 100
EPF10K100E
ICC Supply
Current (mA)
0
Frequency (MHz)
I
CC Supply
Current (mA)
200
150
100
50
50 100
EPF10K50E
96 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Figure 31. FLEX 10KE ICCACTIVE vs. Oper a t in g Fr eq ue ncy (P art 2 of 2)
Configuration &
Operation
The FLEX 10KE architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The FLEX 10KE architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers up.
The pr ocess of physically l oading the SRAM data in to the device is ca lle d
configuration. Before configuration, as VCC rise s, the device initiates a
Power-On Reset ( POR). This POR ev ent cl ears the de vice and prepar es it
for configuration. The FLEX 10KE POR time does not exceed 50 µs.
When configuring with a configuration device, refer to the respective
configurat ion device data sheet for POR timing information.
0Frequency (MHz)
600
400
200
50 100
EPF10K200S
ICC
Supply
Current (mA)
0Frequency (MHz)
400
300
200
100
50 100
EPF10K130E
ICC Supply
Current (mA)
0
Frequency (MHz)
600
400
200
50 100
EPF10K200E
I
CC Supply
Current (mA)
Altera Corporation 97
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
During initialization, which occurs immediately after configuration, the
device resets registers, enab les I/O pin s, and b egins to operate as a l ogic
device. The I/O pins are tri-stated during power-up, and before and
during configuration. Together, the configuration and initialization
pr ocesses ar e called comman d mode; nor mal device operation is called user
mode.
SRA M confi gura tion elem en ts allo w FL EX 10KE devices to be
reconfi gured in-circu it by loading new co nfiguration data into t he device.
Real-time reconfiguration is performed by forcing the device into
command mode with a device pin, loading different configuration data,
reinit iali zing the devic e, and resuming use r-mode operat ion. The entire
reconfiguration process requires less than 85 ms and can be used to
reconfig ure an entire system dynamically. In-field upgrades can be
performed by distributing new configuration files.
Before and during con fi gu ration, all I/O pins (excep t de di cated inputs,
clock, or configuration pins) are pulled high by a weak pull-up resistor.
Progra mming Files
Despite being function- and pin-compatible, FLEX 10KE devices are not
programming- or configuration file-compatible with FLEX 10K or
FLEX 10KA devices. A design therefo re must be recompil ed before it is
transfe rred from a FLEX 10K or FLEX 10KA device to an equivalent
FLEX 10KE device. This recompilation should be performed both to create
a new programming or configuration file and to check design timing in
FLEX 10K E devices, which ha s differ e nt timing character istics than
FLEX 1 0K or FLEX 10KA device s.
FLEX 10KE devices are generally pin-compatible with equivalent
FLEX 10KA devices. In some cases, FLEX 10KE device s have fewer I/O
pins than the equivalent FLEX 10KA devices. Table 81 shows which
FLEX 10KE devices have fewer I/O pins than equivalent FLEX 10KA
devices. However, power, ground, JTAG, and configuration pins are the
same on FLEX 10KA and FLEX 10KE devices, enabling migration from a
FLEX 10KA de sign to a FLEX 10KE design.
98 Altera Corporation
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces D ata Sheet
Addition ally, the Alte ra software offer s several feat ures that help pla n for
future device migration by preventing the use of conflicting I/O pins.
Configuration Schemes
The configu ration data for a FLEX 10KE device can be loaded with one of
five conf iguration schemes (s ee Table 82), ch osen on the basis of t he target
application. An EPC1, EPC2, or EPC16 configuration device, intelligent
controller, or the JTAG port can be used to control the configuration of a
FLEX 10KE device, allowing automatic configuration on system
power-up.
Multiple FLEX 10KE devices can be configured in any of the five
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device. Additional
FLEX 10K, FLEX 10KA, FLEX 10KE, an d FLEX 6000 devic es can be
configured in the same serial chain.
Table 81. I/O Counts for FLEX 10KA & FLEX 10KE Devi ces
FLEX 10KA FLEX 10KE
Device I/ O Count D evice I/O Count
EPF10K30AF256 191 EPF10K30EF256 176
EPF10K30AF484 246 EPF10K30EF484 220
EPF10K50VB356 274 EPF10K50SB356 220
EPF10K50VF484 291 EPF10K50EF484 254
EPF10K50VF484 291 EPF10K50SF484 254
EPF10K100AF484 369 EPF10K100EF484 338
Table 82. Data Sources for FLE X 10KE Configuration
Con f ig ur a t io n Sc heme D at a Sour c e
Configuration device EPC1, EPC2, or EPC16 configuration device
Passive serial (PS) BitBlaster, ByteBlasterMV, or MasterBlaster download cables,
or s eria l data s ource
Passive parallel asynchronous (PPA) Parallel data source
Passive parallel synchronous (PPS) Parallel data source
J T AG BitBlaster or ByteBl asterMV down load ca bles , or
microprocessor with a Jam STAPL file or JBC file
Altera Corporation 99
FLEX 10KE Embed d ed Prog ra mmable Logic De vi ces Data Shee t
Device
Pin-Outs
See the Altera web site (http://www.altera.com) or the Altera Digital
Library for pin-out information.
Revision
History
The information contained in the FLEX 10KE Embedded Programmable Logic
Data Sheet version 2.5 supersedes information published in previous
versions.
Version 2.5
The following changes were made to the FLEX 10KE Embedded
Programmable Logic Data Sheet ve rsion 2 .5:
■Note (1) added to Figure 23.
■Text added to “I/O Elem ent” sectio n on page 34.
■Updated Table 22.
Version 2.4
The following changes were made to the FLEX 10KE Embedded
Programmable Logic Data Sheet version 2.4: updated text on page 34 and
page 63.
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FLE X 10KE Embe dde d Pr ogra m mable Logic Devic e s Dat a Sheet
100 Altera Corporation
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