PIC24F04KA201-I/P - Microchip Technology

 2011 Microchip Technology Inc. DS80474B-page 1

PIC24F04KA201 FAMILY

The PIC24F04KA201 family devices that you have

received conform functionally to the current Device Data

Sheet (DS39937B), except for the anomalies described

in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata describ ed in this document will be addressed

in future revisio ns of the PIC 24F04KA201 fam ily silicon.

Data Sheet clarifications and corrections start on page 5,

following the discu ssion of silicon issues .

The silicon revision level can be identified using the

current version of MPLAB® IDE and Microchip’s

programmers, debuggers and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect

the device to the MPLAB ICD 2

programmer/debu gger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Select Tool).

4. Perform a “Connect” operation to the device

(Debugger>Connect). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The DEVREV values for the various PIC24F04KA201

family silicon revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A1). Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Par t Numb er Device ID(1) Revision ID for Silicon

Revision(2)

PIC24F04KA201 0B00h 01h

PIC24F04KA200 0B02h

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses in program

memory. They are shown in hexadecimal in the format, “DEVID DEVREV”.

2: Refer to the “PIC24FXXKAXXX Flash Programming Specification” (DS39919) for detailed information on

Device and Revision IDs for your specific devi ce.

PIC24F04KA201 Family

Silicon Errata and Data Sheet Clarification

PIC24F04KA201 FAMILY

DS80474B-page 2  2011 Microchip Technology Inc.

TABLE 2: SILICON ISSUE SUMMARY

Module Feature Item

Number Issue Summary

Affected

Revisions(1)

Resets BOR 1. Inadvertent Reset when disabling/enabling BOR. X

Core Deep Sleep 2. Failure to avoid Deep Sleep entry. X

Comparator — 3. Change in maximum VIOFF.X

SPI Enhanced

Buffer mode 4. Err ors when pollin g SPITB F flag. X

Core Low-Voltage

BOR 5. LPBOR configuration results in ambiguous Resets. X

Comparator I/O Pins 6. Enabling comparators disables some digital I/O ports. X

Comparator — 7. Output polarity inversion also inverts edge-detect sensing. X

Core Doze mode 8. Instruction execution glitches following DOZE bit changes. X

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

 2011 Microchip Technology Inc. DS80474B-page 3

PIC24F04KA201 FAMILY

Silicon Errata Issues

1. Module: Resets (BOR)

A device Reset may occur if the BOR is disabled

and immediately re-enabled in software

(RCON<14> is cleared, and then immediately

set).

Work around

It is recommended that several NOP instructions

be added to a BOR disable/enable sequence.

Alternatively, place several instructions or a

short rou tine between the ins tructi ons to d isabl e

and enabl e the BOR.

Affected Silicon Revisions

2. Module: Core (Deep Sleep)

Deep Sleep wake-up sources may be ignored if

they occur just prior to entry into Deep Sleep

mode. As a result, the device may enter Deep

Sleep mode when it should not.

Work around

If possible, configure external Deep Sleep

wake-up sources to repeat themselves once. If

the device does enter Deep Sleep, the second

occurrence of the wake-up source will wake the

device.

Alternatively, synchronize the entry into Deep

Sleep with external wake-up sources, where

possible.

Affected Silicon Revisions

3. Module: Comparator

The maximum value for the input offset voltage

(specification D300, VIOFF), shown in

Table 26-12 of the Device Data Sheet, has

changed for this silicon revision. The new value

is shown in Table 3 (changes in bold).

Work around

None.

Affected Silicon Revisions

TABLE 3: COMPARATOR DC SPECIFICATIONS (PARTIAL)

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated by the shaded column in

the following tables apply to the current

silicon revision (A1).

Param

No. Symbol Characteristics Min Typ Max Units Comments

VIOFF Input Offset Voltage — 20 60 mV

PIC24F04KA201 FAMILY

DS80474B-page 4  2011 Microchip Technology Inc.

4. Module: SPI (Enhanced Buffer Mode)

In Enhanced Buffer mode (SPI1CON2<0> = 1),

polling the SPI Transmit Buffer Full bit, SPITBF

(SPI1STAT<1>), may produc e erroneous results.

This occurs only unde r two circu mst anc es:

• In Mas t er mode , wh en t he S P I d i vi de c loc k

is 4 o r greater.

• In Sla v e mo de, w hen th e SP I sam pl e c loc k

is slower than 1/4 of the CPU instruction

time (TCY).

For Mas ter mo de, this inc lud es al l c om bi nat ions

of the primary prescale bits (SPI11CON1<1:0>)

and secondary prescale bits (SPI1CON1<4:2>)

that, when combined, create an SPI sample

clock divisor with a value of four or greater.

Work around

Instead of polling the SPITBF bit to test for an

empty buffer (SPI1STAT<1> = 0), implement a

SPI receive interrupt handler in software and

add to the SPI transmit buffer in this routine.

Alternatively, poll the SPI Receive Full bit,

SPIRBF (SPI1STAT<0>), or the Shift Register

Empty bit, SRMPT (SPI1STAT<7>), to determine

when to service the SPI transmit and transmit

buffers.

Affected Silicon Revisions

5. Module: Core (Low-Power BOR)

When the low-power BOR is enabled

(FPOR<6:5> = 00), Brown-out Reset events

may result in a device Reset in which both the

BOR and POR bits are set.

This differs from the expected behavior of simply

re-arming the POR circuit to ensure that a

Power-on Reset occurs when V

drops below

the POR thre shol d.

Work around

None.

Affected Silicon Revisions

6. Module: Comparator (I/O Pins)

Certain I/O pins may not function correctly as

digit al inputs or outputs after specific comp arator

outputs have been enabled with the COE bit

(CMxCON<14> = 1). These are:

• RB1 4 (with Compara tor 1)

• RA6 (with Comp ara tor 2)

This condition m ay continue, even after the c om-

parator in question has been disabled using the

corresponding CON bit (C MxCON< 15> = 0).

Work around

In additi on to clearing t he CON bit, a lso clear the

COE bit.

Affected Silicon Revisions

7. Module: Comparator

When a comparator is programmed to trig-

ger on certain edge-detect events

(CMxCON<7:6> = 10 or 01), setting the CPOL bit

(CMxCON<13> = 1) may cause the comparator to

flag the opposite edge-detect event (e.g., a

high-to-low edge instead of the programmed

low-to-high).

Work around

Leave CPOL = 0. In addition, use the opposite

setting of CMxCON<7:6> to achieve the correct

response (e.g., use ‘10’ for ‘01’).

Affected Silicon Revisions

 2011 Microchip Technology Inc. DS80474B-page 5

PIC24F04KA201 FAMILY

8. Module: Core (Doze Mode)

Operati ons that immediately foll ow any manipu-

lations of the DOZE<2:0> or DOZEN bits

(CLDIV<14:11>) may not execute properly. In

particular, for instructions that operate on an

SFR, data may not be read properly. Also, bits

automatically cleared in hardware may not be

cleared if the operation occurs during this

interval.

Work around

Always insert a NOP instru cti on be for e an d afte r

either of the following:

• En abling or dis abling Do ze mode b y setting

or clearing the DOZEN bit

• Before or after changing the DOZE<2:0> bits

Affected Silicon Revisions

Data Sheet Clarificati ons

The foll owing ty pographic c orrections and clari fications

are to be noted for the l atest ve rsion of the Device Dat a

Sheet (DS39937B):

1. Module: Electrical Specifications

(DC Specifications)

Table 26-5 (“BOR Trip Points”) has changed to

reflect the functionality of the LPBOR trip point

(BORV<1:0> = 00), and to make other typo-

graphic corrections. The minimum and

maximum values for the BOR trip points in

Table 26-5 have changed. The new version of

the table is shown below (changes in bold).

TABLE 26-5: BOR TRIP POINTS

Note: Corrections are shown in bold. Where

possible, the original bold text formatting

has been removed for clarity.

Standard Operating Conditions (unless other w is e stated)

Oper ati ng t em perature -40°C  TA  +85°C for industrial

Param

No. Sym Characteristic Min Typ Max Units Conditions

DC19 BOR V ol t age on

VDD Transition BORV = 00 — — — — Note (1)

BORV = 01 2.92 3 3.25 V

BORV = 10 2.63 2.7 2.92 V

BORV = 11 1.75 1.82 2.01 V

Note 1: L PBOR re-arms the POR circuit, but does not cause a BOR.

PIC24F04KA201 FAMILY

DS80474B-page 6  2011 Microchip Technology Inc.

APPENDIX A: DOCUMENT

REVISION HISTORY

Rev A Document (6/2009)

Initial release of this document; issued for revision A1.

Includes silicon issues 1 (Resets – BOR), 2 (Core –

Deep Sleep), 3 (Comparator) and 4 (SPI – Enhanced

Buffer Mode).

Rev B Document (2/2011)

Adds new silicon issues 5 (Core – Low Power BOR),

6 and 7 (Comparators), and 8 (Core – Doze Mode) to

silicon revision A1.

Added data sheet clarification 1 (Electrical

Specif ications – DC Specifications) t o revision B of the

data sheet.

 2011 Microchip Technology Inc. DS80474B-page 7

Information contained in this publication regarding device

applications and the lik e is p rovided on ly for yo ur c onvenience

and may be superseded by updates . I t is y our respo ns ibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC , PI Cmi cro, PI CSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor ,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSense, HI-TIDE , In -Circuit Seri a l

Programming, ICSP, Mindi, MiWi, MPAS M, MPLAB Cert ified

logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-60932-893-1

Note the following details of the code protection feature on Microchip devices:

• M icrochip products meet the specification contained in their particular Microchip Data Sheet.

• M icrochip believes that its family of products is one of the most secure families of its kind on t he market t oday, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• M icrochip is willing to work with the customer who is concerned about the integrity of their code.

• Neit her Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS80474B-page 8  2011 Microchip Technology Inc.

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08/04/10