Hitachi Single-Chip Microcomputer
H8S/2350 Series
10/12/96
Notice
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part
of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any
intellectual property claims or other problems that may result from applications based on the
examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party
or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in
MEDICAL APPLICATIONS.
3
Preface
Hitachi’s H8S Series of single-chip microcomputers comprises new series which offer the high
performance and low power consumption of the existing H8 Series, which is widely used for machine
control, etc., together with significantly greater ease of use,
This initial series—the H8S/2000 Series—offers CPU object-level compatibility with the H8/300H
Series, H8/300 Series, and H8/300L Series within the H8 Series.
Series Features
H8S/2000 Upward-compatible with the H8/300H Series and H8/300 Series; twice the performance at the
same frequency; multiply-and-accumulate instructions
H8/300H 16-Mbyte linear address space; upward-compatible with the H8/300 Series; concise instruction
set; powerful word-size and longword-size arithmetic instructions
H8/300 64-kbyte address space; general register system; concise instruction set; powerful bit
manipulation instructions
H8/300L Same CPU as the H8/300 Series; consumer application oriented peripheral functions; low
voltage, low power consumption
Intended Readership
This Overview is intended for readers who require a basic understanding of microcomputers, or are
looking for information on the features and functions of the H8S/2350 Series. Readers undertaking
system design using these products, or requiring more detailed information on their use, should refer to
the H8S/2350 Hardware Manual and H8S/2000 Series Programming Manual.
Related Documents
Contents Document Title and No.
On H8S/2350 hardware H8S/2350 Hardware Manual
ADE-602-111
On H8S/2000 Series execution instructions H8S/2600 Series, H8S/2000 Series Programming Manual
ADE-602-083A
4
Contents
Section 1 H8S/2350 Series Features................................................................................. 6
1.1 H8S/2350 Series Functions..................................................................................................... 6
1.2 Pin Description ....................................................................................................................... 10
1.3 Block Diagram........................................................................................................................ 14
Section 2 CPU............................................................................................................................ 15
2.1 Features................................................................................................................................... 15
2.2 Register Configuration............................................................................................................ 18
2.3 Data Formats........................................................................................................................... 22
2.4 Addressing Modes .................................................................................................................. 24
2.5 Instruction Set......................................................................................................................... 26
2.6 Basic Bus Timing ................................................................................................................... 42
2.7 Processing States..................................................................................................................... 46
2.8 Exception Handling................................................................................................................. 48
2.9 Interrupts................................................................................................................................. 50
2.10 Operating Modes..................................................................................................................... 54
2.11 Address Map........................................................................................................................... 56
Section 3 Peripheral Functions............................................................................................ 58
3.1 Bus Controller (BSC).............................................................................................................. 58
3.1.1 Area Partitioning...................................................................................................... 60
3.1.2 Basic Bus Interface.................................................................................................. 62
3.1.3 DRAM Interface...................................................................................................... 64
3.1.4 Burst ROM Interface ............................................................................................... 67
3.2 DMA Controller (DMAC)...................................................................................................... 69
3.2.1 Short Address Mode................................................................................................ 72
3.2.2 Full Address Mode .................................................................................................. 75
3.3 Data Transfer Controller (DTC) ............................................................................................. 77
3.3.1 Data Transfer Operation.......................................................................................... 79
3.3.2 Transfer Modes........................................................................................................ 83
3.4 16-Bit Timer Pulse Unit (TPU) .............................................................................................. 87
3.5 Programmable Pulse Generator (PPG) ................................................................................... 99
3.6 Watchdog Timer ..................................................................................................................... 102
3.7 Serial Communication Interface (SCI) ................................................................................... 106
3.7.1 SCI Asynchronous Mode......................................................................................... 108
3.7.2 SCI Synchronous Communication.......................................................................... 110
3.8 Smart Card Interface............................................................................................................... 113
3.9 A/D Converter......................................................................................................................... 116
3.10 D/A Converter ....................................................................................................................... 119
3.11 I/O Ports.................................................................................................................................. 121
3.12 RAM....................................................................................................................................... 124
3.13 ROM (H8S/2351)*.................................................................................................................. 125
Section 4 Power-Down State ............................................................................................... 126
4.1 Power-Down State.................................................................................................................. 126
5
Appendix
Package...................................................................................................................................128
6
Section 1 H8S/2350 Series Features
1.1 H8S/2350 Series Functions
H8S/2350 Series microcomputers are designed for faster instruction
execution, using a realtime control oriented CPU with an internal 32-
bit architecture, and can run programs based on the C high-level
language efficiently. These microprocessors provide on chip a full
complement of the functions required by control systems as
peripheral functions, and their on-chip multi-function bus controller
allows easy high-speed access to external memory. This allows these
microprocessors to easily implement sophisticated high-performance
systems.
Note: The H8S/2351 is in the planning stage.
High-Performance H8S/2600 CPU
• General-register architecture
— Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• High-speed operation suitable for realtime control
— 20 MHz maximum operating frequency (20 MHz oscillation frequency)
— High-speed arithmetic operations
8/16/32-bit register-register add/subtract: 50 ns
16 × 16-bit register-register multiply: 1000 ns
32 ÷ 16-bit register-register divide: 1000 ns
• Instruction set suitable for high-speed operation
— Sixty-five basic instructions
— 8/16/32-bit move/arithmetic and logic instructions
— Unsigned/signed multiply and divide instructions
— Powerful bit-manipulation instructions
• Two CPU operating modes
— Normal mode: H8/300 Series compatible, maximum 64-kbyte address space
— Advanced mode: Maximum 16-Mbyte address space
On-Chip Byte PROM (Mask ROM) (H8S/2351 Only)
• 64 kbytes
On-Chip 4-kbyte High-Speed Static RAM
Section 1 H8S/2350 Series Features
7
On-Chip Bus Controller
• Address space divided into 8 areas, with bus specifications settable independently for each area
• Chip select output possible for each area
• Selection of 8-bit or 16-bit access space for each area
• 2-state or 3-state access space can be designated for each area
• Number of program wait states can be set for each area
• Burst ROM directly connectable
• Maximum 8-Mbyte DRAM directly connectable (or use of interval timer possible)
• External bus release function
DMA Controller (DMAC)
• Selection of short address mode or full address mode
• Four channels in short address mode, two channels in full address mode
• Transfer possible in repeat mode, block transfer mode, etc.
• Single address mode transfer possible
• Can be activated by internal interrupt
Data Transfer Controller (DTC)
• Activated by internal interrupt or software
• Multiple transfers or multiple types of transfer possible for one activation source
• Transfer possible in repeat mode, block transfer mode, etc.
• Request can be sent to CPU for interrupt that activated DTC
16-Bit Timer-Pulse Unit (TPU)
• Six-channel 16-bit timer on-chip
• Pulse I/O processing capability for up to 16 pins’
• Automatic 2-phase encoder count capability
Programmable Pulse Generator (PPG)
• Maximum 16-bit pulse output possible with TPU as time base
• Output trigger selectable in 4-bit groups
• Non-overlap margin can be set
• Direct output or inverse output setting possible
On-Chip Watchdog Timer (WDT)
• Watchdog timer or interval timer selectable
Section 1 H8S/2350 Series Features
8
Two On-Chip Serial Communication Interface (SCI) Channels
• Asynchronous mode or synchronous mode selectable
• Multiprocessor communication function
• Smart card interface function
On-Chip A/D Converter
• Resolution: 10 bits
• Input: 8 channels
• High-speed conversion : 6.7 µs minimum conversion time (at 20 MHz operation)
• Single or scan mode selectable
• Sample and hold circuit
• A/D conversion can be activated by external trigger or timer trigger
On-Chip D/A Converter
• Resolution: 8 bits
• Output: 2 channels
Thirteen I/O Ports
• 87 I/O pins, 8 input-only pins
On-Chip Interrupt Controller
• Nine external interrupt pins (NMI, IRQ0 to IRQ7)
• 42 internal interrupt sources
• Selection of two interrupt control modes
Power-Down State
• Medium-speed mode
• Sleep mode
• Module stop mode
• Software standby mode
• Hardware standby mode
Section 1 H8S/2350 Series Features
9
Seven MCU Operating Modes
Mode CPU Operating
Mode Description On-Chip ROM
External Data Bus
Initial Value Maximum Value
1 Normal On-chip ROM disabled
expansion mode Disabled 8 bits 16 bits
2*On-chip ROM enabled
expansion mode Enabled 8 bits 16 bits
3*Single-chip mode Enabled —
4 Advanced On-chip ROM disabled
expansion mode Disabled 16 bits 16 bits
5 On-chip ROM disabled
expansion mode Disabled 8 bits 16 bits
6*On-chip ROM enabled
expansion mode Enabled 8 bits 16 bits
7*Single-chip mode Enabled —
Note: *Only applies to the H8S/2351.
On-Chip Clock Pulse Generator (1:1 Oscillation)
• Built-in duty correction circuit
Packages
• 120-pin plastic TQFP (TFP-120)
• 128-pin plastic QFP (FP-128)
Product Lineup
Model
Mask ROM
Version ZTAT™
Version ROM Less
Version ROM/RAM (Bytes) Packages
HD6432351*HD6472351*— 64 k/2 k TFP-120
FP-128
— — HD6412350 —/2 k TFP-120
FP-128
Note: *In the plannning stage
ZTATTM is a trademark of Hitachi Ltd.
Section 1 H8S/2350 Series Features
10
1.2 Pin Description
Pin Arrangement
V
CC
PC
0
/A
0
PC
1
/A
1
PC
2
/A
2
PC
3
/A
3
V
SS
PC
4
/A
4
PC
5
/A
5
PC
6
/A
6
PC
7
/A
7
PB
0
/A
8
PB
1
/A
9
PB
2
/A
10
PB
3
/A
11
V
SS
PB
4
/A
12
PB
5
/A
13
PB
6
/A
14
PB
7
/A
15
PA
0
/A
16
PA
1
/A
17
PA
2
/A
18
PA
3
/A
19
V
SS
PA
4
/A
20
/IRQ4
PA
5
/A
21
/IRQ5
PA
6
/A
22
/IRQ6
PA
7
/A
23
/IRQ7
P6
7
/CS7/IRQ3
P6
6
/CS6/IRQ2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P5
1
P5
0
PF
0
/BREQ
PF
1
/BACK
PF
2
/LCAS/WAIT/BREQO
PF
3
/LWR
PF
4
/HWR
PF
5
/RD
PF
6
/AS
V
CC
PF
7
/ø
V
SS
EXTAL
XTAL
V
CC
STBY
NMI
RES
WDTOVF
P2
0
/PO0/TIOCA3
P2
1
/PO1/TIOCB3
P2
2
/PO2/TIOCC3
P2
3
/PO3/TIOCD3
P2
4
/PO4/TIOCA4
P2
5
/PO5/TIOCB4
P2
6
/PO6/TIOCA5
P2
7
/PO7/TIOCB5
P6
3
/TEND1
P6
2
/DREQ1
P6
1
/TEND0/CS5
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PG
4
/CS0
PG
3
/CS1
PG
2
/CS2
PG
1
/CS3
PG
0
/CAS
MD
2
MD
1
MD
0
P1
0
/PO8/TIOCA0/DACK0
P1
1
/PO9/TIOCB0/DACK1
P1
2
/PO10/TIOCC0/TCLKA
P1
3
/PO11/TIOCD0/TCLKB
P1
4
/PO12/TIOCA1
P1
5
/PO13/TIOCB1/TCLKC
P1
6
/PO14/TIOCA2
P1
7
/PO15/TIOCB2/TCLKD
V
SS
AV
SS
P4
7
/AN7/DA1
P4
6
/AN6/DA0
P4
5
/AN5
P4
4
/AN4
P4
3
/AN3
P4
2
/AN2
P4
1
/AN1
P4
0
/AN0
V
ref
AV
CC
P5
3
/ADTRG
P5
2
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P6
5
/IRQ1
P6
4
/IRQ0
V
CC
PE
0
/D
0
PE
1
/D
1
PE
2
/D
2
PE
3
/D
3
V
SS
PE
4
/D
4
PE
5
/D
5
PE
6
/D
6
PE
7
/D
7
PD
0
/D
8
PD
1
/D
9
PD
2
/D
10
PD
3
/D
11
V
SS
PD
4
/D
12
PD
5
/D
13
PD
6
/D
14
PD
7
/D
15
V
CC
P3
0
/TxD0
P3
1
/TxD1
P3
2
/RxD0
P3
3
/RxD1
P3
4
/SCK0
P3
5
/SCK1
V
SS
P6
0
/DREQ0/CS4
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
120-Pin Plastic TQFP (TFP-120: Top View)
Section 1 H8S/2350 Series Features
11
PG3/CS1
PG4/CS0
VSS
NC
VCC
PC0/A0
PC1/A1
PC2/A2
PC3/A3
VSS
PC4/A4
PC5/A5
PC6/A6
PC7/A7
PB0/A8
PB1/A9
PB2/A10
PB3/A11
VSS
PB4/A12
PB5/A13
PB6/A14
PB7/A15
PA0/A16
PA1/A17
PA2/A18
PA3/A19
VSS
PA4/A20/IRQ4
PA5/A21/IRQ5
PA6/A22/IRQ6
PA7/A23/IRQ7
P67/CS7/IRQ3
P66/CS6/IRQ2
VSS
VSS
P65/IRQ1
P64/IRQ0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
P53/ADTRG
P52
VSS
VSS
P51
P50
PF0/BREQ
PF1/BACK
PF2/LCAS/WAIT/BREQO
PF3/LWR
PF4/HWR
PF5/RD
PF6/AS
VCC
PF7/ø
VSS
EXTAL
XTAL
VCC
STBY
NMI
RES
WDTOVF
P20/PO0/TIOCA3
P21/PO1/TIOCB3
P22/PO2/TIOCC3
P23/PO3/TIOCD3
P24/PO4/TIOCA4
P25/PO5/TIOCB4
P26/PO6/TIOCA5
P27/PO7/TIOCB5
P63/TEND1
P62/DREQ1
P61/TEND0/CS5
VSS
VSS
P60/DREQ0/CS4
VSS
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
PE0/D0
PE1/D1
PE2/D2
PE3/D3
VSS
PE4/D4
PE5/D5
PE6/D6
PE7/D7
PD0/D8
PD1/D9
PD2/D10
PD3/D11
VSS
PD4/D12
PD5/D13
PD6/D14
PD7/D15
VCC
P30/TxD0
P31/TxD1
P32/RxD0
P33/RxD1
P34/SCK0
P35/SCK1
PG2/CS2
PG1/CS3
PG0/CAS
MD2
MD1
MD0
P10/PO8/TIOCA0/DACK0
P11/PO9/TIOCB0/DACK1
P12/PO10/TIOCC0/TCLKA
P13/PO11/TIOCD0/TCLKB
P14/PO12/TIOCA1
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2
P17/PO15/TIOCB2/TCLKD
VSS
AVSS
P47/AN7/DA1
P46/AN6/DA0
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
Vref
AVCC
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
128-Pin Plastic QFP (FP-128: Top View)
Section 1 H8S/2350 Series Features
12
Pin Functions
Type Symbol I/O Name and Function
Power VCC Input Power supply
VSS Input Ground: All VSS pins should be connected to the system power
supply (0 V).
Clock XTAL Input Connects to a crystal oscillator.
EXTAL Input Connects to a crystal oscillator, or external clock input.
ø Output System clock: Supplies the system clock to an external device.
Operating mode
control MD2 to MD0Input Mode pins: These pins set the operating mode.
System control RES Input Reset input
STBY Input Standby
BREQ Input Bus request
BREQO Output Bus request output
BACK Output Bus request acknowledge
Interrupts NMI Input Nonmaskable interrupt
IRQ7 to IRQ0 Input Interrupt request 7 to 0
Address bus A23 to A0Output Address bus
Data bus D15 to D0I/O Data bus
Bus control CS7 to CS0 Output Chip select/low address strobe (CS5 to CS2)
AS Output Address strobe
RD Output Read
HWR Output High write/write enable
LWR Output Low write
CAS Output Upper column address strobe/column address strobe
LCAS Output Lower column address strobe
WAIT Input Wait
DMA controller
(DMAC) DREQ1, DREQ0 Input DMA request 1 and 0
TEND1, TEND0 Output DMA transfer end 1 and 0
DACK1, DACK0 Output DMA transfer acknowledge 1 and 0
Section 1 H8S/2350 Series Features
13
Type Symbol I/O Name and Function
16-bit timer-pulse
unit (TPU) TCLKA to TCLKD Input Clock input A to D
TIOCA0, TIOCB0,
TIOCC0, TIOCD0 I/O Input capture/output compare match A0 to D0
TIOCA1, TIOCB1 I/O Input capture/output compare match A1 and B1
TIOCA2, TIOCB2 I/O Input capture/output compare match A2 and B2
TIOCA3, TIOCB3,
TIOCC3, TIOCD3 I/O Input capture/output compare match A3 to D3
TIOCA4, TIOCB4 I/O Input capture/output compare match A4 and B4
TIOCA5, TIOCB5 I/O Input capture/output compare match A5 and B5
Programmable
pulse generator
(PPG)
PO15 to PO0 Output Pulse output
Watchdog timer
(WDT) WDTOVF Output Watchdog timer overflows
Serial
communication
interface (SCI)
Smart Card
interface
TxD1, TxD0
RxD1, RxD0
SCK1, SCK0
Output
Input
I/O
Transmit data (channel 1, 0)
Receive data (channel 1, 0)
Serial clock (channel 1, 0)
A/D converter AN7 to AN0 Input Analog input
ADTRG Input A/D conversion external trigger input
D/A converter DA1, DA0 Output Analog output
A/D converter and
D/A converters AVCC Input This is the power supply pin for the A/D converter and D/A
converter.
AVSS Input This is the ground pin for the A/D converter and D/A converter.
Vref Input This is the reference voltage input pin for the A/D converter and
D/A converter.
I/O ports P17 to P10I/O Port 1
P27 to P20I/O Port 2
P35 to P30I/O Port 3
P47 to P40Input Port 4
P53 to P50I/O Port 5
P67 to P60I/O Port 6
PA7 to PA0I/O Port A
PB7 to PB0*I/O Port B
PC7 to PC0*I/O Port C
PD7 to PD0*I/O Port D
PE7 to PE0I/O Port E
PF7 to PF0I/O Port F
PG4 to PG0I/O Port G
Note: *Only applies to the H8S/2351.
Section 1 H8S/2350 Series Features
14
1.3 Block Diagram
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Port D
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Port
A
PA7/A23/IRQ
7
PA6/A22/IRQ
6
PA5/A21/IRQ
5
PA4/A20/IRQ4
PA3/A19
PA2/A18
PA1/A17
PA0/A16
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
PB2/A10
PB1/A9
PB0/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
P35/SCK1
P34/SCK0
P33/RxD1
P32/RxD0
P31/TxD1
P30/TxD0
P50
P51
P52
P53/ADTRG
P47/AN7/DA1
P46/AN6/DA0
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
Vref
AVCC
AVSS
P20/PO0/TIOCA3
P21/PO1/TIOCB3
P22/PO2/TIOCC3
P23/PO3/TIOCD3
P24/PO4/TIOCA4
P25/PO5/TIOCB4
P26/PO6/TIOCA5
P27/PO7/TIOCB5
P10/PO8/TIOCA0/DACK0
P11/PO9/TIOCB0/DACK1
P12/PO10/TIOCC0/TCLKA
P13/PO11/TIOCD0/TCLKB
P14/PO12/TIOCA1
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2
P17/PO15/TIOCB2/TCLKD
P67/CS7/IRQ3
P66/CS6/IRQ2
P65/IRQ1
P64/IRQ0
P63/TEND1
P62/DREQ1
P61/TEND0/CS5
P60/DREQ0/CS4
PG4/CS0
PG3/CS1
PG2/CS2
PG1/CS3
PG0/CAS
PF7/ø
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/WAIT/LCAS/BREQO
PF1/BACK
PF0/BREQ
Clock pulse
generator
ROM*
RAM WDT
TPU
SCI
PPG
MD2
MD1
MD0
EXTAL
XTAL
STBY
RES
WDTOVF
NMI
Bus controller
H8S/2000 CPU
DTC
Interrupt controller
Port E
DMAC
Internal data bus
Internal address bus
Port
B
Port
C
Port
3
Port
5
Port 4Port 2Port 1
Port
6
Port
G
Port
F
Peripheral data bus
Peripheral address bus
D/A converter
A/D converter
Note: * Only applies to the H8S/2351.
Block Diagram
15
Section 2 CPU
2.1 Features
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture, and is
upward compatible with the H8/300 and H8/300H CPUs.
The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-
Gbyte) linear access space, and is ideal for realtime control.
Feature
• Upward-compatible with H8/300 and H8/300H CPUs
— Can execute H8/300 and H8/300H object programs
• General-register architecture
— Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• Sixty-five basic instructions
— 8/16/32-bit arithmetic and logic instructions
— Multiply and divide instructions
— Powerful bit-manipulation instructions
• Eight addressing modes
— Register direct (Rn)
— Register indirect (@ERn)
— Register indirect with displacement (@(d:16,ERn) or @(d:32,ERn))
— Register indirect with post-increment or pre-decrement (@ERn+ or @–ERn)
— Absolute address (@aa:8, @aa:16, @aa:24, or @aa:32)
— Immediate (#xx:8, #xx:16, or #xx:32)
— Program-counter relative (@(d:8,PC) or @(d:16,PC))
— Memory indirect (@@aa:8)
• 16-Mbyte address space
— Program: 16 Mbytes
— Data: 16 Mbytes (4 Gbytes architecturally)
Section 2 CPU
16
• High-speed operation
— All frequently-used instructions execute in one or two states
— Maximum clock frequency: 20 MHz
— 8/16/32-bit register-register add/subtract: 50 ns
—8 × 8-bit register-register multiply: 600 ns
— 16 ÷ 8-bit register-register divide: 600 ns
— 16 × 16-bit register-register multiply: 1000 ns
— 32 ÷ 16-bit register-register divide: 1000 ns
• Two CPU operating modes
— Normal mode/advanced mode
• Low-power state
— Transition to power-down state by SLEEP instruction
— CPU clock speed selectable
Differences between the H8S/2600 CPU and the H8S/2000 CPU
• Register configuration
— The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
— The MAC, CLRMAC, LDMAC, and STMAC instructions are supported only by the H8S/2600
CPU.
• Number of states required for execution
— The number of states required for execution of the MULXU and MULXS instructions
Differences from H8/300 CPU
In comparison with the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
— Eight 16-bit registers and one 8-bit control registers added
• Expanded address space
— Normal mode supports the same 64-kbyte address space as the H8/300 CPU
— Advanced mode supports a maximum 16-Mbyte address space
• Enhanced addressing
— For effective use of the 16-Mbyte address space
Section 2 CPU
17
• Enhanced instructions
— Addressing modes of bit-manipulation instructions enhanced
— Signed multiply and divide instructions added
— Two-bit shift instructions added
— Instructions for saving and restoring multiple registers added
— Test-and-set instruction added
• Higher speed
— Basic instructions execute twice as fast
Differences from H8/300H CPU
In comparison with the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
• Additional control register
— One 8-bit control register added
• Enhanced instructions
— Addressing modes of bit-manipulation instructions enhanced
— Two-bit shift instructions added
— Instructions for saving and restoring multiple registers added
— Test-and-set instruction added
• Higher speed
— Basic instructions execute twice as fast
Section 2 CPU
18
2.2 Register Configuration
The H8S/2000 CPU has general registers and control registers.
The eight 32-bit general registers all have identical functions and can be used as either address registers
or data registers. The control registers are the 24-bit program counter (PC), 8-bit extend register (EXR),
and 8-bit condition code register (CCR).
CPU Internal Register Configuration
T
————
I2 I1 I0EXR 76543210
PC
23 0
15 0 7 0 7 0
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
General registers (Rn) and extended registers (En)
Control registers (CR)
Legend
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
UIHUNZVC
CCR 76543210
H:
U:
N:
Z:
V:
C:
Stack pointer
Program counter
Extend register
Trace bit
Interrupt mask bits
Condition code register
Interrupt mask bit
User bit/interrupt mask bit*
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Note: *In the H8S/2350 Series, this bit cannot be used as an interrupt mask.
IUIHUNZVC
Section 2 CPU
19
General Registers
The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be
used as either address registers or data registers.
When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or address registers, they are designated by the
letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to
R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E
registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL
(R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers.
The figure below illustrates the usage of the general registers. The usage of each register can be
selected independently.
Usage of General Registers
• Address registers
• 32-bit registers • 16-bit registers • 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Control Registers
The control registers are the 24-bit program counter (PC), 8-bit extend register (EXR), and 8-bit
condition code register (CCR).
Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will
execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so the least
significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as
0.
Section 2 CPU
20
Extend Register (EXR): This 8-bit register comprises a trace bit (T) and interrupt mask bits (I2 to I0).
• Bit 7—Trace Bit (T)
Specifies whether or not trace mode is set. When this bit is cleared to 0, instructions are executed
sequentially. When set to 1, trace exception handling is started each time an instruction is executed.
• Bits 6 to 3—Reserved
• Bits 2 to 0—Interrupt Mask Bits (I2 to I0)
These bits specify the interrupt request mask level (0 to 7). See section 2.9, Interrupts, for details.
EXR can be manipulated by the LDC, STC, ANDC, ORC, and XORC instructions. Except in the case
of STC, interrupts (including NMI) are not accepted for 3 states after the instruction is executed.
Condition Code Register (CCR): This 8-bit register contains internal CPU status information,
including the interrupt mask bit (I), and the half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags.
• Bit 7—Interrupt Mask Bit (I)
Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I
bit is set to 1 at the start of an exception-handling sequence. See section 2.9, Interrupts for details.
• Bit 6—User Bit or Interrupt Mask Bit (UI)
Can be written or read by software using the LDC, STC, ANDC, ORC, and XORC instructions. In
this IC, this bit cannot be used as an interrupt mask.
• Bit 5—Half-Carry Flag (H)
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag
is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W,
SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0
otherwise.
• Bit 4—User Bit (U)
Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.
• Bit 3—Negative Flag (N)
Stores the value of the most significant bit (sign bit) of data.
• Bit 2—Zero Flag (Z)
Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Section 2 CPU
21
• Bit 1—Overflow Flag (V)
Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
• Bit 0—Carry Flag (C)
Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
— Add instructions, to indicate a carry
— Subtract instructions, to indicate a borrow
— Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit-manipulation instructions.
Section 2 CPU
22
2.3 Data Formats
The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.
Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand
data.
The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
General Register Data Formats
70
70
MSB LSB
MSB LSB
7043
Don’t care
Don’t care
Don’t care
7043
Upper digit Lower digit
70
Don’t care
65432710
70
Don’t care
Don’t care
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
Word data
Word data
Longword data
RnH
RnL
RnH
RnL
RnH
RnL
Rn
En
ERn
15 0
MSB LSB
15 0
MSB LSB
31 16
MSB
15 0
LSB
En Rn
Legend
ERn:
En:
Rn:
RnH:
65432710
Upper digit Lower digit
General register ER
General register E
General register R
General register RH
RnL:
MSB:
LSB:
General register RL
Most significant bit
Least significant bit
Data Type General Register Data Format
Section 2 CPU
23
Memory Data Formats
70
76 543210
MSB LSB
MSB
MSB
LSB
LSB
Address
Address L
Address L
Address 2M
Address 2N
Address 2N + 1
Address 2N + 2
Address 2N + 3
1-bit data
Byte data
Word data
Longword data
Data Type Data Format
Address 2M + 1
Section 2 CPU
24
2.4 Addressing Modes
The H8S/2000 CPU supports eight addressing modes.
Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement @ERn+
@–ERn
5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8
Effective Address (EA) Calculation
In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit
effective address.
No Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Operand is general register contents.
1Register direct (Rn)
2 Register indirect (@Rn)
3 Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
r
op disp
r
op
rm
op rn
31 0
disp
31 0
General register contents
Sign extension
31 0
General register contents
31 2331 0
Don’t care
31 2331 0
Don’t care
24
24
Section 2 CPU
25
No Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Operand is immediate data
5 Absolute address
op 31 23
31 0
abs
@aa:8 7
op 31 23
31 0
Don’t care
@aa:16
op
@aa:24
@aa:32
abs 15
Sign
extension
16
31 2331 0
Don’t care
31 23
31 0
Don’t care
abs
op
abs
6 Immediate
op IMM
#xx:8/#xx:16/#xx:32
8
24
24
24
24
Don’t care H'FFFF
31 23
7 Program-counter relative
@(d:8,PC)/@(d:16,PC)
31 0
Don’t care
23 0
disp
0
31 2331 0
Don’t care
disp
op
23
op
8 Memory indirect @@aa:8
• Normal mode
abs 31 0
abs
H'000000 78
Memory contents 015 31 2331 0
Don’t care 1516
op
• Advanced mode
abs 31 0
abs
H'000000 78
0
31
PC contents
Sign
extension
Memory contents
24
24
24
H'00
Operand Size
Byte
Word
Longword
Value Added/Subtracted
1
2
4
r
op
31 0
31 23
4 Register indirect with post-increment or
pre-decrement
• Register indirect with post-increment @ERn+
• Register indirect with pre-decrement @–ERn
1, 2, or 4
General register contents
31 0
General register contents
1, 2, or 4
31 0
r
op
Don’t care
31 2331 0
Don’t care
24
24
Section 2 CPU
26
2.5 Instruction Set
The H8S/2000 CPU has 65 types of instructions.
Features
• Upward-compatible at object level with H8/300H and H8/300 CPUs.
• General register architecture
• 8/16/32-bit transfer instructions and arithmetic and logic instructions
— Byte (B), word (W), and longword (L) formats for transfer instructions and basic arithmetic and
logic instructions
• Unsigned and signed multiply and divide instructions
• Powerful bit-manipulation instructions
• Instructions for saving and restoring multiple registers
Assembler Format
The ADD instruction format is shown below as an example.
ADD. B Rs, Rd
Mnemonic Size Source
operand Destination
operand
Section 2 CPU
27
Instruction Set Table
1. Data transfer instructions
Addressing Mode/Instruction
Length (Bytes) Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation IHNZVC
Normal
Advanced
MOV MOV.B #xx:8,Rd B 2 #xx:8→Rd8 — — ↕↕0— 1
MOV.B Rs,Rd B 2 Rs8→Rd8 — — ↕↕0— 1
MOV.B @ERs,Rd B 2 @ERs→Rd8 — — ↕↕0— 2
MOV.B @(d:16,ERs),Rd B 4 @(d:16,ERs)→Rd8 — — ↕↕0— 3
MOV.B @(d:32,ERs),Rd B 8 @(d:32,ERs)→Rd8 — — ↕↕0— 5
MOV.B @ERs+,Rd B 2 @ERs→Rd8,ERs32+1→ERs32 — — ↕↕0— 3
MOV.B @aa:8,Rd B 2 @aa:8→Rd8 — — ↕↕0— 2
MOV.B @aa:16,Rd B 4 @aa:16→Rd8 — — ↕↕0— 3
MOV.B @aa:32,Rd B 6 @aa:32→Rd8 — — ↕↕0— 4
MOV.B Rs,@ERd B 2 Rs8→@ERd — — ↕↕0— 2
MOV.B Rs,@(d:16,ERd) B 4 Rd8→@(d:16,ERd) — — ↕↕0— 3
MOV.B Rs,@(d:32,ERd) B 8 Rd8→@(d:32,ERd) — — ↕↕0— 5
MOV.B Rs,@–ERd B 2 ERd32–1→ERd32,Rs8→@ERd — — ↕↕0— 3
MOV.B Rs,@aa:8 B 2 Rs8→@aa:8 — — ↕↕0— 2
MOV.B Rs,@aa:16 B 4 Rs8→@aa:16 — — ↕↕0— 3
MOV.B Rs,@aa:32 B 6 Rs8→@aa:32 — — ↕↕0— 4
MOV.W #xx:16,Rd W 4 #xx:16→Rd16 — — ↕↕0— 2
MOV.W Rs,Rd W 2 Rs16→Rd16 — — ↕↕0— 1
MOV.W @ERs,Rd W 2 @ERs→Rd16 — — ↕↕0— 2
MOV.W @(d:16,ERs),Rd W 4 @(d:16,ERs)→Rd16 — — ↕↕0— 3
MOV.W @(d:32,ERs),Rd W 8 @(d:32,ERs)→Rd16 — — ↕↕0— 5
MOV.W @ERs+,Rd W 2 ERs→Rd16,ERs32+2→ERs32 — — ↕↕0— 3
MOV.W @aa:16,Rd W 4 @aa:16→Rd16 — — ↕↕0— 3
MOV.W @aa:32,Rd W 6 @aa:32→Rd16 — — ↕↕0— 4
MOV.W Rs,@ERd W 2 Rs16→@ERd — — ↕↕0— 2
MOV.W Rs,@(d:16,ERd) W 4 Rs16→@(d:16,ERd) — — ↕↕0— 3
MOV.W Rs,@(d:32,ERd) W 8 Rs16→@(d:32,ERd) — — ↕↕0— 5
MOV.W Rs,@–ERd W 2 ERd32–2→ERd32,Rs16→@ERd — — ↕↕0— 3
MOV.W Rs,@aa:16 W 4 Rs16→@aa:16 — — ↕↕0— 3
MOV.W Rs,@aa:32 W 6 Rs16→@aa:32 — — ↕↕0— 4
MOV.L #xx:32,ERd L 6 #xx:32→ERd32 — — ↕↕0— 3
MOV.L ERs,ERd L 2 ERs32→ERd32 — — ↕↕0— 1
MOV.L @ERs,ERd L 4 @ERs→ERd32 — — ↕↕0— 4
MOV.L @(d:16,ERs),ERd L 6 @(d:16,ERs)→ERd32 — — ↕↕0— 5
MOV.L @(d:32,ERs),ERd L 10 @(d:32,ERs)→ERd32 — — ↕↕0— 7
MOV.L @ERs+,ERd L 4 @ERs→ERd32,ERs32+4→
@ERs32 —— ↕↕0— 5
MOV.L @aa:16,ERd L 6 @aa:16→ERd32 — — ↕↕0— 5
MOV.L @aa:32,ERd L 8 @aa:32→ERd32 — — ↕↕0— 6
Section 2 CPU
28
Addressing Mode/Instruction
Length (Bytes) Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation IHNZVC
Normal
Advanced
MOV MOV.L ERs,@ERd L 4 ERs32→@ERd — — ↕↕0— 4
MOV.L ERs,@(d:16,ERd) L 6 ERs32→@(d:16,ERd) — — ↕↕0— 5
MOV.L ERs,@(d:32,ERd) L 10 ERs32→@(d:32,ERd) — — ↕↕0— 7
MOV.L ERs,@–ERd L 4 ERd32–4→ERd32,ERs32→@ERd — — ↕↕0— 5
MOV.L ERs,@aa:16 L 6 ERs32→@aa:16 — — ↕↕0— 5
MOV.L ERs,@aa:32 L 8 ERs32→@aa:32 — — ↕↕0— 6
POP POP.W Rn W 2 @SP→Rn16,SP+2→SP — — ↕↕0— 3
POP.L ERn L 4 @SP→ERn32,SP+4→SP — — ↕↕0— 5
PUSH PUSH.W Rn W 2 SP–2→SP,Rn16→@SP — — ↕↕0— 3
PUSH.L ERn L 4 SP–4→SP,ERn32→@SP — — ↕↕0— 5
LDM LDM @SP+,(ERm–ERn) L 4 (@SP→ERn32,SP+4→SP)
Repeated for each register
restored
——————7/9/11 [1]
STM STM (ERm–ERn),@–SP L 4 (SP–4 →SP,ERn32→@SP)
Repeated for each register saved ——————7/9/11 [1]
MOVFPE MOVFPE @aa:16,Rd Cannot be used in the H8S/2350 Series [2]
MOVTPE MOVTPE Rs,@aa:16 [2]
Section 2 CPU
29
2. Arithmetic instructions
Addressing Mode/Instruction
Length (Bytes) Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation IHNZVC
Normal
Advanced
ADD ADD.B #xx:8,Rd B 2 Rd8+#xx:8→Rd8 — ↕↕↕↕↕ 1
ADD.B Rs,Rd B 2 Rd8+Rs8→Rd8 — ↕↕↕↕↕ 1
ADD.W #xx:16,Rd W 4 Rd16+#xx:16→Rd16 — [3] ↕↕↕↕ 2
ADD.W Rs,Rd W 2 Rd16+Rs16→Rd16 — [3] ↕↕↕↕ 1
ADD.L #xx:32,ERd L 6 ERd32+#xx:32→ERd32 — [4] ↕↕↕↕ 3
ADD.L ERs,ERd L 2 ERd32+ERs32→ERd32 — [4] ↕↕↕↕ 1
ADDX ADDX #xx:8,Rd B 2 Rd8+#xx:8+C→Rd8 — ↕↕[5] ↕↕ 1
ADDX Rs,Rd B 2 Rd8+Rs8+C→Rd8 — ↕↕[5] ↕↕ 1
ADDS ADDS #1,ERd L 2 ERd32+1→ERd32 —————— 1
ADDS #2,ERd L 2 ERd32+2→ERd32 —————— 1
ADDS #4,ERd L 2 ERd32+4→ERd32 —————— 1
INC INC.B Rd B 2 Rd8+1→Rd8 — — ↕↕↕—1
INC.W #1,Rd W 2 Rd16+1→Rd16 — — ↕↕↕—1
INC.W #2,Rd W 2 Rd16+2→Rd16 — — ↕↕↕—1
INC.L #1,ERd L 2 ERd32+1→ERd32 — — ↕↕↕—1
INC.L #2,ERd L 2 ERd32+2→ERd32 — — ↕↕↕—1
DAA DAA Rd B 2 Rd8 decimal adjust → Rd8 — *↕↕*↕1
SUB SUB.B Rs,Rd B 2 Rd8–Rs8→Rd8 — ↕↕↕↕↕ 1
SUB.W #xx:16,Rd W 4 Rd16–#xx:16→Rd16 — [3] ↕↕↕↕ 2
SUB.W Rs,Rd W 2 Rd16–Rs16→Rd16 — [3] ↕↕↕↕ 1
SUB.L #xx:32,ERd L 6 ERd32–#xx:32→ERd32 — [4] ↕↕↕↕ 3
SUB.L ERs,ERd L 2 ERd32–ERs32→ERd32 — [4] ↕↕↕↕ 1
SUBX SUBX #xx:8,Rd B 2 Rd8–#xx:8–C→Rd8 — ↕↕[5] ↕↕ 1
SUBX Rs,Rd B 2 Rd8–Rs8–C→Rd8 — ↕↕[5] ↕↕ 1
SUBS SUBS #1,ERd L 2 ERd32–1→ERd32 —————— 1
SUBS #2,ERd L 2 ERd32–2→ERd32 —————— 1
SUBS #4,ERd L 2 ERd32–4→ERd32 —————— 1
DEC DEC.B Rd B 2 Rd8–1→Rd8 — — ↕↕↕—1
DEC.W #1,Rd W 2 Rd16–1→Rd16 — — ↕↕↕—1
DEC.W #2,Rd W 2 Rd16–2→Rd16 — — ↕↕↕—1
DEC.L #1,ERd L 2 ERd32–1→ERd32 — — ↕↕↕—1
DEC.L #2,ERd L 2 ERd32–2→ERd32 — — ↕↕↕—1
DAS DAS Rd B 2 Rd8 decimal adjust → Rd8 — *↕↕*—1
MULXU MULXU.B Rs,Rd B 2 Rd8×Rs8→Rd16 (unsigned
multiplication) —————— 12
MULXU.W Rs,ERd W 2 Rd16×Rs16→ERd32 (unsigned
multiplication) —————— 20
MULXS MULXS.B Rs,Rd B 4 Rd8×Rs8→Rd16 (signed
multiplication) —— ↕↕—— 13
MULXS.W Rs,ERd W 4 Rd16×Rs16→ERd32 (signed
multiplication) —— ↕↕—— 21
Section 2 CPU
30
Addressing Mode/Instruction
Length (Bytes) Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation IHNZVC
Normal
Advanced
DIVXU DIVXU.B Rs,Rd B 2 Rd16÷Rs8→Rd16
(RdH: remainder, RdL: quotient)
(unsigned division)
— — [6] [7] — — 12
DIVXU.W Rs,ERd W 2 ERd32÷Rs16→ERd32
(Ed: remainder, Rd: quotient)
(unsigned division)
— — [6] [7] — — 20
DIVXS DIVXS.B Rs,Rd B 4 Rd16÷Rs8→Rd16
(RdH: remainder, RdL: quotient)
(signed division)
— — [8] [7] — — 13
DIVXS.W Rs,ERd W 4 ERd32÷Rs16→ERd32
(Ed: remainder, Rd: quotient)
(signed division)
— — [8] [7] — — 21
CMP CMP.B #xx:8,Rd B 2 Rd8–#xx:8 — ↕↕↕↕↕ 1
CMP.B Rs,Rd B 2 Rd8–Rs8 — ↕↕↕↕↕ 1
CMP.W #xx:16,Rd W 4 Rd16–#xx:16 — [3] ↕↕↕↕ 2
CMP.W Rs,Rd W 2 Rd16–Rs16 — [3] ↕↕↕↕ 1
CMP.L #xx:32,ERd L 6 ERd32–#xx:32 — [4] ↕↕↕↕ 3
CMP.L ERs,ERd L 2 ERd32–ERs32 — [4] ↕↕↕↕ 1
NEG NEG.B Rd B 2 0–Rd8→Rd8 — ↕↕↕↕↕ 1
NEG.W Rd W 2 0–Rd16→Rd16 — ↕↕↕↕↕ 1
NEG.L ERd L 2 0–ERd32→ERd32 — ↕↕↕↕↕ 1
EXTU EXTU.W Rd W 2 0 → (<bits 15 to 8> of Rd16) — — 0 ↕0— 1
EXTU.L ERd L 2 0 → (<bits 31 to 16> of ERd32) — — 0 ↕0— 1
EXTS EXTS.W Rd W 2 (<bit 7> of Rd16) → (<bits 15 to 8>
of Rd16) —— ↕↕0— 1
EXTS.L ERd L 2 (<bit 15> of ERd32) → (<bits 31 to
16> of ERd32) —— ↕↕0— 1
TAS TAS @ERd B 4 @ERd–0 → CRR set, (1) →
(<bit 7> of @ERd) —— ↕↕0— 4
Section 2 CPU
31
3. Logical instructions
Addressing Mode/Instruction
Length (Bytes) Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation IHNZVC
Normal
Advanced
AND AND.B #xx:8,Rd B 2 Rd8∧#xx:8→Rd8 — — ↕↕0— 1
AND.B Rs,Rd B 2 Rd8∧Rs8→Rd8 — — ↕↕0— 1
AND.W #xx:16,Rd W 4 Rd16∧#xx:16→Rd16 — — ↕↕0— 2
AND.W Rs,Rd W 2 Rd16∧Rs16→Rd16 — — ↕↕0— 1
AND.L #xx:32,ERd L 6 ERd32∧#xx:32→ERd32 — — ↕↕0— 3
AND.L ERs,ERd L 4 ERd32∧ERs32→ERd32 — — ↕↕0— 2
OR OR.B #xx:8,Rd B 2 Rd8∨#xx:8→Rd8 — — ↕↕0— 1
OR.B Rs,Rd B 2 Rd8∨Rs8→Rd8 — — ↕↕0— 1
OR.W #xx:16,Rd W 4 Rd16∨#xx:16→Rd16 — — ↕↕0— 2
OR.W Rs,Rd W 2 Rd16∨Rs16→Rd16 — — ↕↕0— 1
OR.L #xx:32,ERd L 6 ERd32∨#xx:32→ERd32 — — ↕↕0— 3
OR.L ERs,ERd L 4 ERd32∨ERs32→ERd32 — — ↕↕0— 2
XOR XOR.B #xx:8,Rd B 2 Rd8⊕#xx:8→Rd8 — — ↕↕0— 1
XOR.B Rs,Rd B 2 Rd8⊕Rs8→Rd8 — — ↕↕0— 1
XOR.W #xx:16,Rd W 4 Rd16⊕#xx:16→Rd16 — — ↕↕0— 2
XOR.W Rs,Rd W 2 Rd16⊕Rs16→Rd16 — — ↕↕0— 1
XOR.L #xx:32,ERd L 6 ERd32⊕#xx:32→ERd32 — — ↕↕0— 3
XOR.L ERs,ERd L 4 ERd32⊕ERs32→ERd32 — — ↕↕0— 2
NOT NOT.B Rd B 2 ¬ Rd8→Rd8 — — ↕↕0— 1
NOT.W Rd W 2 ¬ Rd16→Rd16 — — ↕↕0— 1
NOT.L ERd L 2 ¬ Rd32→Rd32 — — ↕↕0— 1
Section 2 CPU
32
4. Shift instructions
Addressing Mode/Instruction
Length (Bytes) Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation IHNZVC
Normal
Advanced
SHAL SHAL.B Rd
SHAL.B #2,Rd
SHAL.W Rd
SHAL.W #2,Rd
SHAL.L ERd
SHAL.L #2,ERd
B
B
W
W
L
L
2
2
2
2
2
2
C MSB LSB 0
—
—
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
1
1
1
1
1
1
SHAR SHAR.B Rd
SHAR.B #2,Rd
SHAR.W Rd
SHAR.W #2,Rd
SHAR.L ERd
SHAR.L #2,ERd
B
B
W
W
L
L
2
2
2
2
2
2
CMSB LSB
—
—
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
0
0
0
0
0
0
↕
↕
↕
↕
↕
↕
1
1
1
1
1
1
SHLL SHLL.B Rd
SHLL.B #2,Rd
SHLL.W Rd
SHLL.W #2,Rd
SHLL.L ERd
SHLL.L #2,ERd
B
B
W
W
L
L
2
2
2
2
2
2
C MSB LSB 0
—
—
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
0
0
0
0
0
0
↕
↕
↕
↕
↕
↕
1
1
1
1
1
1
SHLR SHLR.B Rd
SHLR.B #2,Rd
SHLR.W Rd
SHLR.W #2,Rd
SHLR.L ERd
SHLR.L #2,ERd
B
B
W
W
L
L
2
2
2
2
2
2
CMSB LSB
0
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
↕
↕
↕
↕
↕
↕
0
0
0
0
0
0
↕
↕
↕
↕
↕
↕
1
1
1
1
1
1
ROTXL ROTXL.B Rd
ROTXL.B #2,Rd
ROTXL.W Rd
ROTXL.W #2,Rd
ROTXL.L ERd
ROTXL.L #2,ERd
B
B
W
W
L
L
2
2
2
2
2
2
CMSB LSB
—
—
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
0
0
0
0
0
0
↕
↕
↕
↕
↕
↕
1
1
1
1
1
1
ROTXR ROTXR.B Rd
ROTXR.B #2,Rd
ROTXR.W Rd
ROTXR.W #2,Rd
ROTXR.L ERd
ROTXR.L #2,ERd
B
B
W
W
L
L
2
2
2
2
2
2
C
MSB LSB
—
—
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
0
0
0
0
0
0
↕
↕
↕
↕
↕
↕
1
1
1
1
1
1
Section 2 CPU
33
Addressing Mode/Instruction
Length (Bytes) Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation IHNZVC
Normal
Advanced
ROTL ROTL.B Rd
ROTL.B #2,Rd
ROTL.W Rd
ROTL.W #2,Rd
ROTL.L ERd
ROTL.L #2,ERd
B
B
W
W
L
L
2
2
2
2
2
2
CMSB LSB
—
—
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
0
0
0
0
0
0
↕
↕
↕
↕
↕
↕
1
1
1
1
1
1
ROTR ROTR.B Rd
ROTR.B #2,Rd
ROTR.W Rd
ROTR.W #2,Rd
ROTR.L ERd
ROTR.L #2,ERd
B
B
W
W
L
L
2
2
2
2
2
2
C
MSB LSB
—
—
—
—
—
—
—
—
—
—
—
—
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
↕
0
0
0
0
0
0
↕
↕
↕
↕
↕
↕
1
1
1
1
1
1
Section 2 CPU
34
5. Bit manipulation instructions
Addressing Mode/Instruction
Length (Bytes) Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation IHNZVC
Normal
Advanced
BSET BSET #xx:3,Rd B 2 (#xx:3 of Rd8)←1 —————— 1
BSET #xx:3,@ERd B 4 (#xx:3 of @ERd)←1 —————— 4
BSET #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)←1 —————— 4
BSET #xx:3,@aa:16 B 6 (#xx:3 of @aa:16)←1 —————— 5
BSET #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)←1 —————— 6
BSET Rn,Rd B 2 (Rn8 of Rd8)←1 —————— 1
BSET Rn,@ERd B 4 (Rn8 of @ERd)←1 —————— 4
BSET Rn,@aa:8 B 4 (Rn8 of @aa:8)←1 —————— 4
BSET Rn,@aa:16 B 6 (Rn8 of @aa:16)←1 —————— 5
BSET Rn,@aa:32 B 8 (Rn8 of @aa:32)←1 —————— 6
BCLR BCLR #xx:3,Rd B 2 (#xx:3 of Rd8)←0 —————— 1
BCLR #xx:3,@ERd B 4 (#xx:3 of @ERd)←0 —————— 4
BCLR #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)←0 —————— 4
BCLR #xx:3,@aa:16 B 6 (#xx:3 of @aa:16)←0 —————— 5
BCLR #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)←0 —————— 6
BCLR Rn,Rd B 2 (Rn8 of Rd8)←0 —————— 1
BCLR Rn,@ERd B 4 (Rn8 of @ERd)←0 —————— 4
BCLR Rn,@aa:8 B 4 (Rn8 of @aa:8)←0 —————— 4
BCLR Rn,@aa:16 B 6 (Rn8 of @aa:16)←0 —————— 5
BCLR Rn,@aa:32 B 8 (Rn8 of @aa:32)←0 —————— 6
BNOT BNOT #xx:3,Rd B 2 (#xx:3 of Rd8)← [¬ (#xx:3 of Rd8)] —————— 1
BNOT #xx:3,@ERd B 4 (#xx:3 of @ERd)← [¬ (#xx:3 of
@ERd)] —————— 4
BNOT #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)← [¬ (#xx:3 of
@aa:8)] —————— 4
BNOT #xx:3,@aa:16 B 6 (#xx:3 of @aa:16)← [¬ (#xx:3 of
@aa:16)] —————— 5
BNOT #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)← [¬ (#xx:3 of
@aa:32)] —————— 6
BNOT Rn,Rd B 2 (Rn8 of Rd8)← [¬ (Rn8 of Rd8)] —————— 1
BNOT Rn,@ERd B 4 (Rn8 of @ERd)← [¬ (Rn8 of
@ERd)] —————— 4
BNOT Rn,@aa:8 B 4 (Rn8 of @aa:8)← [¬ (Rn8 of
@aa:8)] —————— 4
BNOT Rn,@aa:16 B 6 (Rn8 of @aa:16)← [¬ (Rn8 of
@aa:16)] —————— 5
BNOT Rn,@aa:32 B 8 (Rn8 of @aa:32)← [¬ (Rn8 of
@aa:32)] —————— 6
Section 2 CPU
35
Addressing Mode/Instruction
Length (Bytes) Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation IHNZVC
Normal
Advanced
BTST BTST #xx:3,Rd B 2 (#xx:3 of Rd8)→Z ——— ↕—— 1
BTST #xx:3,@ERd B 4 (#xx:3 of @ERd)→Z ——— ↕—— 3
BTST #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)→Z ——— ↕—— 3
BTST #xx:3,@aa:16 B 6 (#xx:3 of @aa:16)→Z ——— ↕—— 4
BTST #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)→Z ——— ↕—— 5
BTST Rn,Rd B 2 (Rn8 of Rd8)→Z ——— ↕—— 1
BTST Rn,@ERd B 4 (Rn8 of @ERd)→Z ——— ↕—— 3
BTST Rn,@aa:8 B 4 (Rn8 of @aa:8)→Z ——— ↕—— 3
BTST Rn,@aa:16 B 6 (Rn8 of @aa:16)→Z ——— ↕—— 4
BTST Rn,@aa:32 B 8 (Rn8 of @aa:32)→Z ——— ↕—— 5
BLD BLD #xx:3,Rd B 2 (#xx:3 of Rd8)→C ————— ↕1
BLD #xx:3,@ERd B 4 (#xx:3 of @ERd)→C ————— ↕3
BLD #xx:3,@aa:8 B 4 (#xx:3 of @aa:8)→C ————— ↕3
BLD #xx:3,@aa:16 B 6 (#xx:3 of @aa:16)→C ————— ↕4
BLD #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)→C ————— ↕5
BILD BILD #xx:3,Rd B 2 ¬ (#xx:3 of Rd8)→C ————— ↕1
BILD #xx:3,@ERd B 4 ¬ (#xx:3 of @ERd)→C ————— ↕3
BILD #xx:3,@aa:8 B 4 ¬ (#xx:3 of @aa:8)→C ————— ↕3
BILD #xx:3,@aa:16 B 6 ¬ (#xx:3 of @aa:16)→C ————— ↕4
BILD #xx:3,@aa:32 B 8 ¬ (#xx:3 of @aa:32)→C ————— ↕5
BST BST #xx:3,Rd B 2 C→(#xx:3 of Rd8) —————— 1
BST #xx:3,@ERd B 4 C→(#xx:3 of @ERd24) —————— 4
BST #xx:3,@aa:8 B 4 C→(#xx:3 of @aa:8) —————— 4
BST #xx:3,@aa:16 B 6 C→(#xx:3 of @aa:16) —————— 5
BST #xx:3,@aa:32 B 8 C→(#xx:3 of @aa:32) —————— 6
BIST BIST #xx:3,Rd B 2 ¬ C→(#xx:3 of Rd8) —————— 1
BIST #xx:3,@ERd B 4 ¬ C→(#xx:3 of @ERd24) —————— 4
BIST #xx:3,@aa:8 B 4 ¬ C→(#xx:3 of @aa:8) —————— 4
BIST #xx:3,@aa:16 B 6 ¬ C→(#xx:3 of @aa:16) —————— 5
BIST #xx:3,@aa:32 B 8 ¬ C→(#xx:3 of @aa:32) —————— 6
BAND BAND #xx:3,Rd B 2 C∧(#xx:3 of Rd8)→C ————— ↕1
BAND #xx:3,@ERd B 4 C∧(#xx:3 of @ERd24)→C ————— ↕3
BAND #xx:3,@aa:8 B 4 C∧(#xx:3 of @aa:8)→C ————— ↕3
BAND #xx:3,@aa:16 B 6 C∧(#xx:3 of @aa:16)→C ————— ↕4
BAND #xx:3,@aa:32 B 8 C∧(#xx:3 of @aa:32)→C ————— ↕5
BIAND BIAND #xx:3,Rd B 2 C∧ [¬ (#xx:3 of Rd8)]→C ————— ↕1
BIAND #xx:3,@ERd B 4 C∧ [¬ (#xx:3 of @ERd24)]→C ————— ↕3
BIAND #xx:3,@aa:8 B 4 C∧ [¬ (#xx:3 of @aa:8)]→C ————— ↕3
BIAND #xx:3,@aa:16 B 6 C∧ [¬ (#xx:3 of @aa:16)]→C ————— ↕4
BIAND #xx:3,@aa:32 B 8 C∧ [¬ (#xx:3 of @aa:32)]→C ————— ↕5
Section 2 CPU
36
Addressing Mode/Instruction
Length (Bytes) Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation IHNZVC
Normal
Advanced
BOR BOR #xx:3,Rd B 2 C∨(#xx:3 of Rd8)→C ————— ↕1
BOR #xx:3,@ERd B 4 C∨(#xx:3 of @ERd24)→C ————— ↕3
BOR #xx:3,@aa:8 B 4 C∨(#xx:3 of @aa:8)→C ————— ↕3
BOR #xx:3,@aa:16 B 6 C∨(#xx:3 of @aa:16)→C ————— ↕4
BOR #xx:3,@aa:32 B 8 C∨(#xx:3 of @aa:32)→C ————— ↕5
BIOR BIOR #xx:3,Rd B 2 C∨ [¬ (#xx:3 of Rd8)]→C ————— ↕1
BIOR #xx:3,@ERd B 4 C∨ [¬ (#xx:3 of @ERd24)]→C ————— ↕3
BIOR #xx:3,@aa:8 B 4 C∨ [¬ (#xx:3 of @aa:8)]→C ————— ↕3
BIOR #xx:3,@aa:16 B 6 C∨ [¬ (#xx:3 of @aa:16)]→C ————— ↕4
BIOR #xx:3,@aa:32 B 8 C∨ [¬ (#xx:3 of @aa:32)]→C ————— ↕5
BXOR BXOR #xx:3,Rd B 2 C⊕ (#xx:3 of Rd8)→C ————— ↕1
BXOR #xx:3,@ERd B 4 C⊕ (#xx:3 of @ERd24)→C ————— ↕3
BXOR #xx:3,@aa:8 B 4 C⊕ (#xx:3 of @aa:8)→C ————— ↕3
BXOR #xx:3,@aa:16 B 6 C⊕ (#xx:3 of @aa:16)→C ————— ↕4
BXOR #xx:3,@aa:32 B 8 C⊕ (#xx:3 of @aa:32)→C ————— ↕5
BIXOR BIXOR #xx:3,Rd B 2 C⊕ [¬ (#xx:3 of Rd8)]→C ————— ↕1
BIXOR #xx:3,@ERd B 4 C⊕ [¬ (#xx:3 of @ERd24)]→C ————— ↕3
BIXOR #xx:3,@aa:8 B 4 C⊕ [¬ (#xx:3 of @aa:8)]→C ————— ↕3
BIXOR #xx:3,@aa:16 B 6 C⊕ [¬ (#xx:3 of @aa:16)]→C ————— ↕4
BIXOR #xx:3,@aa:32 B 8 C⊕ [¬ (#xx:3 of @aa:32)]→C ————— ↕5
Section 2 CPU
37
6. Branch instructions
Addressing Mode/Instruction
Length (Bytes) Operation Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Branching
Conditions IHNZVC
Normal
Advanced
Bcc BRA d:8(BT d:8) — 2 if condition is true Always —————— 2
BRA d:16(BT d:16) — 4 then —————— 3
BRN d:8(BF d:8) — 2 PC←PC+d Never —————— 2
BRN d:16(BF d:16) — 4 else next; —————— 3
BHI d:8 — 2 C∨Z=0 —————— 2
BHI d:16 — 4 —————— 3
BLS d:8 — 2 C∨Z=1 —————— 2
BLS d:16 — 4 —————— 3
BCC d:8(BHS d:8) — 2 C=0 —————— 2
BCC d:16(BHS d:16) — 4 —————— 3
BCS d:8(BLO d:8) — 2 C=1 —————— 2
BCS d:16(BLO d:16) — 4 —————— 3
BNE d:8 — 2 Z=0 —————— 2
BNE d:16 — 4 —————— 3
BEQ d:8 — 2 Z=1 —————— 2
BEQ d:16 — 4 —————— 3
BVC d:8 — 2 V=0 —————— 2
BVC d:16 — 4 —————— 3
BVS d:8 — 2 V=1 —————— 2
BVS d:16 — 4 —————— 3
BPL d:8 — 2 N=0 —————— 2
BPL d:16 — 4 —————— 3
BMI d:8 — 2 N=1 —————— 2
BMI d:16 — 4 —————— 3
BGE d:8 — 2 N⊕V=0 —————— 2
BGE d:16 — 4 —————— 3
BLT d:8 — 2 N⊕V=1 —————— 2
BLT d:16 — 4 —————— 3
BGT d:8 — 2 Z∨(N⊕V)=0 —————— 2
BGT d:16 — 4 —————— 3
BLE d:8 — 2 Z∨(N⊕V)=1 —————— 2
BLE d:16 — 4 —————— 3
JMP JMP @ERn — 2 PC←ERn —————— 2
JMP @aa:24 — 4 PC←aa:24 —————— 3
JMP @@aa:8 — 2 PC←@aa:8 —————— 4 5
BSR BSR d:8 — 2 PC→@–SP,PC←PC+d:8 —————— 3 4
BSR d:16 — 4 PC→@–SP,PC←PC+d:16 —————— 4 5
JSR JSR @ERn — 2 PC→@–SP,PC←ERn —————— 3 4
JSR @aa:24 — 4 PC→@–SP,PC←aa:24 —————— 4 5
JSR @@aa:8 — 2 PC→@–SP,PC←@aa:8 —————— 4 6
RTS RTS — 2 PC←@SP+ —————— 4 5
Section 2 CPU
38
7. System control instructions
Addressing Mode/Instruction
Length (Bytes) Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation IHNZVC
Normal
Advanced
TRAPA TRAPA #xx:2 — 2 PC→@–SP,CCR→@–SP,
EXR→@–SP,<vector>→PC 1————— 7
[9] 8
[9]
RTE RTE — EXR←@SP+,CCR←@SP+,
PC←@SP+ ↕↕↕↕↕↕ 5 [9]
SLEEP SLEEP — Transition to power-down state —————— 2
LDC LDC #xx:8,CCR B 2 #xx:8→CCR ↕↕↕↕↕↕ 1
LDC #xx:8,EXR B 4 #xx:8→EXR —————— 2
LDC Rs,CCR B 2 Rs8→CCR ↕↕↕↕↕↕ 1
LDC Rs,EXR B 2 Rs8→EXR —————— 1
LDC @ERs,CCR W 4 @ERs→CCR ↕↕↕↕↕↕ 3
LDC @ERs,EXR W 4 @ERs→EXR —————— 3
LDC @(d:16,ERs),CCR W 6 @(d:16,ERs)→CCR ↕↕↕↕↕↕ 4
LDC @(d:16,ERs),EXR W 6 @(d:16,ERs)→EXR —————— 4
LDC @(d:32,ERs),CCR W 10 @(d:32,ERs)→CCR ↕↕↕↕↕↕ 6
LDC @(d:32,ERs),EXR W 10 @(d:32,ERs)→EXR —————— 6
LDC @ERs+,CCR W 4 @ERs→CCR,ERs32+2→ERs32 ↕↕↕↕↕↕ 4
LDC @ERs+,EXR W 4 @ERs→EXR,ERs32+2→ERs32 —————— 4
LDC @aa:16,CCR W 6 @aa:16→CCR ↕↕↕↕↕↕ 4
LDC @aa:16,EXR W 6 @aa:16→EXR —————— 4
LDC @aa:32,CCR W 8 @aa:32→CCR ↕↕↕↕↕↕ 5
LDC @aa:32,EXR W 8 @aa:32→EXR —————— 5
STC STC CCR,Rd B 2 CCR→Rd8 —————— 1
STC EXR,Rd B 2 EXR→Rd8 —————— 1
STC CCR,@ERd W 4 CCR→@ERd —————— 3
STC EXR,@ERd W 4 EXR→@ERd —————— 3
STC CCR,@(d:16,ERd) W 6 CCR→@(d:16,ERd) —————— 4
STC EXR,@(d:16,ERd) W 6 EXR→@(d:16,ERd) —————— 4
STC CCR,@(d:32,ERd) W 10 CCR→@(d:32,ERd) —————— 6
STC EXR,@(d:32,ERd) W 10 EXR→@(d:32,ERd) —————— 6
STC CCR,@–ERd W 4 ERd32–2→ERd32,CCR→@ERd —————— 4
STC EXR,@–ERd W 4 ERd32–2→ERd32,EXR→@ERd —————— 4
STC CCR,@aa:16 W 6 CCR→@aa:16 —————— 4
STC EXR,@aa:16 W 6 EXR→@aa:16 —————— 4
STC CCR,@aa:32 W 8 CCR→@aa:32 —————— 5
STC EXR,@aa:32 W 8 EXR→@aa:32 —————— 5
ANDC ANDC #xx:8,CCR B 2 CCR ∧#xx:8→CCR ↕↕↕↕↕↕ 1
ANDC #xx:8,EXR B 4 EXR ∧#xx:8→EXR —————— 2
ORC ORC #xx:8,CCR B 2 CCR ∨#xx:8→CCR ↕↕↕↕↕↕ 1
ORC #xx:8,EXR B 4 EXR ∨#xx:8→EXR —————— 2
XORC XORC #xx:8,CCR B 2 CCR ⊕ #xx:8→CCR ↕↕↕↕↕↕ 1
XORC #xx:8,EXR B 4 EXR ⊕ #xx:8→EXR —————— 2
NOP NOP — 2 PC←PC+2 —————— 1
Section 2 CPU
39
8. Block transfer instructions
Addressing Mode/Instruction
Length (Bytes) Condition Code No. of
States*1
Mnemonic
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation IHNZVC
Normal
Advanced
EEPMOV EEPMOV.B — 4 if R4L≠0
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4L–1→R4L
Until R4L=0
else next;
—————— 4+2n*2
EEPMOV.W — 4 if R4≠0
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4–1→R4
Until R4=0
else next;
—————— 4+2n*2
Notes: *1 The number of states is the number of states required for execution when the instruction and its operands are
located in on-chip memory.
*2 n is the initial value of R4L or R4.
[1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers.
[2] Cannot be used in the H8S/2350 Series.
[3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
[4] Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
[5] Retains its previous value when the result is zero; otherwise cleared to 0.
[6] Set to 1 when the divisor is negative; otherwise cleared to 0.
[7] Set to 1 when the divisor is zero; otherwise cleared to 0.
[8] Set to 1 when the quotient is negative; otherwise cleared to 0.
[9] One additional state is required for execution when EXR is valid.
Section 2 CPU
40
Number of States Required for Execution
The number of states shown in the instruction set table is the number of states required for execution
when the op code and operand data are located in a one-cycle area on which word access is possible,
such as on-chip memory. When the op code or operand data is accessed from an on-chip supporting
module or an external address, the number of states increases as shown in the table below.
Access Conditions
On-Chip Supporting External Data Bus
Cycle On-Chip Module 8-Bit Bus 16-Bit Bus
Memory 8-Bit
Bus 16-Bit
Bus 2-State
Access 3-State
Access 2-State
Access 3-State
Access
Instruction fetch
Branch address read 4 4 6+2m
Stack operation 1 2 2 3+m
Byte data access 2 2 3+m
Word data access 4 4 6+2m
Internal operation 1
Legend
m: Number of wait states inserted into external device access
Condition Code Notation
Symbol Meaning
↕Changes according to the result of instruction execution
*Undetermined (no guaranteed value)
0 Always cleared to 0
1 Always set to 1
— Not affected by execution of the instruction
Section 2 CPU
41
Operation Notation
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
EXR Extend register
CCR Condition code register
N N (negative) flag of CCR
Z Z (zero) flag of CCR
V V (overflow) flag of CCR
C C (carry) flag of CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
×Multiplication
÷Division
∧AND logical
∨OR logical
⊕Exclusive OR logical
→Transfer from left-hand operand to right-hand operand, or
transition from left-hand state to right-hand state
¬ NOT (logical complement)
( ) < > Operand contents
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length
Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L),
16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to
ER7).
Section 2 CPU
42
2.6 Basic Bus Timing
The CPU operates on the basis of the system clock (ø). One ø clock cycle is called a state, and a bus
cycle consists of one, two, or three states. Different access methods are used for on-chip memory, on-
chip supporting modules, and external devices.
Basic Clock Timing
An external clock is input to the EXTAL pin, or a crystal oscillator is connected to the EXTAL pin, to
generate the system clock (ø). An external clock or crystal oscillator of the same frequency as the ø
clock should be used.
EXTAL Duty
correction
circuit
Oscillator
Medium-
speed
clock
divider
System clock
To ø pin Internal clock
To on-chip
supporting
modules
Bus master clock
To CPU, DTC, DMAC
ø/2 to ø/32
SCK1, SCK0
SCKCR
Bus
master
clock
selection
circuit
XTAL
CPU Read/Write Cycles
The CPU operates on the basis of the system clock (ø). One ø clock cycle is called a state, and a bus
cycle consists of one, two, or three states. Different access methods are used for on-chip memory, on-
chip supporting modules, and external devices. Access to the external address space can be controlled
by the bus controller.
Section 2 CPU
43
On-Chip Memory: On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting
both byte and word access.
Internal address bus
Internal read signal
Internal data bus
Internal write signal
Internal data bus
ø
Bus cycle
T1
Address
Read data
Write data
Read access
Write access
On-Chip Memory Access Cycle (One-State Access)
Bus cycle
T1
HeldAddress bus
AS
RD
HWR, LWR
Data bus
ø
High
High
High
High impedance
Pin States during On-Chip Memory Access
Section 2 CPU
44
On-Chip Supporting Module: The on-chip supporting modules are accessed in two states. The data
bus is 8 or 16 bits wide, depending on the internal I/O register being accessed.
Bus cycle
T1 T2
Address
Read data
Write data
Internal address bus
Internal read signal
Internal data bus
Internal write signal
Internal data bus
ø
Read access
Write access
On-Chip Supporting Module Access Timing (Two-State Access)
Bus cycle
T1 T2
Held
High
High
High
High impedance
Address bus
AS
RD
HWR, LWR
Data bus
ø
Pin States during On-Chip Supporting Module Access
Section 2 CPU
45
External Address Space: The external address space is accessed via an 8-bit or 16-bit bus, and in two
or three states. Wait state insertion is possible in the case of 3-state access. See the Bus Controller
section for details.
Section 2 CPU
46
2.7 Processing States
The CPU has five processing states: the reset state, program execution state, exception-handling state,
bus-released state, and power-down state.
Reset State
State in which the CPU and all on-chip supporting modules are initialized and halted
Program Execution State
State in which the CPU executes the program sequentially
Exception-Handling State
Transient state in which exception handling is executed as the result of an reset, interrupt, or trap
instruction exception handling source
Bus-Released State
State in which the external bus is released in response to a bus request signal from a bus master other
than the CPU
Power-Down State
State in which CPU operation is stopped, and power consumption is kept low (sleep mode, software
standby mode, hardware standby mode). The power-down state also includes medium-speed mode and
module stop mode.
Section 2 CPU
47
State Transition Diagram
End of bus release
Bus request
Interrupt request
External interrupt
RES = High
Request for exception handling
STBY = High, RES = Low
End of bus request
Bus request
SLEEP instruction
with SSBY = 0
SLEEP instruction with
SSBY = 1
End of exception handling
Reset state*1
Exception-handling state
Bus-released state
Hardware standby mode*2
Software standby mode
Sleep mode
Power-down state
Program execution state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low. A transition to the reset state can also be caused by watchdog
timer overflow.
2. From an
y
state, a transition to hardware standb
y
mode occurs when STBY
g
oes low.
Section 2 CPU
48
2.8 Exception Handling
The CPU exception handling is initiated by a reset, a trap instruction, or an interrupt. A priority system
is provided for exception handling, and simultaneously generated exceptions are handled in order of
priority.
Exception Handling Types and Priorities
Priority Exception Type Start of Exception Handling
High
Low
Reset
Trace
Interrupt
Trap instruction
(TRAPA)
After a low-to-high transition at the RES pin, or when the watchdog timer
overflows
After instruction or exception handling execution when the trace (T) bit is 1
When an interrupt is generated, after instruction or exception handling
execution
When a trap (TRAPA) instruction is executed
Exception Handling Operation
Exception handling is started by any of the exception handling sources. Trap instruction exception
handling is always accepted in the program execution state.
The operations in trap instruction and interrupt exception handling are as follows.
(1) The program counter (PC), condition code register (CCR), and extended register (EXR) are saved
on the stack.
(2) The interrupt mask bit is updated, and the T bit is cleared to 0.
(3) The vector address corresponding to the activation source is generated, and program execution is
started from the address indicates by the contents of the vector address.
In reset exception handling, only operations (2) and (3) are performed.
Section 2 CPU
49
Exception Vector Table
Vector Address*1
Exception Source Vector Number Normal Mode Advanced Mode
Power-on reset 0 H'0000–H'0001 H'0000–H'0003
Manual reset 1 H'0002–H'0003 H'0004–H'0007
Reserved for system use 2
3
4
H'0004–H'0006
H'0006–H'0007
H'0008–H'0009
H'0008–H'000B
H'000C–H'000F
H'0010–H'0013
Trace 5 H'000A–H'000B H'0014–H0017
Reserved for system use 6 H'000C–H'000D H'0018–H001B
External interrupt NMI 7 H'000E–H'000F H'001C–H'001F
Trap instruction (4 sources) 8
9
10
11
H'0010–H'0011
H'0012–H'0013
H'0014–H'0015
H'0016–H'0017
H'0020–H'0023
H'0024–H'0027
H'0028–H'002B
H'002C–H'002F
Reserved for system use 12
13
14
15
H'0018–H'0019
H'001A–H'001B
H'001C–H'001D
H'001E–H'001F
H'0030–H'0033
H'0034–H'0037
H'0038–H'003B
H'003C–H'003F
External interrupt IRQ0 16 H'0020–H'0021 H'0040–H'0043
IRQ1 17 H'0022–H'0023 H'0044–H'0047
IRQ2 18 H'0024–H'0025 H'0048–H'004B
IRQ3 19 H'0026–H'0027 H'004C–H'004F
IRQ4 20 H'0028–H'0029 H'0050–H'0053
IRQ5 21 H'002A–H'002B H'0054–H'0057
IRQ6 22 H'002C–H'002D H'0058–H'005B
IRQ7 23 H'002E–H'002F H'005C–H'005F
Internal
interrupt*224
to
91
H'0030–H'0031
to
H'00AE–H'00AF
H'0060–H'0063
to
H'015C–H'015F
Notes: 1. Lower 16 bits of address
2. See the Interrupt Exception Vector Table for the internal interrupt vector table.
Section 2 CPU
50
2.9 Interrupts
This section describes the sru interrupt, one of the external interrupt sources.
Interrupts are controlled by the interrupt controller. There are a total of 51 interrupt sources, comprising
nine external interrupts from the external pins (NMI, IRQ0 to IRQ7), and 42 internal interrupts from
on-chip supporting modules. A separate vector number is assigned to each interrupt.
Interrupt Control
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system
control register (SYSCR).
The interrupt controller controls interrupts on the basis of the control mode set by the INTM1 and
INTM0 bits, the interrupt priorities set by interrupt priority register (IPR), and the masking conditions
set by the I bit in CCR and bits I2 to I0 in EXR.
NMI is the highest-priority interrupt, and is always accepted.
Block Diagram of Interrupt Controller
SYSCR
NMI input
IRQ input
Internal interrupt request
WOVI to TEI
INTM1 INTM0
NMIEG
NMI input unit
IRQ input unit
ISR
ISCR IER
IPR
Interrupt controller
Priority
determination
Interrupt request
Vector number
I2 to I0
ICCR
EXR
CPU
Legend
ISCR:
IER:
ISR:
IRQ sense control register
IRQ enable register
IRQ status register
IPR:
SYSCR: Interrupt priority register
System control register
Section 2 CPU
51
Interrupt Control Modes
Interrupt
Control
Mode
SYSCR
INTM1 INTM0
Priority
Setting
Registers Interrupt
Mask Bits Description
0 0 0 — I Interrupt mask control is performed by the I bit.
1*1— — —
2 1 0 IPR I2 to I0 8-level interrupt mask control is performed by bits I2
to I0.
8 priority levels can be set with IPR.
3*1— — —
Note: * Interrupt control modes 1 and 3 cannot be set.
Block Diagram of Interrupt Control Operation
IPR
I2 to I0I
8-level mask
control
Default
priority
determination Vector number
Interrupt
acceptance
control
Interrupt source
Interrupt control
mode 0 Interrupt control
mode 2
Interrupt Control Mode 0
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means
of the I bit in CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1.
Interrupt Control Mode 2
Eight-level masking can be implemented for IRQ interrupts and on-chip supporting module interrupts
by comparing the interrupt mask level bits (I2 to I0) in EXR and the IPR priority level.
Section 2 CPU
52
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of Vector Address*
Interrupt Source Interrupt
Source Vector
Number Normal
Mode Advanced
Mode IPR Priority
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
SWDTEND (software
activation interrupt end)
WOVI (interval timer)
CMI (compare-match)
ADI (A/D conversion end)
TGI0A (TGR0A input capture/
compare-match)
TGI0B (TGR0B input capture/
compare-match)
TGI0C (TGR0C input capture/
compare-match)
TGI0D (TGR0D input capture/
compare-match)
TCI0V (overflow 0)
TGI1A (TGR1A input capture/
compare-match)
TGI1B (TGR1B input capture/
compare-match)
TCI1V (overflow 1)
TCI1U (underflow 1)
TGI2A (TGR2A input capture/
compare-match)
TGI2B (TGR2B input capture/
compare-match)
TCI2V (overflow 2)
TCI2U (underflow 2)
External
pin
DTC
Watchdog
timer
Refresh
controller
A/D
TPU
channel 0
TPU
channel 1
TPU
channel 2
7
16
17
18
19
20
21
22
23
24
25
26
28
32
33
34
35
36
40
41
42
43
44
45
46
47
H'000E
H'0020
H'0022
H'0024
H'0026
H'0028
H'002A
H'002C
H'002E
H'0030
H'0032
H'0034
H'0038
H'0040
H'0042
H'0044
H'0046
H'0048
H'0050
H'0052
H'0054
H'0056
H'0058
H'005A
H'005C
H'005E
H'001C
H'0040
H'0044
H'0048
H'004C
H'0050
H'0054
H'0058
H'005C
H'0060
H'0064
H'0068
H'0070
H'0080
H'0084
H'0088
H'008C
H'0090
H'00A0
H'00A4
H'00A8
H'00AC
H'00B0
H'00B4
H'00B8
H'00BC
IPRA6–IPRA4
IPRA2–IPRA0
IPRB6–IPRB4
IPRB2–IPRB0
IPRC6–IPRC4
IPRC2–IPRC0
IPRD6–IPRD4
IPRD2–IPRD0
IPRE2–IPRE0
IPRF6–IPRF4
IPRF2–IPRF0
IPRG6–IPRG4
High
Low
Note: * Lower 16 bits of the start address.
Section 2 CPU
53
Origin of Vector Address*
Interrupt Source Interrupt
Source Vector
Number Normal
Mode Advanced
Mode IPR Priority
TGI3A (TGR3A input capture/
compare-match)
TGI3B (TGR3B input capture/
compare-match)
TGI3C (TGR3C input capture/
compare-match)
TGI3D (TGR3D input capture/
compare-match)
TCI3V (overflow 3)
TGI4A (TGR4A input capture/
compare-match)
TGI4B (TGR4B input capture/
compare-match)
TCI4V (overflow 4)
TCI4U (underflow 4)
TGI5A (TGR5A input capture/
compare-match)
TGI5B (TGR5B input capture/
compare-match)
TCI5V (overflow 5)
TCI5U (underflow 5)
DEND0A (channel 0/channel
0A transfer end)
DEND0B (channel 0B transfer
end)
DEND1A (channel 1/channel
1A transfer end)
DEND1B (channel 1B transfer
end
ERI0 (receive error 0)
RXI0 (reception completed 0)
TXI0 (transmit data empty 0)
TEI0 (transmission end 0)
ERI1 (receive error 1)
RXI1 (reception completed 1)
TXI1 (transmit data empty 1)
TEI1 (transmission end 1)
TPU
channel 3
TPU
channel 4
TPU
channel 5
DMAC
SCI
channel 0
SCI
channel 1
48
49
50
51
52
56
57
58
59
60
61
62
63
72
73
74
75
80
81
82
83
84
85
86
87
H'0060
H'0062
H'0064
H'0066
H'0068
H'0070
H'0072
H'0074
H'0076
H'0078
H'007A
H'007C
H'007E
H'0090
H'0092
H'0094
H'0096
H'00A0
H'00A2
H'00A4
H'00A6
H'00A8
H'00AA
H'00AC
H'00AE
H'00C0
H'00C4
H'00C8
H'00CC
H'00D0
H'00E0
H'00E4
H'00E8
H'00EC
H'00F0
H'00F4
H'00F8
H'00FC
H'0120
H'0124
H'0128
H'012C
H'0140
H'0144
H'0148
H'014C
H'0150
H'0154
H'0158
H'015C
IPRG2–IPRG0
IPRH6–IPRH4
IPRH2–IPRH0
IPRJ6–IPRJ4
IPRJ2–IPRJ0
IPRK6–IPRK4
High
Low
Note: *Lower 16 bits of the start address
Section 2 CPU
54
2.10 Operating Modes
The H8S/2351 supports seven operating modes, while the H8S/2350 supports three operating modes.
These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the
initial bus width setting, by setting the mode pins (MD2 to MD0).
Normal Modes (Modes 1 to 3)
Mode 1 (Expansion Mode with On-Chip ROM Disabled): The CPU can access a 64-kbyte address
space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set immediately after a
reset.
Ports B and C function as an address bus, port D functions as a data bus, and part of port F carries bus
control signals.
Mode 2 (Expansion Mode with On-Chip ROM Enabled) (H8S/2351 Only): The CPU can access a
64-kbyte address space in normal mode. The on-chip ROM is enabled, and 8-bit bus mode is set
immediately after a reset.
Ports B and C function as input ports immediately after a reset. They can each be set to output
addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions
as a data bus, and part of port F carries bus control signals.
The amount of on-chip ROM that can be used is limited to 56 kbytes.
Mode 3 (Single-Chip Mode) (H8S/2351 Only): The CPU can access a 64-kbyte address space in
normal mode. The on-chip ROM is enabled, but external addresses cannot be accessed.
All I/O ports are available for use as input-output ports.
The amount of on-chip ROM that can be used is limited to 56 kbytes.
Advanced Modes (Modes 4 to 7)
Mode 4 (Expansion Mode with On-Chip ROM Disabled): The CPU can access a 16-Mbyte address
space in advanced mode. The on-chip ROM is disabled.
Ports A, B and C function as an address bus, ports D and E function as a data bus, and part of port F
carries bus control signals.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access is
designated by the bus controller for all areas, the bus mode switches to 8 bits.
Mode 5 (Expansion Mode with On-Chip ROM Disabled): The CPU can access a 16-Mbyte address
space in advanced mode. The on-chip ROM is disabled.
Section 2 CPU
55
Ports A, B and C function as an address bus, port D function as a data bus, and part of port F carries
bus control signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if at least one area is
designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes
a data bus.
Mode 6 (Expansion Mode with On-Chip ROM Enabled) (H8S/2351 Only): The CPU can access a
16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
Ports A, B and C function as input ports immediately after a reset. They can each be set to output
addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions
as a data bus, and part of port F carries bus control signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas.
Mode 7 (Single-Chip Mode) (H8S/2351 Only): The CPU can access a 16-Mbyte address space in
advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed.
All I/O ports are available for use as input-output ports.
Kinds of Operating Mode
MCU CPU External Data Bus
Operating
Mode MD2 MD1 MD0 Operating
Mode Description On-Chip ROMInitial
Width Max.
Width
0 000 — — — — —
1 1 Normal Expanded mode with
on-chip ROM disabled Disabled 8 bits 16 bits
2*1 0 Expanded mode with
on-chip ROM enabled Enabled 8 bits 16 bits
3*1 Single-chip mode — —
4 1 0 0 Advanced Expanded mode with
on-chip ROM disabled Disabled 16 bits 16 bits
5 1 8 bits 16 bits
6*1 0 Expanded mode with
on-chip ROM enabled Enabled 8 bits 16 bits
7*1 Single-chip mode — —
Note: *Only applies to the H8S/2351.
Section 2 CPU
56
2.11 Address Map
This section shows the address map in each operating mode.
The address space is 64 kbytes in mode 1 (normal mode), and 16 Mbytes in modes 4 and 5 (advanced
modes).
The on-chip ROM size is 64 kbytes, but only 56 kbytes of on-chip ROM can be used in modes 2 and 3
(normal modes) (H8S/2351 only).
Address Map in Each Operating Mode
Mode 3*1
(normal single-chip mode)
H'0000
H'E400
H'FBFF
H'FC00
H'FE3F
H'FF28
H'FFFF
H'DFFF
H'E000
H'0000
H'E400
H'FBFF
H'FC00
H'FE3F
H'DFFF
H'0000
H'E400
H'FBFF
External
address space
On-chip RAM*2
External address space
Internal I/O registers
External address space
Internal I/O registers
On-chip ROM
On-chip RAM*2
External address space
Internal I/O registers
External address space
Internal I/O registers
External address space
On-chip ROM
On-chip RAM
Internal I/O registers
Internal I/O registers
Notes: 1. Modes 2 and 3 only apply to the H8S/2351.
2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Mode 2*1
(normal expanded mode
with on-chip ROM enabled)
Mode 1
(normal expanded mode
with on-chip ROM disabled)
H'FF08
H'FFFF
H'FF08
H'FF28 H'FFFF
H'FE40
H'FF07
H'FF28
Section 2 CPU
57
Modes 4 and 5
(advanced expanded modes
with on-chip ROM disabled)
Mode 6*1
(advanced expanded mode
with on-chip ROM enabled)
Mode 7*1
(advanced single-chip mode)
H'000000
H'FFE400
H'FFFBFF
H'FFFC00
H'FFFE3F
H'01FFFF
H'00FFFF
H'010000
H'020000
H'000000
H'FFE400
H'FFFBFF
H'FFFC00
H'FFFE3F
H'00FFFF
H'000000
H'FFE400
H'FFFBFF
External
address space
On-chip RAM*3
External address space
Internal I/O registers
External address space
Internal I/O registers
On-chip ROM
External address
space/
reserved area*2
On-chip RAM*3
External address space
Internal I/O registers
External address space
Internal I/O registers
External
address space
On-chip ROM
On-chip RAM
Internal I/O registers
Internal I/O registers
Notes: 1. Modes 6 and 7 only apply to the H8S/2351.
2. When the EAE bit in BCRL is set to 1, this area is external address space. When the EAE bit is cleared to 0,
it is a reserved area.
3. External addresses can be accessed b
y
clearin
g
the RAME bit in SYSCR to 0.
H'FFFFFF
H'FFFF08
H'FFFF28 H'FFFFFF
H'FFFF08
H'FFFF28 H'FFFFFF
H'FFFE40
H'FFFF07
H'FFFF28
In modes 4 to 7 the address space is divided into 8 areas. See section 3.1.1, Area Partitioning, for
details.
58
Section 3 Peripheral Functions
3.1 Bus Controller (BSC)
The bus controller (BSC) manages the external address space divided into eight areas. The bus
specifications, such as bus width and number of access states, can be set independently for each area,
enabling multiple memories to be connected easily. The bus controller also has a bus arbitration
function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC),
and data transfer controller (DTC).
Features
• Manages external address space in area units
— In advanced mode, manages the external space as 8 areas of 2-Mbytes
— In normal mode, manages the external space as a single area
— Bus specifications can be set independently for each area
— DRAM/burst ROM interfaces can be set
• Basic bus interface
— Chip select (CS0 to CS7) can be output for areas 0 to 7
— 8-bit access or 16-bit access can be selected for each area
— 2-state access or 3-state access can be selected for each area
— Program wait states can be inserted for each area
• DRAM interface
— DRAM interface can be set for areas 2 to 5 (in advanced mode)
• Burst ROM interface
— Burst ROM interface can be set for area 0
• Idle cycle insertion
• Write buffer functions
— External write, DMAC single-address mode transfer, and internal access can be executed in
parallel
• Bus arbitration function
— Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC
• Other features
— Refresh counter (refresh timer) can be used as an interval timer
— External bus release function
Section 3 Peripheral Functions
59
Bus Controller Block Diagram
Internal address bus
CS0 to CS7
External bus control signals
BREQ
BACK
BREQO Internal control signals
Internal data bus
Bus mode signal
Bus arbiter
CPU bus request signal
DTC bus request signal
DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal
External DRAM
control signals
WAIT Wait
controller
DRAM
controller
WCRH
WCRL
RTCNT
RTCOR
DRAMCR
MCR
Area decoder
Bus
controller
ABWCR
ASTCR
BCRH
BCRL
Legend
ABWCR: Bus width control register
ASTCR: Access state control register
BCRH: Bus control register H
BCRL: Bus control register L
WCRH: Wait control register H
WCRL: Wait control register L
MCR: Memory control register
DRAMCR: DRAM control register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
Section 3 Peripheral Functions
60
3.1.1 Area Partitioning
In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas, 0 to 7, in
2-Mbyte units, and performs bus control for external space in area units. In normal mode, it controls a
64-kbyte access space comprising part of area 0.
Area partitioning is only effective in expanded mode, and has no significance in single-chip mode.
Overview of Area Partitioning
Area 0
(2 Mbytes)
H'000000
H'FFFFFF
H'0000
H'1FFFFF
H'200000 Area 1
(2 Mbytes)
H'3FFFFF
H'400000 Area 2
(2 Mbytes)
H'5FFFFF
H'600000 Area 3
(2 Mbytes)
H'7FFFFF
H'800000 Area 4
(2 Mbytes)
H'9FFFFF
H'A00000 Area 5
(2 Mbytes)
H'BFFFFF
H'C00000 Area 6
(2 Mbytes)
H'DFFFFF
H'E00000 Area 7
(2 Mbytes)
H'FFFF
(1) Advanced mode (2) Normal mode
Section 3 Peripheral Functions
61
Bus Specifications
The external address space bus specifications consist of three elements: bus width, number of access
states, and number of program wait states. The bus width and number of access states for on-chip
memory and internal I/O registers are fixed , and are not affected by the bus controller.
Bus specifications can be set as shown below by means of the bus controller control registers.
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR ASTCR WCRH, WCRL Bus Specifications (Basic Bus Interface)
ABWn ASTn Wn1 Wn0 Bus Width Access States Program Wait States
00—— 16 2 0
100 3 0
11
10 2
13
10—— 8 2 0
100 3 0
11
10 2
13
Memory Interfaces
The H8S/2350 Series’ memory interfaces comprise (1) a basic bus interface that allows direct
connection of ROM, SRAM, and so on; (2) a DRAM interface that allows direct connection of
DRAM; and (3) a burst ROM interface that allows direct connection of burst ROM. The interface can
be designated independently for each area.
Section 3 Peripheral Functions
62
3.1.2 Basic Bus Interface
This interface can be designated for areas 0 to 7. When external address space is accessed, the chip
select signal (CS0 to CS7) for each area can be output.
In 3-state access space, 0 to 3 program wait states or a pin wait by means of the WAIT pin can be
inserted.
After a reset, all areas are designated as basic bus interface, 3-state access space (the bus width is
determined by the MCU operating mode).
Basic Bus Timing
Bus cycle
T1T2
Address bus
ø
CSn
AS
RD
D15 to D8Valid
D7 to D0Valid
Read
HWR
LWR
D15 to D8Valid
D7 to D0Valid
Write
Note: n = 0 to 7
Basic Bus Timing (Word Access to 16-Bit 2-State Access Space)
Section 3 Peripheral Functions
63
Bus cycle
T1T2
Address bus
ø
CSn
AS
RD
D15 to D8Valid
D7 to D0Valid
Read
HWR
LWR
D15 to D8Valid
D7 to D0Valid
Write
Note: n = 0 to 7
T3
Basic Bus Timing (Word Access to 16-Bit 3-State Access Space)
Section 3 Peripheral Functions
64
3.1.3 DRAM Interface
In advanced mode, external space areas 2 to 5 can be designated as DRAM space, and DRAM
interfacing performed. With the DRAM interface, DRAM can be directly connected to the H8S/2350
Series. Selectable DRAM space settings are: one area (area 2); two areas (areas 2 and 3); and four areas
(areas 2 to 5). In an area designated as DRAM space, the CS pin functions as the RAS pin.
Features
• 2/4/8-Mbyte or 128/256/512-kbyte DRAM space can be set
• Address multiplexing
— Row address and column address are multiplexed.
— Selection of 8, 9, or 10 bits as the row address shift size
• Basic timing
— 4-state basic timing
— Wait state insertion possible
• DRAM interface
— 2-CAS line scheme for the control signals required for DRAM byte access
• Burst operation
— Fast page mode
• Refresh control
— Selection of CAS-before-RAS refreshing or self-refreshing
— Can be used as interval timer
Section 3 Peripheral Functions
65
DRAM Basic Timing
Tp
ø
CSn (RAS)
Read
Write
CAS, LCAS
HWR (WE)
D15 to D0
HWR (WE)
D15 to D0
A23 to A0
TrTc1 Tc2
Row Column
Note: n = 2 to 5
Basic Access Timing (2-CAS System)
Section 3 Peripheral Functions
66
Tp
ø
CSn (RAS)
Byte control
A23 to A0
TrTc1 Tc2
Row
CAS (UCAS)
LCAS (LCAS)
HWR (WE)
Column
Note: n = 2 to 5
Byte Access Control Timing (Upper Byte Write Access)
H8S/2350 Series
(Address shift size set
to 9 bits)
CS (RAS)
2-CAS type 4-Mbit DRAM
256-kbyte × 16-bit configuration
9-bit column address
Low address input:
A8 to A0
Column address input:
A8 to A0
OE
RAS
CAS (UCAS)UCAS
LCAS (LCAS)LCAS
HWR (WE)WE
A9A8
A8A7
A7A6
A6A5
A5A4
A4A3
A3A2
A2A1
A1A0
D15 to D0D15 to D0
Example of 2-CAS Type DRAM Connection
Section 3 Peripheral Functions
67
3.1.4 Burst ROM Interface
External space area 0 can be designated as burst ROM space, and burst ROM space interfacing can be
performed. The burst ROM space interface enables 16-bit configuration ROM with burst access
capability to be accessed at high speed.
Consecutive burst accesses of a maximum or 4 words or 8 words can be performed for CPU instruction
fetches only. One or two states can be selected for burst access.
T1
Address bus
ø
CS0
AS
Data bus
T2T3T1T2T1
Full access
T2
RD
Burst access
Only lower address changed
Read data Read data Read data
Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
Section 3 Peripheral Functions
68
T
1
Address bus
ø
CS0
AS
Data bus
T
2
T
1
T
1
Full access
RD
Burst access
Only lower address changed
Read data Read data Read data
Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)
Section 3 Peripheral Functions
69
3.2 DMA Controller (DMAC)
The DMA controller (DMAC) can carry out data transfer on up to 4 channels (channels 0A, 0B, 1A,
and 1B). Short address transfer can be performed on each channel independently, and full address
transfer is possible by using pairs of channels.
Features
• Selection of short address mode or full address mode
Short address mode
— Maximum of four channels can be used
— Selection of dual address mode or single address mode
— In dual address mode, one of the two addresses, transfer source and transfer destination, is
specified as 24 bits and the other as 16 bits
— In single address mode, transfer source or transfer destination address only is specified as 24 bits
— In single address mode, transfer can be performed in one bus cycle
— Selection of sequential mode, idle mode, or repeat mode for dual address mode and single
address mode
Full address mode
— Maximum of two channels can be used
— Transfer source and transfer destination address specified as 24 bits
— Selection of normal mode or block transfer mode
• 16-Mbyte address space can be specified directly
• Byte or word can be set as the transfer unit
• Activation sources: internal interrupt, external request, auto-request (depending on transfer mode)
— Six 16-bit timer-pulse unit (TPU) compare-match/input capture interrupts
— Serial communication interface (SCI1, SCI0) transmission complete interrupt, reception
complete interrupt
— A/D converter conversion end interrupt
— External request
— Auto-request
Section 3 Peripheral Functions
70
DMAC Block Diagram
Internal address bus
Address buffer
Processor
Internal interrupts
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
TXI0
RXI0
TXI1
RXI1
ADI
External pins
DREQ0
DREQ1
TEND0
TEND1
DACK0
DACK1
Interrupt signals
DEND0A
DEND0B
DEND1A
DEND1B
Control logic
DMAWER
DMACR1B
DMACR1A
DMACR0B
DMACR0A
DMATCR
DMABCR
Data buffer
Internal data bus
Channel 0
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B
Legend
DMAWER:
DMATCR:
DMABCR:
DMACR:
MAR:
IOAR:
ETCR:
Module data bus
Channel 1
Channel 0AChannel 0BChannel 1AChannel 1B
DMA write enable register
DMA terminal control register
DMA band control register (for all channels)
DMA control register
Memory address register
I/O address register
Executive transfer counter register
Section 3 Peripheral Functions
71
Transfer Modes
The DMAC has the transfer modes shown in the table below. In short address mode, up to four-channel
transfer is possible, with channels A and B operating independently. In full address mode, up to two-
channel transfer is possible, with channels A and B combined.
Transfer Mode Table
Address Register Bit Length
Transfer Mode Transfer Source Source Destination
Short
address
mode
Dual
address
mode
(1) Sequential mode
• 1-byte or 1-word transfer executed for
one transfer request
• Memory address incremented/
decremented by 1 or 2
• 1 to 65536 transfers
(2)Idle mode
• 1-byte or 1-word transfer executed
for one transfer request
• Memory address fixed
• 1 to 65536 transfers
(3)Repeat mode
• 1-byte or 1-word transfer executed
for one transfer request
• Memory address incremented/
decremented by 1 or 2
• After specified number of transfers
(1 to 256), initial state is restored
and operation continues
• TPU channel 0 to 5
compare-match/input
capture A interrupt
• SCI transmission
complete interrupt
• SCI reception complete
interrupt
• A/D converter
conversion end interrupt
• External request
24/16 16/24
Single
address
mode
• 1-byte or 1-word transfer executed
for one transfer request
• Transfer in 1 bus cycle using DACK
pin in place of address specifying I/O
• Specifiable for modes (1) to (3)
• External request 24/DACK DACK/24
Full address mode (4)Normal mode
Auto-request
• Transfer request retained internally
• Transfers continue for the specified
number of times (1 to 65536)
• Selection of burst or cycle steal
transfer
• Auto-request 24 24
External request
• 1-byte or 1-word transfer executed
for one transfer request
• 1 to 65536 transfers
• External request
(5)Block transfer mode
• Specified block size transfer
executed for one transfer request
• 1 to 65536 transfers
• Either source or destination
specifiable as block area
• Block size: 1 to 256 bytes or words
• TPU channel 0 to 5
compare-match/input
capture A interrupt
• SCI transmission
complete interrupt
• SCI reception complete
interrupt
• External request
• A/D converter
conversion end interrupt
24 24
Section 3 Peripheral Functions
72
3.2.1 Short Address Mode
There are two kinds of short address mode—dual address mode and single address mode. Each mode
includes (1) sequential mode, (2) idle mode, (3) repeat mode, and (4) single address mode.
In short address mode, data transfer can be performed on a maximum of four channels.
Operation in Sequential Mode: One byte or word is transferred per transfer request, and a designated
number of these transfers are executed. A CPU or DTC interrupt can be requested on completion of the
designated number of transfers. One 24-bit address and one 16-bit address are specified. The transfer
direction is programmable.
Address T
Address B
Transfer IOAR
1 byte or word transfer performed
per transfer request
Legend
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N – 1))
Where: L = Value set in MAR
N = Value set in ETCR
Operation in Sequential Mode
Section 3 Peripheral Functions
73
Operation in Idle Mode: One byte or word is transferred per transfer request, and a designated
number of these transfers are executed. A CPU or DTC interrupt can be requested on completion of the
designated number of transfers. One 24-bit address and one 16-bit address are specified. The transfer
source and transfer destination addresses are fixed. The transfer direction is programmable.
Transfer IOAR
1 byte or word transfer performed
per transfer request
MAR
Operation in Idle Mode
Operation in Repeat Mode: One byte or word is transferred per transfer request, and a designated
number of these transfers are executed. On completion of the specified number of transfers, address and
transfer counter are automatically restored to their original settings and operation continues. No CPU or
DTC interrupt is requested. One 24-bit address and one 16-bit address are specified. The transfer
direction is programmable.
Address T
Address B
Transfer IOAR
1 byte or word transfer performed
per transfer request
Legend
Address T = L
Address B = L + (–1)
DTID
· (2
DTSZ
· (N – 1))
Where: L = Value set in MAR
N = Value set in ETCR
Operation in Repeat Mode
Section 3 Peripheral Functions
74
Single Address Mode: One byte or word is transferred per transfer request, and a designated number
of these transfers are executed between external memory and an external device. Unlike dual transfer,
the source and destination accesses are performed in parallel. Consequently, either the source or the
destination is an external device that can be accessed only by a strobe by means of the DACK pin. One
address is 24 bits, and for the other, the pins are set automatically. The transfer direction is
programmable.
Sequential, idle, and repeat modes can also be specified in single address mode.
Single address mode can only be specified for channel B.
Address T
Address B
Transfer DACK
1 byte or word transfer performed
per transfer request
Legend
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N – 1))
Where: L = Value set in MAR
N = Value set in ETCR
Operation in Single Address Mode (When Sequential Mode is Specified)
Section 3 Peripheral Functions
75
3.2.2 Full Address Mode
Full address mode includes (5) normal mode and (6) block transfer mode.
In full address mode, data transfer can be performed on a maximum of two channels, with channels A
and B combined.
Normal Mode: One byte or word is transferred per transfer request, and a designated number of these
transfers are executed. A CPU or DTC interrupt can be requested on completion of the designated
number of transfers. Both addresses are 24-bit addresses. There are two transfer requests (activation
sources)—an external request and an auto request.
Address TA
Address BA
Transfer Address TB
Legend
Address TA= LA
Address TB= LB
Address BA= LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1))
Address BB= LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1))
Where: LA= Value set in MARA
LB= Value set in MARB
N = Value set in ETCRA
Address BB
Operation in Normal Mode
Section 3 Peripheral Functions
76
Block Transfer Mode: One block of the specified size is transfer per request, and a designated number
of block transfers are executed. At the end of each block transfer, one address is restored to its initial
value. When the designated number of blocks have been transferred, a CPU or DTC interrupt can be
requested. Both addresses are 24-bit addresses.
Address TA
Address BA
Transfer
Address TB
Legend
Address TA= LA
Address TB= LB
Address BA= LA + SAIDE · (–1)SAID · (2DTSZ · (M · N–1))
Address BB= LB + DAIDE · (–1)DAID · (2DTSZ · (N–1))
Where: LA= Value set in MARA
LB= Value set in MARB
N = Value set in ETCRB
M = Value set in ETCRAH and ETCRAL
Address BB
1st block
2nd block
nth block
Block area
Consecutive
transfer of
M bytes or words
performed per
request
Operation in Block Transfer Mode (When BLKDIR = 0: MARB is Block Area)
Section 3 Peripheral Functions
77
3.3 Data Transfer Controller (DTC)
The data transfer controller (DTC) is activated by an interrupt or software, and can transfer data
without imposing any load on the CPU.
Features
• Transfer possible over any number of channels
— Transfer information is stored in memory
— One activation source can trigger a number of data transfers (chain transfer)
• Variety of transfer modes
— Normal, repeat, and block transfer modes available
— Incrementing, decrementing, and fixing of source and destination addresses can be selected
(destination → destination )
• Direct specification of 16-Mbyte address space possible
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
— An interrupt request can be issued to the CPU after one data transfer ends
— An interrupt request can be issued to the CPU after all specified data transfers have ended
• Can be activated by software
Section 3 Peripheral Functions
78
DTC Block Diagram
Internal data bus
DTCER
A
to
DTCER
F
DTVECR
Interrupt controller DTC On-chip RAM
Internal data bus
Register information
Control logic
DTC
activa-
tion
request
CPU interrupt
request
MRA MRB
CRA
CRB
DAR
SAR
Interrupt
request
Legend
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERF:
DTVECR:
DTC mode registers A and B
DTC transfer count registers A and B
DTC source address register
DTC destination address register
DTC enable registers A to F
DTC vector register
Section 3 Peripheral Functions
79
3.3.1 Data Transfer Operation
The DTC reads register information previously stored in memory, and transfers data on the basis of that
register information. After the data transfer, it writes updated register information back to memory.
Pre-storage of register information in memory makes it possible to transfer data over any required
number of channels. The DTC can also execute a number of transfers with a single activation (chain
transfer).
Next transfer
Read DTC vector
Read register information
Data transfer
Write register information
Clear an activation flag
CHNE = 1?
Transfer counter = 0
or
DISEL = 1
No
No
Yes
Yes
Clear DTCER
Interrupt
exception handling
End
Start
Flowchart of DTC Operation
DTC Activation Sources
The DTC operates when activated by an interrupt or by a write to the DTC vector register (DTVECR)
by software. An interrupt request can be designated as a CPU interrupt source or a DTC activation
source.
When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt
controller priorities have no effect. If there is more than one activation source at the same time, the
DTC operates in accordance with the default priorities.
Section 3 Peripheral Functions
80
Interrupt Sources and DTC Vector Address
The DTC vector address indicates the start address of the register information in memory. The MRA,
SAR, MRB, DAR, CRA, and CRB registers are located in that order from the start address of the
register information. Locate the register information in the on-chip RAM (addresses H'FFF800 to
H'FFFBFF).
Lower address
0123
MRA SAR
DARMRB
CRA CRB
MRA SAR
DARMRB
CRA CRB
Register information
Register information
for 2nd transfer in
chain transfer
Register
information
start address
Chain
transfer
4 bytes
Location of DTC Register Information in Address Space
Section 3 Peripheral Functions
81
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Interrupt Source Origin of
Interrupt Source Vector
Number Vector
Address*DTCE Priority
Write to DTVECR
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
ADI (A/D conversion end)
TGI0A (GR0A compare-match/input capture)
TGI0B (GR0B compare-match/input capture)
TGI0C (GR0C compare-match/input capture)
TGI0D (GR0D compare-match/input capture)
TGI1A (GR1A compare-match/input capture)
TGI1B (GR1B compare-match/input capture)
TGI2A (GR2A compare-match/input capture)
TGI2B (GR2B compare-match/input capture)
TGI3A (GR3A compare-match/input capture)
TGI3B (GR3B compare-match/input capture)
TGI3C (GR3C compare-match/input capture)
TGI3D (GR3D compare-match/input capture)
TGI4A (GR4A compare-match/input capture)
TGI4B (GR4B compare-match/input capture)
TGI5A (GR5A compare-match/input capture)
TGI5B (GR5B compare-match/input capture)
DMTEND0A (DMAC transfer end 0)
DMTEND0B (DMAC transfer end 1)
DMTEND1A (DMAC transfer end 2)
DMTEND1B (DMAC transfer end 3)
RXI0 (reception complete 0)
TXI0 (transmit data empty 0)
RXI1 (reception complete 1)
TXI1 (transmit data empty 1)
Software
External pin
A/D
TPU channel 0
TPU channel 1
TPU channel 2
TPU channel 3
TPU channel 4
TPU channel 5
DMAC
SCI channel 0
SCI channel 1
DTVECR
16
17
18
19
20
21
22
23
28
32
33
34
35
40
41
44
45
48
49
50
51
56
57
60
61
72
73
74
75
81
82
85
86
H'0400+
DTVECR
[6:0]<<1
H'0420
H'0422
H'0424
H'0426
H'0428
H'042A
H'042C
H'042E
H'0438
H'0440
H'0442
H'0444
H'0446
H'0450
H'0452
H'0458
H'045A
H'0460
H'0462
H'0464
H'0466
H'0470
H'0472
H'0478
H'047A
H'0490
H'0492
H'0494
H'0496
H'04A2
H'04A4
H'04AA
H'04AC
—
DTCEA7
DTCEA6
DTCEA5
DTCEA4
DTCEA3
DTCEA2
DTCEA1
DTCEA0
DTCEB6
DTCEB5
DTCEB4
DTCEB3
DTCEB2
DTCEB1
DTCEB0
DTCEC7
DTCEC6
DTCEC5
DTCEC4
DTCEC3
DTCEC2
DTCEC1
DTCEC0
DTCED5
DTCED4
DTCEE7
DTCEE6
DTCEE5
DTCEE4
DTCEE3
DTCEE2
DTCEE1
DTCEE0
High
Low
Note: * Lower 16 bits of the address.
Section 3 Peripheral Functions
82
DTC Operation Timing (Example for Normal and Repeat Modes)
DTC activation
request
DTC request
Address
Vector read
Transfer information
read Transfer information
write
Data transfer
Read Write
ø
Number of DTC Execution States
Mode Vector Read
I
Register
Information
Read/Write
JData Read
KData Write
L
Internal
Operations
M
Normal 1 6 1 1 3
Repeat 1 6 1 1 3
Block transfer 1 6 N N 3
N: Block size (initial setting of CRAH and CRAL)
Number of States Required in Each Execution State
Access To
On-
Chip
RAM
On-
Chip
ROM On-Chip I/O
Registers External Devices
Bus width 32 16 8 16 8 8 16 16
Access states 11222323
Execution state Vector read SI— 1 — — 4 6+2m 2 3+m
Register information
read/write SJ
1 ———————
Byte data read SK112223+m23+m
Word data read SK114246+2m 2 3+m
Byte data write SL112223+m23+m
Word data write SL114246+2m 2 3+m
Internal operation SM11111111
The number of execution states is calculated from the formula below.
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM
Section 3 Peripheral Functions
83
Σ indicates the sum of all transfers activated by one activation event (the number in which the CHNE
bit is set to 1, plus 1).
3.3.2 Transfer Modes
There are three DTC transfer modes—normal mode, repeat mode, and block transfer mode.
The 24-bit DTC source address register (SAR) designates the DTC transfer source address and the 24-
bit destination address register (DAR) designates the transfer destination address. After each transfer,
SAR and DAR are independently incremented, decremented, or left fixed.
Address Registers
Transfer Mode Activation Source Transfer
Source Transfer
Destination
• Normal mode
— One transfer request transfers one byte or
one word
— Memory addresses are incremented or
decremented by 1 or 2
— Up to 65,536 transfers possible
• Repeat mode
— One transfer request transfers one byte or
one word
— Memory addresses are incremented or
decremented by 1 or 2
— After the specified number of transfers (1 to
256), the initial state resumes and operation
continues
• Block transfer mode
— One transfer request transfers a block of the
specified size
— Block size is from 1 to 256 bytes or words
— Up to 65,536 transfers possible
— A block area can be designated at either the
source or destination
• IRQ
• TPU TGI
• SCI TXI or RXI
• A/D converter ADI
• DMAC DEND
• Software
24 bits 24 bits
Section 3 Peripheral Functions
84
Operation in Normal Mode
In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can
be specified. When the specified number of transfers have ended, a CPU interrupt can be requested.
Transfer
SAR DAR
SAR:
DAR:
CRA:
Transfer source address
Transfer destination address
Transfer count
Operation in Normal Mode
Section 3 Peripheral Functions
85
Operation in Repeat Mode
In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be
specified. When the specified number of transfers have ended, the initial settings are restored and
transfer is repeated. A CPU interrupt is not requested.
Transfer
Repeat area
SAR or
DAR DAR or
SAR
SAR:
DAR:
CRA:
Transfer source address
Transfer destination address
Transfer count (8 bits × 2)
Operation in Repeat Mode
Section 3 Peripheral Functions
86
Operation in Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is specified as a block area. The block size is 1 to 256. When the transfer of one
block ends, the initial setting of the address register specified in the block area is restored. The other
address register is incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. When the specified number of transfers have ended, a CPU
interrupt can be requested.
Transfer
SAR or
DAR DAR or
SAR
Block area
.
.
.
First block
nth block
SAR:
DAR:
CRA:
CRB:
Transfer source address
Transfer destination address
Block size (8 bits × 2)
Transfer count
Operation in Block Transfer Mode
Section 3 Peripheral Functions
87
3.4 16-Bit Timer Pulse Unit (TPU)
The 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. The TPU can provide up to
16 kinds of pulse input/output.
The TPU can perform PWM output, pulse width measurement, and two-phase encoder processing, and
can activate the data transfer controller (DTC) and DMA controller (DMAC). It can also generate a
programmable pulse generator (PPG) output trigger and A/D converter start trigger.
Features
• Maximum 16 pulse input/outputs
— A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3, and
two each for channels 1, 2, 4, and 5), each of which can be set independently as an output
compare/input capture register
• Selection of eight counter input clocks for each channel
— Internal clocks: ø, ø/4, ø/16, ø/64, ø/256, ø/1024, ø/4096
— External clocks: TCLKA, TCLKB, TCLKC, TCLKD
• The following operations can be set for each channel:
— Waveform output at compare-match: Selection of 0, 1, or toggle output
— Input capture function: Selection of rising edge, falling edge, or both edge detection
— Counter clear operation: Counter clearing possible by compare-match or input capture
— Synchronous operation:
Multiple timer counters (TCNT) can be written to simultaneously
Simultaneous clearing by compare-match and input capture possible
Simultaneous input/output possible for each register by counter synchronous operation
— PWM mode:
Any PWM output duty can be set
Maximum 15-phase PWM output possible by combination with synchronous operation
• Buffer operation settable for channels 0 and 3
— Input capture register double-buffering possible
— Automatic rewriting of output compare register possible
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
— Two-phase encoder pulse up/down-count possible
Section 3 Peripheral Functions
88
• Cascaded operation
— Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4)
overflow/underflow
• Fast access via internal 16-bit bus
— Fast access is possible via a 16-bit bus interface
• 26 interrupt sources
— For channels 0 and 3, four compare-match/input capture dual-function interrupts and one
overflow interrupt can be requested independently
— For channels 1, 2, 4, and 5, two compare-match/input capture dual-function interrupts, one
overflow interrupt, and one underflow interrupt can be requested independently
• Automatic transfer of register data
— Block transfer, one-word transfer, and one-byte transfer possible by data transfer controller
(DTC) or DMA controller (DMAC) activation
• Programmable pulse generator (PPG) output trigger can be generated
— Channel 0 to 3 compare-match/input capture signals can be used as a PPG output trigger
• A/D converter conversion start trigger can be generated
— Channel 0 to 5 compare-match A/input capture A signals can be used as an A/D converter
conversion start trigger
Section 3 Peripheral Functions
89
TPU Block Diagram
Channel 3Channel 4Channel 5
Control logic for
channels 3 to 5
Channel 2
TIOR
TGRA
TCNT
TGRB
TGRC
Channel 1
TMDR
TSR
TCR
TIER
TGRA
TCNT
TGRB
Channel 0
Control logic for
channels 0 to 2
TGRA
TCNT
TGRB
TGRD
Bus interface
Common
TSYR
Control logic
TSTR
[Input pins]
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
[Clock input]
ø/1
ø/4
ø/16
ø/64
ø/256
ø/1024
ø/4096
TCLKA
TCLKB
TCLKC
TCLKD
[Input pins]
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
[Interrupt request signals]
Channel 3:
Channel 4:
Channel 5:
[Interrupt request signals]
Channel 0:
Channel 1:
Channel 2:
Internal data bus
A/D conversion start
request signal
PPG output trigger signal
Module data bus
TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
TGI4A
TGI4B
TCI4V
TCI4U
TGI5A
TGI5B
TCI5V
TCI5U
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
TGI1A
TGI1B
TCI1V
TCI1U
TGI2A
TGI2B
TCI2V
TCI2U
Channel 3:
Channel 4:
Channel 5:
Internal clock:
External clock:
Channel 0:
Channel 1:
Channel 2:
TIOR TIOR
TMDR
TSR
TCR
TIORH
TIER TIORL TMDR
TIORL
TSR
TCR
TIORH
TIER
TGRA
TCNT
TGRB
TGRC
TGRD
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
Legend
TSTR:
TSYR:
TCR:
TMDR:
TIOR (H, L):
TIER:
TSR:
TGR (A, B, C, D): Timer general registers (A, B, C, D)
Timer start register
Timer synchro register
Timer control register
Timer mode register
Timer I/O control register (H, L)
Timer interrupt enable register
Timer status register
TMDR
TSR
TCR
TIER
Section 3 Peripheral Functions
90
Interrupt Sources and Data Transfer Controller (DTC) and DMA Controller (DMAC)
Activation
TPU Interrupts
Channel Interrupt
Source Description DMAC
Activation DTC
Activation Priority
0
1
2
3
4
5
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
TGI1A
TGI1B
TCI1V
TCI1U
TGI2A
TGI2B
TCI2V
TCI2U
TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
TGI4A
TGI4B
TCI4V
TCI4U
TGI5A
TGI5B
TCI5V
TCI5U
TGR0A input capture/compare-match
TGR0B input capture/compare-match
TGR0C input capture/compare-match
TGR0D input capture/compare-match
TCNT0 overflow
TGR1A input capture/compare-match
TGR1B input capture/compare-match
TCNT1 overflow
TCNT1 underflow
TGR2A input capture/compare-match
TGR2B input capture/compare-match
TCNT2 overflow
TCNT2 underflow
TGR3A input capture/compare-match
TGR3B input capture/compare-match
TGR3C input capture/compare-match
TGR3D input capture/compare-match
TCNT3 overflow
TGR4A input capture/compare-match
TGR4B input capture/compare-match
TCNT4 overflow
TCNT4 underflow
TGR5A input capture/compare-match
TGR5B input capture/compare-match
TCNT5 overflow
TCNT5 underflow
Possible
Not possible
Not possible
Not possible
Not possible
Possible
Not possible
Not possible
Not possible
Possible
Not possible
Not possible
Not possible
Possible
Not possible
Not possible
Not possible
Not possible
Possible
Not possible
Not possible
Not possible
Possible
Not possible
Not possible
Not possible
Possible
Possible
Possible
Possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Possible
Possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Not possible
High
Low
Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed
by the interrupt controller.
Section 3 Peripheral Functions
91
Operation
Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is
also capable of free-running operation, synchronous counting, and external event counting. Each TGR
can be used as an input capture register or output compare register.
Buffer Operation
• When TGR is an output compare register
When a compare-match occurs, the value in the buffer register for the relevant channel is transferred
to TGR.
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transfer to TGR and the value previously held in
TGR is transferred to the buffer register.
Waveform Output by Compare-Match
0, 1, or toggle output can be selected.
Example of 0 Output/1 Output Operation: In this example, TCNT has been designated as a free-
running counter, and settings have been made so that 0 is output by compare-match A, and 1 is output
by compare-match B.
TCNT value
H'FFFF
H'0000
TIOCA
TIOCB
Time
TGRA
TGRB
Does not change
Does not change Does not change
1 output
0 output
Does not change
Example of 0 Output/1 Output Operation
Section 3 Peripheral Functions
92
Example of Toggle Output: In this example, settings have been made so that TCNT counter clearing
is performed by compare-match B, and output is toggled by both by compare-match A and compare-
match B.
TCNT value
H'FFFF
H'0000
TIOCB
TIOCA
Time
TGRB
TGRA
Toggle output
Counter cleared by TGRB compare-match
Toggle output
Example of Toggle Output Operation
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. There are two PWM modes—PWM
mode 1 with a maximum of 8-phase pulse output, and PWM mode 2 with a maximum of 15-phase
pulse output.
PWM Mode 1: PWM output is generated by pairing TGRA with TGRB and TGRC with TGRD.
In PWM mode 1, a maximum 8-phase PWM output is possible.
• Example of operation in PWM mode 1
In this example, TGRA compare-match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 output is set as the TGRB output value. In this case, the
value set in TGRA is the cycle, and the value set in TGRB is the duty.
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
Counter cleared by TGRA
compare-match
Operation in PWM Mode 1
Section 3 Peripheral Functions
93
PWM Mode 2: PWM output is generated using one TGR register as the cycle register and the others as
duty registers. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with
synchronous operation.
• Example of operation in PWM mode 2
In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare-match
is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value
of the other TGR registers, to output a 5-phase PWM waveform. In this case, the value set in
TGR1B is the cycle, and the value set in the other TGR registers is the duty.
TCNT value
TGR1B
H'0000
TIOCA0
Counter cleared by TGR1B
compare-match
TGR1A
TGR0D
TGR0C
TGR0B
TGR0A
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Time
Operation in PWM Mode 2
Section 3 Peripheral Functions
94
Input Capture Operation
The TCNT value can be transferred to TGR on detection of the TIOC pin input edge.
Rising edge, falling edge, or both edges can be selected as the input edge.
• Example of input capture operation
In this example both rising and falling edges have been selected as the TIOCA pin input edge, falling
edge has been selected as the TIOCB pin input edge, and counter clearing by TGRB input capture
has been designated for TCNT.
TCNT value
H'0180
H'0000
TIOCA
TGRA
Time
H'0010
H'0005
Counter cleared by TIOCB
input (falling edge)
H'0160
H'0005 H'0160 H'0010
TGRB H'0180
TIOCB
Input Capture Operation
Section 3 Peripheral Functions
95
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and TCNT
operates as an up/down-counter. There are four modes (phase counting modes 1 to 4) with different
setting conditions. These modes can be set for channels 1, 2, 4, and 5.
Example of Operation in Phase Counting Mode 1
TCNT value
Time
Down-countUp-count
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
• Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA
(Channels 1 and 5) TCLKB
(Channels 1 and 5) Phase Counting Mode
TCLKC
(Channels 2 and 4) TCLKD
(Channels 2 and 4) 1234
High level Up-count — — Up-count
Low level
Low level —
High level Up-count Up-count
High level Down-count — Down-count Down-count
Low level —
High level —
Low level Down-count
Legend
: Rising edge
: Falling edge
— : Don't care
Section 3 Peripheral Functions
96
Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
• Example of buffer operation (1) (When TGR is an output compare register)
In this example, PWM mode 1 has been designated for channel 0, and buffer operation has been
designated for TGRA and TGRC. The settings used are TCNT clearing by a compare-match B, 1
output at compare-match A, and 0 output at compare-match B. When a compare-match A occurs, the
output is changed and the value in buffer register TGRC is simultaneously transferred to timer
general register TGRA.
TCNT value
TGR0B
H'0000
TGR0C
Time
TGR0A
H'0200 H'0520
TIOCA
H'0200
H'0450 H'0520
H'0450
TGR0A H'0450H'0200
Transfer
Example of Buffer Operation (1) (When TGR Is an Output Compare Register)
Section 3 Peripheral Functions
97
• Example of buffer operation (2) (When TGR is an input capture register)
In this example, TGRA has been designated as an input capture register, and buffer operation has
been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for
TCNT, and detection of both rising and falling edges has been selected for the TIOCA pin. When the
TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in
TGRA is simultaneously transferred to TGRC.
TCNT value
H'09FB
H'0000
TGRC
Time
H'0532
TIOCA
TGRA H'0F07H'0532
H'0F07
H'0532
H'0F07
H'09FB
Example of Buffer Operation (2) (When TGR Is an Input Capture Register)
Section 3 Peripheral Functions
98
Cascading
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter.
Channels 1 and 2, and channels 4 and 5, can be cascaded.
• Example of cascaded operation
In this example, counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and
TGR2A have been designated as input capture registers, and TIOC pin rising edge detection has
been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the
upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
TCNT2
clock
TCNT2 H'FFFF H'0000 H'0001
TIOCA1,
TIOCA2
TGR1A H'03A2
TGR2A H'0000
TCNT1
clock
TCNT1 H'03A1 H'03A2
Example of Cascaded Operation (32-Bit Input Capture Operation)
Synchronous Operation
When synchronous operation is designated for a channel, TCNT for that channel performs synchronous
presetting and clearing. That is, when TCNT for a channel designated for synchronous operation is
rewritten, the TCNT counters for the other channels are also rewritten at the same time. When any
clearing condition occurs, the TCNT counters for the other channels are also cleared simultaneously.
Section 3 Peripheral Functions
99
3.5 Programmable Pulse Generator (PPG)
The programmable pulse generator (PPG) can handle up to 16 outputs simultaneously, using a signal
from the 16-bit timer-pulse unit (TPU) as input.
Features
• 16-bit output data
— Maximum 16-bit data can be output, and pulse output can be enabled on a bit-by-bit basis.
• Four output groups
— Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit
outputs.
• Selectable output trigger signals
— Output trigger signals can be selected for each group from the compare-match signals of four
TPU channels.
• Non-overlap mode
— A non-overlap margin can be provided between pulse outputs.
• Can operate together with the data transfer controller (DTC) and DMA controller (DMAC)
— The compare-match signals selected as trigger signals can activate the DTC or DMAC for
sequential output of data without CPU intervention.
• Settable inverted output
— Inverted data can be output for each group.
Section 3 Peripheral Functions
100
PPG Block Diagram
Compare-match signals
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
PO7
PO6
PO5
PO4
PO3
PO2
PO1
PO0
Legend
PMR:
PCR:
NDERH:
NDERL:
NDRH:
NDRL:
PODRH:
PODRL:
Internal data bus
Pulse output
pins, group 3
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
PODRH
PODRL
Control logic
NDERH
PMR
NDERL
PCR
NDRH
NDRL
PPG output mode register
PPG output control register
Next data enable register H
Next data enable register L
Next data register H
Next data register L
Output data register H
Output data register L
Section 3 Peripheral Functions
101
Example of Four-Phase Complementary Non-Overlapping Output
In this example, pulse output is used for four-phase complementary non-overlapping pulse output.
When a TGRB compare-match occurs, outputs change from 1 to 0. When a TGRA compare-match
occurs, outputs change from 0 to 1. Set the non-overlap margin in the TPU TGRA for which the output
trigger is selected, and set the cycle in TGRB.
If the DTC or DMAC is set for activation by a TGIA interrupt, pulse output can be performed without
imposing a load on the CPU.
TCNT value
TCNT
TGRB
TGRA
H'0000
NDRH 95 65 59 56 95 65
00 95 05 65 41 59 50 56 14 95 05 65
PODRH
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Time
Non-
overlap margin
Example of Non-Overlapping Pulse Output (Four-Phase Complementary Non-Overlapping )
Section 3 Peripheral Functions
102
3.6 Watchdog Timer
The H8S/2350 Series can perform system monitoring using its watchdog timer (WDT). When not used
as a watchdog timer, this module can be used as an interval timer.
Features
• Selection of eight counter clock sources
— ø/2, ø/64, ø/128, ø/512, ø/2048, ø/8192, ø/32768, ø/131072
• Can be used as an interval timer
•WDTOVF signal output in watchdog timer mode
— When the counter overflows, the WDT outputs WDTOVF signal externally. It is possible to
select whether or not the entire chip is reset at the same time. Power-on reset or manual reset can
be selected as the internal reset.
• Interrupt generation in interval timer mode
— When the counter overflows, the WDT generates an interval timer interrupt.
Section 3 Peripheral Functions
103
Watchdog Timer Block Diagram
Overflow
Interrupt
control
WOVI (interrupt
request signal)
WDTOVF
Internal reset signal*Reset
control
RSTCSR TCNT TSCR
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
Clock Clock
select
Internal clocks
Bus
interface
Module bus
Note: *The internal reset signal can be generated by a register setting. Either power-on reset or manual
reset can be selected.
Internal bus
WDT
Legend
TCSR:
TCNT:
RSTCSR:
Timer control/status register
Timer counter
Reset control/status register
Section 3 Peripheral Functions
104
Watchdog Timer Operation
The example below shows this module used as a watchdog timer. The timer counter (TCNT) starts
counting up using the specified clock.
TCNT value
H'00 Time
H'FF
WT/IT = 1
TME = 1 H'00 written
to TCNT WT/IT = 1
TME = 1 H'00 written
to TCNT
132 states
*2
518 states
WDTOVF signal
Internal reset signal
*1
WT/IT: Timer mode select bit
TME: Timer enable bit
Note: 1. The internal reset signal is generated only if the RSTE bit is set to 1.
2. 130 states when the RSTE bit is cleared to 0.
Overflow
WDTOVF and internal
reset generated
WOVF = 1
Section 3 Peripheral Functions
105
Interval Timer Operation
The example below shows this module used as an interval timer. The timer counter (TCNT) starts
counting up using the specified clock, and an interval timer request (WOVI) is generated each time
TCNT overflows. This function can be used to generate interrupt requests at regular intervals.
TCNT value
H'00 Time
H'FF
WT/IT = 0
TME = 1 WOVI
Overflow Overflow Overflow Overflow
WOVI WOVI WOVI
WOVI: Interval timer interrupt request generation
Section 3 Peripheral Functions
106
3.7 Serial Communication Interface (SCI)
The H8S/2350 Series is equipped with a two-channel serial communication interface (SCI). All two
channels have the same functions, and can handle both asynchronous and synchronous serial
communication. A function is also provided for serial communication between processors
(multiprocessor communication function).
Features
• Selection of synchronous or asynchronous serial communication mode
• Full-duplex communication capability
• Data register double-buffering enables continuous transmission/reception
• On-chip dedicated baud rate generator allows any bit rate to be selected
• Selection of internal clock from baud rate generator or external clock input (SCK pin) as serial clock
source
• Detection of three receive errors
— Overrun errors, framing errors, and parity errors can be detected
• Break detection
• Four interrupt sources
— Four interrupt sources—transmit data empty, transmission end, receive data full, and receive
error—that can issue requests independently:
— The transmit data empty interrupt and receive data full interrupt can activate the DMA controller
(DMAC) or data transfer controller (DTC) to execute data transfer
• Built-in multiprocessor communication function
• Choice of LSB-first or MSB-first transfer
— Can be selected regardless of the communication mode (except in case of asynchronous mode 7
bit data)
Section 3 Peripheral Functions
107
SCI Block Diagram
RxD
TxD
SCK
Clock
ø
ø/4
ø/16
ø/64
TEI
TXI
RXI
ERI
SCMR
SSR
SCR
SMR
Transmission/
reception
control
Baud rate
generator
BRR
Module data bus
Bus interface
Internal
data bus
RDR
TSRRSR
Parity generation
Parity check
Legend
SCMR: Smart card mode register
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate re
g
ister
TDR
External clock
SCI Block Diagram (One Channel)
SCI Interrupt Sources
Channel Interrupt
Source Description DTC
Activation DMAC
Activation Priority*
0
1
ERI
RXI
TXI
TEI
ERI
RXI
TXI
TEI
Interrupt due to receive error (ORER, FER, or PER)
Interrupt due to receive data full (RDRF)
Interrupt due to transmit data empty (TDRE)
Interrupt due to transmission end (TEND)
Interrupt due to receive error (ORER, FER, or PER)
Interrupt due to receive data full (RDRF)
Interrupt due to transmit data empty (TDRE)
Interrupt due to transmission end (TEND)
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
High
Low
Note: *This table shows the initial state immediately after a reset. Relative priorities among channels can be
changed by means of interrupt controller.
Section 3 Peripheral Functions
108
3.7.1 SCI Asynchronous Mode
There are two SCI operating modes—asynchronous mode and synchronous mode. Asynchronous mode
is described here.
Asynchronous mode is a serial communication mode in which synchronization is achieved character by
character basis, using a start bit and one or two stop bits.
Features
• Twelve serial data transfer formats
— Data length: 7 or 8 bits
— Stop bit length: 1 or 2 bits
— Parity: Even/odd/none
— Multiprocessor bit: 1 or 0
• Selection of internal baud rate generator or external clock from SCK pin as clock source
• Transmit/receive clock can be output from SCK pin
• Break detection capability
— Break can be detected by reading the RxD pin level directly in case of a framing error
• Multiprocessor communication capability
Section 3 Peripheral Functions
109
Transfer Format and Frame Length in Asynchronous Communication
PE
0
0
1
1
0
0
1
1
—
—
—
—
S 8-bit data
STOP
S 7-bit data
STOP
S 8-bit data
STOP STOP
S 8-bit data P
STOP
S 7-bit data
STOP
P
S 8-bit data
MPB STOP
S 8-bit data
MPB STOPSTOP
S 7-bit data
STOPMPB
S 7-bit data
STOPMPB STOP
S 7-bit data
STOPSTOP
CHR
0
0
0
0
1
1
1
1
0
0
1
1
MP
0
0
0
0
0
0
0
0
1
1
1
1
STOP
0
1
0
1
0
1
0
1
0
1
0
1
SMR Settings
123456789101112
Serial Transmit/Receive Format and Frame Length
STOP
S 8-bit data P
STOP
S 7-bit data
STOP
P
STOP
Legend
S: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
Multiprocessor Communication Function
A multiprocessor format, in which a multiprocessor bit is added to the transfer data, can be used for
serial communication, enabling data transfer to be performed among a number of processors.
The transmitting station first sends the ID of the receiving station with which it wants to perform serial
communication as data with a 1 MPB (multiprocessor bit) added. It then sends transmit data as data
with a 0 MPB added.
Receiving stations skip data until data with a 1 MPB is received. Each receiving station then compares
that data with its own ID. The station whose ID matches then continues with reception, and accepts
data. Stations whose ID does not match continue to skip the data until data with a 1 MPB is sent again.
Section 3 Peripheral Functions
110
3.7.2 SCI Synchronous Communication
There are two SCI operating modes—asynchronous mode and synchronous mode. Synchronous mode
is described here.
In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it
suitable for high-speed serial communication.
• Data length: 8 bits per character
• Overrun error detection
• Selection of internal baud rate generator or external clock from SCK pin as transmit/receive clock
source
• Choice of LSB-first or MSB-first Transfer
• Communication is possible with chips provided with a synchronous mode, such as the H8 Series,
HD64180, and HD6301
When the internal baud rate generator is selected, the SCK pin is automatically set to output mode, and
outputs eight synchronization clock pulses.
Transmitting
station
Receiving
station A
(ID = 01)
Receiving
station B
(ID = 02)
Receiving
station C
(ID = 03)
Receiving
station D
(ID = 04)
Serial transmission line
Serial
data
ID transmission cycle =
receiving station
specification
Data transmission cycle =
Data transmission to
receiving station
specified by ID
(MPB = 1) (MPB = 0)
H'01 H'AA
Legend
MPB: Multiprocessor bit
Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
Section 3 Peripheral Functions
111
Don’t
care
Don’t
care
One unit of transfer data (character or frame)
Bit 0
Serial data
Serial clock
Bit 1 Bit 3 Bit 4 Bit 5
LSB MSB
Bit 2 Bit 6 Bit 7
**
Note: * High except in continuous transfer
Data Format in Synchronous Communication
Sample BRR Settings for Various Bit Rates (Synchronous Mode)
ø (MHz)
2 4 8 10 16 20
Bit Rate (bit/s) n N n N n N n N n N n N
110 370——————————
250 2 124 2 249 3 124 — — 3 249 — —
500 1 249 2 124 2 249 — — 3 124 — —
1 k 1 124 1 249 2 124 — — 2 249 — —
2.5 k 0 199 1 99 1 199 1 249 2 99 2 124
5 k 0 99 0 199 1 99 1 124 1 199 1 249
10 k 0 49 0 99 0 199 0 249 1 99 1 124
25 k 0 19 0 39 0 79 0 99 0 159 0 199
50 k 0 9 0 19 0 39 0 49 0 79 0 99
100 k 0 4 0 9 0 19 0 24 0 39 0 49
250 k 0 1 0 3 0 7 0 9 0 15 0 19
500 k 0 0*01 03 04 07 09
1 M 0 0*01 —— 03 04
2.5 M — — 0 0*—— 0 1
5 M —— 0 0*
Note: As far as possible, the setting should be made so that the error is no more than 1%.
The BRR setting is found from the following formula:
N = ø
8 × 22n–1 × B × 106 – 1
Section 3 Peripheral Functions
112
Legend
Blank: Cannot be set.
—: Can be set, but there will be a degree of error.
* Continuous transfer is not possible.
N: Baud rate generator setting (0 ≤ N ≤ 255)
ø: Operating frequency (MHz)
B: Bit rate (bit/s)
n: Baud rate generator input clock (n = 0 to 3)
See the table below for the relation between n and the clock.
n Clock
0ø
1 ø/4
2 ø/16
3 ø/64
Section 3 Peripheral Functions
113
3.8 Smart Card Interface
The SCI supports a smart card interface as an IC card interface serial communication function
conforming to ISO/IEC7816-3 (Identification Card).
Features
• Asynchronous mode
— Data length: 8 bits
— Parity bit generation and checking
— Transmission of error signal (parity error) in receive mode
— Error signal detection and automatic data retransmission in transmit mode
— Direct convention and inverse convention both supported
• Internal baud rate generator allows any bit rate to be selected
• Three interrupt sources
— Three interrupt sources—transmit data empty, receive data full, and transmit/receive error—that
can issue requests independently
— The transmit data empty interrupt and receive data full interrupt can activate the DMA controller
(DMAC) or data transfer controller (DTC) to execute data transfer
Section 3 Peripheral Functions
114
Smart Card Interface Block Diagram
Bus interface
TDR
TSR
Transmission/
reception control
Baud rate
generator
Internal
data bus
RxD
TxD
SCK
Parity generation
Parity check Clock
ø
ø/4
ø/16
ø/64
TXI
RXI
ERI
Module data bus
RSR
RDR SCMR
SSR
SCR
BRR
SMR
Legend
SCMR: Smart card mode register
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
Outline of Operation
• Only asynchronous communication is supported, with one frame consisting of 8-bit data plus a
parity bit.
• In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit)
is left between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for a 1 etu period 10.5
etu after the start bit.
• If the error signal is sampled during transmission, the same data is transmitted automatically after the
elapse of 2 etu or longer.
Section 3 Peripheral Functions
115
Schematic Connection Diagram
TxD
RxD
H8S/2350 Series
VCC
I/O
Connected equipment
IC card
Schematic Diagram of Smart Card Interface Pin Connections
Data Format
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
When there is no parity error
Transmitting station output
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
When a parity error occurs
Transmitting station output
DE
Receiving
station output
Legend
Ds: Start bit
D0 to D7: Data bits
Dp: Parity bit
DE: Error si
g
nal
Smart Card Interface Data Format
Section 3 Peripheral Functions
116
3.9 A/D Converter
The H8S/2350 Series has an on-chip A/D converter with 10-bit precision. Analog signals can be input
on up to eight channels by the program.
Features
• 10-bit resolution
• Eight input channels
• Settable analog conversion voltage range
— Conversion of analog voltages from 0 V to Vref, with the reference voltage pin (Vref) as the
analog reference voltage
• High-speed conversion
— Minimum conversion time:
6.7 µs per channel (at 20 MHz operation)
• Selection of single mode or scan mode
— Single mode: A/D conversion of one channel
— Scan mode: continuous conversion on one to four channels
• Three kinds of conversion start
— Selection of software or timer conversion start trigger (TPU), or ADTRG pin
• Four data registers
— Conversion results held in a data register for each channel
• Sample and hold function
• A/D conversion end interrupt generation
— A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion
Section 3 Peripheral Functions
117
A/D Converter Block Diagram
On-chip
data bus
Bus interface
Module data bus
10-bit D/A
Successive-
approximations register
ADDRA
ADDRB
ADDRC
ADDRD
ADCSR
ADCR
Control circuit
Comparator
Sample-and-
hold circuit
+
–ø/8
ø/16
ADI
Externally triggered
by TPU
Analog
multi-
plexer
AV
CC
V
ref
AV
SS
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADTRG
Legend
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
ADDRD:
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
Section 3 Peripheral Functions
118
Input Channel Setting
Eight-channel analog input is performed by means of the scan mode bit (SCAN) and channel select bits
(CH2 to CH0) in ADCSR.
Bit 2 Bit 1 Bit 0 Description
CH2 CH1 CH0 Single mode (SCAN = 0) Scan mode (SCAN = 1)
0 0 0 AN0 (initial value) AN0
1 AN1 AN0 to AN1
1 0 AN2 AN0 to AN2
1 AN3 AN0 to AN3
1 0 0 AN4 AN4
1 AN5 AN4 to AN5
1 0 AN6 AN4 to AN6
1 AN7 AN4 to AN7
Operation
The successive comparison method is used for A/D conversion, with a 10-bit resolution. There are two
operating modes—single or scan.
Single Mode: Single mode is selected when A/D conversion is to be performed on a single channel
only.
A/D conversion is started when the ADST bit is set to 1, according to the specified conversion start
condition.
On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI
interrupt request is generated.
Scan Mode: Scan mode is selected when A/D conversion is to be performed repeatedly on a number of
channels.
Once the ADST bit is set to 1 according to the specified conversion start condition, A/D conversion is
performed repeatedly on the selected channel until the ADST bit is cleared to 0 by software.
An ADI interrupt request can be generated on completion of the first conversion operation for all the
selected input channels.
Section 3 Peripheral Functions
119
3.10 D/A Converter
The H8S/2350 Series has an on-chip D/A converter with 8-bit precision. Analog signals can be output
on up to two channels by the program.
Features
• Eight-bit resolution
• Two output channels
• Maximum conversion time of 10 µs (with 20 pF load capacitance)
• Output voltage of 0 V to Vref
• D/A output hold function in software standby mode
Operation
D/A converter operation is enabled by setting the D/A output enable bit to 1. While this bit is set to 1,
DADR contents are constantly converted and output to the corresponding pin.
The output value is:
DADR contents
256 × Vref
Section 3 Peripheral Functions
120
D/A Converter Block Diagram
Module data bus Internal data bus
Vref
AVCC
DA1
DA0
AVSS
8-bit D/A
Control circuit
DADR0
Bus interface
DADR1
DACR
Legend
DACR: D/A control register
DADR0: D/A data register 0
DADR1: D/A data register 1
Block Diagram of D/A Converter
Section 3 Peripheral Functions
121
3.11 I/O Ports
The H8S/2350 Series has twelve I/O ports (ports 1, 2, 3, 5, 6, and A to G), and one input-only port (port
4). The ports also function as bus control pins and on-chip supporting module I/O pins.
Each port includes a data direction register (DDR) that controls input/output, a data register (DR) that
stores output data, and a port register (PORT) used to read the pin states.
In addition to DDR and DR, ports A to E also have a MOS input pull-up control register (PCR) to
control the on/off state of MOS pull-up.*
Port Functions in Each Operating Mode
Port Functions
Port Description Pins Mode 1 Mode 2*Mode 3*Mode 4 Mode 5 Mode 6*Mode 7*
Port 1 • 8-bit I/O port P17/PO15/TIOCB2/
TLCKD
P16/PO14/TIOCA2
P15/PO13/TIOCB1/
TLCKC
P14/PO12/TIOCA1
P13/PO11/TIOCD0/
TLCKB
P12/PO10/TIOCC0/
TLCKA
P11/PO9/TIOCB0/
DACK1
P10/PO8/TIOCA0/
DACK0
8-bit I/O port multiplexed as DMA controller output pins (DACK0 and DACK1),
TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0,
TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2) and PPG output pins (PO15 to
PO8)
Port 2 • 8-bit I/O port
• Schmitt-
triggered
input
P27/PO7/TIOCB5
P26/PO6/TIOCA5
P25/PO5/TIOCB4
P24/PO4/TIOCA4
P23/PO3/TIOCD3
P22/PO2/TIOCC3
P21/PO1/TIOCB3
P20/PO0/TIOCA3
8-bit I/O port multiplexed as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3,
TIOCD3, TIOCA4, TIOCB4, TIOCA5, TIOCB5), and PPG output pins (PO7 to
PO0)
Port 3 • 6-bit I/O port
• Open-drain
output
capability
P35/SCK1
P34/SCK0
P33/RxD1
P32/RxD0
P31/TxD1
P30/TxD0
6-bit I/O port multiplexed as SCI (channels 0 and 1) I/O pins (TxD0, RxD0,
SCK0, TxD1, RxD1, SCK1)
Note: *Only applies to the H8S/2351.
Section 3 Peripheral Functions
122
Port Description Pins Mode 1 Mode 2*Mode 3*Mode 4 Mode 5 Mode 6*Mode 7*
Port 4 • 8-bit I/O port P47/AN7/DA1
P46/AN6/DA0
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
8-bit input port multiplexed as A/D converter analog inputs (AN7 to AN0) and
D/A converter analog outputs (DA1 and DA0)
Port 5 • 4-bit I/O port P53/ADTRG
P52
P51
P50
4-bit I/O port multiplexed as A/D converter input pin (ADTRG)
Port 6 • 8-bit I/O port
• Schmitt-
triggered
input (P64 to
P67)
P67/IRQ3/CS7
P66/IRQ2/CS6
P65/IRQ1
P64/IRQ0
P63/TEND1
P62/DREQ1
P61/TEND0/CS5
P60/DREQ0/CS4
8-bit I/O port multiplexed as
DMA controller I/O pins
(DREQ0, TEND0, DREQ1,
TEND1) and interrupt input pins
(IRQ0 to IRQ3)
8-bit I/O port multiplexed as
DMA controller I/O pins
(DREQ0, TEND0, DREQ1,
TEND1), bus control output pins
(CS4 to CS7), and interrupt
input pins (IRQ0 to IRQ3)
8-bit I/O
port multi-
plexed as
interrupt
input pins
(IRQ0 to
IRQ3)
Port A • 8-bit I/O port
• Built-in MOS
input pull-
up*
• Open-drain
output
capability
• Schmitt-
triggered
input (PA4 to
PA7)
PA7/A23/IRQ7
PA6/A22/IRQ6
PA5/A21/IRQ5
Multiplexed as I/O port and
interrupt input pins (IRQ7 to
IRQ4)
When DDR = 0
(after reset):
multiplexed as input
port and interrupt
input pins (IRQ7 to
IRQ5)
When DDR = 1:
address output
When
DDR = 0
(after
reset):
multi-
plexed as
input port
and
interrupt
input pins
(IRQ7 to
IRQ4)
Multi-
plexed as
I/O port
and
interrupt
input pins
(IRQ7 to
IRQ4)
PA4/A20/IRQ4 Address output When
DDR = 1:
address
output
PA3/A19 to
PA0/A16
I/O port Address output When
DDR = 0
(after
reset):
input port
When
DDR = 1:
address
output
I/O port
Port B • 8-bit I/O port
• Built-in MOS
input pull-
up*
PB7/A15 to PB0/A8Address
output When
DDR = 0
(after
reset):
input port
When
DDR = 1:
address
output
I/O port Address output When
DDR = 0
(after
reset):
input port
When
DDR = 1:
address
output
I/O port
Note: *Only applies to the H8S/2351.
Section 3 Peripheral Functions
123
Port Description Pins Mode 1 Mode 2*Mode 3*Mode 4 Mode 5 Mode 6*Mode 7*
Port C • 8-bit I/O port
• Built-in MOS
input pull-
up*
PC7/A7 to PC0/A0Address
output When
DDR = 0
(after
reset):
input port
When
DDR = 1:
address
output
I/O port Address output When
DDR = 0
(after
reset):
input port
When
DDR = 1:
address
output
I/O port
Port D • 8-bit I/O port
• Built-in MOS
input pull-
up*
PD7/D15 to PD0/D8Data bus input/output I/O port Data bus input/output I/O port
Port E • 8-bit I/O port
• Built-in MOS
input pull-
up*
PE7/D7 to PE0/D0In 8-bit bus mode:
I/O port
In 16-bit bus mode:
data bus input/output
I/O port In 8-bit bus mode: I/O port
In 16-bit bus mode: data bus
input/output
I/O port
Port F • 8-bit I/O port PF7/ø When DDR = 0:
input port
When DDR = 1 (after
reset): ø output
When
DDR = 0
(after
reset):
input
port
When
DDR = 1:
ø output
When DDR = 0: input port
When DDR = 1 (after reset):
ø output
When
DDR = 0
(after
reset):
input
port
When
DDR = 1:
ø output
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
AS, RD, HWR, LWR
output I/O port AS, RD, HWR, LWR output I/O port
PF2/LCAS/WAIT/
BREQO When WAITE = 0
and BREQOE = 0
(after reset): I/O port
When WAITE = 1
and BREQOE = 0:
WAIT input
When WAITE = 0 and
BREQOE = 1:
BREQO input
When WAITE = 0 and BREQOE
= 0 (after reset): I/O port
When WAITE = 1 and BREQOE
= 0: WAIT input
When WAITE = 0 and BREQOE
= 1: BREQO output
When RMTS2 to RMTS0 = B'001
to B'011, CW2 = 0, and
LCASS = 0: LCAS output
PF1/BACK
PF0/BREQ
When BRLE = 0
(after reset): I/O port
When BRLE = 1:
BREQ input, BACK
output
When BRLE = 0 (after reset):
I/O port
When BRLE = 1: BREQ input,
BACK output
Port G • 5-bit I/O port PG4/CS0 When DDR = 0*1:
input port
When DDR = 1*2
(after reset): CS0
output
I/O port When DDR = 0*1: input port
When DDR = 1*2 (after reset):
CS0 output
I/O port
PG3/CS1
PG2/CS2
PG1/CS3
I/O port When DDR = 0 (after reset):
input port
When DDR = 1: CS1, CS2, CS3
output
PG0/CAS DRAM space set: CAS output
Otherwise (after reset): I/O port
Notes: * Only applies to the H8S/2351.
1. After a reset in mode 2 or 6.
2. After a reset in mode 1, 4, or 5.
Section 3 Peripheral Functions
124
3.12 RAM
The H8S/2350 Series has 2 kbytes of on-chip high-speed static RAM. The on-chip RAM is connected
to the CPU by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. This
makes it possible to perform fast word data transfer.
The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system
control register (SYSCR).
Block Diagram of RAM
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFE400
H'FFE402
H'FFE404
H'FFFBFE
H'FFE401
H'FFE403
H'FFE405
H'FFFBFF
Section 3 Peripheral Functions
125
3.13 ROM (H8S/2351)*
The H8S/2351* has 64 kbytes of on-chip ROM (PROM or mask ROM). The ROM is connected to the
CPU by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. This
makes possible rapid instruction fetches and high-speed processing.
In normal mode, a maximum of 56 kbytes of ROM can be used.
Block Diagram of ROM
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000002
H'000004
H'00FFFE
H'000001
H'000003
H'000005
H'00FFFF
PROM Programming (ZTAT™)
This programming can be done with a PROM programmer set up in the same way as for the
HN27C101 EPROM (VPP = 12.5 V). Use of a 120- or 128-pin/32-pin socket adapter enables
programming with a commercial PROM programmer. The address range is H'00000 to H'0FFFF.
However, page programming is not supported.
Note: * The H8S/2351 is in the planning stage.
126
Section 4 Power-Down State
4.1 Power-Down State
In addition to the normal program execution state, the H8S/2350 Series has a power-down state in
which operation of the CPU and oscillator is halted and power consumption is reduced. The CPU, on-
chip peripheral functions, etc., are controlled individually, enabling low-power operation to be
achieved. The power-down state includes medium-speed mode, sleep mode, module stop mode,
software standby mode, and hardware standby mode.
Medium-Speed Mode: When one or both of the SCK1 and SCK0 bits in the system clock control
register (SCKCR) are set to 1, medium-speed mode is entered as soon as the current bus cycle ends. In
medium-speed mode, the bus masters—the CPU, DMAC, and DTC—operate on the operating clock
(ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK0 and SCK1 bits. However, on-chip peripheral
functions other than the bus masters operate on the high-speed clock (ø).
In medium-speed mode, a bus access is executed in the specified number of states with respect to the
bus master operating clock. For example, if ø/4 is selected as the operating clock, on-chip memory is
accessed in four states, and internal I/O registers in eight states.
Medium-speed mode is cleared by clearing both the SCK1 and the SCK0 bit to 0. High-speed mode is
restored at the end of the current bus cycle.
Sleep Mode: If a SLEEP instruction is executed when the SSBY bit in the system standby register
(SBYCR) is cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the
contents of the CPU’s internal registers are retained. Other peripheral functions do not stop.
Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program execution
state via the exception handling state.
Module Stop Mode: Module stop mode can be set for individual on-chip peripheral functions.
When the MSTP bit corresponding to a particular peripheral function in the module stop control
register (MSTPCR) is set to 1, operation of the specified module stops at the end of the bus cycle and a
transition is made to module stop mode. The CPU continues operating independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts
operating at the end of the bus cycle.
In module stop mode, the internal states of modules other than the SCI and A/D are retained.
After a reset, all modules except the DMAC and DTC are in module stop mode.
Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1,
software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator
all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip
peripheral functions other than the SCI, A/D and I/O ports are retained.
Section 4 Power-Down State
127
Software standby mode is cleared by a reset or an external interrupt. After the elapse of the oscillation
stabilization time, the program execution mode is restored via the exception handling state.
As the oscillator is stopped in this mode, power consumption is extremely low.
Hardware Standby Mode: When the STBY pin is driven low, a transition is made to hardware
standby mode from any state.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in extremely
low power consumption. As long as the prescribed voltage is supplied, on-chip RAM data is retained.
I/O ports are set to the high-impedance state.
Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is
driven high while the RES pin is low, the reset state is entered and clock oscillation is started. When
the RES pin is subsequently driven high, the program execution state is restored via reset exception
handling.
In this mode, as in software standby mode, power consumption is extremely low since the oscillator is
stopped.
Operating States
Operating Transition Clearing CPU Modules
Mode Condition Condition Oscillator Registers Registers I/O Ports
High-speed
mode Control register Functions High
speed Functions High
speed Functions High speed
Medium-
speed mode Control register Functions Medium
speed Functions High/
medium
speed*1
Functions High speed
Sleep
mode Instruction Interrupt Functions Halted Retained High
speed Functions High speed
Module stop
mode Control register Functions High/
medium
speed
Functions Halted Retained/
reset *2Retained
Software
standby
mode
Instruction External
interrupt Halted Halted Retained Halted Retained/
reset*2Retained
Hardware
standby
mode
Pin Halted Halted Undefined Halted Reset High
impedance
Notes: 1. The bus master operates on the medium-speed clock, and other on-chip peripheral functions operate
on the high-speed clock.
2. The SCI and A/D are reset, and other on-chip peripheral functions retain their state.
128
Appendix
Package
Package Outline Dimensions (Unit: mm)
0.12 Mb
When the terminal width b is the maximum dimension, it indicates that a divergence from the true position
of the center position of up to 0.12 mm is permitted.
If b is smaller than the maximum dimension, the common difference corresponding to b can be extended.
Example
Indication of Terminal Precision “y”
y
Permitted value
Terminal precision
Indication of Geometric Common Difference
Mode of common difference in
which the maximum physical
state is taken as the base
Value of the common difference
Type of geometric common
difference (in this case,
the common difference of
degree of position)
MX
FP-128
0.10 M
20
16.0 ± 0.2
65
38
128
0.5
0.10
1.0
0.5 ± 0.2
3.15 Max
0 – 10°
22.0 ± 0.2
102 64
39
103
1
0.22 ± 0.05
14
0.17 ± 0.05
2.70
0.10 +0.15
–0.10
0.75 0.75
0.20 ± 0.04
0.15 ± 0.04
Appendix
129
TFP-120
16.0 ± 0.2
14
0.07
0.10 0.5 ± 0.1
16.0 ± 0.2
0.4
0.10 ± 0.10
1.20 Max
0.17 ± 0.05
0 – 8°
90 61
130
91
120 31
60
M
0.17 ± 0.05
1.0
1.00
1.20
0.15 ± 0.04
0.15 ± 0.04