Ultra-Low Bias Current
Difet
®
OPERATIONAL AMPLIFIER
FEATURES
●ULTRA-LOW BIAS CURRENT: 100fA max
●LOW OFFSET: 2mV max
●LOW DRIFT: 10µV/°C max
●HIGH OPEN-LOOP GAIN: 94dB min
●LOW NOISE: 15nV/√Hz at 10kHz
● PLASTIC DIP AND SO PACKAGES
APPLICATIONS
●PHOTODETECTOR PREAMPS
●CHROMATOGRAPHY
●ELECTROMETER AMPLIFIERS
●MASS SPECTROMETERS
●pH PROBE AMPLIFIERS
●ION GAGE MEASUREMENT
DESCRIPTION
The OPA129 is an ultra-low bias current monolithic
operational amplifier offered in an 8-pin PDIP and
SO-8 package. Using advanced geometry
dielectrically-isolated FET (
Difet
®) inputs, this monolithic
amplifier achieves a high performance level.
Difet
fabrication eliminates isolation-junction leakage
current—the main contributor to input bias current with
conventional monolithic FETs. This reduces
input bias current by a factor of 10 to 100. Very low
input bias current can be achieved without resorting to
small-geometry FETs or CMOS designs which can
suffer from much larger offset voltage, voltage noise,
drift, and poor power-supply rejection.
The OPA129 special pinout eliminates leakage current
that occurs with other op amps. Pins 1 and 4 have no
internal connection, allowing circuit board guard traces—
even with the surface-mount package version.
OPA129 is available in 8-pin DIP and SO packages,
specified for operation from –40°C to +85°C.
+In
Output
6
Noise-Free
Cascode
7
5
V–
V+
30kΩ30kΩ
–In
3
2
Simplified Circuit
8
Substrate
OPA129
OPA129
OPA129
SBOS026A – JANUARY 1994 – REVISED APRIL 2007
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1994–2007, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Difet is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
OPA129
2SBOS026A
www.ti.com
SPECIFICATIONS
ELECTRICAL
At VS = ±15V and TA = +25°C, unless otherwise noted. Pin 8 connected to ground.
NOTES: (1) High-speed automated test.
(2) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input
overdrive.
OPA129PB, UB OPA129P, U
PARAMETER CONDITION MIN TYP MAX MIN TYP MAX UNITS
INPUT BIAS CURRENT(1) VCM = 0V ±30 ±100 * ±250 fA
vs Temperature Doubles every 10°C*
INPUT OFFSET CURRENT VCM = 0V ±30 * fA
OFFSET VOLTAGE
Input Offset Voltage VCM = 0V ±0.5 ±2±1±5mV
vs Temperature ±3±10 ±5µV/°C
Supply Rejection VS = ±5V to ±18V ±3±100 * * µV/V
NOISE
Voltage f = 10Hz 85 * nV/√Hz
f = 100Hz 28 * nV/√Hz
f = 1kHz 17 * nV/√Hz
f = 10kHz 15 * nV/√Hz
fB = 0.1Hz to 10Hz 4 * µVPP
Current f = 10kHz 0.1 * fA/√Hz
INPUT IMPEDANCE
Differential 1013 || 1 * Ω || pF
Common-Mode 1015 || 2 * Ω || pF
VOLTAGE RANGE
Common-Mode Input Range ±10 ±12 * * V
Common-Mode Rejection VIN = ±10V 80 118 * * dB
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain RL ≥ 2kΩ94 120 * * dB
FREQUENCY RESPONSE
Unity Gain, Small Signal 1 * MHz
Full Power Response 20Vp-p, RL = 2kΩ47 * kHz
Slew Rate VO = ±10V, RL = 2kΩ1 2.5 * * V/µs
Settling Time: G = –1, RL = 2kΩ, 10V Step
0.1% 5*µs
0.01% 10 * µs
Overload Recovery, 50% Overdrive(2) G = –15 *µs
RATED OUTPUT
Voltage Output RL = 2kΩ±12 ±13 * * V
Current Output VO = ±12V ±6±10 * * mA
Load Capacitance Stability Gain = +1 1000 * pF
Short-Circuit Current ±35 ±55 * * mA
POWER SUPPLY
Rated Voltage ±15 * V
Voltage Range, Derated Performance ±5±18 * * V
Current, Quiescent IO = 0mA 1.2 1.8 * * mA
TEMPERATURE
Specification Ambient Temperature –40 +85 * * °C
Operating Ambient Temperature –40 +125 * * °C
Storage –40 +125 * * °C
Thermal Resistance
θ
JA, Junction-to-Ambient
DIP-8 90 * °C/W
SO-8 100 * °C/W
OPA129 3
SBOS026A www.ti.com
1001 1M 10M1k 10k 100k10
POWER SUPPLY REJECTION vs FREQUENCY
Frequency (Hz)
Power Supply Rejection (dB)
140
120
100
80
60
40
20
0
+PSRR
–PSRR
OPEN-LOOP FREQUENCY RESPONSE
Frequency (Hz)
Voltage Gain (dB)
140
120
100
80
60
40
20
01001 1M 10M
θ
45
90
135
180
Pulse Shift (degrees)
Gain
1k 10k 100k10
Phase
Margin
≈90°
Power Supply Voltage ...................................................................... ±18V
Differential Input Voltage ............................................................V– to V+
Input Voltage Range.................................................................... V– to V+
Storage Temperature Range .........................................–40°C to +125°C
Operating Temperature Range ......................................–40°C to +125°C
Output Short Circuit Duration(1) .................................................................. Continuous
Junction Temperature (TJ) ............................................................ +150°C
ABSOLUTE MAXIMUM RATINGS
NOTE: (1) Short circuit may be to power supply common at +25°C ambient.
PACKAGE INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR
OPA129P DIP-8 P
OPA129PB DIP-8 P
OPA129U SO-8 D
OPA129UB SO-8 D
NOTE: (1) For the most current package and ordering information, see the
Package Option Addendum at the end of this data sheet, or see the TI website
at www.ti.com.
CONNECTION DIAGRAM
ELECTROSTATIC
DISCHARGE SENSITIVITY
Any integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to ob-
serve proper handling and installation procedures can
cause damage.
ESD damage can range from subtle performance deg-
radation to complete device failure. Precision inte-
grated circuits may be more susceptible to damage
because very small parametric changes could cause
the device not to meet published specifications.
Top View DIP/SO
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +15VDC, unless otherwise noted.
1
2
3
4
8
7
6
5
Substrate
V+
Output
V–
NC
–In
+In
NC
OPA
NC: No internal connection.
OPA129
4SBOS026A
www.ti.com
0
Frequency (Hz)
FULL-POWER OUTPUT vs FREQUENCY
Output Voltage (VPP)
10k 100k1k 1M
30
20
10
10
Frequency (Hz)
INPUT VOLTAGE NOISE SPECTRAL DENSITY
Voltage Density (nV/√Hz)
1 10 100 1k 10k 100k
1k
100
10
1
0.1
0.01–15 –10 –551015
Common-Mode Voltage (V)
BIAS AND OFFSET CURRENT
vs INPUT COMMON-MODE VOLTAGE
Normalized Bias and Offset Current
0
BIAS AND OFFSET CURRENT vs TEMPERATURE
Ambient Temperature (°C)
Bias and Offset Current (fA)
100pA
10pA
1pA
100
10
1–50 50 125–25 0 25 75 100
IB and IOS
1001 1M 10M1k 10k 100k10
COMMON-MODE REJECTION vs FREQUENCY
Frequency (Hz)
Common-Mode Rejection (dB)
140
120
100
80
60
40
20
0
COMMON-MODE REJECTION
vs INPUT COMMON-MODE VOLTAGE
Common-Mode Voltage (V)
Common-Mode Rejection (dB)
70 15 1510 10
505
120
110
100
90
80
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, +15VDC, unless otherwise noted.
OPA129 5
SBOS026A www.ti.com
OPEN-LOOP GAIN, PSR AND CMR vs TEMPERATURE
Ambient Temperature (°C)
PSR, CMR, Voltage Gain (dB)
130
120
110
100
90
CMR
A
OL
PSR
–75 125–50 75–25 0 25 50 100
SUPPLY CURRENT vs TEMPERATURE
Ambient Temperature (°C)
Supply Current (mA)
2.0
1.5
1.0
0.5
0–75 125–50 75
–25 0 25 50 100
0
Supply Voltage (±V
CC
)
GAIN BANDWIDTH AND SLEW RATE
vs SUPPLY VOLTAGE
Gain Bandwidth (MHz)
515020
3
2
1
10 0
Slew Rate (v/µs)
6
4
2
+Slew
–Slew
GBW
GAIN BANDWIDTH AND SLEW RATE
vs TEMPERATURE
Ambient Temperature (°C)
Gain Bandwidth (MHz)
Slew Rate (V/µs)
4
3
2
1
4
3
2
1
0
0–75 125–50 75–25 0 25 50 100
LARGE SIGNAL TRANSIENT RESPONSE
Time (µs)
Output Voltage (V)
10
0
–10
05025
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, +15VDC, unless otherwise noted.
SMALL SIGNAL TRANSIENT RESPONSE
Time (µs)
Output Voltage (mV)
80
40
0
–40
010
2468
–80
5µs
5V 1µs
20mV
OPA129
6SBOS026A
www.ti.com
0
Supply Voltage (±V
CC
)
COMMON-MODE INPUT RANGE vs SUPPLY VOLTAGE
Common-Mode Voltage (+V)
510020
15
10
5
15
BIAS CURRENT vs ADDITIONAL POWER DISSIPATION
Additional Power Dissipation (mW)
Bias Current (fA)
100pA
10pA
1pA
100
10
10 200 35050 100 150 250 300
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, +15VDC, unless otherwise noted.
APPLICATIONS INFORMATION
NON-STANDARD PINOUT
The OPA129 uses a non-standard pinout to achieve lowest
possible input bias current. The negative power supply is
connected to pin 5—see Figure 1. This is done to reduce the
leakage current from the V- supply (pin 4 on conventional
op amps) to the op amp input terminals. With this new
pinout, sensitive inputs are separated from both power
supply pins.
FIGURE 1. Offset Adjust Circuit.
OFFSET VOLTAGE TRIM
The OPA129 has no conventional offset trim connections.
Pin 1, next to the critical inverting input, has no internal
connection. This eliminates a source of leakage current and
allows guarding of the input terminals. Pin 1 and pin 4, next
to the two input pins, have no internal connection. This
allows an optimized circuit board layout with guarding—see
the Circuit Board Layout section.
Due to its laser-trimmed input stage, most applications do
not require external offset voltage trimming. If trimming is
required, the circuit shown in Figure 1 can be used. Power
supply voltages are divided down, filtered and applied to the
non-inverting input. The circuit shown is sensitive to varia-
tion in the supply voltages. Regulation can be added, if
needed.
GUARDING AND SHIELDING
Ultra-low input bias current op amps require precautions to
achieve best performance. Leakage current on the surface of
circuit board can exceed the input bias current of the ampli-
fier. For example, a circuit board resistance of 1012Ω from
a power supply pin to an input pin produces a current of
15pA—more than 100 times the input bias current of the op
amp.
To minimize surface leakage, a guard trace should com-
pletely surround the input terminals and other circuitry
connecting to the inputs of the op amp. The DIP package
should have a guard trace on both sides of the circuit board.
The guard ring should be driven by a circuit node equal in
potential to the op amp inputs—see Figure 2. The substrate,
pin 8, should also be connected to the circuit board guard to
assure that the amplifier is fully surrounded by the guard
potential. This minimizes leakage current and noise pick-up.
Careful shielding is required to reduce noise pickup. Shield-
ing near feedback components may also help reduce noise
pick-up.
Triboelectric effects (friction-generated charge) can be a
troublesome source of errors. Vibration of the circuit board,
input connectors and input cables can cause noise and drift.
Make the assembly as rigid as possible. Attach cables to
avoid motion and vibration. Special low noise or low leak-
age cables may help reduce noise and leakage current. Keep
all input connections as short possible. Surface-mount com-
ponents may reduce circuit board size and allow a more rigid
assembly.
OPA129 V
OUT
V
IN
R
F
R
IN
2
36
7
5V+
V–
0.1µF220Ω
470kΩ470kΩ
V–
V+
OPA129 7
SBOS026A www.ti.com
CIRCUIT BOARD LAYOUT
The OPA129 uses a new pinout for ultra low input bias
current. Pin 1 and pin 4 have no internal connection. This
allows ample circuit board space for a guard ring surround-
ing the op amp input pins—even with the tiny SO-8 surface-
mount package. Figure 3 shows suggested circuit board
layouts. The guard ring should be connected to pin 8 (sub-
strate) as shown. It should be driven by a circuit node equal
in potential to the input terminals of the op amp—see Figure
2 for common circuit configurations.
TESTING
Accurately testing the OPA129 is extremely difficult due to
its high performance. Ordinary test equipment may not be
able to resolve the amplifier’s extremely low bias current.
Inaccurate bias current measurements can be due to:
1. Test socket leakage.
2. Unclean package.
3. Humidity or dew point condensations.
4. Circuit contamination from fingerprints or anti-static
treatment chemicals.
5. Test ambient temperature.
6. Load power dissipation.
7. Mechanical stress.
8. Electrostatic and electromagnetic interference.
18
5
4
18
5
4
(A) DIP package
(B) SOIC package
V–
V
0
V+
V–
V
0
V+ Connect to proper circuit
node, depending on circuit
configuration (see Figure 2).
Connect to proper circuit
node, depending on circuit
configuration (see Figure 2).
FIGURE 7. Sensitive Photodiode Amplifier.
2
36
8
OPA129 Output
Pin photodiode
HP 5082-4204
5
7
+15V
–15V
0.1µF
5 x 109V/W
0.1µF
1010Ω
~1pF to prevent gain peaking
Guard
Circuit must be well shielded.
Out
In 2
36
8
(C) Inverting
Out
In
2
36
8
(A) Non-Inverting
Out
In
2
36
8
(B) Buffer
Guard top and bottom of board.
FIGURE 2. Connection of Input Guard.
FIGURE 3. Suggested Board Layout for Input Guard.
FIGURE 5. High Impedance (1015Ω) Amplifier.
FIGURE 6. Piezoelectric Transducer Charge Amplifier.
1VDC
Output
2
36
8
Guard
500Ω9.5kΩ
OPA129
pH Probe
R
S
≈ 500MΩ
50mV Out
7
5
V–
V+
FIGURE 4. Current-to-Voltage Converter.
2
36
7
5
8
OPA129
1000MΩ
RF
Output
VO = –IIN • RF
VO = –10V/nA
18kΩ2kΩ
Current
Input
IIN
V–
V+
VOUT
2
36
8
CF
OPA129
Low frequency cutoff =
1/(2πRFCF) = 0.16Hz
10pF
1011Ω
Output
VOUT = –∆Q/CF
∆Q
RF
7
5
V–
V+
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
OPA129P OBSOLETE PDIP P 8 TBD Call TI Call TI
OPA129PB OBSOLETE PDIP P 8 TBD Call TI Call TI
OPA129U ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA129UB ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA129UB/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA129UB/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA129UBE4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA129UBG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA129UE4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Feb-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA129UB/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA129UB/2K5 SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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